Icom IC-F50V, IC-F51V Service Manual

VHF TRANSCEIVER

S-14406XZ-C1
Sep. 2007

INTRODUCTION

This service manual describes the latest service information
for the IC-F50V/F51V VHF TRANSCEIVER at the time of
publication.

Model Version Symbol

USA [A]

USA

USA-01 [B] Yes N/A

F50V

Export

Europe

F51V

USA-02 [C] Yes Yes

EXP [D]
EXP-01 [E] Yes N/A
EXP-02 [F] Yes Yes

EUR [G]
EUR-01 [H] Yes N/A
EUR-02 [I] Yes Yes

CHN [J]

China

CHN-01 [K] Yes N/A
CHN-02 [L] Yes Yes

UNIT ABBREVIATIONS:

F=FRONT UNIT
M=MAIN UNIT
V=VR UNIT
CO=CONNECT UNIT

Channel
spacing

(kHz)

15.0/30.0

12.5/25.0

12.5/20.0/25.0

12.5/25.0

Vibration

Voice

storage

N/A N/A

N/A N/A

N/A N/A

N/A N/A

To upgrade quality, any electrical or mechanical parts and
internal circuits are subject to change without notice or
obligation.

CAUTION

NEVER connect the transceiver to an AC outlet or to a DC

power supply that uses more than specified. This will ruin
the transceiver.

DO NOT reverse the polarities of the power supply when
connecting the transceiver.

DO NOT apply an RF signal of more than 20 dBm (100 mW) to
the antenna connector. This could damage the transceiver’s
front-end.

ORDERING PARTS

Be sure to include the following four points when ordering
replacement parts:

1. 10-digit Icom parts numbers

2. Component name

3. Equipment model name and unit name

4. Quantity required

<ORDER EXAMPLE>

1110003491 S.IC TA31136FNG IC-F50V MAIN UNIT 5 pieces

8820001210 Screw 2438 screw IC-F51V Top cover 10 pieces

Addresses are provided on the inside back cover for your
convenience.

REPAIR NOTES

1. Make sure the problem is internal before disassembling
the transceiver.

2. DO NOT open the transceiver until the transceiver is
disconnected from its power source.

3. DO NOT force any of the variable components. Turn
them slowly and smoothly.

4. DO NOT short any circuits or electronic parts. An
insulated tuning tool MUST be used for all adjustments.

5. DO NOT keep power ON for a long time when the
transceiver is defective.

6. DO NOT transmit power into a Standard Signal
Generator or a Sweep Generator.

7. ALWAYS connect a 50 dB to 60 dB attenuator between
the transceiver and a Deviation Meter or Spectrum
Analyzer when using such test equipment.

8. READ the instructions of test equipment throughly
before connecting a test equipment to the transceiver.

Icom, Icom Inc. and

logo are registered trademarks of Icom Incorporated (Japan) in the United States, the United

Kingdom, Germany, France, Spain, Russia and/or other countries.

CONTENTS

SECTION 1 SPECIFICATIONS

SECTION 2 INSIDE VIEWS

SECTION 3 DISASSEMBLY INSTRUCTIONS

SECTION 4 CIRCUIT DESCRIPITON

4-1 RECEIVER CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4-2 TRANSMITTER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4-3 FREQUENCY SYNTHESIZER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4-4 OTHER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

4-5 VOLTAGE BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

4-6 CPU (F: IC401) PORT ALLOCATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

SECTION 5 ADJUSTMENT PROCEDURES

5-1 PREPARATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5-2 FREQUENCY ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5-3 TRANSMIT ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

5-4 RECEIVE ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

SECTION 6 PARTS LIST

SECTION 7 MECHANICAL PARTS

SECTION 8 BOARD LAYOUTS

SECTION 9 BLOCK DIAGRAM

SECTION 10 VOLTAGE DIAGRAM

FRONT UNIT (Incl. CONNECT and VR UNITS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

MAIN UNIT (Left side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

MAIN UNIT (Right side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

SECTION 1 SPECIFICATIONS

M GENERAL

• Frequency coverage : TX/RX 136–174 MHz

• Number of conventional channels : 128 ch / 8 banks

• Type of emission : Wide 16K0F3E (25.0 kHz)

• Antenna impedance : 50 Ω (Nominal)

• Operating temperature range : –30˚C to +60˚C; –22˚F to +140˚F [USA], [EXP], [CHN]

• Power supply requirement (nominal) : Specified Icom's battery packs only (7.2 V DC; negative ground)

• Current drain (Approx.) : Receiving 85 mA (stand-by)

• Dimensions (Projections not included) : 56.0 (W)×97.0 (H)×36.4 (D) mm; 2

• Weight (Incl. BP-227) : Approx. 280 g; 9

M TRANSMITTER

• Output power : 5 W (High)/2 W (Low2)/1 W (Low1)

• Modulation : Variable reactance frequency modulation

• Maximum frequency deviation : ±5.0 kHz (Wide)

• Frequency stability : ±2.5 ppm

• Spurious emissions : 70 dB typ. [USA], [EXP], [CHN]

• Adjacent channel power : 70 dB min. (Wide, Middle)

• Audio harmonic distortion : 3% (at AF 1 kHz 40% deviation)

• FM Hum and noise (without CCITT filter)
[USA], [EXP], [CHN] only

• Residual modulation (with CCITT filter)
[EUR] only

• Limitting charact of modulator : 60–100% of max. deviation

• Microphone impedance : 2.2 k

Middle 14K0F3E (20.0 kHz) [EUR] only
Narrow 11K0F3E (12.5 kHz)

–25˚C to +55˚C [EUR]

500 mA (max. audio with internal speaker)
350 mA (max. audio with external speaker)
Transmitting 1.8 A (at 5.0 W)

0.7 A (at 1.0 W)

7

/8 oz.

±4.0 kHz (Middle) [EUR] only
±2.5 kHz (Narrow)

0.25 μW (≤1 GHz), 1.0 μW (>1 GHz) [EUR]

60 dB min. (Narrow)

: 40 dB min., 46 dB typ. (Wide)

34 dB min., 40 dB typ. (Narrow)

: 50 dB min., 55 dB typ. (Wide)

43 dB min., 53 dB typ. (Middle)
40 dB min., 50 dB typ. (Narrow)

Ω

7

/32 (W)×3 13⁄16 (H)×1 7⁄16 (D) in.

M RECEIVER

• Receive system : Double-conversion superheterodyne system

• Intermediate frequencies : 1st IF: 46.35 MHz, 2nd IF: 450 kHz

• Sensitivity : 0.25 μV typ. at 12 dB SINAD [USA], [EXP], [CHN]
–4 dBµ V (EMF) typ. at 20 dB SINAD [EUR]

• Squelch sensitivity (at threshold) : 0.25 μV typ. [USA], [EXP], [CHN]
–4 dBµ V (EMF) typ. [EUR]

• Adjacent channel selectivity : 70 dB min., 75 dB typ. (Wide, Middle)

• Spurious response : 70 dB

• Intermodulation rejection ratio : 70 dB min., 74 dB typ. [USA], [EXP], [CHN]

• Hum and noise (without CCITT filter)

[USA], [EXP], [CHN] only

• Hum and noise (with CCITT filter)

[EUR] only

• Audio output power

(at 5% distortion with an 8 Ω load)

• Audio output impedance : 8

Specifications are measured in accordance with TIA/EIA 603 ([USA], [EXP], [CHN]) or EN 300 086 ([EUR]).

All stated specifications are subject to change without notice or obligation.

60 dB min., 65 dB typ. (Narrow)

65 dB min., 67 dB typ. [EUR]

: 40 dB min., 45 dB typ. (Wide)

34 dB min., 40 dB typ. (Narrow)

: 45 dB min., 55 dB typ. (Wide)

43 dB min., 53 dB typ. (Middle)
40 dB min., 50 dB typ. (Narrow)

: 0.7 W typ. (max. audio with internal speaker)

0.5 W typ. (max. audio with external speaker)

Ω

1 - 1

SECTION 2 INSIDE VIEWS

• FRONT UNIT

AF POWER AMP
(IC405: TDA8547TS)

EXPANDER
(IC410: CD4094BPWR)

CPU
(IC401: HD64F2268TFV)

CPU CLOCK
(X401: CR-764)

RESET IC
(IC408: BD5242G)

• MAIN UNIT

MIC AMP
(IC407: NJM12904V)

AF BUFFER, AF MIXER
(IC5: NJM12904V)

RF CIRCUITS

EEPROM
(IC409: HN58X24256FPIE)

DAC
(IC6: M62363FP-650C)

DISCRIMINATOR
(X1: CDBKB450KCAY24)

VIBRATION MOTOR
(MF1: QX10A(R5.5X3))

TX POWER AMP
(Q7: RD07MVS2-T112)

DRIVE AMP
(Q8: RD01MUS1-T113)

AF BUFFER
(IC6: NJM12904V)

LOCK VOLTAGE SWITCH
(IC17: TC4S66F)

2 - 1

BASE BAND IC
(IC10: AK2346)

EXPANDER
(IC12: CD4094BPWR)

SECTION 3 DISASSEMBLY INSTRUCTION

1. REMOVING THE CHASSIS UNIT

q Unscrew the ANT nut, and remove the VR knob.
w Remove the VR washer, and unscrew the top screw.
e Unscrew side screws and washers.
r Unscrew bottom screws.
t Take off the CHASSIS UNIT in the direction of the

arrow.

y Disconnect the flat cable from the CHASSIS UNIT

(MAIN UNIT).

CHASSIS

VR washer

VR knob

ANT nut

Side screw & Washer

Top screw

Side screw & washer

Bottom screws

Flat cable

2. REMOVING THE FRONT UNIT

q Disconnect the VR cable from J402.
w Disconnect the flat cable from J403.

3. REMOVING THE MAIN UNIT

q Unsolder 6 points from the shield cover.
w Unsolder 4 points from the contact spring.
e Unsolder 1 point from the antenna connector.

Unsolder ×4

(contact spring)

Unsolder ×6

(shield cover)

MAIN UNIT

Unsolder ×1

(antenna connector)

r Unscrew 2 screws, and remove the shield cover.
t

Disconnect the motor connector* from the MAIN UNIT.

Unscrew ×2

VR cable

J402

Flat cable

J403

e Unscrew 4 screws.
r Unsolder 2 points (at the speaker leads).
t Take off the FRONT UNIT in the direction of the

arrow.

Unscrew ×4

Unsolder ×2

(Speaker leads)

FRONT UNIT

Shield cover

CHASSIS

*: Except [A], [D], [G], [J]

MAIN UNIT

Disconnect

(motor connector)

y Unscrew 5 screws, and take off the MAIN UNIT.

Unscrew ×5

MAIN UNIT

*

3 - 1

CHASSIS

SECTION 4 CIRCUIT DESCRIPTION

4-1 RECEIVER CIRCUITS

RF CIRCUITS

RF circuits consist of RF fi lters, antenna switch (ANT SW),
RF amplifi er (RF AMP), etc., and extracts and amplifi es the
signals of frequency which desired to receive.

The received signals (RX signals) from the antenna are passed
through the LPF, ANT SW (as an LPF in RX), limitter , BEF
(Band Eliminate Filter) and the two-staged tuned BPF. The
fi ltered RX signals are amplifi ed by the RF AMP, and passed
through another two-staged tuned BPF. The fi ltered RX signals
are then applied to the 1st IF circuits.

The ANT SW toggles RX line and TX line. While receiving,
the TX line and the antenna is disconnected to prevent RX
signals entering. The RX line is disconnected from the GND
simultaneously, and an LPF which guides received signals
to the RX circuits is composed.

While transmitting, serial-connected PIN diodes are ON,
thus the TX line is connected to the antenna, and the RX
line is connected to the GND simultaneously to prevent TX
signal entering.

The limitter protects RX line from over-level RF inputs, and
the BEF (=trap) damps unwanted signals to GND.

The tuned-BPF is adjusted so that it responds to receiving
frequency and rejects all others, by the variable capacitor
whose capacitance is varied by added voltage "T1" and "T2."

The RF AMP amplifi es RX signals to a level suited to the 1st
mixer.

• RF CIRCUITS

R5V

L1

2

C322

1stLO

C41

C44

Two-staged

TUNED BPF

LPF

C183

L14

C49

C324

C323

C40

D10

L11

C45

R23

C43

D9

C39

R21

R22

C42

R17

C35

C36

L9

RF

AMP

C37

Q2

C38

C32

R20

C33

R16

T2

C184

R172

R18

C186

C31

R19

C30

R12

R213

C29

R15

L8

1ST IF CIRCUITS

The 1st IF circuits consist of 1st mixer, 1st IF fi lter and 1st IF
amplifi er (IF AMP). And it converts the RX signals into the
1st IF signal, then filters to remove unwanted signals and
amplifi es.

R171

C28

AGC LINE

Q1

DRIVER

R173

RSSI

R174

D23

R175

Two-staged

C23

TUNED BPF

C22

D4

C26

R13

C27

LIMITTER

C19

C25

6P

D8

L7

C20

R11

R14

BEF

C24

T1

D6

C18

L31

C17

D7

To TX AMP

L6

L5

D5

C16

LPF (ANT SW)

C14

C5

The converted 1st IF signal is passed through the 1st IF fi lter
to be removed unwanted signals. The fi ltered 1st IF signal is
applied to the 1st IF AMP via the limitter. The amplifi ed 1st
IF signal is then applied to the 2nd IF circuits.

L2

C4

C3

LPF

To ANT

L1C6

C2

R51

C1

The filtered RX signals are applied to the 1st mixer to be
converted into the 1st IF signal, by being mixed with the 1st
Local Oscillator (LO) signals “1stLO” from the RX VCO via
the LPF.

• 1ST IF CIRCUITS

R5V R5V

56

FL-335

R31

C53

C54

FI1

1

IN

C55

R48

1stIF

Q4

R34

1st IF

AMP

C329

C59

R35

C60

C58

R33

D26

LIMITTER

1st IF

FILETR

4

GND

2

OU T3GND

C56

L13

R32

1st

MIXER

4 - 1

C51

R5V

C57

R27

C322

C321

C52

R30

1

Q3

R29

R26

R28

C50

1stLO

C41

R25

C48

LPF

C183

L1

2

C44

L14

C49

C324

C323

C40

D10

L11

C45

R21

R23

C35

C36

D9

C38

R20

C39

Two-staged

2ND IF AND FM DEMODULATOR CIRCUITS

The 2nd IF circuits consist of 2nd mixer, 2nd IF filter, 2nd
IF amplifier. And it converts the 1st IF signal into the 2nd
IF signal, then filters to remove unwanted signals and
amplifi es. IF IC "TA31136FNG" contains whole of the 2nd IF
circuits and FM demodulator circuit too.

The 1st IF signal is applied to the IF IC, and converted into
the 2nd IF signal, by being mixed with the 2nd LO signal
(from the X2 via the PLL IC (IC4, pins 1, 2) and tripler), at
internal 2nd mixer. The converted 2nd IF signal is filtered by
external 2nd IF filter (ceramic filter), and saturation-amplified
by internal 2nd IF AMP. The amplified 2nd IF signal is
F

M-demodulated by the quadrature detector.

The demodulated AF signals "SQLI" are applied to the RX
AF circuits.

• 2ND IF AND FM DEMODULATOR CIRCUITS

R115

R116

C185

C166

C165

L35

Q19

C162

C163

C164

L33

2nd IF

FILTER

FI2

C169

C167

IO

C168

C71

Ref.Freq.

C161

TRIPLER

(×3)

R46

R39

R44

C69

R40

C70

NOISE

FILTER

IF IC

IC1

1

OSCIN

2

OSCOUT

3

M IXOUT

4

VCC

5

IFIN

6

DEC

7

FILOUT

8

FILIN

TA31136FNG

R45

C68

R42

SQLO

IF IC (TA31136FNG) BLOCK DIAGRAM

FM

Detector

9

8

73

5

Noise
Filter

2nd IF

AMP

1110

Noise
AMP

RSSI

Noise Det.

12

QUADRATURE

DETECTOR

MIXIN

N-REC
N-DET

IFOUT

AFOUT

SQLI

RSSI

QUAD

C67

16
15

GND

14
13
12
11
10
9

R43

C188

C66

C75

1stIF

C63

R36

X1

R38

C61

C62

C65

NOIS

RSSI

2

2nd
Mixer

14

16

RX AF CIRCUITS

The RX AF circuits consist of AF filters, AF amplifier (AF
AMP), AF power amplifier, etc., and amplify, filter the AF
signals FM-demodulated by the FM IF IC.

This transceiver employs the base band IC for audio signal
processing for both transmit and receive. The base band
IC is an audio processor and composed of RF AMPlifier,
compressor, expander, scrambler, etc. in its package.

The demodulated AF signals from the IF IC are applied to
the base band IC (IC10, pin 23). The applied AF signals are
amplified at the amplifier section and level adjusted at the
volume controller section, then suppressed unwanted 3 kHz
and higher audio signals at LPF. The filtered AF signals are
applied (bypassed) the TX/RX HPF, scrambler, de-emphasis
sections in sequence.

• BASE BAND IC BLOCK DIAGRAM

Com-

pressor

TXA1

VR1

(HPF)

3 TXIN

Pre-

emphasis

TX/RX

HPF

The TX/RX HPF filters out 250 Hz and lower audio signals,
and the de-emphasis circuit obtains –6 dB/oct of audio
characteristics. The expander expands the compressed
audio signals and also noise reduction function is provided.

The AF signals are then level adjusted at the volume
controller section and amplified at the amplifier section, then
output from pin 20 (IC10).

The processed AF signals from the base band IC (IC10) are
applied to the FRONT UNIT via J1 (MAIN) and J401
(FRONT).

The AF signals from the MAIN UNIT

"SIGNAL" are passed
through the AF mute SW, LPF and variable register (VR
UNIT) for audio level adjustment, then applied to the AF
power AMP. The amplified AF signals

"AFO" are applied to
the internal speaker, or external speaker via the [SP MIC]
jack (MP701; CHASSIS).

BASE BAND IC (IC10)

SMF

7 MOD

Scrambler/

De-scrambler

Limiter Splatter VR2

23 RXIN

21 SDEC

RXA1

VR3

(HPF)

RX

LPF

4 - 2

De-

emphasis

Expander

VR4

RXA2

18

19

20

SIGNAL

SQUELCH CIRCUITS

• NOISE SQUELCH

The noise squelch cuts off the AF output signals when
no RF signals are received. Extracting noise components
(approx. 30 kHz signals) in the demodulated AF signals,
the squelch circuit turns the AF power amplifier and AF
switches ON and OFF.

A portion of FM-demodulated AF signal from the IF IC is
adjusted its level (=squelch threshold level) by DAC (D/A
converter; IC6, pins 1, 2), then passed through the noise
filter (M: IC1, pins 7, 8 and R42, 44–46, C68–70) to extract
the noise components (approx. 30 kHz signals) only. The
noise components are rectified to be
pulse-type signal

by noise detector to produce DC voltage
corresponding to the noise level "NOIS". Then the DC
voltage is applied to the CPU (IC401, pin 41) and compared
with the reference level preset in the CPU.

If the CPU interpretes that the noise level is higher than
preset one, the CPU sets the "AFON" signal to "High" to
turn the AF power AMP controller OFF, and the AF mute
SW is turned OFF simultaneously. Thus closing the squelch
is accomplished.

To RX AF circuits

From IF IC (Pin16)

NOISE SQUELCH DIAGRAM

1 2

DAC

Fc=30 kHz

Noise
AMP

Active filter

converted into the

Rectify

“NOIS”

Noise detector

• TONE SQUELCH

The tone squelch connects the RX AF line and activates
the AF power amplifier to emit the AF signals only when
receiving a signal which contains the tone frequency
matched with preset in the CPU. Detecting signal in the
demodulated AF signals, the tone squelch circuit turns the
AF power amplifier and AF switches ON and OFF.

<CTCSS/DTCS>
A portion of FM-demodulated AF signals from the FM IF
IC are passed through the tone filter (M: Q6, pins 5, 6) to
remove unwanted voice siganls. The filtered tone signals
are applied to the CPU (IC401, pin 44).

<2/5 TONE, DTMF>
A portion of FM-demodulated AF signals are output from
the baseband IC (M: IC10, pin 21), and passed through
the tone filter (M: R136, C220) to remove unwanted voice
siganls. The filtered tone signals are applied to the CPU
(IC401, pin 43).

The CPU compars the tone frequency/code preset in the
CPU, and if the applied tone frequency/code is matched to
preset one, the CPU controls the AF power AMP and AF
mute SW as same as "NOISE SQUELCH."

4-2 TRANSMITTER CIRCUITS

TX AF CIRCUITS

The TX AF circuits consist of microphone amplifier (MIC
AMP) and AF fi lters. The AF fi lter cuts off the signals except
voice signals (300 Hz or lower and 3 kHz or higher).

The audio signals from the internal microphone (MIC
signals) are passed through MIC mute SW and amplifi ed by
two MIC AMPs (#1 and #2).

• TX AF CIRCUITS

AFO

R401

C404

AUDIO

VR UNIT

SP401

W601

4
3
2
1

LEVEL

ADJUST

J402

56

1
2
3
4

W401

Q413

R445

W402

BPMAX

R446

PWON

C502

C503

C426

C496

C435

MC401

R434

R517

R518

C437

R519

R520

R402

R521

R522

R541

C423

C401

R430

C425

R432

13

14

12

IC403

LPF

C513

R537

The MIC signals from the external microphone "EXMIC” are
applied to the FRONT UNIT via [SP MIC] jack, and amplifi ed
by MIC AMP (#2).

The amplified MIC signals "MIC” are applied to the MAIN
UNIT via J401(FRONT UNIT) and J1 (MAIN UNIT).

The MIC signals from the FRONT UNIT are applied to the
baseband IC (IC10, pin 3) and processed.

5

8

7

6

IC406

MUTE SW

1

2

3

4

C497

R433

C482

C512

Q415

R538

AF POWER AMP

IC405
20
19
18
17
16
15
14
13
12
11

VCC1
NC
OUT1­IN1­IN1+
IN2+
IN2­OUT2­NC
VCC2

R523

R539

GND1

OUT1 +

MODE
SVRR

SELECT

OUT2 +

GND2

NC

NC

NC

MIC/AF

MIC AMP

R513

R408

C481

R535

1
2
3
4
5
6
7
8
9
10

C510

#1

2

3

C498

R511

R429

R524

IC407

Q406

1

R426

R428

R525

EXMIC

R406

R405

R512

Q401, Q402

MIC AMP

C407

R407

6

5

C406

C405

C421

AF POWER AMP

CONTROLLER

#2

IC407

AFON

7

DUSE

BEEP

MIC

SIGNAL

AFON

VCC

SPON

4 - 3

VCC

The applied MIC signals are amplified at the amplifier
(TXA1), and level adjusted at the volume controller (VR1).
The level adjusted MIC signals are applied (bypassed) the
compressor section, pre-emphasis section, TX/RX HPF,
de-scrambler, limiter, splatter, in sequence, then applied to
another volume controller.

The compressor compresses the MIC signals to provide
high S/N ratio for receive side, and the pre-emphasis obtains
+6 dB/oct audio characteristics. The TX/RX HPF fi lters out
250 Hz and lower audio signals, the limiter limits its level and
the splatter fi lters out 3 kHz and higher audio signals. The
filtered MIC signals are level adjusted at another volume
controller (VR2), and then output from pin 7 via smoothing
fi lter (SMF).

The output MIC signals are passed through the FM/PM
SW (IC11, pins 6, 1) and LPF (IC5, pins 2, 1) then applied
to the DAC (D/A Converter; IC6, pin 4) and level-adjusted
(deviation adjustment). The level-adjusted MIC siganls are
output from pin 3, then applied to the modulation circuit as
the modulation signals

"MOD” via buffer (IC5, pins 6, 7).

<CTCSS/DTCS>
CTCSS/DTCS signals ("CEN0"–"CEN2") are generated by

the CPU (F: IC401, pins 79–81) and converted its wave
form by R461–R463 (F), then passed through the LPF (F:
IC403, pins 3, 1). The fi ltered CTCSS/DTCS signals are
then level-adjusted by DAC (M: IC6, pins 9, 10) and applied
to the AF mixer (M: IC5, pin 2) to be mixed with MIC signals,
then applied to the TX VCO as the modulation signals. The

CTCSS/DTCS signals are also applied to the reference
signal oscillator (M; X2) too, via the buffer (M: IC16, pins 2, 1).

<2/5 TONE, DTMF>
2/5 tone and DTMF signals are ("SEN0"–"SEN3") are
generated by the CPU (F: IC401, pins 72–75) and converted

its wave form by R471–R474 (F), then passed through
the two-staged LPF (F: IC403, pins 5, 7 and pins 10, 8).
The filtered 2/5 tone and DTMF signals are applied to the

AF mixer (M: IC5, pin 2) to be mixed with MIC signals.
The mixed signals are then applied to the TX VCO as the
modulation signals). The CTCSS/DTCS signals are also

applied to the reference signal oscillator (M: X2, pin 1) too,
via the buffer (M: IC16, pins 2, 1).

MODULATION CIRCUIT

The modulation circuit FM-modulates the VCO oscillating
signal with the modulation signals from the TX AF circuits.

• VOICE SIGNAL

The buffer-amplified AF signals are applied to the variable
capacitor (VD) to change its reactance for FM modulation.

• TONE SIGNALS

Tone signals are generated in the CPU and applied to the
both of the VCO and reference frequency oscillator to be
modulated.

• MODULATION CIRCUIT AND TX/RX VCOs

RIPPLE

C148

C190

C191

L28

Freq.

adjust

TX VCO

C195

L27

Freq.

adjust

Q17

FILTER

RX VCO

D1 9

C194

C192

C193

C127

D2 0

L37

L39

Modulation

C124

D17

L24

D1 6

L38

L26

C139

R79

R85

C126

C134

D22

L42

C203

L25

C129

D18

R86

L43

LVA

Q14

R81

C114

C115

C119

R84

R83

C123

R82

C133

C121

D21

C122

R98

C137

LV

MOD

The modulated VCO output is buffer-amplifi ed by two buffers
(Q12, Q10), and applied to the pre-driver via TX/RX SW.

T5V

C110

Q13

from VCO

C120

EP1

C116

C104

C118

R88

C117

C113

Q12

BUFFER

R87

Q15

5

R78

R77

VCO

SW

C109

R76

R75

C105

C102

C103

1

2

34

L41

R72

Q11

R80

Q16

C111

R5V

C107

R71

BUFFERBUFFER

C205

To PLL

R70

L21

C100

Q10

1stLO

C108

C99

TX/RX

SW

D14

D15

R69

LPF

L14

C49

C323

0.01

0.001

TX

R68

R67

C93

C183

C324

R65

C95

4 - 4

TRANSMIT AMPLIFIERS

0

The transmit amplifiers consist several RF amplifiers (pre­driver, driver, power), and amplify the TX VCO output to the
transmit output level.

The TX VCO output is applied to the pre-drive amplifi er

via

the TX/RX switch. The amplified TX signal is amplified by
drive amplifier, then power-amplified by the power amplifier
to obtain 5 W (max.) of TX output power.

The power-amplified TX signal is passed through the LPFs
(as a harmonic filter), ANT SW (TX), and another LPF, then
applied to the antenna.

• TRANSMIT AMPLIFIERS AND APC CIRCUIT

L20

R68

C108

TX/RX

SW

0

R69

LPF

C49

C323

0.01

C99

0.001

R67

D14

C93

TX

D15

R65

C183

L14

C95

C324

R61

Pre-

DRIVE

R63

C106

C96

C97

DRIVE

L19

AMP

C92

Q9

C90

R62

R59

C91

C94

C292

R58

EP2

C81

C85

L18

Q8

C87

R57

C89

C88

C98

C82

C86

Q7

R53

R54

R55

C77

C76

R9

R10

C73

APC CIRCUIT

APC CIRCUIT

The APC (Automatic Power Control) circuit stabilizes
transmit output power to prevent transmit output power level
change which is caused by load mismatching or heat effect,
etc. The APC circuit also selects transmit output power from
high, middle and low power.

A portion of the TX signal is rectifi ed by the power detector
to be converted into DC voltage which is in proportion to the
transmit output power level. The detected voltage is applied
to the comparator. The transmit power setting voltage is ap­plied to another input terminal as the reference voltage.

The comparator compares the detected voltage and refer­ence voltage, and the difference of voltage is output. The
output voltage controls the bias of the TX amplifiers to re­duce/increase the gain of these amplifi ers for stable transmit
output power.

The change of transmit power is carried out by changing
reference voltage.

R52

C291

PWR

L17

2681

C84

0.1

AMP

L16

MP 1

C83

R3

4

LPF

L4

C302

C12

C13

C79

R8

IC2

5

3

1

2

LPF

R1

C11

C308

C15

D25

L3

C9

TX POWER

DETECTOR

R2

C10

D1

COMPARATOR

R5

R7

R6

C80

C74

T2

R4

C101

C8

C78

C72

L15

C7

ANT SW

(TX)

TMUT

D2

C6

C5

LPF

L2

C4

To ANT

L1

C2

C1

C3

R51

4 - 5

4-3 FREQUENCY SYNTHESIZER CIRCUITS

3

1

5

VCOs

A VCO is an oscillator which its oscillation frequency is
determined by the applied voltage. This transceiver has
two VCOs; RX VCO and TX VCO. The RX VCO generates
the 1st LO signals for the 1st IF produce, and TX VCO
generates TX signal. The VCO SW toggles these VCOs.

• RX VCO

The RX VCO oscillates 89.65 to 127.65 MHz LO signals.
The generated 1st LO signals are applied to the 1st mixer
(Q3) via two buffers (Q12 and Q10) and LPF.

RIPPLE

C148

C190

C191

L28

Freq.

adjust

TX VCO

C195

L27

Freq.

adjust

Q17

FILTER

RX VCO

D1 9

C194

C192

C193

C127

D2 0

L37

L39

Modulation

C124

D17

L24

D1 6

L38

L26

C110

C139

R79

R85

C126

C134

D22

L42

C203

L25

C129

D18

R86

L43

LVA

Q14

R81

C114

C115

R84

C123

C133

D21

C121

C122

R82

C119

R83

C120

Q13

R98

C137

LV

MOD

• TX VCO

The TX VCO oscillates 136 to 174 MHz TX signal. The
generated TX signal is applied to the pre-driver (one of TX
AMPs) via the TX/RX SW.

A portion of the VCO output is applied to the PLL IC via the
buffer (Q11).

• VCOs AND BUFFERS

T5V

R68

EP1

C116

C104

C118

C117

C113

Q12

BUFFER

R87

Q15

5

R88

R78

R77

VCO

SW

C109

R76

R75

C105

C102

Q11

C103

R80

1

2

Q16

34

C107

L41

R71

R72

Q10

BUFFERBUFFER

C205

C111

To PLL

R5V

C108

0.01

R70

C99

0.001

TX/RX

L21

SW

D14

C100

TX

D15

R69

LPF

L14

C49

C323

1stLO

R67

C183

C324

C93

R61

Pre-

DRIVE

R65

R63

C95

C106

C96

L19

C92

Q9

C90

R62

R59

C94

PLL (Phase Locked Loop) CIRCUIT

The PLL circuit provides stable oscillation for both of the
transmit and 1st LO frequencies (for receive). By comparing
the feed backed VCO output and the reference frequency
signal, the oscillating frequency is stabilized.

The PLL output frequency is controlled by the serial data
including divide ratio from the CPU.

A portion of VCO output from the buffer (Q11) is applied
to the PLL IC via LPF. The applied VCO output is divided
according to the serial data including divide ratio from
the CPU, at the prescaler and programmable divider. In
the same way, the reference frequency signal from the
reference frequency signal oscillator is applied to the PLL
IC and divide so that these are the same frequency.

• PLL CIRCUITS

R103

47K

C211

BAL

REF

LVIN

S5V

UNLK

SCK

SO
PLST

R104

C154

R105

C151

C153

2

3

Ref. Freq.

C213

OSCILLATOR

ACZ1005Y

C155

R94

D24

R117

R118

C152

IC16

1

EP6

9
10
11
12
13
14
15
16

X2

1

VCON

2

GND3OUT

CR-783

C140

R93

PLL IC

MB15A02PFV1

CLOCK

DATA
LE
FC
NC
FOUT
P
B

FIN

GND

VCC

OSCOUT

OSCIN

IC4

PLL

LD

DO

VP

E

C1

R108

CP1

C141

C156

R97

C158

4

VCC

C157

LOOP

FILTER

8
7
6
5
4
3
2
1

C209

R109

C143

C208

0.001

LPF

R10

R100

L32

C149

C207

C1

Q18

R89

R96

C147

3.3 MSVA

R187

C206

R95

The frequency-matched signals are applied to the phase
comparator and phase-compared. The resulted phase
difference is detected as a phase-type signal, and level­adjusted at the charge pump then output. The output pulse
type signal is passed through the loop filter to be converted
into the DC voltage (=Lock Voltage).

Applying the lock voltage to the variable capacitors
(VD) which composes a part of the resonator of VCO,
the capasitance of VDs changes corresponding to the
applied lock voltage. This causes the change of resonation
frequency that determines the VCO oscillating frequency to
keep the VCO frequency constant.

When the oscillation frequency drifts, its phase changes
from that of the reference frequency, causing a lock voltage
change to compensate for the drift in the VCO oscillating
frequency.

C137

C148

RX VCO

L26

R92

R91

C132

R90

C190

L28

Freq.

C191

C127

D2 0

L37

D1 9

L39

adjust

LV

C146

R110

C150

C145

C138

TX VCO

C195

L27

Freq.

adjust

MOD

C194

Modulation

D17

C192

C193

D1 6

L38

L24

C124

C126

C134

D22

L42

C203

L25

C129

D18

R86

R85

LVA

R79

R81

C114

C115

R84

C123

C133

D21

L43

4 - 6

Q14

C121

C122

C117

C116

C104

C120

C119

R83

R82

Q13

from VCO

C113

C118

R87

R

4-4 OTHER CIRCUITS

VIBERATION MOTOR CIRCUIT

(except [A], [D], [G], [J])

MF1 is a vibration motor. When the matched RX code signal
is received, MF1 rotates to produce viberation.

In vibration mode, and when the transceiver is called, "VIB"
signal from the expander (IC12, pin 6) turns to "High(=VCC
level)" and motor driver (Q30, Q31) is activated to rotate the
vibration motor (MF1).

• MOTOR DRIVER

VCC

Q31

M

MF1

C317

C316

Q30

C315

R201

R202

R203

VIB

C318

AGC (Automatic Gain Controller) CIRCUIT

The AGC circuit effectively reduces the RX signal level if
the signal is strong, and raises it when it is weaker. The
AGC circuit detects the overall strength of the signal and
automatically adjusting the gain of the RF AMP to maintain
an approximately constant average level of the received
signals.

RSSI signal which is in proportion to the RX signal level is
applied to the gate terminal of AGC line driver. The driver
controls the voltage which supplied to the RF AMP to
control the gain of RF AMP.

• AGC CIRCUIT

R22

R5V

C184

R172

R18

C186

C31

R19

C30

R12

R213

C29

R15

L8

R17

C35

C36

L9

RF

AMP

C37

Q2

D9

C38

C32

R20

C39

42

C33

R16

R171

C28

Q1

R173

AGC LINE

DRIVER

R174

D23

R175

Two-staged

C23

TUNED BPF

C22

D4

C26

R13

C25

6P

D8

L7

C20

R11

R14

4

4-5 VOLTAGE BLOCK DIAGRAM

Voltage from the battery pack is routed to whole of the transceiver via switches and regulators.

Q21

T5

REG

Q22

R5

REG

FRONT UNIT

T5V

Pre-drive AMP (Q9), APC AMP (IC2), etc.

R5V

IF IC (IC1), 1st IF AMP (Q4), 1st mixer (Q3), RF AMP (Q2), etc.

S5V

PLL IC (IC4), VCOs, etc.

+5V

Base-band IC (IC10), DAC (IC6), etc.

CPU5

CPU (IC401), EEPROM (IC409), expander (IC410)

2

FRONT UNIT

BATTERY PACK

T5C

R5C

Q25

Q24

Q23

S5C

VCC

MAIN UNITVR UNIT

S5
REG

+5

REG

IC9

1

PWR

R601

Q26

POWER

SW

F1

4 - 7