ICOM F24, F25 Service Manual

SERVICE
MANUAL

UHF TRANSCEIVERS

INTRODUCTION

This s e r v i c e manual d e s c r i b e s t h e latest s e r v i c e
information for the

IC-F24/IC-F24S/IC-F25/IC-F25S UHF

TRANSCEIVER

at the time of publication.

DANGER

NEVER connect the transceiver to an AC outlet or to a DC

power supply that uses more than 8 V. Such a connection
could cause a fire or electric hazard.

DO NOT expose the transceiver to rain, snow or any liquids.

DO NOT reverse the polarities of the power supply when

connecting the transceiver.

DO NOT apply an RF signal of more than 20 dBm (100mW)
to the antenna connector. This could damage the trans­ceiver's front end.

ORDERING PARTS

Be sure to include the following four points when ordering
replacement parts:

1. 10-digit order numbers

2. Component part number and name

3. Equipment model name and unit name

4. Quantity required

<SAMPLE ORDER>

2260002840 Switch SKHLLFA010 IC-F24 Main unit 5 pieces
8930063350 Lens 2775 Lens IC-F24 Chassis 10 pieces

Addresses are provided on the inside back cover for your
convenience.

1. Make sure the problem is internal before disassembling the transceiver.

2. DO NOT open the transceiver until the transceiver is disconnected from its power source.

3. DO NOT force any of the variable components. Turn them slowly and smoothly.

4. DO NOT short any circuits or electronic parts. An insulated turning tool MUST be used for all adjustments.

5. DO NOT keep power ON for a long time when the transceiver is defective.

6. DO NOT transmit power into a signal generator or a sweep generator.

7. ALWAYS connect a 30 dB to 40 dB attenuator between the transceiver and a deviation meter or spectrum analyzer when
using such test equipment.

8. READ the instructions of test equipment thoroughly before connecting equipment to the transceiver.

To upgrade quality, all electrical or mechanical parts and
internal circuits are subject to change without notice or
obligation.

Icom, Icom Inc. and are registered trademarks of Icom Incorporated (Japan) in the United States, the United Kingdom,
Germany, France, Spain, Russia and/or other countries.

MODEL VERSION SYMBOL CH FREQUENCY

IC–F24

USA–02 US2 16 400–470 MHz

USA–03 US3 16 450–512 MHz
GEN–02 GE2 16 450–470 MHz
GEN–03 GE3 16 450–520 MHz

IC–F24S

USA–02 US2S 2 400–470 MHz

USA–03 US3S 2 450–512 MHz
GEN–02 GE2 2 400–470 MHz
GEN–03 GE3 2 450–520 MHz

IC–F25 EUR–02 EU2 16 400–470 MHz

IC–F25S EUR–02 EU2S 2 400–470 MHz

REPAIR NOTES

TABLE OF CONTENTS

SECTION 1 SPECIFICATIONS

SECTION 2 INSIDE VIEWS

SECTION 3 DISASSEMBLY INSTRUCTIONS

SECTION 4 CIRCUIT DESCRIPITON

4-1 RECEIVER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4-2 TRANSMITTER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4-3 PLL CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4-4 OTHER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4-5 POWER SUPPLY CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4-6 PORT ALLOCATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

SECTION 5 ADJUSTMENT PROCEDURES

5-1 PREPARATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5-2 CONFIGURATION LISTS FOR ADJUSTMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5-3 SOFTWARE ADJUSTMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

SECTION 6 PARTS LIST

SECTION 7 MECHANICAL PARTS AND DISASSEMBLY

SECTION 8 SEMI-CONDUCTOR INFORMATION

SECTION 9 BOARD LAYOUTS

9-1 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9-2 ANT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9-3 CONNECT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

SECTION 10 BLOCK DIAGRAM

SECTION 11 VOLTAGE DIAGRAM

11-1 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

SECTION 1 SPECIFICATIONS

GENERAL



• Frequency coverage : 400–470 MHz [USA–02], [GEN–02], [EUR]
450–512 MHz [USA–03]
450–520 MHz [GEN–03]

• Type of emission :

• Number of conventional channels : 2 ch (IC-F24S/F25S), 16 ch (IC-F24/F25)

• Antenna impedance : 50 Ω (nominal)

• Operating temperature range : –30˚C to +60˚C (–22˚F to +140˚F) [USA], [GEN]

• Power supply requirement : 7.2 V DC nominal (negative ground)

• Current drain (at 7.2 V DC ; approx.) :

VERSION WIDE MIDDLE NARROW

[USA], [GEN]

[EUR]

–25˚C to +55˚C [EUR]

RECEIVING TRANSMITTING

Stand-by Max. audio

75 mA 300 mA 1.6 A 0.8 A

16K0F3E (25.0 kHz)

N/A

14K0F3E (20.0 kHz) 8K50F3E (12.5 kHz)

High (at 4 W) Low (at 1 W)

11K0F3E (12.5 kHz)

• Dimensions (projections not included) : 53(W)×120(H)×38(D) mm; 2

• Weight (Including BP-231) : Approximately 260 g (9

TRANSMITTER



• Output power (at 7.2 V DC) : 4 W

• Modulation : Variable reactance frequency modulation

• Maximum permissible deviation : ±5.0 kHz (Wide), ±4.0 kHz (Middle), ±2.5 kHz (Narrow)

• Frequency error : ±2.5 ppm

• Spurious emissions : 70 dB (min.) [USA], [GEN]

• Adjacent channel power : 70 dB min. (75 dB typical) for Wide
70 dB min. (73 dB typical) for Middle

60 dB min. (68 dB typical) for Narrow

• Audio harmonic distortion : 3% typical (1 kHz, 40% deviation)

• Hum and Noise ([USA], [GEN]) : 40 dB min. (46 dB typical) for Wide

• Residual modulation ([EUR] only) : 45 dB min. (55 dB typical) for Wide

(with CCITT filter) 43 dB min. (53 dB typical) for Middle
40 dB min. (50 dB typical) for Narrow

• Limiting charact of modulator : 60–100% of maximum deviation

• Microphone impedance : 2.2 k



• Receive system : Double conversion superheterodyne system

• Intermediate frequencies : 1st IF: 46.35 MHz, 2nd IF: 450 kHz

• Sensitivity : 0.25 µV (–119 dBm) typical at 12 dB SINAD [USA], [GEN]

• Squelch sensitivity (at threshold) : 0.25 µV typical [USA], [GEN]

• Adjacent channel selectivity : 70 dB min. (75 dB typical) for Wide

70 dB min. (73 dB typical) for Middle
60 dB min. (65 dB typical) for Narrow

• Spurious response : 70 dB min.

• Intermodulation rejection ratio : 70 dB min. (74 dB typical) [USA], [GEN]

• Hum and Noise ([USA], [GEN] only) : 40 dB min. (45 dB typical) for Wide

• Hum and Noise ([EUR] only) : 45 dB min. (55 dB typical) for Wide

• Audio output power : 0.5 W typical at 5% distortion with an 8 Ω load

• Output impedance (Audio) : 8

(without CCITT filter) 34 dB min. (40 dB typical) for Narrow

RECEIVER

(without CCITT filter) 34 dB min. (40 dB typical) for Narrow

(with CCITT filter) 43 dB min. (53 dB typical) for Middle
40 dB min. (50 dB typical) for Narrow

0.25 µW (≤1 GHz), 1.0 µW (>1 GHz) [EUR]

Ω

–4 dBµV (–111 dBm) emf typical at 20 dB SINAD

–4 dBµV emf typical [EUR]

65 dB min. (67 dB typical) [EUR]

Ω

3

⁄32(W)×423⁄32(H)×11⁄2(D) in

3

⁄16 oz)

[EUR]

Specifications are measured in accordance with EIA-152-C/204D, TIA-603 or EN 300 086.

All stated specifications are subject to change without notice or obligation.

1 - 1

SECTION 2 INSIDE VIEWS

•

MAIN UNIT

2 - 1

+5 Regulator
(IC9: NJM2870)

AF amplifier
(IC12: TA7368F)

D/A converter
(IC8: M62363FP)

R5 Regulator
(Q22: 2SA1577)

CPU
(IC13: HD6433687A91FP)

S5 Regulator
Q23: 2SB1132
Q24: XP6501
Q25: UNR9113J

Crystal filter
(FI1: FL-335)

FM IF IC
(IC1: TA31136FN)

IF amplifier
(Q4: 2SC4215)

EEPROM
(IC15: BR24L16FV)

Power amplifier
(Q7: RD07MVS1)

T5 Regulator
(Q21: 2SA1577)

PLL IC
(IC4: MB15A02)

Pre-drive
(Q5: 2SC3356)

APC amplifier
(IC2: TC75S51F)

VCO circuit

TOP VIEW BOTTOM VIEW

Drive amplifier
(Q8: RD01MUS1)

SECTION 3 DISASSEMBLY INSTRUCTIONS

3 - 1

Chassis unit

D

A

*B

C

E

*: IC-F24/F25 only

Shield cover

Earth plate

Main unit

K

M

M

N

M

F

G

Chassis unit

N

L

I

H

•

REMOVING THE CHASSIS UNIT

1 Unscrew 1 nut A, and remove 2 knobs *B, C.
2 Unscrew 2 screws D.
3 Take off the chassis unit in the direction of the arrow.
4 Unplug the connector E from the chassis unit.

•

REMOVING THE MAIN UNIT (IC-F24/F25)

1 Unscrew 2 nuts F, and remove the top plate G.
2 Unsolder 1 point H, and remove the earth plate.
3 Unsolder 5 points I, and remove the shield cover.
4 Unscrew 2 screws K, and remove the side plate L.
5 Unscrew 7 screws M.
6 Unsolder 4 points N, and take off the main unit in the

direction of the arrow.

Main unit

Chassis unit

Shield cover Earth plate

a

a

K

L

M

M

N

M

I

N

G

F

H

•

REMOVING THE MAIN UNIT (IC-F24S/F25S)

1 Remove the switch connector O.
2 Unsolder 2 nuts F, and remove the top plate G.
3 Unsolder 1 point H, and remove the earth plate.
4 Unsolder 5 points J, and remove the shield cover.
5 Unscrew 2 screws K, and remove the side plate L.
6 Unscrew 7 screws M.
7 Unsolder 4 points N, and take off the main unit in the

direction of the arrow.

SECTION 4 CIRCUIT DESCRIPTION

4-1 RECEIVER CIRCUITS

4-1-1 ANTENNA SWITCHING CIRCUIT

The antenna switching circuit functions as a low-pass filter
while receiving and a resonator circuit while transmitting.
This circuit does not allow transmit signals to enter the
receiver circuits.

Received signals enter the antenna connector (CHASSIS;
J1) and pass through the low-pass filter (L1, L2, L45, C1–C6,

C175). The filtered signals are passed through the
antenna switching circuit (D2, D5, L5) and then applied to
the RF circuit.

4-1-2 RF CIRCUIT

The RF circuit amplifies signals within the range of fre­quency coverage and filters out-of-band signals.

The signals from the antenna switching circuit pass through
the bandpass filter (D3, D4, D7, D8, L7, L8, C21, C23,
C24). The filtered signals are amplified at the RF amplifier
(Q2) and then passed through the another bandpass filter
(D9, D10, C39, C40, C45) to suppress unwanted signals.
The filtered signals are applied to the 1st mixer circuit.

D3, D4, D7–D10 employ varactor diodes, that are con­trolled by the CPU via the D/A converter (IC8), to track
the bandpass filter. These varactor diodes tune the center
frequency of an RF passband for wide bandwidth receiving
and good image response rejection.

4-1-3 1ST MIXER AND 1ST IF CIRCUITS

The 1st mixer circuit converts the received signal into fixed
frequency of the 1st IF signal with the PLL output fre­quency. By changing the PLL frequency, only the desired
frequency passes through a crystal filter at the next stage
of the 1st mixer.

1

⁄

λ type

4

The RF signals from the bandpass filter are mixed with the
1st LO signals, where come from the RX VCO circuit via
the BPF (L12, L38, C49, C304, C305), at the 1st mixer cir­cuit (Q3) to produce a 46.35 MHz 1st IF signal. The 1st IF
signal is passed through a monolithic filter (FI1) in order to
obtain selection capability and to pass only the desired sig­nal. The filtered signal is applied to the 2nd IF circuit after
being amplified at the 1st IF amplifier (Q4).

4-1-4 2ND IF AND DEMODULATOR CIRCUITS

The 2nd mixer circuit converts the 1st IF signal into a 2nd
IF signal. The double-conversion superheterodyne system
(which converts receive signals twice) improves the image
rejection ratio and obtains stable receiver gain.

The 1st IF signal from the IF amplifier (Q4) is applied to
the 2nd mixer section of the FM IF IC (IC1, pin 16), and
is mixed with the 2nd LO signal to be converted into a
450 kHz 2nd IF signal.

The FM IF IC (IC1) contains the 2nd mixer, 2nd local oscil­lator, limiter amplifier, quadrature detector, active filter and
noise amplifier circuits. The 2nd LO signal (45.9 MHz) is
produced at the PLL circuit by tripling it’s reference fre­quency (15.3 MHz).

The 2nd IF signal from the 2nd mixer (IC1, pin 3) passes
through the ceramic filter (FI2) to remove unwanted het­erodyned frequencies. It is then amplified at the limiter
amplifier section (IC1, pin 5) and applied to the quadrature
detector section (IC1, pins 10, 11) to demodulate the 2nd
IF signal into AF signals.

The demodulated AF signals are output from pin 9 (IC1) as
“DET” signal, and are then applied to the AF circuit.

• 2ND IF AND DEMODULATOR CIRCUITS

87

Active
filter

"SQLC" signal from the
D/A converter IC
(IC8, pin 2)

To D/A converter IC
(IC8, pin 1)

AF signal "DET"
to the AF circuit

FM

detector

X1

Noise

AMP

Limiter
AMP

5

2nd IF filter
450 kHz

Noise

detector

RSSI

FI2

Noise

comparator

3

Mixer

45.9 MHz

2

Q19

×3

X2

15.3 MHz

IC1 TA31136FN

11109

12

"RSSI" signal to the CPU (IC13, pin 63)

R5V

13

"NOIS" signal to the CPU (IC13, pin 53)

16

1st IF signal from the IF amplifier (Q4)

4 - 1

4-1-5 AF AMPLIFIER CIRCUIT

The AF amplifier circuit amplifies the demodulated AF sig­nals to drive a speaker.

The AF signals from the FM IF IC (IC1, pin 9) pass through
the high-pass filter (IC6, pins 3 and 1) to suppress unwant­ed harmonic components. The signals pass through the
RX mute switch (Q34) which is controlled by “RMUT” sig­nal from the CPU (IC13, pin 56), and are then applied to
another high-pass filter (IC6, pins 13 and 14). The filtered
signals pass through the low-pass filter (IC6, pins 6 and

7) via the analog switch (IC10, pins 1 and 2). The signals
are applied to the analog switch (IC10, pin 10) again, and
are then applied to the AF power amplifier (IC12, pin 4) via
the AF volume (R226). The amplified AF signals are output
from pin 10, and are then applied to the internal speaker
which is connected to J1 via the [SP] jack (J3).

4-1-6 RECEIVE MUTE CIRCUITS

• NOISE SQUELCH

A squelch circuit cuts out AF signals when no RF signals
are received. By detecting noise components in the AF sig­nals, the squelch circuit switches the AF mute switch.

Some noise components in the AF signals from the FM IF
IC (IC1, pin 9) are applied to the D/A converter (IC8, pin

1) as “DET” signal, and are then output from pin 2. The
signals are applied to the active filter section in the FM IF
IC (IC1, pin 8). The active filter section filters and amplifies
noise components. The amplified signals are converted into
the pulse-type signals at the noise detector section and
output from pin 13 as “NOIS” signal.

The “NOIS” signal from the FM IF IC is applied to the CPU
(IC13, pin 53). Then the CPU analyzes the noise condition
and outputs the AF mute control signal from the CPU (pin

56) as “RMUT” signal from pin 56. The signal is applied to
the RX mute switch (Q34) to control the AF signal muting.

• CTCSS AND DTCS

The tone squelch circuit detects tone signals and opens the
squelch only when the receiving signal contains matched
subaudible tone (CTCSS or DTCS). When tone squelch is
in use, and a signal with a mismatched or no subaudible
tone is received, the tone squelch circuit mutes the AF sig­nals even when noise squelch is open.

A portion of the “DET” signals from the FM IF IC (IC1, pin

9) passes through the low-pass filter (IC7, pins 5 and 7)
to remove AF (voice) signals, and are then applied to the
amplifier (IC7, pin 3). The amplified signals are applied to
the CTCSS or DTCS decoder inside of the CPU (IC13, pin

60) as the “CDEC” signal. The CPU outputs AF mute con­trol signal from pin 56, and is then applied to the RX mute
switch (Q34) and analog switch (IC10, pins 12 and 13) to
control AF signals muting as “RMUT” signal.

4-2 TRANSMITTER CIRCUITS

4-2-1 MICROPHONE AMPLIFIER CIRCUIT

The microphone amplifier circuit amplifies audio signals
within +6 dB/octave pre-emphasis characteristics from the
microphone to a level needed for the modulation circuit.

The AF signals from the microphone are passed through
the microphone mute switch (Q35), and are then applied
to the amplifier (IC6, pins 9 and 8) via the high-pass filter
(IC6, pins 13 and 14). The amplified signals are applied to
the analog switch (IC10, pin 4), and outputs from pin 3. The
signals pass through the low-pass filter (IC6, pins 6 and 7),
then applied to the analog switch (IC10, pin 9) again and
output from pin 8.

The signals are applied to the D/A converter (IC8, pin 4).
The converted signals output from pin 3, and applied to the
modulation circuit (D18) as “MOD” signal.

• ANALOG SWITCHING CIRCUITS

"DET" AF signal
from FM IF IC (IC1, pin 9)

IC6 B

LPF

"CTCSS/DTCS" signal from
D/A conveter IC (IC8, pin 10)

"TONE" signal from CPU (IC13) via low-pass
filters (IC5 A / B pin 7)

2

3

9

10

8

IC8

D/A converter

IC6 A

HPF

Analog SW

(IC10)

MUTE

1

IC6 C

4

11

D18

FM mod.

Q34

RX

AMP

IC6 D

HPF

AF

volume

R226

to TX VCO circuit
(Q13, D17, D21)

IC12

AF
AMP

Q35

MIC

MUTE

Microphone

Speaker

4 - 2

4-2-2 MODULATION CIRCUITS

The modulation circuit modulates the VCO oscillating signal
(RF signal) using the audio signals from the microphone.

4-2-4 APC CIRCUITS

The bias current of the drive (Q8) and power (Q7) amplifiers
are controlled by the APC circuit.

The AF signals from the D/A converter (IC8, pin 3) change
the reactance of varactor diode (D18) to modulate the oscil­lated signal at the TX VCO circuit (Q13, D17, D21). The
modulated VCO signal is amplified at the buffer amplifiers
(Q10, Q12) and then applied to the drive amplifier circuit via
the T/R switch (D14).

The CTCSS/DTCS signals (“CENC0,” “CENC1,” “CENC2”)
from the CPU (IC13, pins 23–25) pass through the low-pass
filter (IC5, pins 12 and 14) via 3 registers (R191–R193) to
change its waveform. Then the signals are applied to the
D/A converter (IC8, pin 9). The output signals from the D/A
converter (IC8, pin 10) pass through the low-pass filter
(IC6, pins 6 and 7) to be mixed with “MOD” signal, and then
applied to the D/A converter again (IC8, pin 4) after passing
through the analog switch (IC10, pins 8 and 9).

4-2-3 TRANSMIT AMPLIFIER CIRCUITS

Transmit amplifiers amplify the TX VCO oscillating signal to
transmit power level.

The modulated RF signal from the TX VCO circuit passes
through the T/R switch (D14) and is amplified at the YGR
(Q9), pre-drive (Q5), drive (Q8), and power (Q7) amplifiers
to obtain 4 W (max.) of RF power (at 7.2 V DC).

The amplified signal passes through the low-pass filter (L4,
C11, C13, C16), antenna switch (D2), the low-pass filter (L1
–L3, C2–C5, C175, C176) and power detector (D1, D30),
then applied to the antenna connector (CHASSIS unit; J1).

The APC circuit (IC2, D1, D30) protects drive and power
amplifiers from the reflected signal, and selects output
power of HIGH, LOW2 or LOW1.

The power detector (D1, D30) detects transmit output power
and converts it into DC voltage. The DC voltage is at a mini­mum level when the antenna impedance is matched to 50 Ω,
and increased when mismatched.

The detected voltage is applied to the differential amplifier
(IC2, pin 3), and the “T2” signal from the D/A converter (IC8,
pin 23), controlled by the CPU (IC13), is applied to pin 1 for
reference. When antenna impedance is mismatched, the
detected voltage exceeds the power setting voltage. Then
the output voltage of the differential amplifier (IC2, pin 4)
controls the input current of the drive (Q8), and power (Q7)
amplifiers to reduce the output power.

• APC CIRCUITS

VCC
T5V

RF signal
from Buffer AMP

T2

TMUT

YGR
AMP

Q9

+

IC2

APC
AMP

–

Q5

Pre-drive
AMP

Q8
Drive
AMP

Powe r
AMP

Q7

LPF

ANT

SW

D2, D5

D30 D1

LPF

to ANT

Power DET

4 - 3

4-3 PLL CIRCUITS

4-3-1 PLL CIRCUIT

A PLL circuit provides stable oscillation for the transmit fre­quency and the receive 1st LO frequency. The PLL output
compares the phase of the divided VCO frequency to the
reference frequency. The PLL output frequency is controlled
by the divided ratio (N-data) of a programmable divider.

The PLL circuit contains the TX/RX VCO circuits (TX:
Q13, D17, D18, D21; RX: Q14, D16, D22). The oscillated
signal is amplified at the buffer amplifiers (Q11, Q12) and
then applied to the PLL IC (IC4, pin 8) after being passed
through the low-pass filter (L32, C206, C208).

The PLL IC (IC4) contains a prescaler, programmable
counter, programmable divider and phase detector, charge
pump, etc. The entered signal is divided at the prescaler and
programmable counter section by the N-data ratio from the
CPU. The divided signal is detected on phase at the phase
detector using the reference frequency. The phase detected
signal is applied to the charge pump to be converted into
the DC voltage, and output from pin 5. After passes through
the loop filter (C130, C138, C146, C147, R95–R97), the DC
voltage is applied to the TX/RX VCO as the lock voltage.

If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.

4-3-2 VCO CIRCUITS

The VCO circuit contains a separate RX VCO (Q14, D16,
D22) and TX VCO (Q13, D17, D21). The oscillated signal
is amplified at the buffer amplifiers (Q10, Q12) and is then
applied to the T/R switch (D14 for TX, D15 for RX). Then the
receive 1st LO (RX) signal is applied to the 1st mixer circuit
(Q3) and the transmit (TX) signal to the pre-drive amplifier
(Q9).

A portion of the signal from the buffer amplifier (Q12) is fed
back to the PLL IC (IC4, pin 8) via the buffer amplifier (Q11)
and low-pass filter (L32, C206, C208) as the comparison
signal.

• PLL CIRCUITS

"LVIN" signal to the CPU
(IC13, pin 64)

45.9 MHz 2nd LO
signal to the FM IF IC
(IC1, pin 2)

Buffer

Q18

Tripler

Q19

3

Loop

filter

Q14, D16, D22

Q13, D17, D21

Phase

5

detector

Programmable
divider

RX VCO

TX VCO

2

Charge

pump

Buffer
Q12

Programm­able counter

Shift register

Buffer
Q10

Buffer
Q11

IC4 MB15A02

Prescaler

1

X2

15.3 MHz

8

10
11

9

CLOCK
DATA
PLST

D15

D14

LPF

to 1st mixer circuit

to transmitter circuit

4 - 4