Icom DS-100 Service Manual
CLASS D/DSC TERMINAL
SERVICE
MANUAL
DS-100
INTRODUCTION
This service manual describes the latest service information
for the DS-100 CLASS D/DSC TERMINAL at the time of
publication
DANGER
NEVER connect the terminal unit to an AC outlet or to a DC
power supply that uses more than 16 V. This will ruin the
terminal unit.
DO NOT expose the terminal unit to rain, snow or any liquids.
DO NOT reverse the polarities of the power supply when
conecting the terminal unit.
DO NOT apply an RF signal of more than 20 dBm (100 mW)
to the antenna connector. This could damage the terminal
unit’s front end.
ORDERING PARTS
Be sure to include the following four points when ordering
replacement parts:
1. 10-digit order numbers
2. Component part number and name
3. Equipment model name and unit name
4. Quantity required
<SAMPLE ORDER>
1110003200 S.IC TA31136FN DS-100 MAIN UNIT 5 pieces
8810006050 Screw Icom screw E7 DS-100 Rear panel 10 pieces
Addresses are provided on the inside back cover for your
convenience.
REPAIR NOTES
1. Make sure a problem is internal before disassembling the
terminal unit.
2. DO NOT open the terminal unit until the terminal unit is
disconnected from its power source.
3. DO NOT force any of the variable components. Turn
them slowly and smoothly.
4. DO NOT short any circuits or electronic parts. An insulated tuning tool MUST be used for all adjustments.
5. DO NOT keep power ON for a long time when the termi-
nal unit is defective.
6. READ the instructions of test equipment thoroughly
before connecting equipment to the terminal unit.
To upgrade quality, any electrical or mechanical parts and
internal circuits are subject to change without notice or
obligation.
TABLE OF CONTENTS
SECTION 1 SPECIFICATIONS
SECTION 2 INSIDE VIEWS
SECTION 3 CIRCUIT DESCRIPTION
3 - 1 RECEIVER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 1
3 - 2 PLL CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 2
3 - 3 DSC CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 2
3 - 4 NMEA AND DATAINTERFACE CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 2
3 - 5 POWER SUPLLY CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 2
3 - 6 LOGIC CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 2
3 - 7 PORT ALLOCATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 2
SECTION 4 ADJUSTMENT PROCEDURES
4 - 1 PREPARATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 1
4 - 2 REFERENCE AND RECEIVER ADJUSTMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 2
SECTION 5 PARTS LIST
SECTION 6 MECHANICAL PARTS
SECTION 7 SEMI-CONDUCTOR INFORMATION
SECTION 8 BOARD LAYOUTS
8 - 1 LOGIC UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 1
8 - 2 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 3
SECTION 9 BLOCK DIAGRAM
SECTION 10 VOLTAGE DIAGRAM
10 - 1 LOGIC UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 1
10 - 2 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 2
1 - 1
SECTION 1 SPECIFICATIONS
‘‘
GENERAL
• Frequency coverage : 156.525 MHz (Ch 70) Rx only
• Mode : 16K0G2B
• Power supply requirement : 13.8 V DC (negative ground)
• Usable temperature range : –20˚C to +60˚C
• Current drain (at 13.8 V DC) : 1.0 A(approx.)
• Antenna impedance : 50 Ω (nominal)
• Output impedance (for testing) : 100 kΩ (nominal)
• Dimensions (projections not included) : 165(W)×110(H)×78(D) mm
• Weight : 1 kg (approx.)
‘‘
RECEIVER
• Receive system : Double conversion superheterodyne system
• Intermediate frequencies : 1st 21.7 MHz
2nd 450 kHz
• Sensitivity : -10 dBµ typical at 12 dB SINAD
• Adjacent channel selectivity : 70 dB
• Spurious response : 70 dB
• Intermodulation rejection ratio : 68 dB
• Hum and noise : –40 dB
Specifications are measured in accordance with EN301-025.
All stated specifications are subject to change without notice or obligation.
SECTION 2 INSIDE VIEWS
2 - 1
• MAIN UNIT
• LOGIC UNIT
Speaker
(SP1: PS1740P02)
FM IF IC
(IC1: TA31136FN)
2nd IF filter
(FI3: ALFY450E)
1st mixer
(Q2: 3SK166)
Crystal filter
(FI1, FI2: FL-310)
DSC decoder
(IC4: NJM2211M)
Reference Oscillator
(X2: CR-659 21.25 MHz)
LCD driver
IC6, IC7: HD61202UFS
IC8: HD61203UFS
VCO circuit
PLL IC
(IC2: µPD3140GS)
System clock
(X1: CR–610 7.9872 MHz)
CPU
(IC1: MB90F583BPFV-G)
Reset IC
(IC4: S-80928ANMP)
Inverter IC
(IC5: NJM2360M)
SECTION 3 CIRCUIT DESCRIPTION
3 - 1
3-1 RECEIVER CIRCUITS
3-1-1 RF AMPLIFER CIRCUIT (MAIN UNIT)
The RF circuit amplifies signals within the range of frequency coverage and filters out-of-band signals.
The signals from the antenna connector are amplified at the
RF amplifier (Q1) via the bandpass filter (L1, C3). The amplified signals are applied to the 1st mixer circuit (Q2) after outof-band signals are suppressed at the 3-stage of bandpass
filters (L2, L3, L4, C11, C14, C17).
3-1-2 1ST MIXER AND 1ST IF CIRCUITS
(MAIN UNIT)
The 1st mixer circuit converts the received signal into a fixed
frequency of the 1st IF signal with a PLL output frequency.
By changing the PLL frequency, only the desired frequency
will pass through a crystal filter at the next stage of the 1st
mixer.
The signals from the RF circuit are mixed at the 1st mixer
(Q2) with a 1st LO signal coming from the PLL circuit to produce a 21.7 MHz 1st IF signal.
The 1st IF signal is applied to the crystal filters (FI1, FI2) to
suppress out-of-band signals. The filtered 1st IF signal is
amplified at the 1st IF amplifier (Q3), then applied to the 2nd
mixer circuit (IC1, pin 16).
3-1-3 2ND IF AND DEMODULATOR CIRCUITS
(MAIN UNIT)
The 2nd mixer circuit converts the 1st IF signal into a 2nd IF
signal. Adouble conversion superheterodyne system (which
converts receive signals twice) improves the image rejection
ratio and obtains stable receiver gain.
The 1st IF signal from the IF amplifier is applied to the 2nd
mixer section of the FM IF IC (IC1, pin 16), and is mixed with
the 2nd LO signal to be converted into a 450 kHz 2nd IF signal.
The FM IF IC contains the 2nd mixer, limiter amplifier, quadrature detector and active filter circuits. A 2nd LO signal
(21.25 MHz) is produced at the PLL circuit using reference
frequency.
The 2nd IF signal from the 2nd mixer (IC1, pin 3) passes
through ceramic filter (FI3) to remove unwanted heterodyned frequencies. It is then amplified at the limiter amplifier (IC1, pin 5), and is applied to the quadrature detector
(IC1, pins 10, 11) to demodulate the 2nd IF signal into AF
signals.
3-1-4 SQUELCH CIRCUIT (MAIN UNIT)
A portion of the AF signals from the FM IF IC (IC1, pin 9) is
applied to the active filter section (IC1, pin 8) where noise
components are amplified and detected with an internal
noise detector. The squelch level adjustment pot (R29) is
connected to the active filter input (pin 8) to control the input
noise level.
The active filter section amplifies noise components. The filtered signals are rectified at the noise detector section and
converted into “SQL” signal (DC voltage) at the noise comparator section. The “SQL” signal is output from pin 13.
This squelch circuit is only used for the BUSY detection of
Ch70, and is not related the DSC decoder sensitivity and
etc.
• 2nd IF and demodulator circuits
Squelch level
adjustment pot
AF signal "DEMOD"
87 5 3
Noise
Active
filter
FM
detector
detector
Limiter
amp.
2nd IF filter
450 kHz
FI3
RSSI
Mixer
(21.25 MHz)
2
17
21.25 MHz
16
PLL IC
IC2
X2
IC1 TA31136FN
11109
X1
13
R8V
16
1st IF (21.7 MHz)
from Q3
"SQL" signal to the CPU
(LOGIC unit; IC1) pin 38
3 - 2
3-2 PLL CIRCUIT
3-2-1 PLL CIRCUIT (MAIN UNIT)
A PLL circuit provides stable oscillation of the receiver 1st
LO frequency. The PLL output compares the phase of the
divided VCO frequency to the reference frequency. The PLL
output frequency is controlled by the divided ratio (N-data) of
a programmable divider.
The PLL IC (IC2) contains a prescaler, programmable
counter, programmable divider phase detector, charge
pomp and etc. The entered signal is divided at the prescaler
and programmable counter section by the N-data ratio from
the CPU. The divided signal is detected on phase at the
phase detector using the reference frequency (21.25 MHz).
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
3-3 DSC CIRCUITS
3-3-1 DSC DECODE CIRCUIT (MAIN UNIT)
The AF signals from FM IF IC (IC1, pin 9) are filtered at the
bandpass filter (IC3) with +18 dB/octave characteristics to
remove except 1300 Hz and 2100 Hz signals. The filtered
signals are converted analog signals into digital signals at
IC4, and are then applied to the CPU after shaping waveform at IC6.
3-3-2 DSC ENCODE CIRCUT (MAIN UNIT)
The DSC signals from the D/A outputs of CPU are amplified
at the buffer amplifier (Q17) and converted into 600 Ω
impedance at T1. The signals are output to the connected
transceiver as floating system output.
3-4 NMEA AND DATA INTERFACE
CIRCUITS
3-4-1 NMEA CIRCUIT (MAIN UNIT)
The NMEA signals (GGA) from OPC-945 are applied to IC5
and are shaped waveform at IC6, and are then applied to
the CPU.
3-4-2 DATA INTERFACE CIRCUIT (MAIN UNIT)
The control signals from the connected transceiver with
OPC-951 are applied to IC8 and are shaped wave form at
IC6, and are then applied to the CPU.
3-5 POWER SUPPLY CIRCUITS
3-5-1 VOLTAGE LINE (MAIN UNIT)
LINE
13.8 V
8 V
5 V
R8V
DESCRIPTION
The voltage from the connected transceiver.
Common 8 V converted from the 13.8 V line and
regulated by the 8 V regulator circuit (IC9).
Common 5 V converted from the 8 V line and
regulated by the 5 V regulator circuit (IC10).
8 V for receiver circuits regulated by the R8V
regulator circuit (Q15, Q16).
• PLL circuit
21.25 MHz signal
to the FM IF IC
Loop
filter
X2
21.25 MHz
Q5, D4, D5
IC2 (PLL IC)
8
17
VCO
Phase
detector
Programmable
divider
16
Buffer
Q6
Programmable
counter
Shift register
Prescaler
Buffer
Q8
Buffer
Q7
to 1st mixer circuit
2
3
PSTB
4
PCK
5
PDATA
3 - 3
3-6 LOGIC CIRCUITS (LOGIC UNIT)
• CPU
IC1 is 16 bit single chip microcomputer and contains serial
I/O, timer, A/D converter, D/Aconverter, programmable I/O,
ROM and RAM.
• SYSTEM CLOCK CIRCUIT
X1 is a high-stability crystal oscillator and oscillated a
7.9872 MHz system clock for the CPU (IC1).
• RESET CIRCUIT
IC4 is a reset IC. When turn power ON, IC4 outputs a reset
signal (“LOW” pulse) to CPU (IC1, pin 75).
• LCD DRIVER
IC6–IC8 are LCD driver for a dot matrix LCD.
• INVERTER CIRCUIT
IC4 is a –8V DC-DC converter IC and converts –8 V from the
HV line. The converted voltage (–8V) is used for driving the
LCD.
• CLOCK CIRCUIT
IC3 is a clock IC and also used for backup the position/time
information for DSC.
• DIMMER CIRCUIT
Q2, Q3, Q6 are dimmer circuit and control the LCD backlight
(LED).
3-7 PORT ALLOCATIONS
3-7-1 CPU (LOGIC UNIT)
Outputs control signal for the LCD
contrast.
Input port for serial signal from the
NMEA connector (MAIN unit; J1) via
the photo coupler (MAIN unit; IC5)
and buffer amplifer (MAIN unit; IC6).
Outputs serial signal to the NMEA
connector (MAIN unit; J1) via the
buffer amplifier (Q13, Q14, D11).
Input port for noise level signal (DC
voltage) for squelch operation.
Output LCD backlight control signals
for the dimmer circuit (Q2, Q3, Q6).
Input port for the DSC decode signal.
Low : DSC signal is decoded.
Input port for the PLL unlock signal.
Low : While PLL is locked.
Outputs chip select signal for the LCD
drivers (IC6–IC8).
Output control signals for the LCD driver (IC6–IC8).
Input port for the control signal from
IC-M501EURO via the photo coupler
(MAIN unit; IC8) and buffer amplifier
(MAIN unit; IC6).
Outputs the control signal to ICM501EURO via the Buffer amplifier
(MAIN unit; Q11, Q12, D10).
Outputs busy LED (MAIN unit; DS1)
control signal.
Input port for the [ENT] key.
Input port for the [CLR] key.
Input port for the [CALL] key.
Input port for the [DISTRESS] key.
Outputs beep audio signal.
Outputs chip select signal for the clock
IC (IC3).
Outputs strobe signals for the PLL circuit.
Output data signals for the LCD driver
(IC6–IC8).
Outputs clock signal to the clock IC
(IC3).
Outputs serial signal for the clock IC
(IC3).
Input port for serial signal from the
clock IC (IC3).
Input port for the [1], [2] keys.
CADJ
NMEAI
NMEAO
SQL
DIM0–
DIM3
DDEC
UNLK
CS1,
CS2
RW,
DI, E
DATAS
DATAM
BUSY
KEY-ENT
KEY-CLR
KEY-CAL
KEY-DTR
BEEP
CCS
PSTB
DB0–
DB7
SCK
SO
SI
KEY-1,
KEY-2
31
36
37
38
41–44
45
46
52, 53
54,
55, 56
57
58
60
65
66
67
68
69
73
74
83–90
96
97
98
99, 100
1–7
8
10
11
12
13
14
15
19
20
23
24
26
30
KEY-3–
KEY-9
KEY-0
KEY-L
KEY-U
KEY-D
KEY-R
KEY-A
KEY-BS
CLRX
CLTX
ECK
EDA
RCEV
DSMOD
Input port for the [3]–[9] keys.
Input port for the [0] key.
Input port for the [LEFT] key.
Input port for the [UP] key.
Input port for the [DOWN] key.
Input port for the [RIGHT] key.
Input port for the [A/a] key.
Input port for the [BS] key.
Input port for the cloning data from the
buffer (MAIN unit; D8).
Output port for the cloning data to the
buffer (MAIN unit; Q9).
Outputs clock signal for EEPROM
(IC2).
Outputs serial data signal for EEP-
ROM (IC2).
Outputs the R8V regulator circuit
(MAIN unit; Q15, Q16) control signal.
High : While receiving
D/A output port for the DSC encode
signal to the buffer amplifier (MAIN
unit; Q17).
Pin Port
Description
number name
Pin Port
Description
number name
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