IBM A2 User Manual

A2 Processor

User’s Manual

for Blue Gene/Q

Note: This document and the information it contains are provided on an as-is basis. There is no plan for providing for future updates and corrections to this document.

Title Page

October 23, 2012 Version 1.3

Copyright and Disclaimer

Printed in the United States of America October 2012

IBM, the IBM logo, and ibm.com are trademarks or registered trademarks of International Business Machines Corp., registered in many jurisdictions worldwide. Other product and service names might be trademarks of IBM or other companies. A current list of IBM trademarks is available on the Web at “Copyright and trademark information” at www.ibm.com/legal/copytrade.shtml

Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

Other company, product, and service names may be trademarks or service marks of others.

All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in applications such as implantation, life support, or other hazardous uses where malfunction could result in death, bodily injury, or catastrophic property damage. The information contained in this document does not affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary.

THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN “AS IS” BASIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document.

IBM Systems and Technology Group 2070 Route 52, Bldg. 330 Hopewell Junction, NY 12533-6351

The IBM home page can be found at ibm.com®. The IBM semiconductor solutions home page can be found at ibm.com/chips.

Version 1.3 October 23, 2012

User’s Manual

A2 Processor

List of Figures ............................................................................................................... 21

List of Tables ................................................................................................................. 23

Revision Log ................................................................................................................. 29

About This Book .......................................................................................................... 31

Who Should Use This Book .................................................................................................................. 31

How to Use This Book ........................................................................................................................... 31

Notation ................................................................................................................................................. 32

Related Publications ............................................................................................................................. 33

List of Acronyms and Abbreviations .......................................................................... 35

1. Overview .................................................................................................................... 45

1.1 A2 Core Key Design Fundamentals ................................................................................................ 45

1.2 A2 Core Features ............................................................................................................................ 46

1.3 The A2 Core as a Power ISA Implementation ................................................................................ 49

1.3.1 Embedded Hypervisor ........................................................................................................... 49

1.4 A2 Core Organization ...................................................................................................................... 49

1.4.1 Instruction Unit ....................................................................................................................... 50

1.4.2 Execution Unit ....................................................................................................................... 51

1.4.3 Instruction and Data Cache Controllers ................................................................................. 51

1.4.3.1 Instruction Cache Controller ........................................................................................... 51

1.4.3.2 Data Cache Controller .................................................................................................... 51

1.4.4 Memory Management Unit (MMU) ........................................................................................ 52

1.4.5 Timers .................................................................................................................................... 54

1.4.6 Debug Facilities ..................................................................................................................... 54

1.4.6.1 Debug Modes ................................................................................................................. 54

1.4.6.2 Development Tool Support ............................................................................................. 55

1.4.7 Floating-Point Unit Organization ............................................................................................ 55

1.4.7.1 Arithmetic and Load/Store Pipelines .............................................................................. 56

1.4.8 IEEE 754 and Architectural Compliance ............................................................................... 56

1.4.8.1 IEEE 754 Compliance .................................................................................................... 57

1.4.9 Floating-Point Unit Implementation ....................................................................................... 57

1.4.9.1 Reciprocal Estimates ...................................................................................................... 57

1.4.9.2 Denormalized B Operands ............................................................................................. 57

1.4.9.3 Non-IEEE mode ............................................................................................................. 57

1.4.10 Floating-Point Unit Interfaces .............................................................................................. 57

1.4.10.1 A2 Processor Core Interface ........................................................................................ 57

1.4.10.2 Clock and Power Management Interface ..................................................................... 58

1.5 Core Interfaces ................................................................................................................................ 58

1.5.1 System Interface .................................................................................................................... 58

1.5.2 Auxiliary Execution Unit (AXU) Port ...................................................................................... 59

1.5.3 JTAG Port .............................................................................................................................. 59

Version 1.3 October 23, 2012

Contents

Page 3 of 864

User’s Manual

A2 Processor

2. CPU Programming Model ......................................................................................... 61

2.1 Logical Partitioning .......................................................................................................................... 61

2.1.1 Overview ................................................................................................................................ 61

2.2 Storage Addressing ......................................................................................................................... 62

2.2.1 Storage Operands .................................................................................................................. 62

2.2.2 Effective Address Calculation ................................................................................................ 64

2.2.2.1 Data Storage Addressing Modes .................................................................................... 65

2.2.2.2 Instruction Storage Addressing Modes ........................................................................... 65

2.2.3 Byte Ordering ......................................................................................................................... 66

2.2.3.1 Structure Mapping Examples ......................................................................................... 66

2.2.3.2 Instruction Byte Ordering ................................................................................................ 67

2.2.3.3 Data Byte Ordering ......................................................................................................... 68

2.2.3.4 Byte-Reverse Instructions .............................................................................................. 69

2.3 Multithreading .................................................................................................................................. 70

2.3.1 Thread Identification .............................................................................................................. 70

2.3.1.1 Thread Identification Register (TIR) ............................................................................... 70

2.3.1.2 Processor Identification Register (PIR) .......................................................................... 70

2.3.1.3 Guest Processor Identification Register (GPIR) ............................................................. 71

2.3.2 Thread Run State ................................................................................................................... 71

2.3.2.1 Thread Stop I/O Pin ........................................................................................................ 71

2.3.2.2 Thread Control and Status Register (THRCTL) ............................................................. 71

2.3.2.3 Core Configuration Register 0 (CCR0) ........................................................................... 72

2.3.2.4 Thread Enable Register (TENS, TENC) ......................................................................... 72

2.3.2.5 Thread Enable Status Register (TENSR) ....................................................................... 73

2.3.3 Wake On Interrupt .................................................................................................................. 74

2.3.3.1 Core Configuration Register 1 (CCR1) ........................................................................... 74

2.3.4 Thread Priority ....................................................................................................................... 75

2.3.4.1 Program Priority Register (PPR32) ................................................................................ 75

2.3.4.2 Instruction Unit Configuration Register 1 (IUCR1) .......................................................... 77

2.3.5 Resources Shared between Threads .................................................................................... 77

2.3.6 Shared Resources ................................................................................................................. 77

2.3.6.1 Accessing Shared Resources ........................................................................................ 78

2.3.7 Duplicated Resources ............................................................................................................ 78

2.3.8 Pipeline Sharing ..................................................................................................................... 79

2.3.8.1 Instruction Cache ............................................................................................................ 80

2.3.8.2 Instruction Buffer and Decode Dependency ................................................................... 80

2.3.8.3 Instruction Issue ............................................................................................................. 80

2.3.8.4 Ram Unit ......................................................................................................................... 81

2.3.8.5 Microcode Unit ................................................................................................................ 82

2.3.8.6 Integer Unit ..................................................................................................................... 82

2.4 Registers ......................................................................................................................................... 82

2.4.1 Register Mapping ................................................................................................................... 84

2.4.2 Register Types ....................................................................................................................... 84

2.4.2.1 General Purpose Registers ............................................................................................ 84

2.4.2.2 Special Purpose Registers ............................................................................................. 84

2.4.2.3 Condition Register .......................................................................................................... 85

2.4.2.4 Machine State Register .................................................................................................. 85

2.5 32-Bit Mode ..................................................................................................................................... 85

2.5.1 64-Bit Specific Instructions ..................................................................................................... 85

2.5.2 32-Bit Instruction Selection .................................................................................................... 85

Contents

Page 4 of 864

Version 1.3

October 23, 2012

User’s Manual

A2 Processor

2.6 Instruction Categories ..................................................................................................................... 86

2.7 Instruction Classes .......................................................................................................................... 87

2.7.1 Defined Instruction Class ....................................................................................................... 87

2.7.2 Illegal Instruction Class .......................................................................................................... 88

2.7.3 Reserved Instruction Class .................................................................................................... 88

2.8 Implemented Instruction Set Summary ........................................................................................... 88

2.8.1 Integer Instructions ................................................................................................................ 89

2.8.1.1 Integer Storage Access Instructions ............................................................................... 89

2.8.1.2 Integer Arithmetic Instructions ........................................................................................ 91

2.8.1.3 Integer Logical Instructions ............................................................................................ 92

2.8.1.4 Integer Compare Instructions ......................................................................................... 92

2.8.1.5 Integer Trap Instructions ................................................................................................ 92

2.8.1.6 Integer Rotate Instructions ............................................................................................. 92

2.8.1.7 Integer Shift Instructions ................................................................................................. 93

2.8.1.8 Integer Population Count Instructions ............................................................................ 93

2.8.1.9 Integer Select Instruction ................................................................................................ 93

2.8.2 Branch Instructions ................................................................................................................ 94

2.8.3 Processor Control Instructions .............................................................................................. 94

2.8.3.1 Condition Register Logical Instructions .......................................................................... 94

2.8.3.2 Register Management Instructions ................................................................................. 95

2.8.3.3 System Linkage Instructions .......................................................................................... 95

2.8.3.4 Processor Control Instructions ....................................................................................... 95

2.8.4 Storage Control Instructions .................................................................................................. 95

2.8.4.1 Cache Management Instructions .................................................................................... 96

2.8.4.2 TLB Management Instructions ....................................................................................... 96

2.8.4.3 Processor Synchronization Instruction ........................................................................... 97

2.8.4.4 Load and Reserve and Store Conditional Instructions ................................................... 97

2.8.4.5 Storage Synchronization Instructions ............................................................................. 97

2.8.4.6 Wait Instruction ............................................................................................................... 98

2.8.5 Initiate Coprocessor Instructions ........................................................................................... 98

2.8.5.1 Cache Initialization Instructions ...................................................................................... 98

2.9 Branch Processing .......................................................................................................................... 99

2.9.1 Branch Addressing ................................................................................................................ 99

2.9.2 Branch Instruction BI Field .................................................................................................... 99

2.9.3 Branch Instruction BO Field ................................................................................................... 99

2.9.4 Branch Prediction ................................................................................................................ 100

2.9.4.1 Branch Decoder ........................................................................................................... 100

2.9.4.2 Branch Direction Prediction .......................................................................................... 101

2.9.4.3 Branch Prioritization ..................................................................................................... 104

2.9.4.4 Branch Target Prediction .............................................................................................. 104

2.9.4.5 Redirection ................................................................................................................... 105

2.9.5 Branch Control Registers .................................................................................................... 105

2.9.5.1 Link Register (LR) ........................................................................................................ 105

2.9.5.2 Count Register (CTR) ................................................................................................... 106

2.9.5.3 Condition Register (CR) ............................................................................................... 107

2.10 Integer Processing ...................................................................................................................... 110

2.10.1 General Purpose Registers (GPRs) .................................................................................. 110

2.10.2 Integer Exception Register (XER) ..................................................................................... 110

2.10.2.1 Summary Overflow (SO) Field ................................................................................... 112

2.10.2.2 Overflow (OV) Field .................................................................................................... 112

Version 1.3 October 23, 2012

Contents

Page 5 of 864

User’s Manual

A2 Processor

2.10.2.3 Carry (CA) Field .......................................................................................................... 112

2.10.2.4 Transfer Byte Count (TBC) Field ................................................................................ 113

2.11 Processor Control ........................................................................................................................ 113

2.11.1 Special Purpose Registers General (SPRG0–SPRG8) ..................................................... 114

2.11.2 External Process ID Load Context (EPLC) Register .......................................................... 119

2.11.3 External Process ID Store Context (EPSC) Register ......................................................... 119

2.12 Privileged Modes ......................................................................................................................... 120

2.12.1 Privileged Instructions ........................................................................................................ 121

2.12.1.1 Cache Locking Instructions ........................................................................................ 121

2.12.2 Privileged SPRs ................................................................................................................. 122

2.13 Speculative Accesses ................................................................................................................. 122

2.14 Synchronization ........................................................................................................................... 122

2.14.1 Context Synchronization .................................................................................................... 122

2.14.2 Execution Synchronization ................................................................................................. 124

2.14.3 Storage Ordering and Synchronization .............................................................................. 124

2.15 Software Transactional Memory Acceleration ............................................................................. 125

2.15.1 Summary ............................................................................................................................ 125

2.15.2 Implementation .................................................................................................................. 125

2.15.2.1 L1 D-Cache ................................................................................................................ 126

2.15.3 Watch Operation Ordering Requirements .......................................................................... 126

2.15.4 Impact on Existing Software .............................................................................................. 126

3. FU Programming Model .......................................................................................... 127

3.1 Storage Addressing ....................................................................................................................... 127

3.1.1 Storage Operands ................................................................................................................ 127

3.1.2 Effective Address Calculation .............................................................................................. 128

3.1.3 Data Storage Addressing Modes ......................................................................................... 128

3.2 Floating-Point Exceptions .............................................................................................................. 129

3.3 Floating-Point Registers ................................................................................................................ 129

3.3.1 Register Types ..................................................................................................................... 130

3.3.1.1 Floating-Point Registers (FPR0–FPR31) ..................................................................... 130

3.3.1.2 Floating-Point Status and Control Register (FPSCR) .................................................. 131

3.4 Floating-Point Data Formats ......................................................................................................... 133

3.4.1 Value Representation .......................................................................................................... 134

3.4.2 Binary Floating-Point Numbers ............................................................................................ 135

3.4.2.1 Normalized Numbers .................................................................................................... 135

3.4.2.2 Denormalized Numbers ................................................................................................ 136

3.4.2.3 Zero Values .................................................................................................................. 136

3.4.3 Infinities ................................................................................................................................ 136

3.4.3.1 Not a Numbers ............................................................................................................. 136

3.4.4 Sign of Result ....................................................................................................................... 137

3.4.5 Normalization and Denormalization ..................................................................................... 138

3.4.6 Data Handling and Precision ............................................................................................... 138

3.4.7 Rounding .............................................................................................................................. 139

3.5 Floating-Point Execution Models ................................................................................................... 140

3.5.1 Execution Model for IEEE Operations ................................................................................. 141

3.5.2 Execution Model for Multiply-Add Type Instructions ............................................................ 143

3.6 Floating-Point Instructions ............................................................................................................. 143

3.6.1 Instructions by Category ...................................................................................................... 144

Contents

Page 6 of 864

Version 1.3

October 23, 2012

User’s Manual

A2 Processor

3.6.2 Load and Store Instructions ................................................................................................. 145

3.6.3 Floating-Point Store Instructions ......................................................................................... 146

3.6.4 Floating-Point Move Instructions ......................................................................................... 148

3.6.5 Floating-Point Arithmetic Instructions .................................................................................. 148

3.6.5.1 Floating-Point Multiply-Add Instructions ....................................................................... 149

3.6.6 Floating-Point Rounding and Conversion Instructions ........................................................ 149

3.6.7 Floating-Point Compare Instructions ................................................................................... 150

3.6.8 Floating-Point Status and Control Register Instructions ...................................................... 151

4. Initialization ............................................................................................................. 153

4.1 Core Reset .................................................................................................................................... 153

4.2 A2 Core State After Reset ............................................................................................................. 154

4.3 Software Initiated Reset Requests ................................................................................................ 160

4.3.1 Software Reset Requests .................................................................................................... 160

4.3.1.1 From Debug ................................................................................................................. 161

4.3.1.2 From Watchdog Timer .................................................................................................. 161

4.3.2 Reset Request Status .......................................................................................................... 161

4.3.2.1 Debug Facility Reset Status ......................................................................................... 162

4.3.2.2 Timer Facility Reset Status .......................................................................................... 162

4.4 Initialization Software Requirements ............................................................................................. 163

5. Instruction and Data Caches ................................................................................. 169

5.1 Data Cache Array Organization and Operation ............................................................................ 169

5.2 Instruction Cache Array Organization and Operation ................................................................... 170

5.3 Cache Line Replacement Policy ................................................................................................... 170

5.4 Instruction Cache Controller .......................................................................................................... 170

5.4.1 ICC Operations .................................................................................................................... 171

5.4.2 Instruction Cache Coherency .............................................................................................. 171

5.4.2.1 Self-Modifying Code ..................................................................................................... 172

5.4.2.2 Instruction Cache Synonyms ........................................................................................ 172

5.4.3 Instruction Cache Control and Debug ................................................................................. 172

5.4.3.1 Instruction Cache Management and Debug Instruction Summary ............................... 172

5.4.3.2 Instruction Cache Parity Operations ............................................................................. 173

5.4.3.3 Simulating Instruction Cache Parity Errors for Software Testing ................................. 173

5.5 Data Cache Controller ................................................................................................................... 173

5.5.1 DCC Operations .................................................................................................................. 174

5.5.1.1 Load and Store Alignment ............................................................................................ 175

5.5.1.2 Load Operations ........................................................................................................... 175

5.5.1.3 Store Operations .......................................................................................................... 176

5.5.1.4 Data Read and Instruction Fetch Interface Requests .................................................. 176

5.5.1.5 Data Write Interface Requests ..................................................................................... 176

5.5.1.6 Storage Access Ordering ............................................................................................. 177

5.5.2 Data Cache Coherency ....................................................................................................... 177

5.5.3 Data Cache Control ............................................................................................................. 177

5.5.3.1 Data Cache Management Instruction Summary .......................................................... 177

5.5.3.2 dcbt and dcbtst Operation ............................................................................................ 178

5.5.3.3 Cache Locking Mechanisms ........................................................................................ 179

5.5.3.4 Data Cache Parity Operations ...................................................................................... 183

5.5.3.5 Simulating Data Cache Parity Errors for Software Testing .......................................... 183

Version 1.3 October 23, 2012

Contents

Page 7 of 864

User’s Manual

A2 Processor

5.5.3.6 Data Cache Disable ...................................................................................................... 183

6. Memory Management .............................................................................................. 185

6.1 MMU Overview .............................................................................................................................. 185

6.1.1 Support for Power ISA MMU Architecture ........................................................................... 186

6.2 Page Identification ......................................................................................................................... 186

6.2.1 Virtual Address Formation ................................................................................................... 187

6.2.2 Address Space Identifier Convention ................................................................................... 187

6.2.3 Exclusion Range (X-bit) Operation ...................................................................................... 188

6.2.4 TLB Match Process .............................................................................................................. 189

6.3 Address Translation ...................................................................................................................... 191

6.4 Access Control .............................................................................................................................. 193

6.4.1 Execute Access ................................................................................................................... 193

6.4.2 Write Access ........................................................................................................................ 193

6.4.3 Read Access ........................................................................................................................ 194

6.4.4 Access Control Applied to Cache Management Instructions ............................................... 194

6.5 Storage Attributes .......................................................................................................................... 195

6.5.1 Write-Through (W) ............................................................................................................... 196

6.5.2 Caching Inhibited (I) ............................................................................................................. 196

6.5.3 Memory Coherence Required (M) ....................................................................................... 196

6.5.4 Guarded (G) ......................................................................................................................... 196

6.5.5 Endian (E) ............................................................................................................................ 197

6.5.6 User-Definable (U0–U3) ...................................................................................................... 197

6.5.7 Supported Storage Attribute Combinations ......................................................................... 197

6.5.8 Aliasing ................................................................................................................................ 197

6.6 Translation Lookaside Buffer ......................................................................................................... 198

6.7 Effective to Real Address Translation Arrays ................................................................................ 203

6.7.1 ERAT Context Synchronization ........................................................................................... 204

6.7.2 ERAT Reset Behavior .......................................................................................................... 205

6.7.3 Atomic Update of ERAT Entries ........................................................................................... 205

6.7.4 ERAT LRU Round-Robin Replacement Mode ..................................................................... 205

6.7.5 ERAT LRU Replacement Watermark .................................................................................. 206

6.7.6 ERAT (TLB Lookaside Information) Coherency and Back-Invalidation ............................... 206

6.7.7 ERAT External PID (EPID) Context and Instruction Dependencies .................................... 208

6.8 Logical to Real Address Translation Array (Category E.HV.LRAT) .............................................. 209

6.9 TLB Management Instructions (Architected) ................................................................................. 212

6.9.1 TLB Read and Write Instructions (tlbre and tlbwe) ............................................................. 213

6.9.2 TLB Search Instruction (tlbsx[.]) ........................................................................................ 215

6.9.3 TLB Search and Reserve Instruction (tlbsrx.) .................................................................... 215

6.9.4 TLB Invalidate Virtual Address (Indexed) Instruction (tlbivax) ............................................ 216

6.9.5 TLB Invalidate Local (Indexed) Instruction (tlbilx) ............................................................... 218

6.9.6 TLB Sync Instruction (tlbsync) ............................................................................................ 218

6.10 ERAT Management Instructions (Non-Architected) .................................................................... 219

6.10.1 ERAT Read and Write Instructions (eratre and eratwe) ................................................... 219

6.10.2 ERAT Search Instruction (eratsx[.]) ................................................................................. 220

6.10.3 ERAT Invalidate Virtual Address (Indexed) Instruction (erativax) ..................................... 221

6.10.4 ERAT Invalidate Local (Indexed) Instruction (eratilx) ........................................................ 224

6.11 32-Bit Mode Memory Management Behavior .............................................................................. 224

6.11.1 32-Bit Mode TLB Read and Write Instructions (tlbre and tlbwe) ...................................... 225

Contents

Page 8 of 864

Version 1.3

October 23, 2012

User’s Manual

A2 Processor

6.11.2 32-Bit Mode TLB Search Instruction (tlbsx[.]) ................................................................. 225

6.11.3 32-Bit Mode TLB Search and Reserve Instruction (tlbsrx.) ............................................. 225

6.11.4 32-Bit Mode TLB Invalidate Virtual Address (Indexed) Instruction (tlbivax) ..................... 226

6.11.5 32-Bit Mode TLB Invalidate Local (Indexed) Instruction (tlbilx) ........................................ 226

6.11.6 32-Bit Mode TLB Sync Instruction (tlbsync) ..................................................................... 226

6.11.7 32-Bit Mode ERAT Read and Write Instructions (eratre and eratwe) .............................. 226

6.11.8 32-Bit Mode ERAT Search Instruction (eratsx[.]) ............................................................ 227

6.11.9 32-Bit Mode ERAT Invalidate Virtual Address (Indexed) Instruction (erativax) ................ 227

6.11.10 32-Bit Mode ERAT Invalidate Local (Indexed) Instruction (eratilx) ................................. 228

6.12 Page Reference and Change Status Management .................................................................... 228

6.13 TLB and ERAT Parity Operations ............................................................................................... 229

6.13.1 Parity Errors Generated from tlbre or eratre .................................................................... 230

6.13.2 Simulating TLB and ERAT Parity Errors for Software Testing .......................................... 231

6.14 ERAT-Only Mode Operation ....................................................................................................... 232

6.15 TLB Reservations and TLB Write Conditional (Category E.TWC) .............................................. 232

6.16 Hardware Page Table Walking (Category E.PT) ........................................................................ 237

6.16.1 Searching the TLB for Direct and Indirect Entries ............................................................. 237

6.16.2 Indirect TLB Entry Page and Sub-Page Sizes ................................................................... 238

6.16.3 Hardware Page Table Entry Format .................................................................................. 239

6.16.4 Calculation of Hardware Page Table Entry Real Address ................................................. 240

6.16.5 Hardware Page Table Errors and Exceptions ................................................................... 241

6.16.6 Hardware Page Table Storage Control Attributes ............................................................. 241

6.16.7 TLB Update After Hardware Page Table Translation ........................................................ 242

6.17 Storage Control Registers (Architected) ..................................................................................... 244

6.17.1 Process ID Register (PID) ................................................................................................. 244

6.17.2 Logical Partition ID Register (LPIDR) ................................................................................ 245

6.17.3 External PID Load Context (EPLC) Register ..................................................................... 246

6.17.4 External PID Store Context (EPSC) Register .................................................................... 247

6.17.5 MMU Assist Register 0 (MAS0) ......................................................................................... 248

6.17.6 MMU Assist Register 1 (MAS1) ......................................................................................... 249

6.17.7 MMU Assist Register 2 (MAS2) ......................................................................................... 251

6.17.8 MMU Assist Register 2 Upper (MAS2U) ........................................................................... 252

6.17.9 MMU Assist Register 3 (MAS3) ......................................................................................... 253

6.17.10 MMU Assist Register 4 (MAS4) ....................................................................................... 255

6.17.11 MMU Assist Register 5 (MAS5) ....................................................................................... 256

6.17.12 MMU Assist Register 6 (MAS6) ....................................................................................... 257

6.17.13 MMU Assist Register 7 (MAS7) ....................................................................................... 258

6.17.14 MMU Assist Register 8 (MAS8) ....................................................................................... 259

6.17.15 MAS0_MAS1 Register ..................................................................................................... 260

6.17.16 MAS5_MAS6 Register ..................................................................................................... 261

6.17.17 MAS7_MAS3 Register ..................................................................................................... 262

6.17.18 MAS8_MAS1 Register ..................................................................................................... 263

6.17.19 MMU Configuration Register (MMUCFG) ........................................................................ 264

6.17.20 MMU Control and Status Register 0 (MMUCSR0) .......................................................... 265

6.17.21 TLB 0 Configuration Register (TLB0CFG) ....................................................................... 266

6.17.22 TLB 0 Page Size Register (TLB0PS) .............................................................................. 268

6.17.23 LRAT Configuration Register (LRATCFG) ...................................................................... 269

6.17.24 LRAT Page Size Register (LRATPS) .............................................................................. 270

6.17.25 Embedded Page Table Configuration Register (EPTCFG) ............................................. 272

6.17.26 Logical Page Exception Register (LPER) ........................................................................ 273

Version 1.3 October 23, 2012

Contents

Page 9 of 864

User’s Manual

A2 Processor

6.17.27 Logical Page Exception Register Upper (LPERU) ........................................................... 274

6.17.28 MAS Register Update Summary ...................................................................................... 275

6.18 Storage Control Registers (Non-Architected) .............................................................................. 277

6.18.1 Memory Management Unit Control Register 0 (MMUCR0) ............................................... 277

6.18.2 Memory Management Unit Control Register 1 (MMUCR1) ............................................... 280

6.18.3 Memory Management Unit Control Register 2 (MMUCR2) ............................................... 287

6.18.4 Memory Management Unit Control Register 3 (MMUCR3) ............................................... 290

7. CPU Interrupts and Exceptions .............................................................................. 293

7.1 Overview ....................................................................................................................................... 293

7.2 Directed Interrupts ......................................................................................................................... 293

7.3 Interrupt Classes ........................................................................................................................... 294

7.3.1 Asynchronous Interrupts ...................................................................................................... 294

7.3.2 Synchronous Interrupts ........................................................................................................ 294

7.3.2.1 Synchronous, Precise Interrupts .................................................................................. 294

7.3.2.2 Synchronous, Imprecise Interrupts ............................................................................... 295

7.3.3 Critical and Noncritical Interrupts ......................................................................................... 296

7.3.4 Machine Check Interrupts .................................................................................................... 296

7.4 Interrupt Processing ...................................................................................................................... 297

7.4.1 Partially Executed Instructions ............................................................................................. 299

7.5 Interrupt Processing Registers ...................................................................................................... 300

7.5.1 Register Mapping ................................................................................................................. 301

7.5.2 Machine State Register (MSR) ............................................................................................ 301

7.5.3 Machine State Register Protect (MSRP) ............................................................................. 303

7.5.4 Embedded Processor Control Register (EPCR) .................................................................. 304

7.5.5 Save/Restore Register 0 (SRR0) ......................................................................................... 305

7.5.6 Save/Restore Register 1 (SRR1) ......................................................................................... 306

7.5.7 Guest Save/Restore Register 0 (GSRR0) ........................................................................... 308

7.5.8 Guest Save/Restore Register 1 (GSRR1) ........................................................................... 308

7.5.9 Critical Save/Restore Register 0 (CSRR0) .......................................................................... 310

7.5.10 Critical Save/Restore Register 1 (CSRR1) ........................................................................ 311

7.5.11 Machine Check Save/Restore Register 0 (MCSRR0) ....................................................... 313

7.5.12 Machine Check Save/Restore Register 1 (MCSRR1) ....................................................... 313

7.5.13 Data Exception Address Register (DEAR) ......................................................................... 315

7.5.14 Guest Data Exception Address Register (GDEAR) ........................................................... 316

7.5.15 Interrupt Vector Prefix Register (IVPR) .............................................................................. 318

7.5.16 Guest Interrupt Vector Prefix Register (GIVPR) ................................................................ 318

7.5.17 Exception Syndrome Register (ESR) ................................................................................. 318

7.5.18 Guest Exception Syndrome Register (GESR) ................................................................... 320

7.5.19 Machine Check Status Register (MCSR) ........................................................................... 322

7.6 Interrupt Definitions ....................................................................................................................... 323

7.6.1 Critical Input Interrupt ........................................................................................................... 326

7.6.2 Machine Check Interrupt ...................................................................................................... 327

7.6.2.1 Machine Check Status Register (MCSR) ..................................................................... 329

7.6.3 Data Storage Interrupt ......................................................................................................... 330

7.6.4 Instruction Storage Interrupt ................................................................................................ 334

7.6.5 External Input Interrupt ........................................................................................................ 336

7.6.6 Alignment Interrupt ............................................................................................................... 337

7.6.7 Program Interrupt ................................................................................................................. 338

Contents

Page 10 of 864

Version 1.3

October 23, 2012

User’s Manual

A2 Processor

7.6.8 Floating-Point Unavailable Interrupt .................................................................................... 342

7.6.9 System Call Interrupt ........................................................................................................... 342

7.6.10 Auxiliary Processor Unavailable Interrupt .......................................................................... 343

7.6.11 Decrementer Interrupt ....................................................................................................... 343

7.6.12 Fixed-Interval Timer Interrupt ............................................................................................ 344

7.6.13 Watchdog Timer Interrupt .................................................................................................. 344

7.6.14 Data TLB Error Interrupt .................................................................................................... 345

7.6.15 Instruction TLB Error Interrupt ........................................................................................... 346

7.6.16 Vector Unavailable Interrupt .............................................................................................. 347

7.6.17 Debug Interrupt .................................................................................................................. 347

7.6.18 Processor Doorbell Interrupt .............................................................................................. 351

7.6.19 Processor Doorbell Critical Interrupt .................................................................................. 352

7.6.20 Guest Processor Doorbell Interrupt ................................................................................... 352

7.6.21 Guest Processor Doorbell Critical Interrupt ....................................................................... 353

7.6.22 Guest Processor Doorbell Machine Check Interrupt ......................................................... 353

7.6.23 Embedded Hypervisor System Call Interrupt .................................................................... 354

7.6.24 Embedded Hypervisor Privilege Interrupt .......................................................................... 354

7.6.25 LRAT Error Interrupt .......................................................................................................... 355

7.6.26 User Decrementer Interrupt ............................................................................................... 356

7.6.27 Performance Monitor Interrupt ........................................................................................... 356

7.7 Processor Messages ..................................................................................................................... 357

7.7.1 Processor Message Handling and Filtering ......................................................................... 357

7.7.2 Doorbell Message Filtering .................................................................................................. 358

7.7.3 Doorbell Critical Message Filtering ...................................................................................... 359

7.7.4 Guest Doorbell Message Filtering ....................................................................................... 360

7.7.5 Guest Doorbell Critical Message Filtering ........................................................................... 360

7.7.6 Guest Doorbell Machine Check Message Filtering ............................................................. 361

7.8 Interrupt Ordering and Masking .................................................................................................... 362

7.8.1 Interrupt Ordering Software Requirements .......................................................................... 363

7.8.2 Interrupt Order ..................................................................................................................... 364

7.9 Exception Priorities ....................................................................................................................... 365

7.9.1 Exception Priorities for Integer Load, Store, and Cache Management Instructions ............ 366

7.9.2 Exception Priorities for Floating-Point Load and Store Instructions .................................... 367

7.9.3 Exception Priorities for Floating-Point Instructions (Other) .................................................. 367

7.9.4 Exception Priorities for Privileged Instructions .................................................................... 368

7.9.5 Exception Priorities for Trap Instructions ............................................................................. 368

7.9.6 Exception Priorities for System Call Instruction ................................................................... 368

7.9.7 Exception Priorities for Branch Instructions ......................................................................... 369

7.9.8 Exception Priorities for Return From Interrupt Instructions .................................................. 369

7.9.9 Exception Priorities for Reserved Instructions ..................................................................... 369

7.9.10 Exception Priorities for All Other Instructions .................................................................... 370

8. FU Interrupts and Exceptions ................................................................................ 371

8.1 Floating-Point Exceptions ............................................................................................................. 371

8.2 Exceptions List .............................................................................................................................. 372

8.3 Floating-Point Interrupts ................................................................................................................ 375

8.3.1 Floating-Point Unavailable Interrupt .................................................................................... 375

8.3.2 Floating-Point Assist Interrupt ............................................................................................. 375

8.4 Floating-Point Exception Behavior ................................................................................................ 375

Version 1.3 October 23, 2012

Contents

Page 11 of 864

User’s Manual

A2 Processor

8.4.1 Invalid Operation Exception ................................................................................................. 375

8.4.1.1 Action ............................................................................................................................ 376

8.4.2 Zero Divide Exception .......................................................................................................... 377

8.4.2.1 Action ............................................................................................................................ 377

8.4.3 Overflow Exception .............................................................................................................. 378

8.4.3.1 Action ............................................................................................................................ 378

8.4.4 Underflow Exception ............................................................................................................ 379

8.4.4.1 Action ............................................................................................................................ 379

8.4.5 Inexact Exception ................................................................................................................. 380

8.4.5.1 Action ............................................................................................................................ 380

8.5 Exception Priorities for Floating-Point Load and Store Instructions .............................................. 380

8.6 Exception Priorities for Other Floating-Point Instructions .............................................................. 381

8.7 QNaN ............................................................................................................................................ 381

8.8 Updating FPRs on Exceptions ...................................................................................................... 382

8.9 Floating-Point Status and Control Register (FPSCR) ................................................................... 382

8.10 Updating the Condition Register ................................................................................................. 385

8.10.1 Condition Register (CR) ..................................................................................................... 385

8.10.2 Updating CR Fields ............................................................................................................ 386

8.10.3 Generation of QNaN Results ............................................................................................. 386

9. Timer Facilities ........................................................................................................ 387

9.1 Time Base ..................................................................................................................................... 388

9.1.1 Reading the Time Base ....................................................................................................... 389

9.1.2 Writing the Time Base .......................................................................................................... 389

9.2 Decrementer (DEC) ....................................................................................................................... 389

9.3 User Decrementer (UDEC) ........................................................................................................... 391

9.4 Fixed Interval Timer (FIT) .............................................................................................................. 392

9.5 Watchdog Timer ............................................................................................................................ 393

9.6 Timer Control Register (TCR) ....................................................................................................... 395

9.7 Timer Status Register (TSR) ......................................................................................................... 397

9.8 Freezing the Timer Facilities ......................................................................................................... 397

9.9 Selection of the Timer Clock Source ............................................................................................. 398

9.10 Synchronizing Timers Across Multiple Cores .............................................................................. 398

10. Debug Facilities ..................................................................................................... 399

10.1 Implications of Hypervisor on Debug Controls ............................................................................ 399

10.2 Support for Development Tools ................................................................................................... 399

10.3 Debug Modes .............................................................................................................................. 399

10.3.1 Internal Debug Mode ......................................................................................................... 400

10.3.2 External Debug Mode ........................................................................................................ 400

10.3.3 Trace Debug Mode ............................................................................................................ 401

10.4 Debug Events .............................................................................................................................. 402

10.4.1 Instruction Address Compare (IAC) Debug Event ............................................................. 402

10.4.1.1 IAC Debug Event Fields ............................................................................................. 403

10.4.1.2 IAC Debug Event Processing ..................................................................................... 404

10.4.2 Data Address Compare (DAC) Debug Event ..................................................................... 405

10.4.2.1 DAC Debug Event Fields ............................................................................................ 405

10.4.2.2 DAC Debug Event Processing ................................................................................... 407

Contents

Page 12 of 864

Version 1.3

October 23, 2012

User’s Manual

A2 Processor

10.4.2.3 DAC Debug Events Applied to Instructions that Result in Multiple Storage Accesses 407

10.4.2.4 DAC Debug Events Applied to Various Instruction Types ......................................... 408

10.4.3 Data Value Compare (DVC) Debug Event ........................................................................ 409

10.4.3.1 DVC Debug Event Fields ........................................................................................... 409

10.4.3.2 DVC Debug Event Processing ................................................................................... 410

10.4.3.3 DVC Debug Events Applied to Instructions that Result in Multiple Storage Accesses 410

10.4.3.4 DVC Debug Events Applied to Various Instruction Types ......................................... 411

10.4.3.5 DVC Debug Events Applied to Floating-Point Loads and Stores ............................... 411

10.4.4 Instruction Complete (ICMP) Debug Event ....................................................................... 411

10.4.5 Branch Taken (BRT) Debug Event .................................................................................... 412

10.4.6 Trap (TRAP) Debug Event ................................................................................................ 412

10.4.7 Return (RET) Debug Event ............................................................................................... 412

10.4.8 Interrupt (IRPT) Debug Event ............................................................................................ 413

10.4.9 Unconditional Debug Event (UDE) .................................................................................... 414

10.4.10 Instruction Value Compare (IVC) Debug Event ............................................................... 414

10.4.11 Debug Event Summary ................................................................................................... 415

10.5 Debug Reset ............................................................................................................................... 415

10.6 Debug Timer Freeze ................................................................................................................... 415

10.7 Debug Registers ......................................................................................................................... 415

10.7.1 Debug Control Register 0 (DBCR0) .................................................................................. 416

10.7.2 Debug Control Register 1 (DBCR1) .................................................................................. 418

10.7.3 Debug Control Register 2 (DBCR2) .................................................................................. 419

10.7.4 Debug Control Register 3 (DBCR3) .................................................................................. 421

10.7.5 Debug Status Register (DBSR) ........................................................................................ 422

10.7.6 Debug Status Register Write Register (DBSRWR) ........................................................... 423

10.7.7 Instruction Address Compare Registers (IAC1–IAC4) ...................................................... 425

10.7.8 Data Address Compare Registers (DAC1–DAC2) ............................................................ 426

10.7.9 Data Value Compare Registers (DVC1–DVC2) ................................................................ 427

10.7.10 Instruction Address Register (IAR) .................................................................................. 428

10.7.11 Instruction Match Mask Registers (IMMR) ...................................................................... 429

10.7.12 Instruction Match Registers (IMR) ................................................................................... 429

10.8 Instruction Stuffing ...................................................................................................................... 429

10.8.1 Ram Mode Overview ......................................................................................................... 430

10.8.2 Ram Register Descriptions ................................................................................................ 431

10.8.3 Example Ram Mode Procedures ....................................................................................... 434

10.8.3.1 SPR Read/Write Using GPR as Temporary Storage ................................................. 434

10.8.3.2 Using Microcode Scratch Registers as Temporary Storage ...................................... 435

10.8.4 Supported Ram Instructions .............................................................................................. 436

10.9 Direct Access to I-Cache and D-Cache Directories .................................................................... 437

10.9.1 General Read D-Cache Directory Sequence for L1 D-Cache ........................................... 437

10.9.2 Instruction Unit Debug Register 0 (IUDBG0) ..................................................................... 438

10.9.3 Instruction Unit Debug Register 1 (IUDBG1) ..................................................................... 439

10.9.4 Instruction Unit Debug Register 2 (IUDBG2) ..................................................................... 439

10.9.5 Execution Unit Debug Register 0 (XUDBG0) .................................................................... 440

10.9.6 Execution Unit Debug Register 1 (XUDBG1) .................................................................... 440

10.9.7 Execution Unit Debug Register 2 (XUDBG2) .................................................................... 441

10.10 Thread Control and Status ........................................................................................................ 441

10.10.1 Using THRCTL Register to Stop Thread 0 ...................................................................... 443

10.10.2 Using THRCTL Register to Start Thread 0 ...................................................................... 443

10.10.3 Using THRCTL Register to Instruction Step Thread 0 .................................................... 443

Version 1.3 October 23, 2012

Contents

Page 13 of 864

User’s Manual

A2 Processor

10.11 PC Configuration Register 0 (PCCR0) ...................................................................................... 444

10.12 Trace and Trigger Bus ............................................................................................................... 445

10.12.1 Trace and Trigger Bus Overview ..................................................................................... 445

10.12.2 Unit Level Trace and Trigger Bus Implementation ........................................................... 446

10.12.3 Debug Select Registers ................................................................................................... 447

11. Performance Events and Event Selection ........................................................... 449

11.1 Event Bus Overview .................................................................................................................... 449

11.2 A2 Core Event Bus and PC Unit Controls ................................................................................... 450

11.2.1 Enabling Performance Event and Trace Bus Latches ....................................................... 450

11.2.2 Performance Analysis Operating Modes ........................................................................... 450

11.2.3 Core Performance Event Selection to External Event Bus ................................................ 450

11.2.4 Core Event Select Register (CESR) .................................................................................. 452

11.3 Unit Level Performance Event Selection ..................................................................................... 454

11.3.1 Unit Event Multiplexer Component .................................................................................... 454

11.3.2 Performance Monitor Event Tags and Count Modes ......................................................... 456

11.3.3 Unit Performance Event Tables ......................................................................................... 457

11.4 Unit Performance Event Tables .................................................................................................. 458

11.4.1 FU Performance Events Table ........................................................................................... 458

11.4.2 IU Performance Events Table ............................................................................................ 458

11.4.3 XU Performance Events Table .......................................................................................... 460

11.4.4 LSU Performance Events Table ........................................................................................ 462

11.4.5 MMU Performance Events Table ....................................................................................... 465

11.5 Unit Event Select Registers ......................................................................................................... 466

11.5.1 FU Event Select Register (AESR) ..................................................................................... 466

11.5.2 IU Event Select Registers .................................................................................................. 468

11.5.3 XU Event Select Registers ................................................................................................. 470

11.5.4 LSU Event Select Registers ............................................................................................... 472

11.5.5 MMU Event Select Registers ............................................................................................. 474

11.6 A2 Support for Core Instruction Trace ......................................................................................... 476

11.6.1 Instruction Trace Mode Setup ............................................................................................ 476

11.6.2 Instruction Trace Record Data ........................................................................................... 476

11.6.3 Instruction Trace Record Formats and Ordering ............................................................... 477

11.6.4 Debug Bus Control When in Instruction Trace Mode ......................................................... 478

11.6.4.1 FU Trace Records ...................................................................................................... 479

11.6.4.2 XU Debug Bus Control ............................................................................................... 479

11.7 A2 Support for Instruction Sampling ............................................................................................ 479

12. Implementation Dependent Instructions ............................................................. 481

12.1 Miscellaneous .............................................................................................................................. 481

12.1.1 Attention (attn) ................................................................................................................... 481

12.2 TLB Management Instructions .................................................................................................... 482

12.2.1 TLB Read Entry (tlbre) ...................................................................................................... 482

12.2.2 TLB Write Entry (tlbwe) ..................................................................................................... 484

12.2.3 TLB Search Indexed (tlbsx[.]) ........................................................................................... 486

12.2.4 TLB Search and Reserve Indexed (tlbsrx.) ....................................................................... 488

12.2.5 TLB Invalidate Virtual Address Indexed (tlbivax) .............................................................. 490

12.2.6 TLB Invalidate Local Indexed (tlbilx) ................................................................................. 493

12.3 ERAT Management Instructions ................................................................................................. 496

Contents

Page 14 of 864

Version 1.3

October 23, 2012

User’s Manual

A2 Processor

12.3.1 ERAT Read Entry (eratre) ................................................................................................. 496

12.3.2 ERAT Write Entry (eratwe) ............................................................................................... 499

12.3.3 ERAT Search Indexed (eratsx[.]) ..................................................................................... 502

12.3.4 ERAT Invalidate Virtual Address Indexed (erativax) ........................................................ 504

12.3.5 ERAT Invalidate Local Indexed (eratilx) ........................................................................... 507

12.4 Software Transactional Memory Instructions .............................................................................. 509

12.4.1 Load Doubleword and Watch Indexed X-Form (ldawx.) ................................................... 510

12.4.2 Watch Check All X-Form (wchkall) ................................................................................... 511

12.4.3 Watch Clear X-Form (wclr) ............................................................................................... 512

12.5 Coprocessor Instructions ............................................................................................................ 513

12.5.1 Initiate Coprocessor Store Word Indexed (icswx[.]) ......................................................... 515

12.5.1.1 General Registers ...................................................................................................... 516

12.5.1.2 Initial Execution .......................................................................................................... 517

12.5.2 Initiate Coprocessor Store Word External Process ID Indexed (icswepx[.]) .................... 518

12.5.3 Execution ........................................................................................................................... 518

12.5.3.1 Condition Register 0 ................................................................................................... 519

12.5.4 Coprocessor-Request Block .............................................................................................. 520

12.5.4.1 Available Coprocessor Register (ACOP) ................................................................... 520

12.5.4.2 Hypervisor Available Coprocessor Register (HACOP) ............................................... 521

12.6 Data Cache Block Flush .............................................................................................................. 523

12.6.1 Data Cache Block Flush (dcbf) ......................................................................................... 523

12.7 Data Cache Block Flush by External PID .................................................................................... 524

12.7.1 Data Cache Block Flush by External PID (dcbfep) ........................................................... 524

13. Power Management Methods .............................................................................. 525

13.1 Chip Power Management Controls ............................................................................................. 525

13.2 Power-Saving Instructions .......................................................................................................... 525

13.2.1 Power-Saving Instruction Sequence ................................................................................. 526

14. Register Summary ................................................................................................ 529

14.1 Register Categories .................................................................................................................... 529

14.2 Reserved Fields .......................................................................................................................... 535

14.3 Unimplemented SPRs ................................................................................................................. 535

14.4 Device Control Registers ............................................................................................................ 535

14.5 Alphabetical Register Listing ....................................................................................................... 537

14.5.1 ACOP - Available Coprocessor ......................................................................................... 538

14.5.2 AESR - AXU Event Select Register ................................................................................... 539

14.5.3 CCR0 - Core Configuration Register 0 .............................................................................. 541

14.5.4 CCR1 - Core Configuration Register 1 .............................................................................. 542

14.5.5 CCR2 - Core Configuration Register 2 .............................................................................. 543

14.5.6 CCR3 - Core Configuration Register 3 .............................................................................. 545

14.5.7 CESR - Core Event Select Register .................................................................................. 546

14.5.8 CR - Condition Register ..................................................................................................... 549

14.5.9 CSRR0 - Critical Save/Restore Register 0 ........................................................................ 550

14.5.10 CSRR1 - Critical Save/Restore Register 1 ...................................................................... 551

14.5.11 CTR - Count Register ...................................................................................................... 553

14.5.12 DAC1 - Data Address Compare 1 ................................................................................... 554

14.5.13 DAC2 - Data Address Compare 2 ................................................................................... 555

14.5.14 DAC3 - Data Address Compare 3 ................................................................................... 556

Version 1.3 October 23, 2012

Contents

Page 15 of 864

User’s Manual

A2 Processor

14.5.15 DAC4 - Data Address Compare 4 .................................................................................... 557

14.5.16 DBCR0 - Debug Control Register 0 ................................................................................. 558

14.5.17 DBCR1 - Debug Control Register 1 ................................................................................. 560

14.5.18 DBCR2 - Debug Control Register 2 ................................................................................. 562

14.5.19 DBCR3 - Debug Control Register 3 ................................................................................. 564

14.5.20 DBSR - Debug Status Register ........................................................................................ 565

14.5.21 DBSRWR - Debug Status Register Write Register .......................................................... 567

14.5.22 DEAR - Data Exception Address Register ....................................................................... 569

14.5.23 DEC - Decrementer ......................................................................................................... 570

14.5.24 DECAR - Decrementer Auto-Reload ............................................................................... 571

14.5.25 DVC1 - Data Value Compare 1 ........................................................................................ 572

14.5.26 DVC2 - Data Value Compare 2 ........................................................................................ 573

14.5.27 EPCR - Embedded Processor Control Register .............................................................. 574

14.5.28 EPLC - External Process ID Load Context ...................................................................... 576

14.5.29 EPSC - External Process ID Store Context ..................................................................... 577

14.5.30 EPTCFG - Embedded Page Table Configuration Register .............................................. 578

14.5.31 ESR - Exception Syndrome Register ............................................................................... 579

14.5.32 GDEAR - Guest Data Exception Address Register ......................................................... 581

14.5.33 GESR - Guest Exception Syndrome Register ................................................................. 582

14.5.34 GIVPR - Guest Interrupt Vector Prefix Register ............................................................... 584

14.5.35 GPIR - Guest Processor ID Register ............................................................................... 585

14.5.36 GSPRG0 - Guest Software Special Purpose Register 0 ................................................. 586

14.5.37 GSPRG1 - Guest Software Special Purpose Register 1 ................................................. 587

14.5.38 GSPRG2 - Guest Software Special Purpose Register 2 ................................................. 588

14.5.39 GSPRG3 - Guest Software Special Purpose Register 3 ................................................. 589

14.5.40 GSRR0 - Guest Save/Restore Register 0 ........................................................................ 590

14.5.41 GSRR1 - Guest Save/Restore Register 1 ........................................................................ 591

14.5.42 HACOP - Hypvervisor Available Coprocessor ................................................................. 593

14.5.43 IAC1 - Instruction Address Compare 1 ............................................................................ 594

14.5.44 IAC2 - Instruction Address Compare 2 ............................................................................ 595

14.5.45 IAC3 - Instruction Address Compare 3 ............................................................................ 596

14.5.46 IAC4 - Instruction Address Compare 4 ............................................................................ 597

14.5.47 IAR - Instruction Address Register ................................................................................... 598

14.5.48 IESR1 - IU Event Select Register 1 ................................................................................. 599

14.5.49 IESR2 - IU Event Select Register 2 ................................................................................. 600

14.5.50 IMMR - Instruction Match Mask Register ......................................................................... 601

14.5.51 IMPDEP0 - Implementation Dependent Region 0 ........................................................... 602

14.5.52 IMPDEP1 - Implementation Dependent Region 1 ........................................................... 603

14.5.53 IMR - Instruction Match Register ..................................................................................... 604

14.5.54 IUCR0 - Instruction Unit Configuration Register 0 ........................................................... 605

14.5.55 IUCR1 - Instruction Unit Configuration Register 1 ........................................................... 606

14.5.56 IUCR2 - Instruction Unit Configuration Register 2 ........................................................... 607

14.5.57 IUDBG0 - Instruction Unit Debug Register 0 ................................................................... 608

14.5.58 IUDBG1 - Instruction Unit Debug Register 1 ................................................................... 609

14.5.59 IUDBG2 - Instruction Unit Debug Register 2 ................................................................... 610

14.5.60 IULFSR - Instruction Unit LFSR ....................................................................................... 611

14.5.61 IULLCR - Instruction Unit Live Lock Control Register ...................................................... 612

14.5.62 IVPR - Interrupt Vector Prefix Register ............................................................................ 613

14.5.63 LPER - Logical Page Exception Register ........................................................................ 614

14.5.64 LPERU - Logical Page Exception Register (Upper) ......................................................... 615

Contents

Page 16 of 864

Version 1.3

October 23, 2012

User’s Manual

A2 Processor

14.5.65 LPIDR - Logical Partition ID Register .............................................................................. 616

14.5.66 LR - Link Register ............................................................................................................ 617

14.5.67 LRATCFG - LRAT Configuration Register ....................................................................... 618

14.5.68 LRATPS - LRAT Page Size Register .............................................................................. 619

14.5.69 MAS0 - MMU Assist Register 0 ....................................................................................... 620

14.5.70 MAS0_MAS1 - MMU Assist Registers 0 and 1 ............................................................... 621

14.5.71 MAS1 - MMU Assist Register 1 ....................................................................................... 622

14.5.72 MAS2 - MMU Assist Register 2 ....................................................................................... 624

14.5.73 MAS2U - MMU Assist Register 2 (Upper) ....................................................................... 625

14.5.74 MAS3 - MMU Assist Register 3 ....................................................................................... 626

14.5.75 MAS4 - MMU Assist Register 4 ....................................................................................... 628

14.5.76 MAS5 - MMU Assist Register 5 ....................................................................................... 629

14.5.77 MAS5_MAS6 - MMU Assist Registers 5 and 6 ............................................................... 630

14.5.78 MAS6 - MMU Assist Register 6 ....................................................................................... 631

14.5.79 MAS7 - MMU Assist Register 7 ....................................................................................... 632

14.5.80 MAS7_MAS3 - MMU Assist Registers 7 and 3 ............................................................... 633

14.5.81 MAS8 - MMU Assist Register 8 ....................................................................................... 634

14.5.82 MAS8_MAS1 - MMU Assist Registers 8 and 1 ............................................................... 635

14.5.83 MCSR - Machine Check Syndrome Register .................................................................. 636

14.5.84 MCSRR0 - Machine Check Save/Restore Register 0 ..................................................... 638

14.5.85 MCSRR1 - Machine Check Save/Restore Register 1 ..................................................... 639

14.5.86 MESR1 - MMU Event Select Register 1 .......................................................................... 641

14.5.87 MESR2 - MMU Event Select Register 2 .......................................................................... 642

14.5.88 MMUCFG - MMU Configuration Register ........................................................................ 643

14.5.89 MMUCR0 - Memory Management Unit Control Register 0 ............................................. 644

14.5.90 MMUCR1 - Memory Management Unit Control Register 1 ............................................. 645

14.5.91 MMUCR2 - Memory Management Unit Control Register 2 ............................................. 647

14.5.92 MMUCR3 - Memory Management Unit Control Register 3 ............................................. 649

14.5.93 MMUCSR0 - MMU Control and Status Register 0 .......................................................... 650

14.5.94 MSR - Machine State Register ........................................................................................ 651

14.5.95 MSRP - Machine State Register Protect ......................................................................... 653

14.5.96 PID - Process ID .............................................................................................................. 654

14.5.97 PIR - Processor ID Register ............................................................................................ 655

14.5.98 PPR32 - Program Priority Register .................................................................................. 656

14.5.99 PVR - Processor Version Register .................................................................................. 657

14.5.100 SPRG0 - Software Special Purpose Register 0 ............................................................ 658

14.5.101 SPRG1 - Software Special Purpose Register 1 ............................................................ 659

14.5.102 SPRG2 - Software Special Purpose Register 2 ............................................................ 660

14.5.103 SPRG3 - Software Special Purpose Register 3 ............................................................ 661

14.5.104 SPRG4 - Software Special Purpose Register 4 ............................................................ 662

14.5.105 SPRG5 - Software Special Purpose Register 5 ............................................................ 663

14.5.106 SPRG6 - Software Special Purpose Register 6 ............................................................ 664

14.5.107 SPRG7 - Software Special Purpose Register 7 ............................................................ 665

14.5.108 SPRG8 - Software Special Purpose Register 8 ............................................................ 666

14.5.109 SRR0 - Save/Restore Register 0 ................................................................................... 667

14.5.110 SRR1 - Save/Restore Register 1 ................................................................................... 668

14.5.111 TB - Timebase ............................................................................................................... 670

14.5.112 TBL - Timebase Lower .................................................................................................. 671

14.5.113 TBU - Timebase Upper .................................................................................................. 672

14.5.114 TCR - Timer Control Register ........................................................................................ 673

Version 1.3 October 23, 2012

Contents

Page 17 of 864

User’s Manual

A2 Processor

14.5.115 TENC - Thread Enable Clear Register .......................................................................... 675

14.5.116 TENS - Thread Enable Set Register .............................................................................. 676

14.5.117 TENSR - Thread Enable Status Register ...................................................................... 677

14.5.118 TIR - Thread Identification Register ............................................................................... 678

14.5.119 TLB0CFG - TLB 0 Configuration Register ..................................................................... 679

14.5.120 TLB0PS - TLB 0 Page Size Register ............................................................................. 680

14.5.121 TRACE - Hardware Trace Macro Control Register ........................................................ 681

14.5.122 TSR - Timer Status Register .......................................................................................... 682

14.5.123 UDEC - User Decrementer ............................................................................................ 683

14.5.124 VRSAVE - Vector Register Save ................................................................................... 684

14.5.125 XER - Fixed Point Exception Register ........................................................................... 685

14.5.126 XESR1 - XU Event Select Register 1 ............................................................................ 686

14.5.127 XESR2 - XU Event Select Register 2 ............................................................................ 687

14.5.128 XESR3 - XU Event Select Register 3 ............................................................................ 688

14.5.129 XESR4 - XU Event Select Register 4 ............................................................................ 689

14.5.130 XUCR0 - Execution Unit Configuration Register 0 ......................................................... 690

14.5.131 XUCR1 - Execution Unit Configuration Register 1 ......................................................... 693

14.5.132 XUCR2 - Execution Unit Configuration Register 2 ......................................................... 694

14.5.133 XUCR3 - Execution Unit Configuration Register 3 ......................................................... 695

14.5.134 XUCR4 - Execution Unit Configuration Register 4 ......................................................... 696

14.5.135 XUDBG0 - Execution Unit Debug Register 0 ................................................................. 697

14.5.136 XUDBG1 - Execution Unit Debug Register 1 ................................................................. 698

14.5.137 XUDBG2 - Execution Unit Debug Register 2 ................................................................. 699

15. SCOM Accessible Registers ................................................................................. 701

15.1 Serial Communications (SCOM) Description .............................................................................. 701

15.2 SCOM Register Summary ........................................................................................................... 703

15.2.1 Read and Write Access Methods ....................................................................................... 703

15.2.1.1 Reset with AND Mask ................................................................................................. 703

15.2.1.2 Set with OR Mask ....................................................................................................... 703

15.2.2 SCOM Register Summary Table ....................................................................................... 703

15.3 Alphabetical Register Listing ....................................................................................................... 705

15.3.1 AXU Debug Select Register (ABDSR) ............................................................................... 705

15.3.2 Error Injection Register (ERRINJ) ...................................................................................... 706

15.3.3 Fault Isolation Register 0 and Associated Registers ......................................................... 707

15.3.4 Fault Isolation Register 1 and Associated Registers ......................................................... 711

15.3.5 Fault Isolation Register 2 and Associated Registers ......................................................... 716

15.3.6 IU Debug Select Register (IDSR) ...................................................................................... 720

15.3.7 MMU/PC Debug Select Register (MPDSR) ....................................................................... 723

15.3.8 PC Configuration Register 0 (PCCR0) ............................................................................... 725

15.3.9 Ram Data Registers (RAMD, RAMDH, RAMDL) ............................................................... 726

15.3.10 Ram Instruction and Command Registers (RAMC, RAMI, RAMIC) ................................ 727

15.3.11 Special Attention Register (SPATTN) .............................................................................. 729

15.3.12 Thread Control and Status Register (THRCTL) ............................................................... 730

15.3.13 XU Debug Select Register1 (XDSR1) .............................................................................. 731

15.3.14 XU Debug Select Register2 (XDSR2) .............................................................................. 734

Contents

Page 18 of 864

Version 1.3

October 23, 2012

User’s Manual

A2 Processor

Appendix A. Processor Instruction Summary ......................................................... 737

A.1 Instruction Formats ....................................................................................................................... 737

A.2 Implemented Instructions Sorted by Mnemonic ............................................................................ 737

Appendix B. FU Instruction Summary ...................................................................... 756

B.1 FU Instructions Sorted by Opcode ................................................................................................ 756

Appendix C. Debug and Trigger Groups .................................................................. 761

C.1 Unit Debug Multiplexer Component .............................................................................................. 761

C.2 Debug Multiplexer Component Ordering on the Ramp Bus ......................................................... 761

C.3 Example Debug Multiplexer Configuration Settings ..................................................................... 762

C.3.1 Multiplexer Configuration for Trace/Trigger Signals from a Single Unit .............................. 762

C.3.2 Multiplexer Configuration for Trace/Trigger Signals from Multiple Units ............................. 762

C.4 AXU Debug Select Register and Debug Group Tables ................................................................ 763

C.5 IU Debug Select Register and Debug Group Tables .................................................................... 766

C.6 MMU and PC Debug Select Register and Debug Group Tables .................................................. 778

C.7 XU Debug Select Register1 and Debug Group Tables ................................................................ 798

C.8 XU Debug Select Register2 and Debug Group Tables ................................................................ 817

Appendix D. Instruction Execution Performance and Code Optimizations .......... 833

D.1 A2 Pipeline Overview ................................................................................................................... 833

D.1.1 Arbitration Stages ............................................................................................................... 834

D.1.2 Stall Stages ......................................................................................................................... 835

D.1.3 Flush Stages ....................................................................................................................... 835

D.2 Fetch ............................................................................................................................................. 835

D.2.1 Fetch Arbitration .................................................................................................................. 837

D.2.2 Next Instruction Fetch Address Computation ..................................................................... 837

D.2.3 Instruction Cache Access and Alignment ........................................................................... 837

D.2.4 Instruction Cache Misses .................................................................................................... 837

D.2.5 I-ERAT Misses .................................................................................................................... 838

D.2.6 Instruction Buffer Operation ................................................................................................ 838

D.2.7 Branches and Branch Prediction ........................................................................................ 838

D.2.7.1 Branch Direction Prediction and the Branch History Table (BHT) ............................... 840

D.2.7.2 Taken-Branch Redirection ........................................................................................... 840

D.2.7.3 Branch Target Prediction ............................................................................................. 840

D.2.7.4 Branch Resolution and Mispredictions ........................................................................ 841

D.3 Instruction Issue Operation ........................................................................................................... 841

D.4 Instruction Pair Execution Performance Rules ............................................................................. 841

D.4.1 Defining Latency, Penalty, and Execution Time ................................................................. 841

D.4.2 Unified CR Dependency ..................................................................................................... 842

D.4.3 General CR Operand Dependency ..................................................................................... 842

D.4.4 Move To Condition Register Fields (mtcrf) Instruction Dependency ................................... 843

D.4.5 Move From Condition Register (mfcr) Instruction Dependency .......................................... 843

D.4.6 Move From and Move To Special Purpose Register (mfspr) Dependency ......................... 843

D.4.7 Move From Machine State Register (mfmsr) Dependency ................................................. 843

D.4.8 Multiply Dependency ........................................................................................................... 843

D.4.9 Divide Dependency ............................................................................................................. 844

D.4.10 Store Word Conditional Indexed (stwcx.) Instruction Dependency ................................... 844

Version 1.3 October 23, 2012

Contents

Page 19 of 864

User’s Manual

A2 Processor

D.4.11 TLB Management Instruction Dependencies .................................................................... 845

D.4.12 Processor Control Instruction Operation ........................................................................... 845

D.4.13 Load Instruction Dependency ............................................................................................ 846

D.4.14 String/Multiple Operations ................................................................................................. 846

D.4.15 Load-and-Reserve and Store-Conditional Instructions ..................................................... 846

D.4.16 Storage Synchronization Operations ................................................................................. 847

D.5 Loads, Stores, and Data Cache Organization .............................................................................. 847

D.5.1 Overview ............................................................................................................................. 847

D.5.2 Loads ................................................................................................................................... 848

D.5.3 Stores .................................................................................................................................. 848

D.5.4 Load Miss Queue ................................................................................................................ 849

D.5.5 L2 Command Arbitration ..................................................................................................... 849

D.5.6 D-ERAT Misses ................................................................................................................... 849

D.5.7 Back Invalidations ............................................................................................................... 849

D.5.8 Address Alignment .............................................................................................................. 849

D.6 Interrupt Effects ............................................................................................................................ 850

D.7 Floating-Point Instruction Handling ............................................................................................... 850

D.7.1 General FPR Operand Dependency ................................................................................... 852

D.7.2 Denormalized Results ......................................................................................................... 852

D.7.3 Denormalized Operands ..................................................................................................... 852

D.7.4 Not a Number (NaN) Cases ................................................................................................ 852

D.7.5 Floating-Point Load Dependency ........................................................................................ 852

D.7.6 Floating-Point Store Data Dependency ............................................................................... 852

D.7.7 General CR Operand Dependency ..................................................................................... 853

D.7.8 Floating-Point Divide Dependency ...................................................................................... 853

D.7.9 Floating-Point Square Root Dependency ............................................................................ 853

D.7.10 Move to Condition Register from Floating-Point Status and Control Register Dependency ....

853

D.7.11 Move to FPSCR Fields and FPSCR Dependencies .......................................................... 854

D.7.12 Floating-Point Record Forms ............................................................................................ 854

D.8 Interrupt Conditions ...................................................................................................................... 854

D.9 Flush Conditions ........................................................................................................................... 858

Appendix E. Programming Examples ........................................................................ 861

E.1 Wait Instruction with Fast Wakeup for Power Savings ................................................................. 861

E.2 Floating-Point Conversions ........................................................................................................... 861

E.2.1 Conversion from Floating-Point Number to Signed Integer Word ....................................... 861

E.2.2 Conversion from Floating-Point Number to Unsigned Integer Word ................................... 862

E.3 Floating-Point Selection ................................................................................................................ 862

E.3.1 Comparison to Zero ............................................................................................................. 863

E.3.2 Minimum and Maximum ...................................................................................................... 863

E.3.3 Simple If-Then-Else Constructions ...................................................................................... 863

E.4 Notes ............................................................................................................................................. 863

Contents

Page 20 of 864

Version 1.3

October 23, 2012

User’s Manual

A2 Processor

List of Figures

Figure 1-1. A2 Core Organization ............................................................................................................. 50

Figure 1-2. A2 Processor Block Diagram ................................................................................................. 56

Figure 2-1. A2 Core Instruction Unit ......................................................................................................... 79

Figure 2-2. Instruction Issue Timing Diagram 1 ........................................................................................ 80

Figure 2-3. Instruction Issue Timing Diagram 2 ........................................................................................ 81

Figure 2-4. Instruction Issue Timing Diagram 3 ........................................................................................ 81

Figure 2-5. User Programming Model Registers ...................................................................................... 83

Figure 3-1. Approximation to Real Numbers .......................................................................................... 135

Figure 3-2. Selection of z1 and z2 .......................................................................................................... 140

Figure 4-1. Software-Initiated Reset Request Overview ........................................................................ 163

Figure 6-1. Virtual Address to TLB Entry Match Process ....................................................................... 190

Figure 6-2. Effective-to-Real Address Translation Flow ......................................................................... 192

Figure 6-3. ERAT Entry Word Definitions ............................................................................................... 220

Figure 6-4. ERAT Entry Word Definitions for 32-Bit Mode ..................................................................... 227

Figure 6-5. Indirect Entry to Page Table Size Calculation ...................................................................... 238

Figure 6-6. Page Table Entry Format ..................................................................................................... 239

Figure 9-1. Relationship of Timer Facilities to the Time Base ................................................................ 387

Figure 9-2. Watchdog State Machine ..................................................................................................... 395

Figure 10-1. Pass-Through Trace and Trigger Bus Overview .................................................................. 446

Figure 10-2. Trace and Trigger Bus Unit Description ............................................................................... 447

Figure 11-1. Performance Event Selection Overview ............................................................................... 449

Figure 11-2. Core Event Multiplexer Description ...................................................................................... 451

Figure 11-3. A2 Common Unit Event Multiplexer Component .................................................................. 456

Figure 12-1. ICSWX (RS

Figure 12-2. Coprocessor Command Word (CCW) .................................................................................. 518

Figure 12-3. Generic Coprocessor-Request Block ................................................................................... 520

Figure 15-1. Chip Level Infrastructure Example to Access SCOM Registers in the A2 Core .................. 702

Figure 15-2. Principle Timing of Information Carried on CCH and DCH .................................................. 702

Figure C-1. Debug Multiplexer Component ............................................................................................. 761

Figure D-1. A2 Pipeline Structure ........................................................................................................... 833

Figure D-2. Instruction Cache ................................................................................................................. 836

Figure D-3. Branch Prediction ................................................................................................................. 839

Figure D-4. FU Dataflow ......................................................................................................................... 851

) Coprocessor-Command Word ................................................................. 517

32:63

Version 1.3 October 23, 2012

List of Figures

Page 21 of 864

User’s Manual

A2 Processor

List of Figures

Page 22 of 864

Version 1.3

October 23, 2012

User’s Manual

A2 Processor

List of Tables

Table 2-1. Data Operand Definitions ....................................................................................................... 63

Table 2-2. Alignment Effects for Storage Access Instructions ................................................................ 63

Table 2-3. Priority Levels ......................................................................................................................... 76

Table 2-4. Other “or” Instruction Hints ..................................................................................................... 76

Table 2-5. Program Priority Register (PPR32) ........................................................................................ 76

Table 2-6. Register Mapping ................................................................................................................... 84

Table 2-7. Category Listing ..................................................................................................................... 86

Table 2-8. Instruction Categories ............................................................................................................ 89

Table 2-9. Integer Storage Access Instructions ...................................................................................... 90

Table 2-10. Integer Storage Access Instructions by External Process ID ................................................. 90

Table 2-11. Operand Handling Dependent on Alignment ......................................................................... 90

Table 2-12. Integer Arithmetic Instructions ................................................................................................ 91

Table 2-13. Integer Logical Instructions .................................................................................................... 92

Table 2-14. Integer Compare Instructions ................................................................................................. 92

Table 2-15. Integer Trap Instructions ........................................................................................................ 92

Table 2-16. Integer Rotate Instructions ..................................................................................................... 93

Table 2-17. Integer Shift Instructions ........................................................................................................ 93

Table 2-18. Integer Population Count Instructions .................................................................................... 93

Table 2-19. Integer Select Instruction ....................................................................................................... 93

Table 2-20. Branch Instructions ................................................................................................................ 94

Table 2-21. Condition Register Logical Instructions .................................................................................. 94

Table 2-22. Register Management Instructions ........................................................................................ 95

Table 2-23. System Linkage Instructions .................................................................................................. 95

Table 2-24. Processor Control Instruction ................................................................................................. 95

Table 2-25. Cache Management Instructions ........................................................................................... 96

Table 2-26. Cache Management Instructions by External Process ID ...................................................... 96

Table 2-27. TLB Management Instructions ............................................................................................... 96

Table 2-28. Processor Synchronization Instruction ................................................................................... 97

Table 2-29. Load and Reserve and Store Conditional Instructions ........................................................... 97

Table 2-30. Storage Synchronization Instructions ..................................................................................... 97

Table 2-31. Wait Instruction ...................................................................................................................... 98

Table 2-32. Initiate Coprocessor Instructions ............................................................................................ 98

Table 2-33. Cache Initialization Instructions .............................................................................................. 98

Table 2-34. BO Field Encodings ............................................................................................................. 100

Table 2-35. ‘at’ Bit Encodings .................................................................................................................. 100

Table 2-36. CR Updating Instructions ..................................................................................................... 108

Table 2-37. GPR Registers ..................................................................................................................... 110

Table 2-38. XER[SO,OV] Updating Instructions ...................................................................................... 111

Version 1.3 October 23, 2012

List of Tables

Page 23 of 864

User’s Manual

A2 Processor

Table 2-39. XER[CA] Updating Instructions ............................................................................................111

Table 2-40. SPRG0 Register ...................................................................................................................114

Table 2-41. SPRG1 Register ...................................................................................................................114

Table 2-42. SPRG2 Register ...................................................................................................................115

Table 2-43. SPRG3 Register ...................................................................................................................115

Table 2-44. SPRG4 Register ...................................................................................................................115

Table 2-45. SPRG5 Register ...................................................................................................................116

Table 2-46. SPRG6 Register ...................................................................................................................116

Table 2-47. SPRG7 Register ...................................................................................................................116

Table 2-48. SPRG8 Register ...................................................................................................................117

Table 2-49. GSPRG0 Register ................................................................................................................117

Table 2-50. GSPRG1 Register ................................................................................................................117

Table 2-51. GSPRG2 Register ................................................................................................................118

Table 2-52. GSPRG3 Register ................................................................................................................118

Table 2-53. Privileged Instructions .......................................................................................................... 121

Table 3-1. Data Operand Definitions .....................................................................................................128

Table 3-2. Invalid Operation Exception Categories ............................................................................... 129

Table 3-3. Floating-Point Registers (FPR0–FPR31) ............................................................................. 130

Table 3-4. Floating-Point Status and Control Register (FPSCR) ...........................................................131

Table 3-5. Floating-Point Single Format ................................................................................................134

Table 3-6. Floating-Point Double Format ............................................................................................... 134

Table 3-7. Format Fields ........................................................................................................................134

Table 3-8. IEEE 754 Floating-Point Fields .............................................................................................134

Table 3-9. Rounding Modes .................................................................................................................. 140

Table 3-10. IEEE 64-Bit Execution Model ...............................................................................................141

Table 3-11. Interpretation of the G, R, and X Bits .................................................................................... 141

Table 3-12. Location of the Guard, Round, and Sticky Bits in the IEEE Execution Model ......................142

Table 3-13. Multiply-Add 64-Bit Execution Model ....................................................................................143

Table 3-14. Location of Guard, Round, and Sticky Bits in the Multiply-Add Execution Model .................143

Table 3-15. Floating-Point Load Instructions ...........................................................................................146

Table 3-16. Floating-Point Store Instructions ..........................................................................................147

Table 3-17. Floating-Point Move Instructions .......................................................................................... 148

Table 3-18. Floating-Point Elementary Arithmetic Instructions ................................................................148

Table 3-19. Floating-Point Multiply-Add Instructions ...............................................................................149

Table 3-20. Floating-Point Rounding and Conversion Instructions .........................................................150

Table 3-21. Comparison Sets ..................................................................................................................150

Table 3-22. Floating-Point Compare and Select Instructions .................................................................. 151

Table 3-23. Floating-Point Status and Control Register Instructions .......................................................151

Table 4-1. Register Reset Values ..........................................................................................................155

List of Tables

Page 24 of 864

Version 1.3

October 23, 2012

User’s Manual

A2 Processor

Table 4-2. Shadow TLB Array Entry Initialization .................................................................................. 158

Table 5-1. Data Cache Array Organization ........................................................................................... 169

Table 5-2. Cache Size and Parameters ................................................................................................ 169

Table 5-3. Instruction Cache Array Organization .................................................................................. 170

Table 5-4. Cache Size and Parameters ................................................................................................ 170

Table 5-5. XUCR Bits ............................................................................................................................ 183

Table 6-1. Page Size and Effective Address to EPN Comparison ........................................................ 191

Table 6-2. Page Size and Real Address Formation .............................................................................. 192

Table 6-3. Access Control Applied to Cache Management Instructions ............................................... 194

Table 6-4. TLB Entry Fields ................................................................................................................... 199

Table 6-5. ERAT Class Field Reload Value For UTLB Hits .................................................................. 208

Table 6-6. LRAT Entry Fields ................................................................................................................ 211

Table 6-7. TLB Management Instruction Privilege Levels ..................................................................... 212

Table 6-8. TLB Congruence Class Hashing Function (of EPN Address Bits) ....................................... 214

Table 6-9. Supported EPN[27:51] Field Values in Downbound TLBIVAX Request .............................. 218

Table 6-10. ERAT Management Instruction Privilege Levels .................................................................. 219

Table 6-11. Summary of Supported IS Field Values in ERATIVAX ........................................................ 222

Table 6-12. Supported EPN[27:51] Field Values in Downbound erativax Request ............................... 224

Table 6-13. TLB Reservation Fields ........................................................................................................ 233

Table 6-14. TLB Update After Page Table Translation ........................................................................... 242

Table 6-15. MAS Register Update Summary .......................................................................................... 275

Table 7-1. Register Mapping in Guest State ......................................................................................... 301

Table 7-2. Interrupt Types and Associated Offsets ............................................................................... 316

Table 7-3. Interrupt and Exception Types ............................................................................................. 323

Table 8-1. Invalid Operation Exception Categories ............................................................................... 372

Table 8-2. MSR[FE0, FE1] Modes ........................................................................................................ 374

Table 8-3. Invalid Operation Exceptions ............................................................................................... 376

Table 8-4. QNaN Result ........................................................................................................................ 381

Table 8-5. FPSCR[FPRF] Result Flags ................................................................................................. 382

Table 8-6. Floating-Point Status and Control Register (FPSCR) .......................................................... 383

Table 8-7. Bit Encodings for a CR Field ................................................................................................ 386

Table 9-1. Timebase Register (TB) ....................................................................................................... 388

Table 9-2. Timebase Lower Register (TBL) .......................................................................................... 388

Table 9-3. Timebase Upper Register (TBU) .......................................................................................... 389

Table 9-4. Decrementer Register (DEC) ............................................................................................... 390

Table 9-5. Decrementer Auto-Reload Register (DECAR) ..................................................................... 390

Table 9-6. Fixed Interval Timer Period Selection .................................................................................. 392

Table 9-7. Watchdog Timer Period Selection ........................................................................................ 393

Table 9-8. Watchdog Timer Exception Behavior ................................................................................... 394

Version 1.3 October 23, 2012

List of Tables

Page 25 of 864

User’s Manual

A2 Processor

Table 10-1. PCCR0[DBA] (Debug Action) Definition per Thread ............................................................ 400

Table 10-2. Debug Events .......................................................................................................................402

Table 10-3. Debug Event Summary ........................................................................................................415

Table 10-4. Ram Instruction and Command Register (RAMIC) ..............................................................431

Table 10-5. Ram Instruction Register (RAMI) ..........................................................................................431

Table 10-6. Ram Command Register (RAMC) ........................................................................................431

Table 10-7. Ram Data Register (RAMD) .................................................................................................433

Table 10-8. Ram Data Register High (RAMDH) ......................................................................................433

Table 10-9. Ram Data Register Low (RAMDL) ....................................................................................... 434

Table 10-10. Thread Control and Status Register (THRCTL) ...................................................................442

Table 10-11. PC Configuration Register 0 (PCCR0) .................................................................................444

Table 11-1. Core Event Multiplexer to External Event Bus ......................................................................451

Table 11-2. Performance Monitor Event Tags .........................................................................................457

Table 11-3. FU Performance Events Table .............................................................................................458

Table 11-4. IU Performance Events Table ..............................................................................................458

Table 11-5. XU Performance Events Table .............................................................................................460

Table 11-6. LSU Performance Events Table ...........................................................................................462

Table 11-7. MMU Performance Events Table .........................................................................................465

Table 11-8. Core Instruction Trace Data and Control Signals .................................................................477

Table 11-9. First Instruction Trace Record Format ..................................................................................477

Table 11-10. Format of Subsequent Instruction Trace Records ................................................................478

Table 11-11. Trace Record Type Decode and Instruction Trace Record Ordering ...................................478

Table 14-1. Register Summary ................................................................................................................530

Table 15-1. SCOM Register Summary ....................................................................................................703

Table 15-2. Error Injection Register .........................................................................................................706

Table 15-3. Fault Isolation Register 0 (FIR0) ........................................................................................... 708

Table 15-4. FIR0 Action1 Register (FIR0A1) ...........................................................................................709

Table 15-5. FIR0 Mask Register (FIR0M) ................................................................................................710

Table 15-6. FIR0 and FIR1 Registers (Read Only) ................................................................................. 711

Table 15-7. Fault Isolation Register 1 ......................................................................................................711

Table 15-8. FIR1 Action0 Register (FIR1A0) ...........................................................................................713

Table 15-9. FIR1 Action1 Register (FIR1A1) ...........................................................................................714

Table 15-10. FIR1 Mask Register (FIR1M) ................................................................................................714

Table 15-11. Fault Isolation Register 2 (FIR2) ........................................................................................... 716

Table 15-12. FIR2 Action0 Register (FIR2A0) ...........................................................................................717

Table 15-13. FIR2 Action1 Register (FIR2A1) ...........................................................................................718

Table 15-14. FIR2 Mask Register (FIR2M) ................................................................................................720

Table 15-15. PC Configuration Register 0 (PCCR0) .................................................................................725

Table 15-16. Ram Data Register (RAMD) .................................................................................................726

List of Tables

Page 26 of 864

Version 1.3

October 23, 2012

User’s Manual

A2 Processor

Table 15-17. Ram Data Register High (RAMDH) ...................................................................................... 726

Table 15-18. Ram Data Register Low (RAMDL) ....................................................................................... 727

Table 15-19. Ram Command Register (RAMC) ........................................................................................ 727

Table 15-20. Ram Instruction Register (RAMI) ......................................................................................... 729

Table 15-21. Ram Instruction and Command Register (RAMIC) .............................................................. 729

Table 15-22. Special Attention Register .................................................................................................... 729

Table 15-23. Thread Control and Status Register (THRCTL) ................................................................... 730

Table A-1. A2 Core Instructions by Mnemonic ...................................................................................... 738

Table B-1. FU Instructions by Opcode ................................................................................................... 756

Table C-1. AXU Debug Select Register (ADBSR) ................................................................................. 763

Table C-2. AXU Debug Multiplexer Debug and Trigger Groups ............................................................ 764

Table C-3. IU Debug Select Register (IDSR) ......................................................................................... 766

Table C-4. IU Debug Mux1 Debug and Trigger Groups ........................................................................ 768

Table C-5. IU Debug Mux2 Debug and Trigger Groups ........................................................................ 774

Table C-6. MMU and PC Debug Select Register (MPDSR) .................................................................. 778

Table C-7. MMU Debug Multiplexer Debug and Trigger Groups ........................................................... 781

Table C-8. PC Debug Multiplexer Debug and Trigger Groups .............................................................. 796

Table C-9. XU Debug Select Register1 (XDSR1) .................................................................................. 798

Table C-10. XU Debug Mux1 Debug and Trigger Groups ....................................................................... 800

Table C-11. XU Debug Mux2 Debug and Trigger Groups ....................................................................... 807

Table C-12. XU Debug Select Register2 (XDSR2) .................................................................................. 817

Table C-13. XU Debug Mux3 Debug and Trigger Groups ....................................................................... 819

Table C-14. XU Debug Mux4 Debug and Trigger Groups ....................................................................... 830

Table D-1. Multiply Instructions and Their Associated Latency ............................................................. 844

Table D-2. Divide Instructions and Their Associated Latency ............................................................... 844

Table D-3. SRAM Operations ................................................................................................................ 847

Table D-4. Interrupt Conditions .............................................................................................................. 854

Table D-5. Flush Conditions .................................................................................................................. 858

Version 1.3 October 23, 2012

List of Tables

Page 27 of 864

User’s Manual

A2 Processor

List of Tables

Page 28 of 864

Version 1.3

October 23, 2012

User’s Manual

A2 Processor

Revision Log

Each release of this document supersedes all previously released versions. The revision log lists all significant changes made to the document since its initial release. In the rest of the document, change bars in the margin indicate that the adjacent text was modified from the previous release of this document.

Revision Date Pages Description

October 23, 2012

657

May 25, 2011 — Version 1.2.

April 1, 2011 Version 1.1.

518 Added a programming note to Section 12.5.3 Execution.

90 Revised Table 2-11 Operand Handling Dependent on Alignment.

December 15, 2010 — Version 1.0. Initial release.

Version 1.3. Updated Section 14.5.99 PVR - Processor Version Register.

Removed “IBM Confidential.”

Version 1.3 October 23, 2012

Revision Log

Page 29 of 864

User’s Manual

A2 Processor

Revision Log

Page 30 of 864

Version 1.3

October 23, 2012

+ 834 hidden pages

IBM A2 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Title Page

Copyright and Disclaimer

Contents

List of Figures

List of Tables

Revision Log