HYNIX HV7131D Datasheet
HV7131D
Semiconductor Inc.
System IC SBU
DESCRIPTION
HV7131D is a highly integrated single chip CMOS color image sensor using Hynix 0.5um CMOS process
developed for image application to realize high efficiency R/G/B photo sensor. The sensor has 648X488 pixel
array , and in general color interpolation method using 3x3 spatial mask with window size 642X482 pixels may
be used for VGA(640X480) display mode. Each compact active pixel element has high photo-sensitivity and
converts photon energy to analog voltage signal. The sensor has three on-chip 8 bit Digital to Analog Convert
(DAC) and 648 comparators to digitize the pixel output. The three on-chip 8 bit DAC can be used for
independent R/G/B gain control. Hynix proprietary on-chip Correlated Double Sampling (CDS) circuit can
reduce Fixed Pattern Noise (FPN) dramatically. The whole 8 bit digital color raw data is directly available on
the package pins and just a few control signals are needed for whole chip control so that it is very easy to
configure CMOS imaging system.
CMOS IMAGE SENSOR
With 8-bit ADC
FEATURES
l 648 x 488 pixel array size l Full function control through standard I2C bus
l Active pixel size: 8um x 8um l Built-in Automatic Gain Control AGC
l High efficiency R/G/B photo sensors l 48Pin CLCC/PLCC
l Integrated 8-bit ADC for direct digital output l Bayer R/G/B color pattern
l Low power 3.3V operation (5V tolerant I/O) l Anti-blooming circuit
l Integrated pan control and window sizing l Flexible exposure time control
l Clock speed up to 15MHz l Integrated on-chip timing and drive control
l Programmable frame rate and synchronous format l 1/3" optical format
TECHNICAL SPECIFICATION FUNCTIONAL BLOCK DIAGRAM
Total Pixel Array 648x488
Effective Pixel Array 642x482
Pixel size 8x8um
2
Fill factor 30%
Format VGA
Sensitivity 3,150mV/lux·sec
Supply voltage for analog 3.3V
Supply voltage for digital 3.3V
I2C
Pixel Array
Control Register & Logic
Decoder/Pixel Driver
Supply voltage for 5V tolerant input 5.0V
Power Consumption (max.)
80mW @10MHz
Operating temperature 0~40 Centigrade
ADC Block
Line Buffer
Technology 0.5um 2metal CMOS
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 1 - 2001 Hy nix System IC SBU
HV7131D
Semiconductor Inc.
System IC SBU
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
l Supply voltage(Analog, Digital) : 3.0 V ~ 3.6 V
l Voltage on any input pins : 0 V ~ 5.0 V
l Operating Temperature(Centigrade) : 0 ~ 40
l Storage Temperature(Centigrade) : -30 ~ 80
Note : Input pins are 5V tolerant. Stresses exceeding the absolute maximum ratings may induce failure.
DC Operating Conditions
CMOS IMAGE SENSOR
With 8-bit ADC
Symbol Parameter Units Min. Max. Load[pF] Notes
Vdd Internal operation supply voltage Volt 3.0 3.6
Vih Input voltage logic "1" Volt 2.0 5 6.5
Vil Input voltage logic "0" Volt 0 0.8 6.5
Voh Output voltage logic "1" Volt 2.15 3.6 60
Vol Output voltage logic "0" Volt 0.4 0.4 60
Ta Ambient operating temperature Celsius 0 40
AC Operating Conditions
Symbol Parameter Max Operation Frequency Units Notes
MCLK Main clock frequency 15 MHz 1
SCK I2C clock frequency 400 KHz 2
1. MCLK can be divided according to Clock Divide Register for internal clock.
2. SCK is driven by host processor. For the detail serial bus timing, refer to I
2
C Spec.
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 2 - 2001 Hy nix System IC SBU
HV7131D
Semiconductor Inc.
System IC SBU
ELECTRO-OPTICAL CHARACTERISTICS
Color temperature of light source: 3200K / IR cut-off filter (CM-500S, 1mm thickness) is used. --- 8)
Parameter Units Min. Typical Max. Note
Sensitivity mV / luxžsec 2100 3150 1)
Dark Signal mV 5 100 2)
Output Saturation Signal mV 1200 1250 3)
Dynamic Range dB 48 4)
Output Signal Shading % 8 13 5)
Dark Signal Shading mV/sec 3 300 6)
Frame Rate fps 45 7)
CMOS IMAGE SENSOR
With 8-bit ADC
Note:
1) Measured at 28lux illumination for exposure time 10ms.
2) Measured at zero illumination for exposure time 50ms. (T
3) Measured at Vdd =3.3V and 100lux illumination for exposure time 50ms.
4) 48dB is limited by 8-bit ADC.
5) Variance of average value of 4x4 pixels response of each block over all equal blacks at 50%
6) Range between V
7) Measured at MCLK 15MHz.
8) We recommend the IR cut-off filter with transmittance 50% at cut-off frequency 650nm for the real
Soldering
= 40 Centigrade)
temp
saturation level illumination for exposure time 10msec.
max
and V
at zero illumination for exposure time 50ms, where V
min
max
and V
the maximum and minimum values of each block’s response, respectively.
Integration time must be set in order for effective window height not to exceed window height.
It ’s because effective window height is directly proportional to integration time.
applications.
min
are
Infrared(IR) / Convection solder reflow condition
Parameter Units Min. Typical Max. Note
Peak Temperature Range Celsius - 230 240 1)
Note:
1) Time within 5 Celsius of actual peak temperature, 10sec
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 3 - 2001 Hy nix System IC SBU
MCLK
HV7131D
Semiconductor Inc.
System IC SBU
INPUT / OUTPUT AC CHARACTERISTICS
l All output timing delays are measured with output load 60[pF].
l Output delay include the internal clock path delay[6ns] and output driving delay that changes in
respect to the output load, the operating environment, and a board design.
l Due to the variable valid time delay of the output, output signals may be latched in the negative
edge of MCLK for the stable data transfer between the image sensor and a host for less than
15MHz operation.
MCLK to HSYNC/VSYNC Timing
T1 T1
CMOS IMAGE SENSOR
With 8-bit ADC
MCLK
HSYNC/VSYNC
T2
T1 : MCLK rising to HSYNC/VSYNC valid maximum Time : 18ns [output load: 60pF]
T2 : HSYNC/VSYNC valid Time : minimum 1clock(subject to T1, T2 timing rule)
MCLK to DATA Timing
T3
T3
DATA[7:0]
Valid DATA
T3 : MCLK rising to DATA Valid maximum Time : 18ns [output load: 60pF]
Note) HSYNC signal is high when valid data is on the DATA bus.
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 4 - 2001 Hy nix System IC SBU
Semiconductor Inc.
System IC SBU
INPUT / OUTPUT AC CHARACTERISTICS (Continue)
ENB Timing
HV7131D
CMOS IMAGE SENSOR
With 8-bit ADC
MCLK
ENB
T4 : ENB Setup Time : 5[ns]
T5 : ENB Hold Time : 5 [ns]
T6 : ENB Valid Time : minimum 2 Clock
RESET Timing
T5 T4
T6
Must in Valid(active low) state at least 8 MCLK periods
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 5 - 2001 Hy nix System IC SBU
Semiconductor Inc.
System IC SBU
INPUT / OUTPUT AC CHARACTERISTICS (Continue)
I2C Bus (Programming Serial Bus) Timing
stop start
HV7131D
CMOS IMAGE SENSOR
With 8-bit ADC
stopstart
SDA
SCK
tbuf
tlow
thd;sta
I2C Bus Interface Timing
Parameter Symbol Min. Max. Unit
SCK clock frequency f
Time that I2C bus must be free before a new
transmission can start
Hold time for a START thd;sta 1.0 - us
LOW period of SCK t
HIGH period of SCK t
Setup time for START tsu;sta 1.2 - us
tr
tf
thd;dat thigh tsu;dat tsu;sta tsu;sto
0 400 KHz
sck
t
1.2 - us
buf
1.2 - us
low
1.0 - us
high
thd;sta
Data hold time thd;dat 1.3 - us
Data setup time tsu;dat 250 - ns
Rise time of both SDA and SCK tr
-
250 ns
Fall time of both SDA and SCK tf - 300 ns
Setup time for STOP tsu;sto 1.2 - us
Capacitive load of each bus lines(SDA,SCK) Cb - - pf
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 6 - 2001 Hy nix System IC SBU
HV7131D
Read out
G B R G G
B
Semiconductor Inc.
System IC SBU
PIN CONFIGURATION (48 pin CLCC/PLCC)
TOP VIEW
Pin9~16, Pin19~20, Pin33~41 : No Connection
PIN NO.
1 SCK
2 DGND
3 ENB
4 DGND
5 MCLK
6 VDD5
7 AVDD
8 AGND
17 AGND
18 AVDD
21 DGND
22 DATA7
23 DATA6
24 DATA5
25 DATA4
NAME
COLOR PATTERN
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 7 - 2001 Hy nix System IC SBU
(647, 487)
DIE
487
486
R G
647
646
P in 1
1 0
CMOS IMAGE SENSOR
With 8-bit ADC
PIN NO.
NAME
26 DGND
27 DATA3
28 DATA2
29 DATA1
30 DATA0
31 DVDD
32 DGND
42 DVDD
43 RESET
44 VSYNC
45 HSYNC
46 DGND
47 SDA
48 DGND
[ Outline Top View ]
P ixel array
Origin (0,0)
[ Pixel Array ]
start point
Semiconductor Inc.
System IC SBU
PIN DESCRIPTION (48 Pin CLCC/PLCC)
PIN NAME I/O
1 SCK I I2C clock ; I2C clock control from I2C master
2 DGND I Digital Ground
3 ENB I
4 DGND I Digital Ground
5 MCLK I
6 VDD5 I I/O bias voltage for 5V tolerant *1)
7 AVDD I Analog Supply Voltage 3.3V
8 AGND I Analog Ground
9 ~ 16 N.C No Connection
17 AGND I Analog Ground
18 AVDD I Analog Supply Voltage 3.3V
19, 20 Reserved Reserved
21 DGND I Digital Ground
22 DATA7 O Image Data bit 7
23 DATA6 O Image Data bit 6
24 DATA5 O Image Data bit 5
25 DATA4 O Image Data bit 4
26 DGND I Digital Ground
27 DATA3 O Image Data bit 3
28 DATA2 O Image Data bit 2
29 DATA1 O Image Data bit 1
30 DATA0 O Image Data bit 0
31 DVDD I Digital Supply Voltage 3.3V
32 DGND I Digital Ground
33 ~ 41 N.C No Connection
42 DVDD I Digital Supply Voltage 3.3V
43 RESET I Hardware Reset Signal, Active Low
44 VSYNC O
45
46 DGND I Digital Ground
47 SDA I/O I2C Data ; I2C standard data I/O port
48 DGND I Digital Ground
HSYNC
/DVALID
Sensor Enable Signal ; 'H' enable normal operation
'L' disable
Master Clock (up to 15MHz)
; Global master clock for image sensor internal timing control
Vertical synchronization signal / Frame start output
; Signal pulse at start of image data frame with programmable
blanking duration
Horizontal synchronization signal / Data valid output
O
; Data valid when 'H' with programmable blanking duration
DESCRIPTION
HV7131D
CMOS IMAGE SENSOR
With 8-bit ADC
*1) Tie to DVDD for 3.3V operation / Tie to 5V for 5V tolerant operation
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 8 - 2001 Hynix System IC SBU
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