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HV7131D
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Datasheet (HYNIX)
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Datasheet HV7131D Datasheet (HYNIX)

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HV7131D
Semiconductor Inc. System IC SBU
DESCRIPTION
HV7131D is a highly integrated single chip CMOS color image sensor using Hynix 0.5um CMOS process developed for image application to realize high efficiency R/G/B photo sensor. The sensor has 648X488 pixel array , and in general color interpolation method using 3x3 spatial mask with window size 642X482 pixels may be used for VGA(640X480) display mode. Each compact active pixel element has high photo-sensitivity and converts photon energy to analog voltage signal. The sensor has three on-chip 8 bit Digital to Analog Convert (DAC) and 648 comparators to digitize the pixel output. The three on-chip 8 bit DAC can be used for independent R/G/B gain control. Hynix proprietary on-chip Correlated Double Sampling (CDS) circuit can reduce Fixed Pattern Noise (FPN) dramatically. The whole 8 bit digital color raw data is directly available on the package pins and just a few control signals are needed for whole chip control so that it is very easy to configure CMOS imaging system.
CMOS IMAGE SENSOR
FEATURES
l 648 x 488 pixel array size l Full function control through standard I2C bus l Active pixel size: 8um x 8um l Built-in Automatic Gain Control AGC l High efficiency R/G/B photo sensors l 48Pin CLCC/PLCC l Integrated 8-bit ADC for direct digital output l Bayer R/G/B color pattern l Low power 3.3V operation (5V tolerant I/O) l Anti-blooming circuit l Integrated pan control and window sizing l Flexible exposure time control l Clock speed up to 15MHz l Integrated on-chip timing and drive control l Programmable frame rate and synchronous format l 1/3" optical format
TECHNICAL SPECIFICATION FUNCTIONAL BLOCK DIAGRAM
Total Pixel Array 648x488 Effective Pixel Array 642x482 Pixel size 8x8um
2
Fill factor 30% Format VGA Sensitivity 3,150mV/lux·sec Supply voltage for analog 3.3V Supply voltage for digital 3.3V
I2C
Pixel Array
Control Register & Logic
Decoder/Pixel Driver
Supply voltage for 5V tolerant input 5.0V Power Consumption (max.)
80mW @10MHz
Operating temperature 0~40 Centigrade
ADC Block
Line Buffer
Technology 0.5um 2metal CMOS
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 1 - 2001 Hy nix System IC SBU
HV7131D
Semiconductor Inc. System IC SBU
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
l Supply voltage(Analog, Digital) : 3.0 V ~ 3.6 V l Voltage on any input pins : 0 V ~ 5.0 V
l Operating Temperature(Centigrade) : 0 ~ 40 l Storage Temperature(Centigrade) : -30 ~ 80
Note : Input pins are 5V tolerant. Stresses exceeding the absolute maximum ratings may induce failure.
DC Operating Conditions
CMOS IMAGE SENSOR
Symbol Parameter Units Min. Max. Load[pF] Notes
Vdd Internal operation supply voltage Volt 3.0 3.6
Vih Input voltage logic "1" Volt 2.0 5 6.5
Vil Input voltage logic "0" Volt 0 0.8 6.5
Voh Output voltage logic "1" Volt 2.15 3.6 60
Vol Output voltage logic "0" Volt 0.4 0.4 60
Ta Ambient operating temperature Celsius 0 40
AC Operating Conditions
Symbol Parameter Max Operation Frequency Units Notes
MCLK Main clock frequency 15 MHz 1
SCK I2C clock frequency 400 KHz 2
1. MCLK can be divided according to Clock Divide Register for internal clock.
2. SCK is driven by host processor. For the detail serial bus timing, refer to I
2
C Spec.
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 2 - 2001 Hy nix System IC SBU
HV7131D
Semiconductor Inc. System IC SBU
ELECTRO-OPTICAL CHARACTERISTICS
Color temperature of light source: 3200K / IR cut-off filter (CM-500S, 1mm thickness) is used. --- 8)
Parameter Units Min. Typical Max. Note
Sensitivity mV / luxžsec 2100 3150 1)
Dark Signal mV 5 100 2)
Output Saturation Signal mV 1200 1250 3)
Dynamic Range dB 48 4)
Output Signal Shading % 8 13 5)
Dark Signal Shading mV/sec 3 300 6)
Frame Rate fps 45 7)
CMOS IMAGE SENSOR
Note:
1) Measured at 28lux illumination for exposure time 10ms.
2) Measured at zero illumination for exposure time 50ms. (T
3) Measured at Vdd =3.3V and 100lux illumination for exposure time 50ms.
4) 48dB is limited by 8-bit ADC.
5) Variance of average value of 4x4 pixels response of each block over all equal blacks at 50%
6) Range between V
7) Measured at MCLK 15MHz.
8) We recommend the IR cut-off filter with transmittance 50% at cut-off frequency 650nm for the real
Soldering
= 40 Centigrade)
temp
saturation level illumination for exposure time 10msec.
max
and V
at zero illumination for exposure time 50ms, where V
min
max
and V
the maximum and minimum values of each block’s response, respectively.
Integration time must be set in order for effective window height not to exceed window height. It ’s because effective window height is directly proportional to integration time.
applications.
min
are
Infrared(IR) / Convection solder reflow condition
Parameter Units Min. Typical Max. Note
Peak Temperature Range Celsius - 230 240 1)
Note:
1) Time within 5 Celsius of actual peak temperature, 10sec
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 3 - 2001 Hy nix System IC SBU
MCLK
HV7131D
Semiconductor Inc. System IC SBU
INPUT / OUTPUT AC CHARACTERISTICS
l All output timing delays are measured with output load 60[pF]. l Output delay include the internal clock path delay[6ns] and output driving delay that changes in
respect to the output load, the operating environment, and a board design.
l Due to the variable valid time delay of the output, output signals may be latched in the negative
edge of MCLK for the stable data transfer between the image sensor and a host for less than 15MHz operation.
MCLK to HSYNC/VSYNC Timing
T1 T1
CMOS IMAGE SENSOR
MCLK
HSYNC/VSYNC
T2
T1 : MCLK rising to HSYNC/VSYNC valid maximum Time : 18ns [output load: 60pF] T2 : HSYNC/VSYNC valid Time : minimum 1clock(subject to T1, T2 timing rule)
MCLK to DATA Timing
T3
T3
DATA[7:0]
Valid DATA
T3 : MCLK rising to DATA Valid maximum Time : 18ns [output load: 60pF] Note) HSYNC signal is high when valid data is on the DATA bus.
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 4 - 2001 Hy nix System IC SBU
Semiconductor Inc. System IC SBU
INPUT / OUTPUT AC CHARACTERISTICS (Continue)
ENB Timing
HV7131D
CMOS IMAGE SENSOR
MCLK
ENB
T4 : ENB Setup Time : 5[ns] T5 : ENB Hold Time : 5 [ns] T6 : ENB Valid Time : minimum 2 Clock
RESET Timing
T5 T4
T6
Must in Valid(active low) state at least 8 MCLK periods
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 5 - 2001 Hy nix System IC SBU
Semiconductor Inc. System IC SBU
INPUT / OUTPUT AC CHARACTERISTICS (Continue)
I2C Bus (Programming Serial Bus) Timing
stop start
HV7131D
CMOS IMAGE SENSOR
stopstart
SDA
SCK
tbuf
tlow
thd;sta
I2C Bus Interface Timing
Parameter Symbol Min. Max. Unit
SCK clock frequency f
Time that I2C bus must be free before a new
transmission can start
Hold time for a START thd;sta 1.0 - us
LOW period of SCK t
HIGH period of SCK t
Setup time for START tsu;sta 1.2 - us
tr
tf
thd;dat thigh tsu;dat tsu;sta tsu;sto
0 400 KHz
sck
t
1.2 - us
buf
1.2 - us
low
1.0 - us
high
thd;sta
Data hold time thd;dat 1.3 - us
Data setup time tsu;dat 250 - ns
Rise time of both SDA and SCK tr
-
250 ns
Fall time of both SDA and SCK tf - 300 ns
Setup time for STOP tsu;sto 1.2 - us
Capacitive load of each bus lines(SDA,SCK) Cb - - pf
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 6 - 2001 Hy nix System IC SBU
HV7131D
Read out
G B R G G
B
Semiconductor Inc. System IC SBU
PIN CONFIGURATION (48 pin CLCC/PLCC)
TOP VIEW
Pin9~16, Pin19~20, Pin33~41 : No Connection
PIN NO.
1 SCK 2 DGND 3 ENB 4 DGND 5 MCLK 6 VDD5 7 AVDD
8 AGND 17 AGND 18 AVDD 21 DGND 22 DATA7 23 DATA6 24 DATA5 25 DATA4
NAME
COLOR PATTERN
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 7 - 2001 Hy nix System IC SBU
(647, 487)
DIE
487 486
R G
647
646
P in 1
1 0
CMOS IMAGE SENSOR
PIN NO.
NAME
26 DGND 27 DATA3 28 DATA2 29 DATA1 30 DATA0 31 DVDD 32 DGND 42 DVDD 43 RESET 44 VSYNC 45 HSYNC 46 DGND 47 SDA 48 DGND
[ Outline Top View ]
P ixel array
Origin (0,0)
[ Pixel Array ]
start point
Semiconductor Inc. System IC SBU
PIN DESCRIPTION (48 Pin CLCC/PLCC)
PIN NAME I/O
1 SCK I I2C clock ; I2C clock control from I2C master 2 DGND I Digital Ground
3 ENB I 4 DGND I Digital Ground 5 MCLK I 6 VDD5 I I/O bias voltage for 5V tolerant *1)
7 AVDD I Analog Supply Voltage 3.3V 8 AGND I Analog Ground
9 ~ 16 N.C No Connection
17 AGND I Analog Ground 18 AVDD I Analog Supply Voltage 3.3V
19, 20 Reserved Reserved
21 DGND I Digital Ground 22 DATA7 O Image Data bit 7 23 DATA6 O Image Data bit 6 24 DATA5 O Image Data bit 5 25 DATA4 O Image Data bit 4 26 DGND I Digital Ground 27 DATA3 O Image Data bit 3 28 DATA2 O Image Data bit 2 29 DATA1 O Image Data bit 1 30 DATA0 O Image Data bit 0 31 DVDD I Digital Supply Voltage 3.3V 32 DGND I Digital Ground
33 ~ 41 N.C No Connection
42 DVDD I Digital Supply Voltage 3.3V 43 RESET I Hardware Reset Signal, Active Low
44 VSYNC O
45 46 DGND I Digital Ground
47 SDA I/O I2C Data ; I2C standard data I/O port 48 DGND I Digital Ground
HSYNC
/DVALID
Sensor Enable Signal ; 'H' enable normal operation 'L' disable
Master Clock (up to 15MHz) ; Global master clock for image sensor internal timing control
Vertical synchronization signal / Frame start output ; Signal pulse at start of image data frame with programmable blanking duration
Horizontal synchronization signal / Data valid output
O
; Data valid when 'H' with programmable blanking duration
DESCRIPTION
HV7131D
CMOS IMAGE SENSOR
*1) Tie to DVDD for 3.3V operation / Tie to 5V for 5V tolerant operation
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 8 - 2001 Hynix System IC SBU
Semiconductor Inc.
Selects integration time unit between line unit and pixel unit. Commonly
luminance or when
Selects continuous frame output and single frame output. When single shot mode is selected, only one frame data is produced and the sensor goes to
Selects imaging array size between programmable window size and full
default
size is 641x482. [Window size is determined by RowStartAddress, Column
data valid
erence
, and image data is deducted by reference data in order to
reduce Fixed Pattern Noise. Generally the technique is called Correlated
Selects sensor operation mode among normal sensing mode and chip test
System IC SBU
CMOS IMAGE SENSOR
REGISTER DESCRIPTION
MODE_A[8’h00]
Represent device identity. High nibble: Sensor Array Size, Low Nibble: Revision Number For HV7131D, identity value is 8’h00, [VGA: 0, Revision 0]
MODE_B[8’h01]
This is operating mode B selection register. Each bit's description is as below.
Bit Function Description
HV7131D
0 Integration time unit
1 Single Frame mode
2 Window Mode
3 HSYNC output mode
4,5 Output data type
line unit is used for its large step control, but under high precise control is needed in the case such as anti-flicker , pixel unit control is used. Default is line unit mode[0].
idle mode. Default is continuous frame output mode[0].
size [648x488]. Default is window size mode[1] and current window StartAddress, WindowWidth, WindowHeight Registers.]
Selects HSYNC output mode between “data valid mode” and “ with clock mode”. Default is data valid mode[0].
Selects output data type among (data – reference), data only or ref only . Internally the sensor produces reference data and image data respectively
Double Sampling(CDS). Default is data - reference (CDS) [00].
6,7 Operation Mode
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 9 - 2001 Hynix System IC SBU
related modes. In normal use, the mode should be set to normal mode[00]. Default is normal operation mode[00].
Semiconductor Inc.
In One Gain Control mode, gain control is controlled by only G Gain Register
(0,487)
{FWWU, FWWL}
{FCSU, FCSL}
System IC SBU
MODE_C[8’h02]
This is operating mode C selection register. Each bit's description is as below.
Bit
1 Display Mode
Function
Selects Three Gain Control Mode or One Gain Control Mode Value
Description
FRAME SIZE CONTROL REGISTERS
HV7131D may image any user specified window area within image sensor array(648x488). This is called panning function, and for this function, FRS(Frame Row Start), FCS(Frame Column Start), FWH(Frame Window Height), and FWW(Frame Window Width) are used. Panning window can be programmed as below.
HV7131D
CMOS IMAGE SENSOR
(647,487)
(646,486)
Metal Shielding
(644,484)
{FWHU, FWHL}
(3,3)
{FRSU, FRSL}
(1,1)
(0,0)
Note1) Metal shielded pixel element produce black level data, and effective image array size 646 x 486. In general, color interpolation algorithm using 3x3 spatial mask for mosaic CFA single sensor require that
pixels around the edge of a programmed image window are used for just color interpolation of neighbor pixels. Accounting for this fact, image array window should be programmed to larger value than the size that is to be displayed. For example, in order to make 640X480 24bit color image data, 642X482 pixel array is necessary. That is to say, you can use the maximum window size as 642{FWWL, FWWL}X 482{FWHU, FWHL} and you must use Row Start Address and Column Start Address from (3, 3) to (644,
484) for getting 642X482 raw image data. Note2) You have to change the frame register value as below to get the full 640X480 window size.
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 10 - 2001 Hynix System IC SBU
{FRSU, FRSL} 3 {FWHU, FWHL} 482 {FCSU, FCSL} 3 {FWWU, FWWL } 642
Semiconductor Inc. System IC SBU
TIMING CONTROL REGISTERS
l HSYNC blank register[8’h20-8’h21]
The HSYNC Blank register defines data blank time between current line and next line by pixel clock unit. The value programmed to HSYNC blank register defines HSYNC Low Time with (Sensor Array Width – Window Width) clocks added. For example, if Window Width = 500, HSYNC Blank = 10, then HSYNC Low Time is HSYNC Blank + (Sensor Array Width – Window Width), 10 + (648 – 500) = 158 clocks.
Window Width(500)
HSYNC Low Time(158)
CMOS IMAGE SENSOR
Window Width(500)
HV7131D
Sensor Array Width(648)
Sensor Array Width(648)
HSYNC Blank(10)
For more timing details, refer to Frame Timing Diagram section.
l VSYNC blank register[8’h22-8’h23]
The VSYNC blank register defines the active high duration of VSYNC output by pixel clock unit. The active high VSYNC indicates frame boundary between continuous frames. For VSYNC-HSYNC timing relation in the frame transition, please refer to Frame Timing Diagram section.
l Integration time value register [8’h25-8’h27]
Integration time value register defines the time during which active pixel element evaluates photon energy that is converted to digital data output by internal ADC processing. Integration time is equivalent to exposure time in general camera so that integration time need to be increased in dark environment and decreased in light environment. Integration time unit is selected between pixel unit and line unit by MODE_B[0] bit. When line unit mode is selected, only two lower bytes of Integration time value register[8’h26-8’h27] are accounted in the internal sensor logic because represent able maximum integration time, Maximum Value(216-1) * Sensor Array Width(648) * Clock Period(100ns for 10Mhz) =
4.246 sec, is quite big enough to adapt to any very dark environment. For pixel unit mode, whole three bytes value are used for integration time, Integration Time Value(8’h25-8’h27) * Clock Period, and represent able maximum value is Maximum Value(224-1) * Clock Period(100ns for 10Mhz) = 1.677sec.
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 11 - 2001 Hynix System IC SBU
HV7131D
Semiconductor Inc. System IC SBU
l Master clock divider register
This four bits register is used to divide external pixel clock for internal use. The actual pixel operating frequency used in the se nsor is the same as external pixel frequency divided by divisor as below.
Register value Divisor Register value Divisor Register value Divisor
0 1 4 16 8 256 1 2 5 32 9 512 2 4 6 64 10 1024 3 8 7 128 11 2048
CHARATERISTICS ADJUSTMENT REGISTERS
Each sensor has a little different photo-diode characteristics so that the sensor provides internal adjustment registers that calibrate internal sensing circuit in order to get optimal performance. There are three kinds of registers as below.
CMOS IMAGE SENSOR
l Reset level regist er[8’h30]
The register controls the voltage level that is initially compared to pixel analog voltage, and the initial voltage level is called as “reference voltage level”. Internal DAC analog voltage decrements from reference voltage level until the pixel analog voltage output is lager than DAC analog voltage. Appropriate reference voltage level varies from various factors, such as process variation, luminance, etc. If the register value is set to too large or too small value, vertical fixed pattern noise may be produced. Therefore this register value must be programmed to appropriate value in order to avoid FPN. For the automatic reset level control, please refer to Reset Level Statistics Register Section. High register value means high reference voltage and large digital output. Program value range is 0~63, User should refer to the "RESET LEVEL CONTROL" application notes for proper using this register.
l RGB gain registers[8’h31-8’h33]
There are three color gain registers for R, G, B pixels, respectively. These registers are used to amplify digital pixel output . If the gain register value is decreased, digital pixel output is increased. That is, under dark light condition the pixel output is not enough to get right image so that we must amplify the output value by decreasing gain value to get good image. These registers may be used for white balance and color effect with independent R,G,B color control. Program value range is 0~63. However, we recommend that the range should be 30~60 for capturing good image quality.
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 12 - 2001 Hynix System IC SBU
HV7131D
Semiconductor Inc. System IC SBU
l Pixel bias voltage register[8’h34]
The register controls pixel analog voltage decrement degree by controlling bias current of pixel output sensing load transistor. With the reset level register(8’h30) it is used to adjust ADC circuit output characteristics. The larger register value causes the higher bias current to increase pixel output decrement degree, and commonly the register default value is used. Program value range is 0~7.
RESET LEVEL STATISTICS REGISTERS
l Low Reset Level Count[8’h57-8’h58]
This two-byte register has a value representing a eighth (1/8) of pixels that have reset value less than 3
CMOS IMAGE SENSOR
during one frame time and is updated when VSYNC gets active. With high reset level counter register it can be used as a parameter for external automatic reset level control logic that update the appropriate value in the reset level register to automatically compensate die to die overall reset level variation.
l High Reset Level Count[8’h59-8’h5a]
This two byte register has a value representing a eighth (1/8) of pixels that have reset value larger than 123 during one frame time and is updated when VSYNC gets active. With low reset level counter register it can be used as a parameter for external automatic reset level control logic that update the appropriate value in the reset level (30H) register to automatically compensate die to die overall reset level variation.
RGB OFFSET REGISTER S[8’h50-8’h52] These registers control offset value of RGB digital output to make color effect. Normally these register
values are set to default zero. So, these registers should be used for the purpose of test only.
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 13 - 2001 Hynix System IC SBU
Semiconductor Inc. System IC SBU
REGISTER ADDRESS AND DEFAULT VALUE
* Note : I2C Device Address of CMOS Image Sensor : 22H
Group Symbol Address Description
Mode-
Registers
MODE_A 00H Device Identity (Read only : 00H ) MODE_B
01H
Operating Mode B Selection ( Default : 04H )
HV7131D
CMOS IMAGE SENSOR
b0 0 Line Unit Integration
MODE_C
02H
1 Pixel Unit Integration
b1 0 Continuous Frame
1 Single Shot Frame
b2 0 Full Image (648X488)
1 Windowed Image
b3 0 HSYNC only
1 HSYNC & Internal Clock
b5 b4 Output Data Type
0 0 Data_Level - Reference_Level 0 1 Reference_Level 1 0 Data_Level 1 1 reserved
b7 b6 Operating Mode
0 0 Normal Mode 0 1 Reserved 1 0 Reserved 1 1 Reserved
Operating Mode C ( Default: 00H )
b1 0 Three Gain Control Mode
1 One Gain Control Mode
Internal
Test
Register
53H, 55H, 56H,
60H, 61H
[ Reserved]
Test Registers for Image Sensor Future Enhancement
[These register should not be used in normal operation]
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 14 - 2001 Hynix System IC SBU
HV7131D
Semiconductor Inc. System IC SBU
REGISTER ADDRESS AND DEFAULT VALUE ( continue )
Group Symbol Address Description Default
Frame-
Registers
FRSU 10H Row Start Address (Upper byte )
FRSL 11H Row Start Address ( Lower byte ) 03H
CMOS IMAGE SENSOR
00H
[3]
Timing-
Register
Adjust-
Register
FCSU 12H Column start Address ( Upper byte ) 00H
[3]
FCSL 13H Column start Address ( Lower byte ) 03H
FWHU 14H Window Height ( Upper byte ) 01H
[482]
FWHL 15H Window Height ( Lower byte ) E2H
FWWU 16H Window Width ( Upper byte ) 02H
[641]
FWWL 17H Window Width ( Lower byte ) 81H
THBU 20H HSYNC Blanking Duration value ( Upper byte ) 00H
THBL 21H HSYNC Blanking Duration value ( Lower byte ) 03H
TVBU 22H VSYNC Blanking Duration value ( Upper byte ) 00H
TVBL 23H VSYNC Blanking Duration value ( Lower byte ) 03H
TITU 25H Integration Time value ( Upper byte ) 00H
TITM 26H Integration Time value ( Middle byte ) 01H
TITL 27H Integration Time value ( Lower byte ) F4H
TMCD 28H Master Clock Divider 00H
ARLV 30H Reset Level Value 38H ARCG 31H Red Color Gain 1EH AGCG 32H Green Color Gain 1EH
ABCG 33H Blue Color Gain 1EH APBV 34H Pixel Bias Voltage Control 02H
Offset
Register
Reset
Level
Statistics
Register
OFSR 50H R Offset Register (Test purpose Only) 00H OFSG 51H G offset Register (Test purpose Only) 00H OFSB 52H B offset Register (Test purpose Only) 00H
LoREfNOH 57H Low Reset Level Counter [<3] (Upper byte) (Read Only)
LoREfNOL 58H Low Reset Level Counter [<3] (Lower byte) (Read Only)
HiRefNOH 59H High Reset Level Counter [>123] (Upper byte) (Read Only)
HiRefNOL 5AH High Reset Level Counter [>123] (Lower byte) (Read Only)
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 15 - 2001 Hynix System IC SBU
Semiconductor Inc. System IC SBU
PROGRAMMING SEQUENCE FOR CMOS IMAGE SENSOR
l Single Register Byte Programming
S
22H
A
01H
A
mode inform
HV7131D
CMOS IMAGE SENSOR
A P
*1 *2
ð Set "Operating Mode" register into Window mode
*3
*4
*5
*1. Drive: I2C start condition *2. Drive: 22H(001_0001 + 0) [device address + R/W bit] *3. Read: acknowledge from sensor *4. Drive: 01H [sub-address] *5. Read: acknowledge from sensor *6. Drive: 04H [sub-address] *7. Read: acknowledge from sensor *8. Drive: I2C stop condition
l Multiple Register Byte Programming using Auto increment Mode
*2
22H
A *3
S *1
ð You can program multiple configuration registers with single I2C bus cycle.
*4
01H
A *5
02H
*6
A *7
*6
*8
65H
*7 *8
A P *9 *10
ð Set "Row Start Address" register as 265H
*1. Drive: I2C start condition *2. Drive: 22H(001_0001 + 0) [device address + R/W bit] *3. Read: acknowledge from sensor *4. Drive: 10H [sub-address] *5. Read: acknowledge from sensor *6. Drive: 02H [row start address upper byte] *7. Read: acknowledge from sensor *8. Drive: 65H [row start address lower byte] *9. Read: acknowledge from sensor *10. Drive: I2C stop condition
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 16 - 2001 Hynix System IC SBU
Semiconductor Inc. System IC SBU
PROGRAMMING SEQUENCE FOR CMOS IMAGE SENSOR ( continue )
l Reading Register Value
S
22H
A
01H
A S 23H A Read Data A P
HV7131D
CMOS IMAGE SENSOR
*1 ð Single Read or Auto-Increment Read
*2
*3
*4
*5 *6
*7
*8
*9
*10 *11
ð Set "Reset Level Value" register
*1. Drive: I2C start condition *2. Drive: 22H(001_0001 + 0) [device address + R/W bit(be careful. R/W=0)] *3. Read: acknowledge from sensor *4. Drive: 10H [sub-address] *5. Read: acknowledge from sensor *6. Drive: I2C start condition *7. Drive: 23H(001_0001 + 1) [device address + R/W bit(be careful. R/W=1)] *8. Read: acknowledge from sensor *9. Read: Read Data from sensor *10. Drive: acknowledge to sensor(if there is no more read data Ack=1, else Ack=0) *11. Drive: I2C stop condition
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 17 - 2001 Hynix System IC SBU
SensorArrayHeight
SensorArrayWidth
RowStartAddress
WindowHeight
EffectiveWindowHeight
HV7131D
Semiconductor Inc. System IC SBU
FRAME TIMING DIAGRAMS
There are two frame timing cases,
l Integration Time < EffectiveWindowHeight * Scale l Integration Time > EffectiveWindowHeight * Scale
EffectiveWindowHeight is equal to the number of data lines generated in a frame and is defined to be selected by if((RowStartAddress + WindowHeight + 1) <= SensorArrayHeight) EffectiveWindowHeight = WindowHeight; else EffectiveWindowHeight = (SensorArrayHeight - RowStartAddress - 1);
CMOS IMAGE SENSOR
The above selection logic is somewhat confusing in respect of general counting measure. It’s partly due to the mixed use of indexing start points, i.e. ‘0’ and ‘1’ in the chip design. Therefore in order to avoid the confusion it is desirable to just follows the equation when you estimate the frame rate.
For example, RowStartAddress = 200 and WindowHeight = 400, EffectiveWindowHeight is 287 and 287 data lines per a frame are generated.
[488]
[648]
[287]
(0,0)
[200]
[400]
Scale is selected according to Integration Time Mode by If(PixelMode) Scale = SensorArrayWidth; // For H7131B[648x488], SensorArrayWidth is 648 else Scale = 1;
When Integration Time > (EffectiveWindowHeight * Scale), next frame VSYNC does not follow immediately after current frame’s last line has been produced. Instead, one of the following two idle time slots is inserted according to Integration Time Mode before next frame VSYNC gets active.
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 18 - 2001 Hynix System IC SBU
HV7131D
Line 0
Line 1
, Line 2
Line 480
Line 481
VSYNC
Line 0
Line 1
, Line 2
Line 480
Line 481
VSYNC
Line 0
Line 1
, Line 2
Line 480
Line 481
VSYNC
Semiconductor Inc. System IC SBU
< Idle Slots >
l Line Mode: (Integration Time - EffectiveWindowHeight) * 1024 clks l Pixel Mode: (Integration Time - EffectiveWindowHeight *Scale)
= (Integration Time - EffectiveWindowHeight *SensorArrayWidth) clks
Each Frame Timing of the above cases may be decomposed into four timing segments
l Initial Data Setup Time after ENB gets active l Even Line l Odd Line l Frame Transition
The subsections will describe frame timing diagram for said frame time cases, (Integration Time <
CMOS IMAGE SENSOR
Effective Window Height * Scale) and (Integration Time > Effective Window Height * Scale).
1. Frame Timing Diagram for Integration Time < (EffectiveWindowHeight * Scale) Frame timing related registers are programmed to suit for the above condition as follows RowStartAddress = 3; WindowHeight = 482; ColumnStartAddress = 3; WindowWidth = 642; IntegrationTime = 400 [Line Mode];
EffectiveWindowHeight is “482” for (SensorArrayHeight > (RowStartAddress + WindowHeight + 1)), i.e. 488 > (3 + 482 + 1), is met, and Scale is “1” for integration time is line mode. Therefore, (Integration Time < EffectiveWindowHeight * Scale), i.e. 400 < 482 * 1, is met.
Overall Frames Sequence
Initial Data Setup Time
....
Frame 1 Frame 2 Frame 0
....
....
....
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 19 - 2001 Hynix System IC SBU
Semiconductor Inc.
ENB
Sensor Reset
One Line Time Delay
[651 clocks]
VSYNC
Integration Time *
IMAGE RAW DATA
Line Head
HBLANK
Line Tail
SensorArrayWidth (648)
HBLANK(3)
System IC SBU
MCLK
ENB
VSYNC
Delay Slots
Deglitch
2 clocks
SensorArrayHeight clocks
[488 clocks]
Scale clocks
[400 * 648 clocks]
CMOS IMAGE SENSOR
(SensorArrayWidth +
HBLANK) clocks
HV7131D
3 clocks
MCLK
HSYNC
DATA
Time Slot
Blank
3 clks
Fig. 1 Initial Data Setup Time after ENB gets active
Window Width
642 clks
Blank
3 clks
3 clks
Clock Ruler
Fig.2 Even Line Data Timing
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 20 - 2001 Hynix System IC SBU
Semiconductor Inc.
Line Head
IMAGE RAW DATA
HBLANK
Line Tail
SensorArrayWidth (648)
HBLANK(3)
G
G
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
⋅
G
Line Tail
IMAGE RAW DATA
Line Head
IMAGE RAW DATA
VSYNC
≈
≈
HBLANK
⋅
G B G
B
⋅
⋅ ⋅ ⋅
R
⋅
System IC SBU
MCLK
HSYNC
HV7131D
CMOS IMAGE SENSOR
DATA
Time Slot
Clock Ruler
MCLK
HSYNC
Blank
3 clks
B
B
B
G B G B G B
Window Width
642 clks
Fig.3 Odd Line Data Timing
Blank
3 clks
3 clks
VSYNC
DATA
G
G
R R G
Time Slot
Window Width
642 clks
Blank
3 clks
3 clks
3 clks
Blank
3 clks
Window Width
642 clks
Integration Time < EffectiveWindowHeight * Scale
Fig.4 Frame Transition Timing
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 21 - 2001 Hynix System IC SBU
HV7131D
Line 481
ENB
Sensor Reset
One Line Time Delay
[651 clocks]
VSYNC
Integration Time *
Line 1
, Line 2
Line 480
Line 481
Line 0
Line 1
, Line 2
Line 480
VSYNC
Line 0
Line 1
, Line 2
Line 480
Line 481
VSYNC
Line 0
VSYNC
Semiconductor Inc. System IC SBU
2. Frame Timing Diagram for Integration Time > (EffectiveWindowHeight * Scale)
Frame timing related registers are programmed to suit for the above condition as follows RowStartAddress = 3; WindowHeight = 482; ColumnStartAddress = 3; WindowWidth = 642; IntegrationTime = 600 [Line Mode];
EffectiveWindowHeight is “482” for (SensorArrayHeight > (RowStartAddress + WindowHeight + 1)), i.e. 488 > (3 + 482 + 1), is met, and Scale is “1” for integration time is line mode. Therefore, (Integration Time < EffectiveWindowHeight * Scale), i.e. 600 > 482 * 1, is met, and Idle Slot of Line Mode, i.e. (600 - 482) * 1024 clocks idle slot, is inserted before the next frame initiation.
CMOS IMAGE SENSOR
Overall Frames Sequence
Initial Data Setup Time
MCLK
ENB
....
Frame 1 Frame 2 Frame 0
Idle Time
....
Idle Time
....
Idle Time
VSYNC
Delay Slots
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 22 - 2001 Hynix System IC SBU
Deglitch
2 clocks
SensorArrayHeight clocks
[488 clocks]
Fig. 5 Initial Data Setup Time after ENB gets ac tive
Scale clocks
[600 * 648 clocks]
(SensorArrayWidth +
HBLANK) clocks
3 clocks
Semiconductor Inc.
IMAGE RAW DATA
Line Head
HBLANK
Line Tail
SensorArrayWidth (648)
HBLANK(3)
R R G
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
⋅
R G R G R
G ⋅ G R G
Line Head
IMAGE RAW DATA
HBLANK
Line Tail
SensorArrayWidth (648)
HBLANK(3)
G
G
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
⋅
G
System IC SBU
MCLK
HSYNC
DATA
HV7131D
CMOS IMAGE SENSOR
Time Slot
Clock Ruler
MCLK
HSYNC
DATA
Blank
3 clks
B
B
B
Window Width
642 clks
Fig.6 Even Line Data Timing
G B G B G B
Blank
3 clks
3 clks
Time Slot
Blank
3 clks
Window Width
642 clks
Blank
3 clks
3 clks
Clock Ruler
Fig.7 Odd Line Data Timing
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 23 - 2001 Hynix System IC SBU
Semiconductor Inc.
R
. . .
R
G
G
B
.
G
System IC SBU
MCLK
HSYNC
VSYNC
HV7131D
CMOS IMAGE SENSOR
DATA
Time Slot
G B
IMAGE RAW DATA
≈
Window Width
Line Tail
Blank
HBLANK
3 clks
Integration Time > EffectiveWindowHeight * Scale
Fig.8 Frame Transition Timin g
Idle Slot
(Integration Time)
VSYNC
3 clks
Line Head
Blank
IMAGE RAW DATA
Window Width
≈
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 24 - 2001 Hynix System IC SBU
HV7131D
Semiconductor Inc. System IC SBU
PACKAGE DISMENSION (48 PIN CLCC/PLCC) UNIT: mm
1) TOP View
CMOS IMAGE SENSOR
* C : Center of Image Area
2) BOTTOM VIEW
C
0.53
0.98
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 25 - 2001 Hynix System IC SBU
Semiconductor Inc. System IC SBU
MEMO
HV7131D
CMOS IMAGE SENSOR
Hynix Semiconductor Inc. System IC SBU
Headquarter & Factory
San 136-1,Ami-Ri,Bubal- Eub,Ichon-Si,Kyoungki-Do,Korea 467-701 Tel : 82-2-3459-5573/5577 , Fax : 82-2-3459-5580, E-mail : knpark@hynix.com
This document is a general product description and is subject to change without notice. Hy nix Semiconductor does not assume any responsibility for use of circuits described. NO patent licenses are implied.
DA31001015R_1.2 - 26 - 2001 Hynix System IC SBU
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