HP Vectra 510, Vectra 515, Vectra 510 5, Vectra 515 5 Technical Reference Manual

HP Vectra 500 Series PC

Hardware and BIOS

Technical Reference Manual

Models: 510 5/xx

515 5/xx

February 1996

Notice

The information contained in this document is subject to change
without notice.
Hewlett-Packard makes no warranty of any kind with regard to this
material, including, but not limited to, the implied warranties of
merchantability and fitness for a particular purpose.
Hewlett-Packard shall not be liable for errors contained herein or for
incidental or consequential damages in connection with the furnishing,
performance, or use of this material.
Hewlett-Packard assumes no responsibility for the use or reliability of
its software on equipment that is not furnished by Hewlett-Packard.
This document contains proprietary information that is protected by
copyright. All rights are reserved. No part of this document may be
photocopied, reproduced, or translated to another language without the
prior written consent of Hewlett-Packard Company.

IBM is a registered trademark of International Business Machines
Corporation.
Intel is a registered trademark of Intel Corporation.
Microsoft and MS-DOS are U.S. registered trademarks of Microsoft
Corporation.
Operating System/2 and OS/2 are registered trademarks of International
Busines Machines Corporation.
PC/XT is a trademark of International Business Machines Corporation.
Pentium is a U.S. registered trademark of Intel Corporation.
XT is a trademark of International Business Machines Corporation.
Windows is a U.S. trademark of Microsoft Corporation.

Hewlett-Packard France
Grenoble Personal Computer Division
Technical Marketing
38053 Grenoble Cedex 9
France

 1996 Hewlett-Packard Company

iii

Preface

This manual is a technical reference and BIOS document for engineers and
technicians providing system level support for HP Vectra 500 Series PCs for
models: 510 5/xx and 515 5/xx.

It is assumed that the reader possesses a detailed understanding of AT­compatible microprocessor functions and digital addressing techniques.

Technical information that is readily available from other sources, such as
manufacturer’s proprietary publications, has not been reproduced.

This manual contains summary BIOS information only. For detailed
information, it is recommend the reference work cited in the next section.
For additional reference material, refer to the bibliography.

Ordering Information for the Phoenix BIOS Manual

System BIOS for IBM PCs, Compatibles, and EISA Computers (ISBN 0-201­57760-7) by Phoenix Technologies is available in many bookstores. It can also
be ordered directly from the publisher as follows:

In the U.S.A.

Call Addison-Wesley in Massachusetts at [phone], and be prepared to
give a credit card number and expiry date.

In Europe

Send your request to Addison-Wesley at the address given below, and be
prepared to give a credit card number and expiry date.

Addison-Wesley
Concertgebouwplein 25
1071 LM Amsterdam, The Netherlands
Tel: [phone]
Fax: [phone]

iv

Conventions

The following conventions are used throughout this manual to identify specific
elements:

❒ Hexadecimal numbers are identified by a lower case h.

For example, 0FFFFFFFh or 32F5h

❒ Binary numbers and bit patterns are identified by a lower case b.

For example, 1101b or 10011011b

Bibliography

❒ System BIOS for IBM PCs, Compatibles, and EISA Computers

(ISBN 0-201-57760-7) by Phoenix Technologies. Addison-Wesley
(publisher).

The following Hewlett-Packard publications may also assist the reader of this
manual.

❒ HP Vectra 500 Series Familiarization Guide. The HP Part Number is:

D41xx+49A90001

❒ HP Vectra 500 Series PC Reference Guide for either the desktop or

minitower (supplied with the PC). The HP Part Number for these books are:

D4140-90001 - Desktop
D4170-90001 - Minitower

❒ HP Vectra 500 Series Service Handbook - 2nd edition. The HP Part

Number is:

5063-9064

The following Intel publication provides more detailed information:
❒ Pentium Processor (241595-1)

Contents

v

1 HP Vectra 500 Series

System Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

HP Vectra 500 Series Desktop – Minitower Comparison . . . . . . . . . . . . . 3

HP Vectra 500 Series Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Principal Components and Features . . . . . . . . . . . . . . . . . . . . . . . . . . 5

HP Vectra 500 Series System Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

HP Vectra 500 Series Desktop Backplane . . . . . . . . . . . . . . . . . . . . . . . . . 7

HP Vectra 500 Series Minitower Backplane. . . . . . . . . . . . . . . . . . . . . . . . 7

Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Superscalar Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Floating Point Unit (FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Dynamic Branch Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Instruction and Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Data Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PCI Chip Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PCI, Cache and Memory Controller (82437FX) . . . . . . . . . . . . . . . . . . . 12

Data Path Unit (82438FX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

The PCI/ISA Bridge and IDE Controller (82371FB) . . . . . . . . . . . . . . . . 14

The 82438FX and 82371FB Feature Summary. . . . . . . . . . . . . . . . . . . . 14

Super I/O Chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

NS PC87332VF Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Flexible Drive Controller (FDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Serial/Parallel Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Graphics/Integrated Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

IDE to PCI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Flash ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Physical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Environmental Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2 Summary of the HP/Phoenix BIOS

HP/Phoenix BIOS Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Overview of Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Contents

vi

System Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

BIOS I/O Port Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Addressing System Board Components . . . . . . . . . . . . . . . . . . . . . . . . . 27

3 Desktop Management Interface

DMI Information Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Accessing BIOS DMI Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

The DMI Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Verifying the DMI Information Structure . . . . . . . . . . . . . . . . . . . . . . . . 35

DMI Sub-Structure Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4 Power-On Self-Tests and Error Messages

Power-On Self Test (POST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Shadow RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Beep Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5 The Ultra VGA Video Controllers

The Integrated Ultra VGA Video Controller . . . . . . . . . . . . . . . . . . . . 50

Video Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Video Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Typical Windows 95 Video Resolutions. . . . . . . . . . . . . . . . . . . . . . . . . . 55

VESA Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

DB15 Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Video Controller Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

1

1

HP Vectra 500 Series

This chapter provides a description of the HP Vectra 500 Series desktop
(Models 510 5/xx) and minitower (Models 515 5/xx) PCs with detailed
system specifications.

2

1 HP Vectra 500 Series

System Overview

System Overview

The HP Vectra 500 Series PC, Models 510 5/xx and 515 5/xx1, are Pentium
processor, ISA/PCI-based PC and features the Intel Triton chip set.

The following table details the main features on the HP Vectra 500 Series
PC, Models 510 5/xx and 515 5/xx.

1. This document does not apply to the HP Vectra 500 Series Models 502, 510,
512, 514, 522, 560, 562, 564, 572 and 574.

Function Features

Processor

Pentium 75
Pentium 100
Pentium 120
Pentium 133
Pentium 150
Pentium 166

Level-two cache memory
(optional)

256 KB synchronous cache are standard on the following models::

515MC 5/133
515MCx 5/133
515MCx 5/166

Main memory

8 MB or 16 MB standard
128 MB maximum

Video controller

Trio 64 PnP on PCI bus

Video memory 1 MB standard

upgradable to 2 MB

Enhanced IDE hard disk controller

Integrated in chip set (part of 82371FB multipurpose chip)
Integrated on PCI bus
Primary channel dedicated for hard disk drives
Secondary channel recommended for CD-ROM drives

Secondary IDE controller

No secondary IDE controller
(Two channels on enhanced IDE controller - see above)

Flexible disk controller

Integrated in SMC 932 Super I/O chip on ISA bus

Serial / parallel port controller

Integrated in SMC 932 Super I/O chip on ISA bus

3

1 HP Vectra 500 Series

System Overview

HP Vectra 500 Series Desktop – Minitower Comparison

Desktop Minitower

IDE Controller
Primary channel connectors

Two connectors for hard disk drives

Two connectors for hard disk drives

IDE Controller
Secondary channel connectors

One red connector recommended for
CD-ROM

Two red connectors recommended
for CD-ROM and supplementary
hard disk drive

Flexible disk controller connectors Two connectors :

- One for a 3.5-inch flexible disk drive

- One for either a tape drive or a

5.25-inch disk drive

Two connectors for 3.5-inch
flexible disk drive
One connector for 5.25-inch flexible
disk drive or a tape drive
Maximum two devices connected
simultaneously

Accessory board slots
(on backplane)

One 16-bit ISA (short 16cm /6.3-inch)
One 16-bit ISA (full-length)
One 32-bit PCI or one
16-bit ISA Combination (full-length)
One 32-bit PCI (full-length)

One 16-bit ISA (short length)
Two 32-bit PCI (full-length)
One 32-bit PCI or one
16-bit ISA Combination
Two 16-bit ISA (full-length)

Internal device shelves One for hard disk drive

Two for hard disk drives

Front-access device shelves One 3.5-inch

One 5.25-inch
One 5.25-inch, 1-inch high (or an
internal drive)

One 3.5-inch
Three 5.25-inch

4

1 HP Vectra 500 Series

HP Vectra 500 Series Block Diagram

HP Vectra 500 Series Block Diagram

256 KB

Level-Two

Cache

Memory

(8 MB -

128 MB)

Intel

82371FB

PCI/ISA

Bridge

S3 Trio

Video

Controller

SMC932
Super I/O

Controller

I/O Decode

Lo gi c

BIOS

Flash ROM

Pentium

Processor

Intel Triton

82437/8FX

Chipset

Host Bus

PCI Bus

ISA Bus

PCI Accessory

Board Slots

ISA Accessory

Board Slots

IDE Controller Channel 1

IDE Controller Channel 2

FDD

Par alle l

Serial 1

Serial 2

Keyboard

Mouse

Flash

Support

5

1 HP Vectra 500 Series

Principal Components and Features

Principal Components and Features

The main features of the system board are:

• supports Pentium processors of several different clock speeds (75, 100,
133 and 166 MHz, and 120 Mhz when available) with accompanying
voltage regulator module (VRM)

• a PCI bus video controller: all models of the HP Vectra 500 Series have an
integrated 64-bit Ultra VGA controller on the PCI bus (S3 Trio 64 Pnp)

• an Enhanced IDE controller with two channels on the PCI bus

❒ a primary IDE channel for two IDE hard disk drives
❒ a secondary IDE channel for an IDE CD-ROM drive and, in the mini-

tower models, a fourth IDE device (such as a third IDE hard disk drive)

• a combined controller on the ISA bus for

❒ 2 flexible disk drives and/or tape drives
❒ 2 serial ports
❒ 1 parallel port

• sockets for DRAM main memory: the HP Vectra 500 Series PCs provide
six sockets for main memory, allowing installation of up to 128 MB

• a system ROM (using flash ROM technology) that can be easily updated
with the latest firmware, using the Phlash.exe program supplied with the
firmware upgrade. The system ROM contains:

❒ the BIOS (system BIOS, video BIOS and low option ROM)
❒ menu-driven SETUP with context-sensitive help (in U.S. English only)

• a keyboard/mouse controller and interface.

6

1 HP Vectra 500 Series

Principal Components and Features

HP Vectra 500 Series System Board

*

This video upgrade applies only to the models with integrated video controller.

3.3V

*

7

1 HP Vectra 500 Series

Principal Components and Features

HP Vectra 500 Series Desktop Backplane

HP Vectra 500 Series Minitower Backplane

8

1 HP Vectra 500 Series

Principal Components and Features

Processor

The Pentium processor uses 64-bit architecture and is 100% compatible
with Intel’s family of x86 processors. All application software that has been
written for Intel386 and Intel486 processors can run on the Pentium without
modification. The Pentium processor contains all the features of the
Intel486 processor, with the following added features which enhance
performance:

• Superscalar Architecture

• Floating Point Unit

• Dynamic Branch Prediction

• Instruction and Data cache

• Data Integrity

• Supports MultiProcessor Specification (MPS) 1.1

• PCI bus architecture

• Advanced Power Management capability for reducing power consumption

The processor is seated in a Zero Insertion Force (ZIF) socket.

Superscalar Architecture

The Pentium processor’s superscalar architecture has two instructions
pipelines and a floating-point unit, each capable of independent operation.
The two pipelines allow the Pentium to execute two integer instructions in
parallel, in a single clock cycle. Using the pipelines halves the instruction
execution time and almost doubles the performance of the processor,
compared with an Intel486 microprocessor of the same frequency.

Frequently, the microprocessor can issue two instructions at once (one
instruction to each pipeline). This is called instruction pairing. Each
instruction must be simple. One pipeline will always receive the next
sequential instruction of the one issued to the other pipeline.

Floating Point Unit (FPU)

The Floating Point Unit incorporates optimized algorithms and dedicated
hardware for multiply, divide, and add functions. This increases the
processing speed of common operations by a factor of three.

9

1 HP Vectra 500 Series

Principal Components and Features

Dynamic Branch Prediction

The Pentium processor uses dynamic branch prediction. To dynamically
predict instruction branches, the processor uses two prefetch buffers. One
buffer is used to prefetch code in a linear way, and one to prefetch code
depending on the contents of the Branch Target Buffer (BTB). The BTB is a
small cache which keeps a record of the last instruction and address used. It
uses this information to predict the way that the instruction will branch the
next time it is used. When it has made a correct prediction, the branch is
executed without delay, thereby enhancing performance.

Instruction and Data Cache

The Pentium processor has separate code and data caches on-chip. Each
cache is 8 KB in size with a 32-bit line. The cache acts as temporary storage
for data and instructions from the main memory. As the system is likely to
use the same data several times, it is faster to get it from the on-chip cache
than from the main memory.

Each cache has a dedicated Translation Lookaside Buffer (TLB). The TLB is
a cache of the most recently accessed memory pages. The data cache is
configured to be Write-Back on a line-by-line basis (a line is an area of
memory of a fixed size).

The data cache tags (directory entries used to reference cached memory
pages) are triple ported to support two data transfers and an inquire cycle in
the same clock cycle. The code cache tags are also triple ported to support
snooping (a way of tracking accesses to main memory by other devices) and
split line accesses.

Individual pages of memory can be configured as cacheable or non­cacheable by software or hardware. They can also be enabled and disabled
by hardware or software.

10

1 HP Vectra 500 Series

Principal Components and Features

Data Integrity

The processor uses a number of techniques to maintain data integrity. It
employs two methods of error detection:

• Data Parity Checking

This is supported on a byte-by-byte basis, generating parity bits for data
addresses sent out of the microprocessor. These parity bits are not used
by the external subsystems.

• Internally

The processor uses functional redundancy checking to provide maximum
error detection of the processor and its interface.

PCI Chip Set

The chip set consists of three devices:

• The PCI, Cache, and Memory Controller (82437FX)

• Two Data Path Units (82438FX)

• The PCI/ISA bridge and IDE controller (82371FB)

The 82437FX and 82438FX2 devices provide the core cache and memory
system architecture, and the PCI interface.

11

1 HP Vectra 500 Series

Principal Components and Features

Level-Two

Cache

Main

Memory

82371FB

PCI/ISA Bridge

BIOS

Pentium

Processor

82437FX PCI, Cache and

Memory Controller

Host Bus

PCI Bus

ISA Bus

82438FX

Data Path Unit

PCI

Master

IDE

Controller

82438FX

Data Path Unit

ISA Bus

Controller

PCI

Master

PCI

Slave

APIC

Cache

Controller

Write

Buffer

Main

Memory

Controller

PCI

Slave

12

1 HP Vectra 500 Series

Principal Components and Features

PCI, Cache and Memory Controller (82437FX)

The 82437FX device integrates cache and memory control functions and
provides bus control functions for the transfer of information between the
microprocessor, cache, main memory and the PCI bus. The cache controller
supports the Pentium Cache Write-Back mode and 256 KB of direct
mapped, write-back level-two cache, using synchronous pipeline burst
SRAMs.

82437FX Feature Summary

Function Features

Cache controller ❒ Direct mapped organization

❒ Buffered write-back
❒ External cache tags
❒ 32-byte line size
❒ Uses synchronous pipeline burst SRAM
❒ Supports 3-1-1-1

1

burst reads

Write buffer ❒ Buffers all processor writes to main memory

❒ Buffers memory writes to PCI for selected memory regions
❒ Supports 3-1-1-1

1

write access timing

DRAM controller ❒ Uses dedicated DRAM memory address and data buses

❒ Page mode - one or two pages open simultaneously
❒ Supports pipelined accesses
❒ Full RAS/CAS programmability
❒ Flexible bank configurations (each bank programmable for

DRAM size, bank width and single or double-sided modules)

❒ Self configuring bank start addresses
❒ Shadow RAM support for the memory region 640 KB - 1 MB

(in 16 KB segments)

❒ System management memory support
❒ RAS only refresh
❒ Fast memory access 7-2-2-2

1

with Extended Data Out (EDO)

memory

PCI slave interface ❒ Becomes processor (local) bus master to generate DRAM

requests on behalf of other PCI bus masters

❒ Supports PCI bus burst cycles
❒ Supports posted writes to DRAM for PCI burst writes
❒ Supports read-ahead from DRAM for PCI burst reads

13

1 HP Vectra 500 Series

Principal Components and Features

Data Path Unit (82438FX)

The 82438FX component contains a 64-bit data path between the host bus
and main memory. A 4

×64-bit deep buffer provides 3-1-1-1 writes to main

memory.

This buffer is used for:

• writes from processor to main memory

• level-two cache write back cycles

• transfers from PCI to main memory.

1.

The Pentium’s internal cache has a 32-byte line size, which is four times the width of the Pentium’s

host data bus. Burst reads and writes by the Pentium involve a full cache line, and so require four
back-to-back cycles to complete. The first cycle in each burst of four always requires more time to
complete than the three subsequent cycles. This is because the first cycle includes the addressing
phase and precharge timing (for memory).

PCI master interface ❒ Provides for programmable PCI bus memory regions in

memory address map

❒ Supports PCI bus burst cycles for 64-bit and 32-bit misaligned

Pentium reads and writes

❒ Optional posting of PCI memory and I/O writes
❒ Optional buffering of PCI memory writes
❒ Optional read-ahead for processor to PCI accesses

PCI bus arbiter ❒ Supports PCI bus arbitration for up to four masters

❒ Supports rotating priority scheme

Function Features