HP MICRO 3000 Diagnostic Manual

HP

3000

Computer

Systems

MICRO

3000

SELFTEST

and

MAINTENANCE MODE

Diagnostic Manual

8010

Part

No.

30534-90001

E i 286

FOOTHILLS

BLVD.,

ROSEVILLE,

CA

95678

Printed

in

U.

S.

A.

12/86

The

information

contained

in

this

NOTICE

document

is

subject

to

change

without

notice.

HEWLETT-PACKARD MATERiAL,

iNCLUDiNG, MERCHANTABILITY be liable furnishing,

Hewlett-Packard is

This reserved. without

not

furnished

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for

errors

performance

No

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contained

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proprietary

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-Packard.

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of

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COMPANY

REGARD

WARRANTIES

Hewlett-Packard

in

connection

sofiware

on

equipment

copyright.

to

another

All

TO

THIS

shall

with

that

rights

language

OF not the

are

New

editions contain the incorporated update

additional

title

page

is

incorporated.

First

are

complete

and

change

into a reprinting

Edition

revisions replacement only

.........................................

of

the

pages

when a new

unless

it

appears

manual.

to

be

edition

Update

merged

or a new

as a

prior

PRINTING HISTORY

into

update;

packages,

the

update

which

manual

is published.

the

by

edition

are

the

does

issued

between

customer.

No

not

change

Dec

information

1986

The

editions,

dates

when

on

is

an

DEC

86

111

The To the the

List

verify

bottom

edition

of

Effective

that

of

or

Pages gives

your

manual

each

page

subsequent

LIST OF EFFECTIVE PAGES

the

contains

with

those listed below.

update

in

which

date

the

of

most

that

the

most

current

page was

The

recent

date

version

information,

on

the

printed.

of

each

check

bottom

page in

the

dates

of

each

the

printed

page

manual.

at

reflects

Effective

all

Pages

....................................

Dec

Date

1986

DEC

1986

Section I

GENERAL

CONTENTS

INFORMATION

Introduction Required

.............................................

Hardware

Self test ROM Code

Seiftest

Power-On Maintenance The

Executive

Remote

Self test

Mode

Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 4

Section 2

OPERA

Introduction Keyswitch

Test

Front Power-On Maintenance

Test Mode Remote

TING

INSTRUCTIONS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Capabilities.

Execution

Panel

LED

Self test

Mode

...............................................

Operator Establishing Disconnecting

Time.

the

Section 3

MAINTENANCE

.........................................

..........................................

.........................................

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . .

Indicators

Execution

.............................

Interface

Remote

the

MODE

....................................

...................................

....................................

Console

Remote

COMMAND

Link

Console

..................

Link

...........................

DESCRIPTIONS

...........

:

...........

, . , ,

.. , ..

)-1

I-I

1i-

1-

2-1

2-) 2-2

2-2 2 - 3

2-4

2-6 2-6

2-7

2

3

Introduction Maintenance

Automatic Automatic Coldstart Cooistart Disc Dump Help Load Newsystem Panel Reload Run

.............................................

Mode

Warmstart.

Restart

..............................................

.................................................

................................................

.................................................

.............................................

................................................

...............................................

.................................................

Commands

........................................

..................................

.....................................

3-1 3-1 3-1

3-

3-3 3-4 3-4

3-

3-5

3-6

3-6 3-6

2

3

5

DEC

86

v

CONTENTS

Speed

.......

Start.

.......

Tape

........

Test

........

Update Warmstart

......

....

(continued)

. . . . . .

·

......

3-6 3-7 3-7 3-7

3-8 3-8

Section TEST

Introduction

Test

Section SOFTPANEL

Introduction Command Com

4

MODE

Mode

Commands

.................................

All Channel

CPU Exit Help

IOMA~

Memory PON

rna

Display Modify Register Execution Input/Output Miscellaneous CPU

.....

ATP

Test PIC Test. LANIC

........

...........................

.................

.....................

....................

.......................

5

Parameters

nd

Desc ri pt Memory Memory

Operations

ROMS

COMMAND

............................

.

...

.

...

.

Test

..

.

.............................................

ions.

.........................................

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Control.

Operations

Commands

Date

Code

DESCRIPTIONS

.

......................

.

. . .

.......................................

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 2

. . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

....................................

2647

Exceptions

..

......................

..........................

. .

·

..........

·

..........

·

..........

·

..........

·

..........

. .

·

..........

........

......

·

.. ..

..

4-1

4-1 4-1 4-3 4-3 4-3 4-4 4-4 4-5

4-6 4-6

4-7

4~8

5-1 5-1

5-

2

5-

3 5 - 4 5-5 5-

5 5-

5

5-6

DEC

86

CONTENTS

(continued)

Appendix

ERROR

A

TP

ATP Test Section I ATP Test Section 2

Test

A

CODES

Error

Codes

.....................................

.....................

.....................................

0

•••••••••••••••

A TP Test Section 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ATP Test Section 4 A

TP

Test Section 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 2

ATP Test Section 6 A

TP

Test Section 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIC Test

Error

PIC Test Section 1 PIC Test Section 2 PIC Test Section

Codes.

......................................

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

......................................

3.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIC Test Section 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIC Test Section 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIC Test Section 6

......................................

PIC Test Section 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIC Test Section 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIC Test Section 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LANIC

Self test Subtest

LANIC Selftest Subtest Codes LANIC Self test

CPU

Test

Error

Codes . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . .

Memory Test Power-On

Error

Self test

and

Error

Codes

Codes.

LED

Interpretation

Error

Codes

...........................

................................

.................................

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

............................

..

.. ..

..

,

A-I A-I A-II

A-I A-I A-I A - 2 A-2

A-3 A - 3

A - 4

A-4 A-4

A - S

A - 5

A-6 A-6 A-6 A-7

A - 7

A-8

A-9

0

Appendix

TOe

TOC RAM

B

RAM

INFORMATION

Data

and

Status

Tables

...............................

B-1

DEC 86

vii

LIST

Table Table Table

OF

TABLES

2-1.

Keyswitch Capabilities

2-2.

Maintenance Mode Commands

2-3.

Test Mode Commands

FIGURES AND TABLES

...............................

..........................

................................

2-1

2-5 2-6

Table A

Table Table Table B-3. System Halt Causes

LIST

Figure

-1.

B-1. 8-2.

OF

FIGURES

2-1.

Power-On

TOC RAM Last-Stop

ACTIVITY/FAULT

Self test LED

Data

and

Value Meanings

Interpretation

Status

............................

.............................

.................................

LEOs

and

....................

Keyswitch

..................

A

-II

B-1 B-2

8-3

2-2

DEC 86

viii

~ER_R_O_R_C_O_D_E_S

______________

~lrH!H,

Appendix A includes

according

A

TP

The error.

The same

ATP

This

TEST

ATP

slot

sequence

Test

section

Code

0108 0109

010A

010C 0100

010E

010F

to

the

test

ERROR CODES

error

codes

test

will

display

as

the

Section

is

the

initializ.ation

Error

Register 8 initialization Register 9 initializ.ation Register A initializ.ation Register C initializa Register D initialization Register E initializa Register F initialization

aU

error

sequence

are

divided

(lne

test

sections.

codes

they

of

1

associa

are

according

the

following

Testing

test

which

tion

ted

wiih

associated

to

one

error

stops

when

initiahl.es

error

(expected

error

(expeded

error

(expected

error

(expected

error

(expected

error

(expected $ 5004)

error

(expected $ 5004)

i he -MiCRO

with:

ATP,

of

the

codes

the

ATP

$0800)

$08(0)

$FFOU)

$0000)

nine

if

first

PIC,

sections

the

failure

and

3000

LANle.

ATP

verifies

seJftest.

CPU,

of

the

test

fads.

is

detected.

registers

The

ur

ATP

The

errOi

MEMOR

test

that

tests

l:ontain

codes

Y.

detected

are

run

expected

are

listed

the

in

the

data.

ATP

This

section

Code

0201 0202

0203

0204

0205

Test

tests

Section

basic

operations,

Error

SMSK/RMSK SMSK/RMSK

A

TP

did

not Improper Improper

IPOLL

OBU response.

set

2

test; test;

IRQ.

and

OBII,

ATP ATP

response

did did

(none,

IPOLL,

not

respond

not

respond

wrong,

SMSK

with with

or

and

RMSK.

mask mask

mUltiple

bit

set.

bit

clear.

channels).

DEC

86

A-I

Error

Codes

ATP

The

section

Code

0300 0301

0307 0310

0377

ATP

This

section

Code

0401 0402 0403 0404 0405 0406

Test

is

Test

is

Section 3

the

port

register

Error

Port

0,

register

Port

0,

register

Port

0,

register 7 pattern

Port

I,

register 0 pattern

Port

7,

register 7 pattern

Section

the

DMA test. SIMB

Error

DMA

state

DMA

state

DMA

write

DMA

read

DMA

read

DMA

counter

test

0 pa

I pa

4

ma\,;hine machine

to

memory

from

memory

from

memory

test failed.

which

ttern

test

ttern

test

test test

test

write

failed

lrallliferrcd

to to

tests registers

failure failure

failure

Word.

to

~o

to

state

10

K{)

to

litatc

improper

RBYTE LBYTE

transferred

0-7

4.

3.

on

ports

data.

improper improper

0-7.

data.

ATP

Port

DEC

Test

selftest.

Code

0500 0501

0507

86

Section

Error

Port

0 self test

Port I selftest

Port 7

selftesl

5

failure failure

failure

Error

Codes

ATP

This

A

This

Test

section

Code

0600 0601

0607

TP

Test

section

Code

0700 0701 Port 1 loopback

0707

Section

is

the

DMA loopback to

Error

Port 0 loopback Port

1 loop back

Port

7 loop

Section

is

the

DMA loopback

Error

Port 0 loopback

Port

7 loopback

6

back

7

failure failure

failure

data

data data

data

port

test.

failure failure

failure

DEC 86

A-3

Error

PIC

If

the

same

PIC

This

Codes

TEST

PIC

sequence

Test

section

ERROR CODES

test

fails,

the

slot

as

the

test sections.

Section

is

the

initialization

1

test

will

display

Testing

whidl

one

of

stops

when

initializes

the

following

first

failure

PIC

and

error

is

verifies

codes.

detected.

regi!;ters

The

contain

tests

are

run

expected

in

the

data.

Code

0104 0105

0106 0107 0108 010A 010C 010f

PIC

This

Code

0201 0202 0203 0204

0205 0206 0207 0208 0209

020A

0208 020C 0200 020E

Test

sedion

Error

Register 4 initialization Register 5 initialization Register 6 initializa Register 7 initialization Register 8 initializa Register A initialization Register C initiallza Register F initialization

Section

tests

basic

Error

St'tlSK/RMSK SMSK/RMSK PIC

did

Improper

wrong Improper Improper Improper Received \Vrong Improper Improper Improper Improper

Improper

(should

2

operations

test; test;

not set

response,

channel

have

IRQ

IPOtl.

OBII

data register IPOll

no

CSRQ

is

CBS!

data

register F data

CSRQ SPOLl 08SI

response

pointed

tion

error

tion

and

0811,

PIC

did

PIC

did

after

response

or

multiple

from

D response

response

after

responding

after

response

after

IIIOP

to

device

error

(expected

error

(expected (expected

error

(expected

error

(expected

error

(expected

error

(expect.ed

error

(expected

IPOLl,

not not

SMSK

after

channels

this

after

(should

issuing a SlOP.

to

SMSK

respond respond

on

selected

SMSK (no response,

channel

SMSK.

have

SPOlL.

SPOLL

after

SPOlL.

after

IIIOP

(should

SPOLL

have

after

7).

SOOOO)

SOOOO) $0020) SOOnG) $0000)

$0000) $0000) $0087+(8

and

RMSK.

with

mask

with

mask

channel.

responding).

after

SMSK.

been

clear).

have

been

zero).

IHOP

t

channelH»

bit

set.

bit

cleared.

been

zero).

DEC

86

PIC

Test

Section

3

Error

Codes

This section tests the

Code

0301 Initialization 0302

0303

0304

0305

0306

PIC

Test

This section tests the Register (PIC Register

Code

0401 Reg2, bit 0 should 0402

0403 0404 0405 0406 0407 0408 0409

040A Reg 0406

Btl-ill

Error

Initialization

ami bits I I

Hit

13

should

controller

Bits

13

and

chip

is

addressed to

Bit 14 should

controller

nits

13

and

chip

is

not

Section

liP-III

3).

Error

Reg

2,

bits 9

(no handshake Reg2, bit 12 should Reg

2,

bit 14 should Reg2, bit 8 should be clear (no Reg

2,

bit 0 should Reg

2,

bit 8 should Reg2. bit 9 should Reg

2,

bits

(outbound

and

illh,llll11i

state).

2,

bit 9 should Reg2. bit 9 should

~oniroiier

error

and

be

chip

is

14 should both

be

one, bit

chip

is

14

should both

addressed to

chip

- bits 0 to 7 should

- bits

12

should

I, bit 14 should

addressed

talk

addresscd to listen,

4

controller

be

set (an

and

13

should

abort

and

be

set (outbound FIFO room available).

be

set (out bound FIFO idle).

be

clear (no

be

set (status change occurred).

be

clear (no handshake abort).

12

and

14 should

FIFO

rOlll11

not available, l)utbllUlHI FIFO not idle,

FiFO

not empi y.

be

set (handshake abort).

be

clear (no handshake abort).

Status

10,

be

to

be and 13

should

be

talk

I.:hip

interrupt

be

inbound FIFO empty).

be

Register (PIC Register n

be

zero.

13,

and

14

slhluld

one.

be

zero when the

talk,

but

not listen.

one when the

listen.

be

7.cro

when

but

not to talk.

zero whcn the

or to listen.

Interrupt

clear

status

interrupt

clear. nit I 3 should

._>

Register (PIC Register

is

pending).

change).

pending).

FIFO

Oits iii uprh'siCc

he

liP-In

the

liP-In

7.cro

IIP-IB

controller

111'-18

controller

be

set

2)

and

Interrupt

Mask

DEC 86

Error

PIC

This

Codes

Test

section

Section

tests

PiC

5

registers 4 and

5 by

reading

and

writing

data.

Functions

are

not

tested.

Code

0501 0502 0503 0504

PIC

This

Code

0601 0602 0603

0604

0605

Test

section

Error

Register 4 fails Register 5 fails Register 4 fails Register 5 fails

Section

tests PIC

register

Error

Register 6 fails Register 6 fails Bits 12

Bits 12

Bit 15

and should

register full

and

register NOT

full

the

liP-Ill

14

and

(PIC

and

(PIC

of

be

to

show

data

to

show

data

to

show

data

to

show

data

6

(IIP-18

to

show

patterns

to

show

patterns

14

of

the

liP-In

register

idle.

14

register

and

idle.

register 6 should

controller

the

uP-In

clear.

of

2)

the

liP-In

2)

chip

controller

patterns patterns patterns patterns

control

controller

should

controller

should

be set interrupt

register).

$802A $4054

be

set

(outbound

be

clear

(clear

register

chip

interrupt

SOOe. SOOAA. S0055. S0055.

for

read/write

chip

(outbound

out

bound

read/write

interrupt

FIFO

NOT

interrupt

1-"1£70

FI£70)

test. Bits 12

register

test.

via

PIC

Test

This

section

Code

0701

0702 0703

0704

DEC

86

Section

tests

PIC

register 7 {IIP-IB

Error

Regisier 7 fails

Register 7 fails

Bit

9

of

Register 7 should

controller

Bits 13 be

Bit

111)-11\

HP-IB

a

off

10

talk

or

to

of

controller controller

always.

7

io to

chip

status

14

of

indicate

register 7 should

show show

the

NOT

'hip chip

address).

patterns

register

IIP-IB

a

status status

be set

(PIC controller

laik

or

be set

register

$ SOGA

$4015

(talk

always)

register

a iisten.

(listen

test. Bit 13 must

for

chip

always)

be

read/write

via

the

I)

test.

register

should

via the

of

on

to

test.

liP-In

the

indicate

Error

Codes

0705

0706

PIC

TIllS

only.

Code

0801

0802 0803

0804

0805

0806

PIC

This

section

Same

stat

Same

is

again status to

Test

Register 9 and

Test

Section

tests

PIC

Error

Register

Register Register Register 8 fails

Register 9 fails

Register

Section

tests

DMA

as

0704

us

register

as

0704

updated

n:;gisler

indicate

NOT a listen

8

register

10 (SA)

8 fails

9 fails

10 fails

10

fails

9

Write/Read/Abort

except

must

except

and

must

8,

9 and 10

are

tested

to

show da

to

show

to

show

to

show

to

bit

be

the

bit

be

show

14

off

IIP-IB

13

on

to

always.

with

for

ta

data

data data data

data

of

the

to

indicate

controller

of

the

indicate

all

16

patterns patterns

patterns patterns patterns

patterns

from

IIP-IB

NOT

UP-In

NOT a listen

read/write

bits.

SOOAA. SAAAA.

SAAAA.

S0055. S5555.

S 5 555.

memory

controller

chip

a listen always.

chip

status

(;ontroller

always.

data

only.

to

PIC

FIFO,

register

chip

Register H is

and

from

PIC

tested

FIFO

for

lower 8 bits

to

memory.

Code

0901 0902

0903

0904

0905

0906

0907

0908

090A 0908

090e

090r

Error

CSRQ

Bit 9 (no CSRQ Bit 5

Bit 6

CSRQ

Data

CSRQ

Bit

Bit 6

Timeout.

response &

Data

transferred

(assuming

of

the

handshake

response &

of

PIC

termination

of

PIC

termination

response &

reat!

response & test via

5

of

PIC

termination

of

PIC

termination

test

via OBSI

to

the

DMA

write

interrupt

abort)

register B should

test.

register B should

test.

from

register B should

test.

register B should

test.

Waiting

test

PIC

register

the

via OBSI

via

on

for

CSRQ.

PIC

abort

DMA

onsl

J)MA

onsl

failed

FIFO

test

(PIC reg

write

failed

be

set

be set

failed

read

failed

be

set

be

set

by

for

test

for

the

DMA

the

above

passed)

2)

should

abort

the

DMA

dlffercnt

for

the

write

transfer

is

incorrect.

(PIC reg

DMA

read

DMA

be

clear

E)

write

than

read

to

PIC.

test.

abort.

abort

from

PIC.

expected.

abort.

abort

DEC

86

Error

Codes

LANIC

TEST

ERROR

CODES

LANIC

Self

test

Subtest

Codes

LANIC

self test

subtest

descriptions

and

c(l<ics

are

h!lited

below:

Code

Test

0001

Z80

instruction

set

0002

EPROM

checksum

0003

Station

address

PROM

checksum

0004

Iligh

byte

la

tch

0005

RAM

data

(background

test)

0005

Byte

RAM

data

(even addresses)

0006

Byte

RAM

data

(odd addresses)

0007

Byte

RAM

address

(in,rementing

addresses)

0008

Byte

RAM

address

(decrementing

addresses)

0009

\Vord

RAM

address

OOOA

\Vord/Byte

address

mapping

OOOB

Z80

memory

reference

instructions

OOOC

Values

from

reset

MDIAG,SYSCON

0000

eTC

data

tcst

OOOE

CTC

mode 0 counting

OOOF

CTC

mode 2 counting

0010

eTC

mode 4 counting

0011

Interrupt

PAL

(bit

4)

0012

Z80

interrupt

0013

Z80

non-maskable

interrupt

0014

Master

handshake

disabled

(MHSDIS)

0015

PAODR

TO

BADDR

(low 15 bits)

0016

ZBANKL

0017

ZBANKH

0018

Preliminary

FIFO

(INREADY,

ADVREAOY,

OUTREADY)

00

19

FIFO

data

(HDATA 7)

001A

FIFO

data

(ilEA 7,8)

001 B

FIFO

data

(BOAT A 2:6)

OOtC

FIFO

data

(BDATA

0,1,13:15)

0010

FIFO

data

(BDATA (8:12)

001 E

FIFO

data

(BA

11:

15)

001 F

FIFO

data

(BA

6:

I 0)

DEC

86

Error

Codes

0020 0021 R 0022 0023 0024 0025 0026 0027 0028 0029

002A 002B 002C Level I 002D 002£

LANIC

The

Code

0179

017A

system

Self

console

o 17B o

17C

017D 017£ 017f

FIFO

data

(SA

14

configuration

OBII

value;

channel COMCON MAU

power

values

on/off

R i 3 CR, CR fuii R

15

self

test

result

82586 81586

Register

82586 82586

82586

MAU

Error

Failure

The

Self

Z 80

Unexpected Unexpected

LANIC

interrupt reset

decode

LANIC

diagnose

chip

write

loopback

test

LANIC

will

display

while

diagnostic.

Error.

82586

interrupting.

test

result

stack

underflow

was failed. preceding may

(This

every

have a failure

lo\)pback

to

performing

did

register

Z80

Z 80

reset

code

1:

5) register

number

from

reset

bit

register

(PilUS

RAM

FIFOS

on

register

addressing

command

media

Codes

,)Ile

of

the

not

clear

its

(R

15)

during non-maskable interrupt.

but

selflest

is

set

in

full self test. )

code

or a random

not

addressing)

following

82586

command

bit

is bad.

self

test.

interrupt

never

the

LEDs by

In

0

error

codes

initiali1.ation

word

(NMI).

started,

t his case,

or

the

value.

for

prior

I.ED

hard

selftest

if

the

to

circuitry

reset

LANIC

test fails:

DEC

86

A-9

Error

Codes

CPU

The same sequence as

Test

Test Section 2 -

Test Section 3 -

Test Section 4 - MPE

TEST

system console displays one

Section 1 - Bank register tests

a 10 1

0102 0103 0104

020 0202

0203

0301

ERROR

the

test sections. Testing stops

Pbank Dbank Sbank Abank

Toe

RAM tests

1

TOe

RAM test not done (power fail)

TOe

RAM

Toe

count

TOe

not

timer

TOe

not counting

CODES

of

the

read/ A bank

read/Shank

read/Dbank

read/Pbank

data

failure

verification

counting

verification

following

write

failure

write

failure

write

failure

write

failure

error

when

codes if

the

first

the

epu

failure

test fails.

is

detected.

The

tests

are

run

in

the

Test Section 5 - Watchdog

050

1 Watchdog

MEMORY

The

system console displays one

the

same sequence as

Code

0000

000 0002 0003 0004 0005

TEST

the

1

ERROR

Error

PFAR Memory

Memory

Memory address test failed Memory Parity

timer

verification

timer

did not rollover

CODES

of

the

following

test sections. Testing stops

test failed (memory dead)

size test failed initialization

pattern

test failed

error

test failed

codes

when

the

if

the

first

memory

failure

test fails.

is

detected.

The

tests

are

run

in

DEe

86

Error

Codes

POWER-ON

ACTIVITY

LED

OFF

ON

OFF

SELFTEST

Table

A-I.

FAULT

LED

OFF

ON

Flashing single blink

LED INTERPRET A

Power-On

SeUtest

INTERPRET

No Power.

Processor

Executing

System in ba

back

CPU failed.

llnsupported detected.

-up

or

mode.

0-2

completely

self test.

LED

ttery

Mb

ATP

TION

Interpretation

ATION

dead.

memory

ACTION

TOTAKE

Check

for AC. Measure

DC

supply

Replace processor.

Wait

completion.

Wait return.

Replace processor PCA.

Remove ATP.

output.

for

self

test

for

AC

unsupported

power

OFF

ON

Flashing blink

OFF

double

triple

ATP

Console

Fast/slow failed.

Console failed sense.

Console failed to sense.

Selftest complete.

"H

for

displayed.

failed.

51MB

to

execution

help"

I/F

speed

prompt

Replace A replace

Check between

Check REMOTE

Console rna y Attempt

da

lacomm

Replace A

TP

processor PCA.

cable

console

that

mode.

loopback

TP.

in slot I

connection

and

console

be defective.

test.

ATP.

is

or

in

DEC 86

L_

..

T_E_S_T_M_O_DE

_COMMAND DESCRIPTIONS _

________________

~1~14i1H,

INTRODUCTION

This section provides a

Test mode allows looping (NORMAL).

Use

Error

TEST

Test mode allows you to

up

the

maintenance

messages

MODE

to

the

system

9999

times;

mode

can

be

found

COMMANDS

All Channel

CPU

Exit

All

definition

operator

the

TE

[s

in

enter

the

of

test mode and a description

to

initiate

default

t]

Appendix A.

is

command

following commands

1.

Looping

to

and

enter

manually

is

disabled

test mode.

at

the

of

test mode commands.

direct

the

self tests. Test mode allows

when

the

"Test

->"

prompt:

Help

IOMAP

Memory

PON

keyswitch

is

in

position

for

111"

The

ALL

command

• CPU test

• Memory test

Channel

•

• IOMAP

runs

test

all

of

the

manually

directed self tests except

the

PON

test

in

the

following order:

DEC 86

Test Mode

The between I and

The

Command

test

may

correct

following

syntax

AL

[L]

1-NORMAL

Test

TOC Addr OOOE OOOf 0010 0000 0011 0000 0012 0004 0013 0014 0000 0015 0000

CPU Memory Channel 1 Channel 4 Test

Descriptions

be

looped by specifying the desired

9999;

the

for

[ coun t ]

illustrates

default

this

the

is

command

use

of

I.

the

(A

is:

space

ALL

->AL RAM

Data 0000 0000

OOOE

Test

passed

Test

passed

Terminal

Peripheral

Interface

Passed

System

number

is

required

command:

Controller

I/O

Configuration

of

loops in

before specifying

Controller

count.

Count

count.)

must

be

an

integer

Memory

Size

Load:

Channel

4 Start/Dump: Channel

4 Channel Channel 4

Device Device

3 10=0260 - 9144

1 ID=$022B 7958

l-NORMAL

Test

->

(MEGABYTES) = nn

Device

3

Device

ID=4 -Terminal ID=2

-

Peripheral

Interface

Cartridge

Disc

Drive

Controller

Tape

Unit

DEC 86

Channel

The

CHANNEL

specifying default channel

tested. failure Appendix A for

the

is

1.

is

selected

The

appropriate

occurs,

ATP

The

1.

Init

2.

Basic

3.

Port

4.

Diagnostic

(A space

test

desired

with

the

failure

ATP, PIC,

Test

ATP

test

check.

I/O

register

performs

number

is

has six sections:

operations.

the

required

the

channel

test (A TP, PIC,

code and

LANIC

Performs

tests.

loopback

ATP, PIC,

of

loops in

before

command.

is

displayed

test

an

ATP

Issues OBII, IPOLL, SMSK,

Writes

using

and

count.

specifying

LANIC

on

error

initializ.ation

patterns

DMA

sequencer

LANIC

If

or

the

codes.

to

registers

Count

count.)

a

none)

system

tests.

must

Count

particular

is

run

console next

and

tests

and

0-7

ROM.

The

be

an

must be

channel

for

each

to

verify

RMSK

of

ports

Test

Mode

CHANNEL

integer

to

and

0-7

between 1 and

specified

is

nut

specified,

PCA

installed

the

PCA

registers

verifies a proper

and

Command

test

may

whenever

in

description.

contain

verifies

Descriptions

be looped by

9999;

a specific

all

channels

the

CPU.

Refer

proper

response.

the

data.

If

data.

the

are

a

to

5.

Initiates

6.

Performs

The

console A

PIC

Test

The

PIC

1.

Init

2.

Basic

3.

Tests

4.

Tests

register

5.

Tests PIC

6.

Tests PIC

7.

Tests PIC

8.

Tests

pec

DMA

TP

test

has

check.

I/O

operations.

the

HP-IB

the

lIP-IB

3).

registers 4 and

register

PIC

registers

test~

on

data

is

speed sensed

nine

sections:

Performs

controller

6.

7.

8,

all 8 ports.

loopback test

PIC initializ.ation

Issues OBII, IPOLL, SMSK,

chip

5 using

9,

and

A using

on

and

communication

status

chip

interrupt

data

all

8 ports.

and

verifies

register

(PIC

patterns.

lines

and

(PIC

register

are

registers

RMSK

register

2)

tested

with

contain

and

verifies a proper

1).

and

interrupt

the

local console.

proper

mask

data.

response.

registers (PIC

9.

Fills

HP-IB

registers

controller

associated

with

chip

DMA

FIFO

and

transfers.

executes

DMA

to

and

from

memory.

Tests

DEC 86

PIC

4-3

Test Mode

Command

Descriptions

LANIC

The self test.

After

the

ATP, PIC,

The

correct

syntax for this

CH[an][

The

following illustrates

1-NORMAL

Test

Channel Channel Test

1-NORMAL

Test

CPU

Test

LANIC code

and

LANIC tests execute,

count[,channel]

the

->CH

-

4 -

Passed

-)

is

not included in the selftest microcode. The LANIC PCA executes its own

command

use

of

CHAN:

Terminal

Peripheral

return

is:

Interface

is

to

the

Controller

"Tes

t - >" prompt.

The test mode

•

• TOC RAM loea tion test.

• TOC

• MPE

• Watchdog

Te,sts

not

performed

• ROM checksum test.

• Full processor

•

Full

• Register file address

CPU

command executes

P,

D,

S,

and A bank

counting

timer

Timer

by this CPU test,

WCS address

the

following CPU tests

register tests.

verification.

counting

verification.

Force Condition verification

but

executed by

chip

function

and

data

test.

the

power-on

and

not

run

FMD

capability

CPU test are:

at

power-on:

test.

Test Mode

Command

Descriptions

The test may

between 1 for this

The following illustrates

be

and

9999;

command

CPU

[

looped by specifying

the

is:

count]

1-NORMAL

Test

->CP

TOC

RAM

Addr

Data

OOOE

0000

ooor

0000 0010 0000 0011 0000 0012 0004 0013

OOOE 0014

0000 0015 0000

CPU

test

passed

1-NORMAL

Test

->

default

the

use

of

is

CPU:

1.

the

(A

desired

space

number

is

required before specifying

of loops in

count.

Count

count.)

must

The

be

an

correct

integer

syntax

Exit

The test mode EXIT

prompt.

The

correct syntax

E[xit]

The

following illustrates

Test

->E

H

for

help->

command

for

this

the

returns

command

use

of

EXIT:

execution

is:

to

maintenance

mode

and

displays

the

"H

for

help-

>"

DEC 86

Test

Mode

Help

The

HELP

available

The

correct

The

following

Command

command

test mode

syntax

for

HELP

illustrates

l-NORMAL

Test

->H

ROM

Version:

Self

test

Descriptions

does

not

commands

this

command

the

nnnn

Menu:

appear

and

use

of

in

the

ROM

is:

HELP:

test mode menu.

version

number.

When

issued,

the

HELP

command

displays

the

AL[l] [ CH[an] [ CP[u] [ E[xit]

I [omap] [

M[emory] [

PON [ count

l-NORMAL

Test

IOMAP

The

IOMAP

IOMAP the

supported

description.

The

between I and

The

runs

system, lists

HP-IB

test

may

correct

syntax

count]

count [ ,chan]

count

1

]

count

]

->

command

the

be looped by specifying

9999;

executes a version

memory

the

devices

for

load

the

this

size

and

attached

default

command

portion start/dump

is

to

1.

the

is:

of

the (A

]

of

the

memory

devices,

PIC

desired

space

IOMAP

and

are

identified

number

is

required

contained

test, displays

identifies

and

their

of

loops

before

specifying

in

all

the

in

selftest

number

peAs

10

code

count.

ROM.

of

installed

is

displayed

Count

count.)

This

megabytes

in

the

with

must

be

version

installed

system. All

an

of

in

a device

integer

I [omap] [

DEC 86

A £

count]

The

following

t-NORMAL

Test

illustrates

->1

the

use

of

IOMAP:

Test

Mode

Command

Descriptions

Memory

Load: Channel Start/Dump: Channel

Channel

l-NORMAL Test

Memory

The

test mode

determined,

are

performed.

The

full

memory number Refer

the

to

Appendix A

Device

->

MEMORY

then

memory

Upon

test executes.

error

Size

(MEGABYTES) = nn

4

Device

4

Device

10=4 -Terminal

4

10=2

3

10=$0260

command

is

initialized

test completion,

was

detected

for

list

of

System

3

-

Peripheral

executes

If

an

error

in.

The

memory

I/O

Configuration

Interface

-

9144

Cartridge

the

power-on

before a refresh

memory

is

FAULT

test

error

is

left

detected,

LED

codes.

Controller

Tape

Unit

memory

test,

with

the

will

test.

an

address test, a

$30F8

system console displays

light

(halt

and

The

amount

pattern

8)

in all locations.

the

ACTIVITY

of

the

installed

test

and a parity

memory

LED

memory

test

section

will go

is

test

out.

The

test

may

be

looped by specifying

between 1 and

Return

The

is

correct

following

9999;

to

the

"Test

syntax

M

[emory]

illustrates

l-NORMAL

Test

->M

Memory

for

Test

the

->"

this

[

count}

default

the

passed

is

mode

prompt.

command

u·se

of

the

desired

l.

(A

space

is:

MEMORY:

number

is

required

of

loops in

before

coun

specifying

t.

coun

Coun t

t.)

must

be

an

integer

DEC

86

Test

Mode

PON

The

test

mode

test,

and

The

correct

The

following

Command

mode

PON

command

IOMAP

This

syntax

PON

[count]

illustrates

is

from

for

Descriptions

command

except

not

executed.

command

keyswitch

this

command

the

executes

the

power-on

cannot

position

use

of

The

PON:

the

PON

be

is:

power-on

CPU

test

run

"2"

(LOCAL)

test

is

NOTE

from

self is

executed

initiated

keyswitch directly

test

count

by

toggling

from

times.

in place

poslhon

position

the

"3"

of

PON

"3"

This

command

the

manually

hne.

(REMOTE)

(REMOTE).

is

executed

or

like

the

ALL

CPU

2-LOCAL

Self

Power Memory Memory

(from Normal)

Test

->PON

on

Self Test Size

Channel 1 Channel 4

2-LOCAL

Self

(from Normal)

Test

->

Test

passed

(MEGABYTES) = nn

Terminal

Peripheral

Interface

Controller

DEC

86

A._!Z

~SO_F_T_P_AN_E_L

________________

~lr~'

INTRODUCTION

Softpanel

memory, requiring

following

is a

diagnostic

perform

parameters

commands

Display

Modify

Register

Execution

Memory

tool

register

must

are

allowed

Operations

DR MR

Control

E

used and have

to

I/O

a "+",

in

softpanel:

examine

operations,

RUN

COMMAND PARAMETERS

Softpanel

bank

command

parameters

One current digit,

are

of

or

defined

the

following radix an

octal

"_If,

or

numeric

software.

and

perform

a space

as:

between

numeric

field, a hexadecimal

field

Softpanel

other

the the

Input/Output

Other

fields

limited

preceded

allows

the

necessary

command

Operations

RIO

WIO

/Miscellaneous

T

ENV

RTOC WTOC

R()X

ST

to a range

numeric

by

a

~

user

to

display

functions.

and

the

of

0 - 255 (8 bits):

field

preceded

and

All

commands

parameter.

by

a $

modify

The

the

or

a

count

epxr

ioaddr

One radix an

A

right

One radix an

of

the

following

numeric

octal

numeric

combination

with

no

of

the

following

numeric

octal

numeric

field, a

precedence.

field, a

field

of

numeric

field

hexadecimal preceded

numeric

hexadecimal

preceded

fields

by

and

fields

by

limited

numeric

a

"/e.

op.

limited

numeric

a

"/e.

to

a

field

Operations

to

a 16

field

16

bit

maximum:

preceded

are

performed

bit

maximum:

preceded

by

a $

or

from

a $

or a digit,

the

a

the

current

digiti

left

current

DEC

or

to

or

86

Softpanel

iodata

numeric

One

radix

an

octal

One

radix

an

octal

of

the

following

numeric

of

Ihe following

numeric

field, a

hexadecimal

field preceded by a

numeric

hexadecimal

field preceded by a

fields

limited

numeric

1-.

limited

numeric

%.

to

a

16

bit

maximum:

field preceded by a $

to

a I tl bit IIl:Ullllum:

field preceded by a $

the

cllrrent

or

a digit,

the

current

or a digit,

or

op

reg

regfile

tocaddr

tocdata

COMMAND

One of: a +,

the

sign bit. : is

One

of

the

following registers: DB, DL, Q,

status

or

One current digit,

One radix an

register

ICS.

of

or

of

numeric

octal

of

numeric

octal

register),

containing

the

following radix an

octal

the

following

numeric

the

foHowing

numeric

DESCRIPTIONS

-,

or

*.

Operations

the

indirection

SB

(the

split

load/boot

numeric

field, a

numeric

field preceded by a

field

numeric

hexadecimal

numeric

hexadecimal

done

on

numeric

operator.

bank

flag, I bit wide), CIR,

device DRT),

fields

limited

hexadecimal

preceded

fields

limited

numeric

Dbank,

to a range

numeric

by a

to

field

1-.

fields

limited

numeric

~.

to

field

fields

S,

PB, PL, Z,

1..

a

16

preceded

a

16

preceded

are

Sbank,

of

field

bit

maximum:

bit

maximum:

signed. Bit

STA

(the

X,

SW

Pbank,

0 - 255

preceded

by a $

(0:

1) is

liP

3000

(the

switch

LPFlg, DISP,

(8

bits):

the

by a $

the

or

the

or a digit,

current

a digit,

current

or

a

Display

The D command display command

The

options

DA

expr

DEA

[+

DSY

[

DEC

Memory

commands

will

always

are:

[:

[

~

l

bank.expr[:

]

-expr [expr]]

86

] [ : [ l

continues

display in

expr]

[~~

from

the

show

multiples

] [

,coun

~expr]]

~

1

expr]

] [

the

last

screen

displayed

current

radix

of

8 words in

(refer

the

t ] Displays

[,count]

,coun

Displays

t ] Displays

and

to

SDM

current

memory

the

absolute

the

absolute

displays

[Set

Display

radix

at

the

address

another

and

given

Mode]

in ASCII.

absol

ute

relative

half

screen

command).

address

to

the

to

sysglobal.

of

data.

The

in

bank

specified

All

display

O.

bank.

[+

]

DDB[-expr

][:

[~:lexpr]][tcount]

[ [expr]]

[ + ]

rU',\1 r

_D-r-nr

1

r.

r

[+]

D-r-nrl1

r

.....

;"\UH#

1

..........

L

~-t"

J L • L [ _ ]

~-t'

j j L

,........ " ..

J

[ [expr]]

[+ ]

DO

[-expr

][:[f:~expr]][,Count]

[ [expr]]

[+

]

DPB[-expr

][:

[f:~expr]]

[,count]

[ [expr]]

[+

)

DS

[-expr

][:

[f:~expr]][,count]

[ [expr]]

[+ ]

DZ

[-expr

][:

[~:~expr]]

[,count]

[ [expr]]

[+

]

DP

[-expr

l[:[~:lexprl][tcount]

[ [expr]]

[+

]

OPL[-expr

][:[f:~expr]][,count]

[ [expr]]

Modify

Memory

Softpanel

Displays

the

absolute

address

relative

to

the

DB register.

Displays

the

absolute

ad,lress

relative

to

the

DL

iegistei

.

Displays

the

absolute

address

relative

to

the

Q register.

Displays

the

absolute

address

relative

to

the

PB register.

Displays

the

absolute

address

relative

to

the

S register.

Displays

the

absolute

address

relative

to

the

Z register,

Displays

the

absolute

address

relative

to

the

P register.

Displays

the

absolute

address

relative

to

the

PI. register.

Modify

memory

commands

will display

the

current

address,

current

contents,

and

wait

for

the

user

to

input a new

value.

Input

the

new

value

using a

numeric

field

with

the

current

default

radix

or

force

the

new

value using

the

radix forces

("%"

or

"S").

The

command

will

terminate

when

the

user

inputs

either"."

or

"'

/"

in response

to

the

prompt.

The

options

are:

MA

expr[: [I:lexpr]]

MEA

bank.expr[:[~:lexpr]]

[+

]

MSY[-expr

][:[~:lexpr]]

[ [expr]]

Modify

the

absolute

address

in

bank

O.

Modify

the

absolute

address

in

the

specified

bank.

Modify

the

absolute

address

in sysglobal.

DEC

86

5-3

Softpanel

[+

MDB[-expr

[ [expr]]

[+ 1

MOL

[-expr [ [expr]]

[+

MQ

[-expr [ [expr]]

[+

MS.

[-expr ] [ : [ [ [expr]]

[+

MZ

[-expr [ [expr]]

[+ ]

MPB[-expr

[ [expr]J

(+ ]

MP

[-expr ]

[ [exprJ]

]

][:[~~~exprJl

J[:

[I~~exprl]

Modify

Modify the absolute address in

the

absolute address in

J

the

][:[I:lexpr]]

]

~:

l expr] ]

]

][:

[f:lexpr]]

][:

[{~~expr]]

[:[I~~exprl)

Modify

absolute address in

the

absolute address in

the

absolute address in

the

absolute address in

the

absolute address in

the

D8

register.

the

DL register.

the

Q register.

the

S register.

the

Z register.

the

MPS register.

the

P register.

[+

MPL[-expr

]

[:[t~~expr]]

[ [expr] J

Register

The

DR

specified to

The

options are:

Operations

command

DR

then

[reg ]

DR

[regfile

MR

{reg }

[,count

regfile

will display

all

common

jj

the

common

registers will

Display

Modify

the

Modify

value

the

registers (i.e.,

be

displayed.

contained

absolute address

P,

PB,

PL, CIR, DB, Q,

in a register.

in

the

PL register.

S,

etc.).

If

no

field

is

DEC 86

Softpanel

Execution

Control

The

options

are:

E Exit

back

to

maintenance

mode

RUN

Run

(return

to

software)

Input/Output

Operations

The

addresses

and

data

patterns

for

Input/Output

operations

conform

to

1MB

and

51MB

formats.

The

options are:

RIO

ioaddr

Read

I/O

from

address ioaddr

WIO

ioaddr~iodata

Write

I/O

address ioaddr

with

data

iodata

Miscellaneous

Commands

The

T (Trace)

command

allows

the

user

to

trace

the

current

(or specified)

stack.

ENV

allows

the

user

to

move back

markers

of

the

current

stack

and

access

data

there

as if

it

were

at

the

current

marker.

ROX

aJIows

the

user to

change

the

current

radix.

Softpanel

starts

with

the

radix set

to

octal.

The

ENV

command

specified

with

no

parameters

will

turn

ENV

off

(q-relative

addresses

revert

to

the

current

en

vironmen

t).

The

options

are:

T[ [numeric.]numeric]

Trace

stack.

ENV[ numeric]

Change

the

environment.

RTOC

tocaddr

Read

TOC

RAM

address.

WTOC

tocaddr,tocdata

Write

TOC

RAM

with

data.

ROX

{~

Change

the

current

radix.

(H

- Ilex; 0 -

Octal)

ST

Give

softpanel

status.

DEC

86

c _ c

Softpanel

CPU ROMS

1.

In

the

softpane!:

"A"." A

oo

.....

C

0") hexadecimal. not

have

between

2.

In

the

3.

In

the

but

there

4.

In

the

interrupt.

5.

The

6.

In

the

case

letter

this

restriction.

the

DB

softpanel,

softpanel.

is

no

softpanel,

and

switch

software

and a value

Imbedded

way

the

register

Date

Any

must

be prel:eded by

letters

register

and

the T (Trace)

to

use

using t he RIO

(,;onsolc

(SR)

display.

of 0 with a lower

Code

hcx.adel.imal

in

The

reason

the

value

the

ENV

comes

back

is

not

the

status

2647

either a zero

a hex

value

for

"SOB".

command

to

the

ill

the

default

register

case

Exceptions

value

starting

or a dollar

starting

this

qualification

to a non

will to

move

maintenance

register

flags M.

letter.

with a numeric

-ex.istent

print

the

back

to a non

I.

with

for

s-bank

last user

to

the

-existent

Illode

display.

T, R,

0,

an

alphabetic

sign.

even

charadcr

numeric

user

prompt.

It

and C indicate a value

does

stack

stack.

register

may

in

not

be

character

if

the

current

(for

the

hex

print

an

if

the

current

produces a watchdog

dIsplayed

example.

radix

is

error

stack

manually.

of 1 with

(for

radix

"ICOO")

to

distinguish

message.

is

an

example,

is

set

to

do

the

ICS,

timer

upper

DEC 86

~

______________________________________________

~I~B;!l16i

_

Toe

RAM INFORMATION

_~

Appendix B contains

tables

defining

the

TOe

RAM

locations displayed

on

the

system

console

during

self test execution.

Toe

RAM DA T A AND

ST A TUS

TABLES

Table

8-1.

TOe

RAM

Data

and

Status

Toe RAM ADDRESS

ST

A TUS

AND

OAT A STORED

IN

TOC

RAM

ADDRESS

$OA

Register A

SOB

Register B

SOC

Register e

SOD

Register D

$OE

Undefined

$OF

Console

ATP

port 0

interrupt

time-out

flag*

$10 Last

stop

information.

See

Table

8-

2.

S

11

Sta

rt

device

S12

Load device

$13

Undefined

$14

Test

loop

counter

(lower byte)

SI5

Test loop

counter

(upper

byte)

SI6-S3F

Undefined

*

If

the A TP

port 0 interrupt

time

-out

flag is set

(contains

SAA)

this

means

port 0 of

the

ATP

in slot 1

of

the

SPU has failed to produce

an

expected

interrupt

within

500

milliseconds

and

the

microcode has

timed-out.

This

flag should

be

checked

if

the

RUN

command

cannot

be

executed.

If

the

flag is set,

port 0 configuration

information

was

not

stored

and

thus

could

not

be

restored

upon

executing

the

RUN

command.

DEC

86

Toe

RAM

Information

Table

8-2.

Last-Stoll

Value

Meanings

VALUE

$OO-$OF $IO-$IF

$20 $11

$22

$23 $24

MEANING

Halts 0 through

System

WCS

parity

Watc.:hdog

Power

Control B (maintenance

Mult

iple bit

$25 51MB bus

$7F

$80

MPE

UP

Restart.

System was

Restart.

$81-$FF Unused.

15

Halt 0 through

error

Timer

failure

paril y error

parity

error

status

removed

runnillg

These

values

(halt

15

MPE

may

instructions

(firmware

mode

invoked)

by

software.

or

other

be seen

executed)

detected

Disables

software.

upon

TOC

traps).

Power

Enables

power-on.

Table

See

Fail

Power

Auto

Fail

8-

Auto

3.

Values

between

SOD

and

$FF

not

NOTE

shown

in

Table

H-2

are

undefined.

SYSTEM HALT

Table

Toe

VALUE CAUSE

8-3.

System

lIalt

Causes

Toe

RAM

Information

I

2

3

4

6

7

9

Values between SI 0

SII

$12

SI3

$14

$16

$17

$19

and

STT violation segment 1

Absent

Code segment I

ICS

Initial program load

Illegal SBnk

I'suedo-Enable when enabled

$1

f not shown

trap

while on les

stack overflow

at

NOTE

ill

Table B-3 are undefined.

tnp

violation

failure

QI-5 during

IXIT

DEC 86

HP MICRO 3000 Diagnostic Manual

Specifications and Main Features

Frequently Asked Questions

User Manual