HP LA-3331P Schematics

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Merom uFCPGA with Intel
Crestline_PM+ICH8-M core logic

3 3

2007-05-15

REV:1.0

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/04/13 2006/06/30

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-3331P

E

1.0

of

159Tuesday, May 1 5, 2007

A

Compal confidential

File Name : LA-3331P

B

C

D

E

ABITA

Thermal Sensor

1 1

LCD conn

page 18

ADM1032ARMZ

page 4

Mobile Merom

uFCPGA-478 CPU

page 4,5,6

CK505

Clock Generator
ICS9LPRS355

page 15

Fan Control

MXM III
Connector

page 17

page 4

PCI-E x 16

H_A#(3..35)
H_D#(0..63)

Intel Crestline MCH

FCBGA 1299

FSB

667/800MHz 1.05V

DDR2 667MHz 1.8V

Dual Channel

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

page 13,14

CRT & HDMI

page 16 page 7,8,9,10,11,12

2 2

CRT & DVI-D OUT
AV & SV OUT

page 36

PCI-E BUS

Intel ICH8-M

10/100/1000 LAN

Intel 82566MM

page 24

RJ45/11 CONN

3 3

page 25

Mini-Card

page 26

CardBus Controller

Rico R5C583

page 27,28

Slot 0/Smart Card

1394 port

6in1 Slot

LED

page 33

RTC CKT.

page 20

Power OK CKT.

page 38

4 4

Power On/Off CKT.

page 35

TPM1.2

SLB9635TT

page 33 page 33

Touch Pad CONN.

TrackPoint CONN.

DC/DC Int erface CKT.

page 37

A

B

PCI BUS

LPC BUS

SMSC KBC 1070

page 34

page 19,20,21,22

Security Classification

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DMI X4

mBGA-676

Int.KBD

Issued Date

C

SPI

SPI ROM

ST M25P32

page 32

COM1

( Docking )

2006/02/13 2006/03/10

USB2.0

Azalia

SATA Master

PATA Slave

SMSC Super I/O

LPC47N217

LPT

( Docking )

Compal Secret Data

Deciphered Date

USB x2
(Docking)

page 36

FingerPrinter AES1610
USBx1

page 33

USB conn x 2(For I/O)
BT Conn USB x 1

page31

MDC V1.5

page 35

Audio CKT

AD1981HD

page 29

SATA HDD Connector

page 23

PATA ODD Connector

page 23

Title

Size Document Number Rev

Custom

D

Date: Sheet

daughter board

MAX9710

AMP & Audio Jack

Docking CONN.

*RJ-45(LED*2)
*RJ-11(Pass Through)
*CRT
*COMPOSITE Video Out
*S-VIDEO OUT
*DVI-D
*LINE IN
*LINE OUT
*PCI-E x2
*Serial Port
*Parallel Port
*PS/2 x2
*USB x2
*DC JACK

Compal Electronics, Inc.

Block Diagram

LA-3331P

E

USB x 4

page 30

of

259Tuesday, May 1 5, 2007

1.0

A

Voltage Rails

+5VS

+3VM
+1.25VM
+1.05VM

O

OO
O
O

X

X

power
plane

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

O MEANS ON X MEANS OFF

LDO3
LDO5

O

O
O
O

O

X

+5VALW
+3VALW

PCI Devices

1 1

EXTERNAL

CARD BUS & 1394

DMA Channel
DMA0
DMA1
DMA2
DMA3
DMA4
DMA5
DMA6
DMA7

USB PORT#

0
1
2
3
4
5
6
7
8
9

IDSEL# REQ/GNT# PIRQ
AD22 2 C,D,E,G

Device
MODEM / LAN
ECP
FLOPPY DISK
AUDIO
(Cascade)
Unused
Unused
Unused

Destination

M/B

Finger Printer

M/B

On Audio Board

On Audio Board

On Audio Board

Blut Tooth

Docking

On Audio Board

Docking

+5V+B
+1.8V

+3VS
+1.8VS

+0.9V

+1.5VS
+1.25VS
+CPU_CORE
+VCCP

O

OO

OO
O
O

X

X

O

X

XX

X

X

XX

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2006/02/13 2006/03/10

IRQ

0
1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

17

18

19

20

21
22
23

Compal Secret Data

Deciphered Date

Device

System Timer

Keyboard

N/A

Serial port (COM2),LAN/Modem

Serial port (COM1)

Audio/VGA

Floppy

Parallel port

System CMOS/R eal-time clock

Microsoft ACPI

N/A,Momem,LAN

Mass strorage co nt ro l/ PCI simple communication control

synactic PS2 port GlidePAD

Numeric Data Process

Primary IDE interface,HDD

Secondary IDE innterface,CD-ROM

Mobile Intel C re st li ne Express Chipset Family
Microsoft UAA Bu s D ri ve r for High Definition Audio
Intel 82801H ( I C H 8 F a m i ly ) PCI Express Root Port -27D0
Broadcom Net X t r e me Gigabit Ethernet

Intel 82801H ( I C H 8 F a m i ly ) PCI Express Root Port - 27D2
Broadcom 802.11b/g WLAN
Intel 82801H ( I C H8 F a m i ly ) USB Universal Host Controll
Intel 82801H ( I C H8 F a m i ly ) USB Universal Host Controll
Ricoh R5C853 C ardbus Control
Ricoh R5C853 I nt eg ra tes FlashMedia Control
Ricoh R5C853 G em co re based SmartCard Control
Intel 82801H ( I C H 8 F a m i ly ) PCI Express Root Port - 27D6
Intel 82801H ( I C H8 F a m i ly ) USB Universal Host Controll

Intel 82801H ( I C H8 F a m i ly ) USB Universal Host Controll
Intel 82801H ( IC H8 Fa mi ly )USB2 Enhanced Host Controll

Intel 82801H ( I C H8 F a m i ly ) USB Universal Host Controll

SDA Standard C om pl ia nt SD Host Controller

HP Mobile Data Protection Sensor

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-3331P

359Tuesday, May 15, 2007

1.0

of

5

4

3

2

1

1
2
3

GND
GND

1
2
3

R443

1 2

1K_0402_5%@

G1
G2

R24
10K_0402_5%

+3VS

+VCCP

CLK_CPU_XDP# 15

H_RESET#
XDP_DBRESET#

THERM_SCI# 21

4
5

0413 add

ITP-XDP Connector

Change to same as
Chimay 4/6

JP31

1

TP_BPM#5

T95

TP_BPM#4

D D

H_A#[3..16]7

H_ADSTB#07

H_REQ#07
H_REQ#17
H_REQ#27
H_REQ#37
H_REQ#47

C C

B B

A A

H_A#[17..35]7

H_ADSTB#17

H_A20M#20

H_FERR#20

H_IGNNE#20
H_STPCLK#20

H_INTR20

H_NMI20
H_SMI#20

H_ADSTB#0
H_REQ#0

H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

JP8A

J4

ADDR GROUP 0 ADDR GROUP 1

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

Merom Ball-out Rev 1aconn@

DEFER#

CONTROL

RESET#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA
THERMDC

ICH

THERMTRIP#

H CLK

BCLK[0]
BCLK[1]

RESERVED

ADS#
BNR#
BPRI#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

PRDY#
PREQ#

TCK
TDO

TMS

TRST#

DBR#

TDI

H1
E2
G5

H5
F21
E1

F1
D20

B3
H4
C1

F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

H_ADS#
H_BNR#
H_BPRI#

H_DEFER#
H_DRDY#
H_DBSY#

H_BR0#
H_IERR#

H_INIT#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

H_HIT#
H_HITM#

XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#

XDP_DBRESET#

H_PROCHOT#

H_THERMTRIP#

CLK_CPU_BCLK
CLK_CPU_BCLK#

R1613 56_0402_5%

Cut them but reserve TP for
ESD request. 5/8

R2188 0_0402_5%

1 2

R2189 0_0402_5%

1 2

H_ADS# 7
H_BNR# 7

H_BPRI# 7

H_DEFER# 7
H_DRDY# 7
H_DBSY# 7

H_BR0# 7

12

H_INIT# 20
H_LOCK# 7
H_RESET# 7

H_RS#0 7

H_RS#1 7

H_RS#2 7

H_TRDY# 7

H_HIT# 7
H_HITM# 7

XDP_BPM#0_TP
XDP_BPM#1_TP
XDP_BPM#2_TP
XDP_BPM#3_TP
XDP_BPM#4_TP
XDP_BPM#5

XDP_DBRESET# 21

R1614 68_0402_5%

H_THERMTRIP# 7,20

CLK_CPU_BCLK 15
CLK_CPU_BCLK# 15

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

T101
T102
T103
T104
T105

12

+VCCP

H_PROCHOT# 46,47

+VCCP

H_THERMDA
H_THERMDC

H_PWRGOOD5,20 CLK_CPU_XDP 15

Removed at 5/30.(Follow
Chimay)

H_PROCHOT# OCP#

T96

TP_BPM#3

T97

TP_BPM#2

T98

TP_BPM#1

T99

R442
1K_0402_5%

12

R1616

56_0402_5%@

C

TP_BPM#0

H_PWRGOOD_R

12

XDP_HOOK1

XDP_TCK

OCP# 21,48

T100

Cut them but reserve TP
for ESD request. 5/8

C539 0.1U_0402_16V4Z

+VCCP

12

B

2

E

3 1

Q78

MMBT3904_SOT23@

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-Aconn@

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

Thermal Sensor ADM1032ARMZ

C69

0.1U_0402_16V4Z

1 2

C68 2200P_0402_50V7K

+3VS

1 2

R25 10K_0402_5%

PWM Fan & System Fan Control circuit

Change to sa m e as Chimay 4/6

FAN_PWM34

Will Reserved R2186 if
don't use 2'rd FAN.
9/8

Add in 9/6.
Change to
GPIO20. 9/8

THERM#

GPIO2021

GND1
OBSFN_C0
OBSFN_C1

GND3

GND5

GND7
OBSFN_D0
OBSFN_D1

GND9

GND11

GND13

GND15

TD0

TRST#

TDI

TMS

GND17

+3VS

2

1

H_THERMDA
H_THERMDC

THERM#

1
2

1 2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

1
2
3

ADM1032ARMZ-2REEL_MSOP8

+3VS

U31

5

TC7SH00FU_SSOP5

P

INB

O

INA

G

3

R2186
0_0402_5%

R2185
10K_0402_5%

Add in 9/7.

XDP_DBRESET#_R

1 2

Change value in 5/02

XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5
XDP_HOOK1
XDP_TRST#
XDP_TCK

CLK_CPU_XDP
CLK_CPU_XDP#

H_RESET#_R
XDP_DBRESET#_R

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE

R524 54.9_0402_1%

1 2

R523 54.9_0402_1%

1 2

R525 54.9_0402_1%

1 2

R526 54.9_0402_1%

1 2

R1612 54.9_0402_1%@

1 2

R521 51_0402_1%

1 2

R522 54.9_0402_1%

1 2

This shall place near CPU

+VCCP+VCCP

R441 1K_0402_1%

1 2

R444 200_0402_1%

R191
0_0402_5%

1 2

12

Place R191 within 200ps (~1") to CPU

ICH_SM_CLK17,21,26

ICH_SM_DA17,21,26

U5

VDD
D+

SDATA

ALERT#

D­THERM#4GND

4

12

SCLK

1 2

ICH_SM_CLK
ICH_SM_DA

Address:100_1100

ICH_SM_CLK

8

ICH_SM_DA

7

THERM_SCI#

6
5

Change conne c tor type from
4pin to 3 pin. 6/8
Change pin connection 4/25

conn@

ACES_85205-03001

1
2
3

4
5

1
2

3
conn@

ACES_85204-03001

R1615

+5VS

0_0402_5%@

+5VS

JP6

JP53

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Merom(1/3)-AGTL+/XDP

LA-3331P

1

1.0

of

459Tuesday, May 15, 2007

5

4

3

2

1

Correct net name 4/27

H_D#[0..15]7

D D

H_DSTBN#07
H_DSTBP#07

H_DINV#07

H_D#[16..31]7

C C

layout note: Route TEST3 & TEST5 traces on
ground referenced layer to the TPs

H_DSTBN#17
H_DSTBP#17

H_DINV#17

R1619 1K_0402_5%@

1 2

R1620 1K_0402_5%@

1 2

C1231 0.1U_0402_16V4Z@

1 2

CPU_BSEL015
CPU_BSEL115
CPU_BSEL215

T49
T50

T51

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

V_CPU_GTLREF

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

CPU_BSEL CPU_BSEL2 CPU_BSEL1

166

B B

200

V_CPU_GTLREF

01

0

+VCCP

12

R1626
1K_0402_1%

12

R1628
2K_0402_1%

AD26

AF26

JP8B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#
GTLREF

C23

TEST1

D25

TEST2

C24

TEST3
TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Merom Ball-out Rev 1aconn@

DATA GRP 0

DATA GRP 1

MISC

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#

DATA GRP 2DATA GRP 3

D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

COMP0
COMP1
COMP2
COMP3

CPU_BSEL0

1

1

0

H_D#[32..47] 7

H_DSTBN#2 7
H_DSTBP#2 7
H_DINV#2 7
H_D#[48..63] 7

H_DSTBN#3 7
H_DSTBP#3 7
H_DINV#3 7

H_DPRSTP# 7,20,46
H_DPSLP# 20

H_DPWR# 7

H_PWRGOOD 4,20
H_CPUSLP# 7

H_PSI# 46

12

R1621

54.9_0402_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.

R1622

27.4_0402_1%

12

R1623

12

R1624

54.9_0402_1%

12

27.4_0402_1%

+VCC_CORE +VCC_CORE

Correct net name 6/16

AA10
AA12
AA13
AA15
AA17
AA18
AA20

AC10
AB10
AB12
AB14
AB15
AB17
AB18

A7

A9
A10
A12
A13
A15
A17
A18
A20

B7

B9
B10
B12
B14
B15
B17
B18
B20

C9
C10
C12
C13
C15
C17
C18

D9
D10
D12
D14
D15
D17
D18

E7

E9
E10
E12
E13
E15
E17
E18
E20

F7

F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9

AB9

JP8C

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

Merom Ball-out Rev 1a

conn@

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

R1617 0_0402_5%

G21
V6

R1618 0_0402_5%

J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

.

+VCC_CORE

VCCSENSE

VSSSENSE

1 2

1 2

Close to CPU pin
within 500mils.

R1627
100_0402_1%

R1629
100_0402_1%

+VCCP

12
12

1

+

2

CPU_VID0 46
CPU_VID1 46
CPU_VID2 46
CPU_VID3 46
CPU_VID4 46
CPU_VID5 46
CPU_VID6 46

VCCSENSE 46

VSSSENSE 46

C1230
330U_D2E_2.5VM_R7

1

2

C1232

Near pin C26

Length match
within 25 mils.
The trace

+1.5VS

1

2

C1233

10U_0805_10V4Z

0.01U_0402_16V7K

Near pin B26

width/space/other
is 20/7/25.

VCCSENSE

VSSSENSE

Close to CPU pin AD26
within 500mils.

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Merom(2/3)-AGTL+/PWR

LA-3331P

1

1.0

of

559Tuesday, May 15, 2007

5

Place these capacitors on L8
(North side,Secondary Layer)

4

+VCC_CORE

1

C412
10U_0805_6.3V6M

2

1

C413
10U_0805_6.3V6M

2

1

C414
10U_0805_6.3V6M

2

3

1

C415
10U_0805_6.3V6M

2

1

C416
10U_0805_6.3V6M

2

1

C417
10U_0805_6.3V6M

2

2

1

C425
10U_0805_6.3V6M

2

1

C479
10U_0805_6.3V6M

2

1

D D

C C

B B

JP8D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

conn@

P6

VSS[082]

P21

VSS[083]

P24

VSS[084]

R2

VSS[085]

R5

VSS[086]

R22

VSS[087]

R25

VSS[088]

T1

VSS[089]

T4

VSS[090]

T23

VSS[091]

T26

VSS[092]

U3

VSS[093]

U6

VSS[094]

U21

VSS[095]

U24

VSS[096]

V2

VSS[097]

V5

VSS[098]

V22

VSS[099]

V25

VSS[100]

W1

VSS[101]

W4

VSS[102]

W23

VSS[103]

W26

VSS[104]

Y3

VSS[105]

Y6

VSS[106]

Y21

VSS[107]

Y24

VSS[108]

AA2

VSS[109]

AA5

VSS[110]

AA8

VSS[111]

AA11

VSS[112]

AA14

VSS[113]

AA16

VSS[114]

AA19

VSS[115]

AA22

VSS[116]

AA25

VSS[117]

AB1

VSS[118]

AB4

VSS[119]

AB8

VSS[120]

AB11

VSS[121]

AB13

VSS[122]

AB16

VSS[123]

AB19

VSS[124]

AB23

VSS[125]

AB26

VSS[126]

AC3

VSS[127]

AC6

VSS[128]

AC8

VSS[129]

AC11

VSS[130]

AC14

VSS[131]

AC16

VSS[132]

AC19

VSS[133]

AC21

VSS[134]

AC24

VSS[135]

AD2

VSS[136]

AD5

VSS[137]

AD8

VSS[138]

AD11

VSS[139]

AD13

VSS[140]

AD16

VSS[141]

AD19

VSS[142]

AD22

VSS[143]

AD25

VSS[144]

AE1

VSS[145]

AE4

VSS[146]

AE8

VSS[147]

AE11

VSS[148]

AE14

VSS[149]

AE16

VSS[150]

AE19

VSS[151]

AE23

VSS[152]

AE26

VSS[153]

A2

VSS[154]

AF6

VSS[155]

AF8

VSS[156]

AF11

VSS[157]

AF13

VSS[158]

AF16

VSS[159]

AF19

VSS[160]

AF21

VSS[161]

A25
AF25

VSS[163]

Merom Ball-out Rev 1a

.

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

1

C411
10U_0805_6.3V6M

C441
10U_0805_6.3V6M

C442
10U_0805_6.3V6M

+VCCP

1

C437

0.1U_0402_10V6K

2

C481
10U_0805_6.3V6M

2

1

C423
10U_0805_6.3V6M

2

1

C435
10U_0805_6.3V6M

2

Removed C434 at 4/18

Removed C1570 ~ C1573 , cause FSB Common clock have move to bottom side.8/1

1

C480
10U_0805_6.3V6M

2

1

C432
10U_0805_6.3V6M

2

1

C436
10U_0805_6.3V6M

2

1

C486
10U_0805_6.3V6M

2

1

C422
10U_0805_6.3V6M

2

1

C443
10U_0805_6.3V6M

2

No istall C67 , C125 at 2007/03/23.

South Side Secondary

+VCC_CORE

1

C409

+

2

330U_D2E_2.5VM_R9

1

C421

0.1U_0402_10V6K

2

1

C67

+

2

@

330U_D2E_2.5VM_R9

C408

1

C429

0.1U_0402_10V6K

2

1

+

2

330U_D2E_2.5VM_R9

1

C418
10U_0805_6.3V6M

2

1

C446
10U_0805_6.3V6M

2

1

C444
10U_0805_6.3V6M

2

North Side Secondary

1

C66

+

2

1

C438

0.1U_0402_10V6K

2

1

C117

+

2

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

1

2

1

+

C125
330U_D2E_2.5VM_R9

2

C428

0.1U_0402_10V6K

1

C482
10U_0805_6.3V6M

2

1

C424
10U_0805_6.3V6M

2

1

C427
10U_0805_6.3V6M

2

@

1

C433

0.1U_0402_10V6K

2

1

C483
10U_0805_6.3V6M

2

1

C445
10U_0805_6.3V6M

2

1

C426
10U_0805_6.3V6M

2

1

C484
10U_0805_6.3V6M

2

1

C485
10U_0805_6.3V6M

2

1

C431
10U_0805_6.3V6M

2

ESR <= 1.5m ohm
Capacitor > 1980uF

Place these inside
socket cavity on L8
(North side
Secondary)

Mid Frequence Decoupling

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Merom(3/3)-GND&Bypass

LA-3331P

1

1.0

of

659Tuesday, May 15, 2007

5

AD12

AC14
AD11
AC11

AE11
AH12

AH13

H_RCOMP

W10

AJ14

M10
N12

AE3
AD9
AC9
AC7

AB2
AD7
AB1

AC6
AE2
AC5
AG3

AH8
AE9

AH5
AE7

AE5
AH2

E2

G2
G7
M6
H7
H3
G4

F3
N8
H2

N9
H5

P13

K9
M2

Y8

V4
M3

J1
N5
N3
W6
W9
N2

Y7

Y9

P4
W3
N1

Y3

AJ9

AJ5
AJ6
AJ7

AJ2
AJ3

B3
C2

W1
W2

B6

E5

B9

A9

U4A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

H_CPURST#
H_CPUSLP#

H_AVREF
H_DVREF

CRESTLINE_1p0

+VCCP

12

R1645

12

R1651

221_0603_1%

1

2

100_0402_1%

HOST

H_SWNGH_VREF

0.1U_0402_16V4Z

C1241

H_ADSTB#_0
H_ADSTB#_1

H_DEFER#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1

H_REQ#_2
H_REQ#_3

H_REQ#_4

H_D#[0..63]5

D D

C C

+VCCP

12

12

R1638

R1639

54.9_0402_1%

54.9_0402_1%

H_RESET#4

H_CPUSLP#5

B B

Layout Note:
H_RCOMP / H_VREF / H_SWNG

trace width and spacing is 18/20

+VCCP

12

1K_0402_1%

R1644

12

A A

R1649

2K_0402_1%

1

2

C1240

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWNG
H_RCOMP

H_SCOMP
H_SCOMP#

H_VREF

12

R1650

24.9_0402_1%

0.1U_0402_16V4Z

Near B3 pinwithin 100 mils from NB

5

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#
H_DBSY#

H_DRDY#

H_HIT#
H_HITM#

H_LOCK#
H_TRDY#

H_RS#_0
H_RS#_1
H_RS#_2

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

K5
L2
AD13
AE13

M7
K3
AD2
AH11

L7
K2
AC2
AJ10

M14
E13
A11
H13
B12

E12
D7
D8

4

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

V_DDR_MCH_REF13,14,45

H_A#[3..35] 4

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BR0# 4
H_DEFER# 4
H_DBSY# 4
CLK_MCH_BCLK 15
CLK_MCH_BCLK# 15
H_DPWR# 5
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4

H_DINV#0 5
H_DINV#1 5
H_DINV#2 5
H_DINV#3 5

H_DSTBN#0 5
H_DSTBN#1 5
H_DSTBN#2 5
H_DSTBN#3 5

H_DSTBP#0 5
H_DSTBP#1 5
H_DSTBP#2 5
H_DSTBP#3 5

H_REQ#0 4
H_REQ#1 4
H_REQ#2 4
H_REQ#3 4
H_REQ#4 4

H_RS#0 4
H_RS#1 4
H_RS#2 4

VGATE21,46

PM_PWROK21,34,46

H_THERMTRIP#4,20

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

SMRCOMP_VOH

Change SN to
SD034301180(LF
part). 5/12

SMRCOMP_VOL

Add for using DDR2 2Gb tech. 6/9

PM_EXTTS#013

PM_EXTTS#114,47

R1484 0_0402_5%
R1483 0_0402_5%@

PLT_RST#19,20,21,26,32,33

Mount R2134.9/6

Reserve R2134 for Cresline A0.
Install R2134 from Cresline B0.

V_DDR_MCH_REF

1

2

C1239

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V

2

2

2.2U_0603_10V6K

2.2U_0603_10V6K

1K_0402_1%@

1K_0402_1%@

C1235

1

0.01U_0402_25V7K

1

C1237

2

0.01U_0402_25V7K

DDR_A_MA1413
DDR_B_MA1414

PM_EXTTS#0

PM_EXTTS#1

CLKREQB#

MCH_CLKSEL015
MCH_CLKSEL115
MCH_CLKSEL215

PM_BMBUSY#21

H_DPRSTP#5,20,46

1 2
1 2

3

12

R1630
1K_0402_1%

12

R1631

3.01K_0402_1%

12

R1632
1K_0402_1%

T52
T53

CFG59

T54

CFG79
CFG89
CFG99

T55

T56

CFG129
CFG139

T57

T58

CFG169

T59

T60

CFG199
CFG209

C1234

1

1

C1236

2

12
12

R1640 100_0402_5%
R2134 0_0402_5%

+1.8V

12

R1643

12

R1646

U4B

P36

RSVD1

P37

RSVD2

R35

RSVD3

N35

RSVD4

AR12

RSVD5

AR13

RSVD6

AM12

RSVD7

AN13

RSVD8

J12

RSVD9

AR37

RSVD10

AM36

RSVD11

AL36

RSVD12

AM37

RSVD13

D20

RSVD14

H10

RSVD20

B51

RSVD21

BJ20

RSVD22

BK22

RSVD23

BF19

RSVD24

BH20

RSVD25

BK18

RSVD26

BJ18

RSVD27

BF23

RSVD28

BG23

RSVD29

BC23

RSVD30

BD24

RSVD31

BJ29

RSVD32

BE24

RSVD33

BH39

+3VS

R1635

12

10K_0402_5%

R1636

12

10K_0402_5%

R1637

12

10K_0402_5%

PAD
PAD

PAD

PAD
PAD

PAD
PAD

PAD
PAD

PWROK

DPRSLPVR21,46

CFG3
CFG4

CFG6

CFG10
CFG11

CFG14
CFG15

CFG17
CFG18

PM_EXTTS#0
PM_EXTTS#1

PLT_RST#_R

2006/02/13 2006/03/10

RSVD34

AW20

RSVD35

BK20

RSVD36

C48

RSVD37

D47

RSVD38

B44

RSVD39

C44

RSVD40

A35

RSVD41

B37

RSVD42

B36

RSVD43

B34

RSVD44

C34

RSVD45

P27

CFG_0

N27

CFG_1

N24

CFG_2

C21

CFG_3

C23

CFG_4

F23

CFG_5

N23

CFG_6

G23

CFG_7

J20

CFG_8

C20

CFG_9

R24

CFG_10

L23

CFG_11

J23

CFG_12

E23

CFG_13

E20

CFG_14

K23

CFG_15

M20

CFG_16

M24

CFG_17

L32

CFG_18

N33

CFG_19

L35

CFG_20

G41

PM_BM_BUSY#

L39

PM_DPRSTP#

L36

PM_EXT_TS#_0

J36

PM_EXT_TS#_1

AW49

PWROK

AV20

RSTIN#

N20

THERMTRIP#

G36

DPRSLPVR

BJ51

NC_1

BK51

NC_2

BK50

NC_3

BL50

NC_4

BL49

NC_5

BL3

NC_6

BL2

NC_7

BK1

NC_8

BJ1

NC_9

E1

NC_10

A5

NC_11

C51

NC_12

B50

NC_13

A50

NC_14

A49

NC_15

BK2

NC_16

CRESTLINE_1p0

Compal Secret Data

Deciphered Date

2

DDR MUXINGCLK

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CFGRSVD

DMI

PM

GRAPHICS VID

ME

NC

SDVO_CTRL_DATA

Connect to GND 4/25 (DG9.0 P.190)

MISC

2

SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4

SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4

SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF_0
SM_VREF_1

DPLL_REF_CLK

DPLL_REF_CLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

NC in 4/24

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#
CL_VREF

SDVO_CTRL_CLK

CLK_REQ#

ICH_SYNC#

TEST_1
TEST_2

1

For Crestline: 20ohm

AV29
BB23
BA25
AV23

AW30
BA23
AW25
AW23

BE29
AY32
BD39
BG37

BG20
BK16
BG16
BE13

BH18
BJ15
BJ14
BE16

BL15
BK14

BK31
BL31

AR49
AW4

SMRCOMP
SMRCOMP#

SMRCOMP_VOH
SMRCOMP_VOL

V_DDR_MCH_REF

For Calero: 80.6ohm

M_CLK_DDR0 13
M_CLK_DDR1 13
M_CLK_DDR2 14
M_CLK_DDR3 14

M_CLK_DDR#0 13
M_CLK_DDR#1 13
M_CLK_DDR#2 14
M_CLK_DDR#3 14

DDR_CKE0_DIMMA 13
DDR_CKE1_DIMMA 13
DDR_CKE2_DIMMB 14
DDR_CKE3_DIMMB 14

DDR_CS0_DIMMA# 13
DDR_CS1_DIMMA# 13
DDR_CS2_DIMMB# 14
DDR_CS3_DIMMB# 14

M_ODT0 13
M_ODT1 13
M_ODT2 14
M_ODT3 14

R1633 20_0402_1%
R1634 20_0402_1%

12
12

Del in 4/24

B42
C42
H48
H47

K44
K45

AN47
AJ38
AN42
AN46

AM47
AJ39
AN41
AN45

AJ46
AJ41
AM40
AM44

AJ47
AJ42
AM39
AM43

E35
A39
C38
B39
E36

AM49
AK50
AT43
AN49

CL_VREF

AM50

H35
K36

CLKREQB#

G39
G40

A37
R32

R1647

20K_0402_5%

Title

Size Document Number Rev

Custom

Date: Sheet

Correct the net name.8/11

CLK_MCH_3GPLL 15
CLK_MCH_3GPLL# 15

DMI_TXN0 21
DMI_TXN1 21
DMI_TXN2 21
DMI_TXN3 21

DMI_TXP0 21
DMI_TXP1 21
DMI_TXP2 21
DMI_TXP3 21

DMI_RXN0 21
DMI_RXN1 21
DMI_RXN2 21
DMI_RXN3 21

DMI_RXP0 21
DMI_RXP1 21
DMI_RXP2 21
DMI_RXP3 21

+1.25VM_AXD

Closed to AM50 pin

12

12

R1648
0_0402_5%

CL_CLK0 21
CL_DATA0 21
M_PWROK 21,38
CL_RST# 21

C1238

0.1U_0402_16V4Z

CLKREQB# 15
MCH_ICH_SYNC# 21

12

R1641
1K_0402_1%

12

1

R1642
392_0402_1%

2

Compal Electronics, Inc.

CRESTLINE(1/6)-AGTL+/DMI/DDR2

LA-3331P

759Tuesday, May 1 5, 2007

1

+1.8V

1.0

of

5

D D

DDR_A_D[0..63]13

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8

DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AR43

AW44

BA45
AY46
AR41
AR45
AT42

AW47

BB45
BF48
BG47

BJ45
BB47
BG50
BH49
BE45

AW43

BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40

AW40

AT39

AW36
AW41

AY41
AV38
AT38
AV13
AT13

AW11

AV11
AU15
AT11
BA13
BA11
BE10
BD10

BG10

AW9

AM8
AN10

AM9
AN11

BD8
AY9

BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3

AT9
AN9

U4D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

CRESTLINE_1p0

DDR SYSTEM MEMORY A

SA_BS_0
SA_BS_1
SA_BS_2

SA_CAS#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_RAS#

SA_RCVEN#

SA_WE#

4

BB19
BK19
BF29

BL17
AT45

BD44
BD42
AW38
AW13
BG8
AY5
AN6

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16

BE18
AY20

BA19

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

SA_RCVEN#

DDR_A_BS0 13
DDR_A_BS1 13
DDR_A_BS2 13

DDR_A_CAS# 13 DDR_B_CAS# 14
DDR_A_DM[0..7] 13

DDR_A_DQS[0..7] 13

DDR_A_DQS#[0..7] 13

DDR_A_MA[0..14] 7,13

DDR_A_RAS# 13

T62

DDR_A_WE# 13

3

DDR_B_D[0..63]14

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8

DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AP49

AR51
AW50
AW51

AN51

AN50

AV50

AV49

BA50

BB50

BA49

BE50

BA51

AY49

BF50

BF49

BL43
BK47
BK49
BK43
BK42

BJ41

BL41

BJ37

BJ36
BK41

BJ40

BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12

BJ10

BK10

BJ50
BJ44
BJ43

BG1

BL9
BK5
BL5
BK9

BJ8
BJ6
BF4
BH5

BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

2

U4E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

CRESTLINE_1p0

1

AY17

SB_BS_0

BG18

SB_BS_1

BG36

SB_BS_2

BE17

SB_CAS#
SB_DM_0

SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

DDR SYSTEM MEMORY B

AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13

AV16
AY18

BC17

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6

DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

SB_RCVEN#

DDR_B_RAS# 14

T61

DDR_B_WE# 14

DDR_B_BS0 14
DDR_B_BS1 14
DDR_B_BS2 14

DDR_B_DM[0..7] 14

DDR_B_DQS[0..7] 14

DDR_B_DQS#[0..7] 14

DDR_B_MA[0..14] 7,14

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((2/6)-DDR2 A/B CH

LA-3331P

1

of

859Tuesday, May 1 5, 2007

1.0

5

4

3

2

1

Strap Pin Table

010 = FSB 800MHz

CFG[2:0] FSB Freq select

D D

Tie to GND 4/24

C C

B B

Tie to GND 4/24

U4C

J40
H39
E39
E40
C37
D35
K40

L41
L43
N41
N40
D46
C45
D44
E42

G51
E51
F49

G50
E50
F48

G44
B47
B45

E44
A47
A45

E27
G27
K27

F27
J27
L27

M35

P33

H32
G32
K29
J29
F29
E29

K33
G35
F33
C32
E33

CRESTLINE_1p0

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2

TVA_DAC
TVB_DAC
TVC_DAC

TVA_RTN
TVB_RTN
TVC_RTN

TV_DCONSEL_0
TV_DCONSEL_1

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

LVDS

TV VGA

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_10

PEG_RX_11

PEG_RX_12

PEG_RX_13

PEG_RX_14

PEG_RX_15

PEG_TX#_0

PEG_TX#_1

PEG_TX#_2

PEG_TX#_3

PEG_TX#_4

PEG_TX#_5

PEG_TX#_6

PEG_TX#_7

PEG_TX#_8

PEG_TX#_9
PEG_TX#_10

PCI-EXPRESS GRAPHICS

PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_10

PEG_TX_11

PEG_TX_12

PEG_TX_13

PEG_TX_14

PEG_TX_15

PEGCOMP trace width and
spacing is 18/25 mils.

N43
M43

J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41

J50

PEG_RX_0

L50

PEG_RX_1

M47

PEG_RX_2

U44

PEG_RX_3

T49

PEG_RX_4

T41

PEG_RX_5

W45

PEG_RX_6

W41

PEG_RX_7

AB50

PEG_RX_8

Y48

PEG_RX_9

AC45
AC41
AH47
AG49
AH45
AG42

N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44

M45

PEG_TX_0

T38

PEG_TX_1

T46

PEG_TX_2

N50

PEG_TX_3

R51

PEG_TX_4

U43

PEG_TX_5

W42

PEG_TX_6

Y47

PEG_TX_7

Y39

PEG_TX_8

AC38

PEG_TX_9

AD47
AC50
AD43
AG39
AE50
AH43

PEGCOMP

PEG_RXP15
PEG_RXP14
PEG_RXP13
PEG_RXP12
PEG_RXP11
PEG_RXP10
PEG_RXP9
PEG_RXP8
PEG_RXP7
PEG_RXP6
PEG_RXP5
PEG_RXP4
PEG_RXP3
PEG_RXP2
PEG_RXP1
PEG_RXP0

PEG_RXN15
PEG_RXN14
PEG_RXN13
PEG_RXN12
PEG_RXN11
PEG_RXN10
PEG_RXN9
PEG_RXN8
PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_RXN4
PEG_RXN3
PEG_RXN2
PEG_RXN1
PEG_RXN0

PEG_TXP15
PEG_TXP14
PEG_TXP13
PEG_TXP12
PEG_TXP11
PEG_TXP10
PEG_TXP9
PEG_TXP8
PEG_TXP7
PEG_TXP6
PEG_TXP5
PEG_TXP4
PEG_TXP3
PEG_TXP2
PEG_TXP1
PEG_TXP0

PEG_TXN15
PEG_TXN14
PEG_TXN13
PEG_TXN12
PEG_TXN11
PEG_TXN10
PEG_TXN9
PEG_TXN8
PEG_TXN7
PEG_TXN6
PEG_TXN5
PEG_TXN4
PEG_TXN3
PEG_TXN2
PEG_TXN1
PEG_TXN0

+VCCP

R1652

24.9_0402_1%

1 2

PEG_RXP[0..15] 17

PEG_RXN[0..15] 17

C1242 0.1U_0402_16V4Z
C1243 0.1U_0402_16V4Z
C1244 0.1U_0402_16V4Z
C1245 0.1U_0402_16V4Z
C1246 0.1U_0402_16V4Z
C1247 0.1U_0402_16V4Z
C1248 0.1U_0402_16V4Z
C1249 0.1U_0402_16V4Z
C1250 0.1U_0402_16V4Z
C1251 0.1U_0402_16V4Z
C1252 0.1U_0402_16V4Z
C1253 0.1U_0402_16V4Z
C1254 0.1U_0402_16V4Z
C1255 0.1U_0402_16V4Z
C1256 0.1U_0402_16V4Z
C1257 0.1U_0402_16V4Z

C1258 0.1U_0402_16V4Z
C1259 0.1U_0402_16V4Z
C1260 0.1U_0402_16V4Z
C1261 0.1U_0402_16V4Z
C1262 0.1U_0402_16V4Z
C1263 0.1U_0402_16V4Z
C1264 0.1U_0402_16V4Z
C1265 0.1U_0402_16V4Z
C1266 0.1U_0402_16V4Z
C1267 0.1U_0402_16V4Z
C1268 0.1U_0402_16V4Z
C1269 0.1U_0402_16V4Z
C1270 0.1U_0402_16V4Z
C1271 0.1U_0402_16V4Z
C1272 0.1U_0402_16V4Z
C1273 0.1U_0402_16V4Z

PEG_M_TXP15
PEG_M_TXP14
PEG_M_TXP13
PEG_M_TXP12
PEG_M_TXP11
PEG_M_TXP10
PEG_M_TXP9
PEG_M_TXP8
PEG_M_TXP7
PEG_M_TXP6
PEG_M_TXP5
PEG_M_TXP4
PEG_M_TXP3
PEG_M_TXP2
PEG_M_TXP1
PEG_M_TXP0

PEG_M_TXN15
PEG_M_TXN14
PEG_M_TXN13
PEG_M_TXN12
PEG_M_TXN11
PEG_M_TXN10
PEG_M_TXN9
PEG_M_TXN8
PEG_M_TXN7
PEG_M_TXN6
PEG_M_TXN5
PEG_M_TXN4
PEG_M_TXN3
PEG_M_TXN2
PEG_M_TXN1
PEG_M_TXN0

PEG_M_TXP[0..15] 17

PEG_M_TXN[0..15] 17

Removed J14 4/27

CFG5 (DMI select)

CFG6

CFG7 (CPU Strap)

CFG8 (Low power PCIE)

CFG9

(PCIE Graphics Lane Reversal)

CFG[11:10]

CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

SDVO_CTRLDATA

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

CFG57

CFG77

CFG87

CFG97

CFG127

CFG137

CFG167

CFG[17:3] have internal pull up
CFG[19:18] have internal pull down

CFG197

A A

CFG207

011 = FSB 667MHz
Others = Reserved

0 = DMI x 2
1 = DMI x 4

*

Reserved

0 = Reserved
1 = Mobile CPU

*

0 = Normal mode
1 = Low Power mode

0 = Reverse Lane
1 = Normal Operation

Reserved
00 = Reserved

01 = XOR Mode Enabled
10 = All Z Mode Enabled

11 = Normal Operation

ReservedCFG[15:14]

0 = Disabled
1 = Enabled

*

ReservedCFG[18:17]

0 = No SDVO Device Present
1 = SDVO Device Present

0 = Normal Operation

(Lane number in Order)

1 = Reverse Lane

0 = Only PCIE or SDVO is operational.
1 = PCIE/SDVO a r e o p e r a t ing simu.

R1653 4.02K_0402_1%~D@

1 2

R1654 4.02K_0402_1%~D@

1 2

R1655 4.02K_0402_1%~D@

1 2

R1656 4.02K_0402_1%~D@

1 2

R1657 4.02K_0402_1%~D@

1 2

R1658 4.02K_0402_1%~D@

1 2

R1661 4.02K_0402_1%~D@

1 2

R1662

1 2

1 2

4.02K_0402_1%~D@

4.02K_0402_1%~D@

R1663

*
*

(Default)

*

+3VS

*

*

*

Change Value
form 2.2K to

4.02K.

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((3/6)-VGA/LVDS/TV

LA-3331P

1

of

959Tuesday, May 1 5, 2007

1.0

5

D D

+1.25VM_HPLL+1.25VM

R1664

0_0805_5%

1 2

Modify from
22uF to 10uF.
6/24

+1.25VM +1.25VM_MPLL

R1667
0_0805_5%

C C

+1.25VS

BLM18PG121SN1D_0603

Add regarding
DG1.0 (page

466). 6/8

B B

1 2

Modify from
22uF to 10uF.
6/24

L15

1 2

R2133

Add in 4/24

C1294

+1.5VS

C1321

1_0603_1%

1 2

10U_0805_10V4Z

1

2

10U_0805_10V4Z

1

2

1

C1276

2

1

1

C1284

C1285

2

2

10U_0805_10V4Z

+1.25VS_PEGPLL

0.1U_0402_16V4Z

1

C1295

2

0.1U_0402_16V4Z
C1323

C1322

1

2

Del R1665,R1666,C1274,C1275,C1277,C1278
4/27

10U_0805_10V4Z

Tied to GND after HP
confirm with Intel. 6/15

+3VS

1

+

2

150U_D_6.3VM

12

R1671
0_0603_5%

C1292

0.1U_0402_16V4Z

R1673
0_0805_5%

1 2

C1297

22U_0805_6.3V4Z

1

C1311

2

12

+1.25VM_A_SM_CK

1

C1303

2

+1.25VS_PEGPLL

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.25VM

R1675 0_0603_5%

5.

0.022U_0402_16V7K

1

+1.25VM_HPLL

2

C1296

4

Connect to GND 4/27
(DG0.9 P.191)

+3VS_PEG_BG

1

2

1

C1298

4.7U_0805_6.3V6K

2

1

C1304

2

22U_0805_6.3V4Z

Change net in 5/02 (DG0.9 P.174)

+1.25VM_A_SM

1

2

1

C1305

2

1U_0603_10V4Z

1U_0402_6.3V4Z

1

C1552

2

0.1U_0402_16V4Z

C1299

1

C1306

2

1

2

1U_0603_10V4Z

0.1U_0402_16V4Z

U4H

J32

3.

4.

VCCSYNC

A33

VCCA_CRT_DAC_1

B33

VCCA_CRT_DAC_2

A30

VCCA_DAC_BG

B32

VSSA_DAC_BG

B49

VCCA_DPLLA

H49

VCCA_DPLLB

AL2

VCCA_HPLL

AM2

VCCA_MPLL

A41

VCCA_LVDS

B41

VSSA_LVDS

K50

VCCA_PEG_BG

K49

VSSA_PEG_BG

U51

VCCA_PEG_PLL

AW18

VCCA_SM_1

AV19

VCCA_SM_2

AU19

VCCA_SM_3

AU18

VCCA_SM_4

AU17

VCCA_SM_5

AT22

VCCA_SM_7

AT21

VCCA_SM_8

AT19

VCCA_SM_9

AT18

VCCA_SM_10

AT17

VCCA_SM_11

AR17

VCCA_SM_NCTF_1

AR16

VCCA_SM_NCTF_2

BC29

VCCA_SM_CK_1

BB29

VCCA_SM_CK_2

C25

VCCA_TVA_DAC_1

B25

VCCA_TVA_DAC_2

C27

VCCA_TVB_DAC_1

B27

VCCA_TVB_DAC_2

B28

VCCA_TVC_DAC_1

A28

VCCA_TVC_DAC_2

M32

VCCD_CRT

L29

VCCD_TVDAC

N28

VCCD_QDAC

AN2

VCCD_HPLL

U48

VCCD_PEG_PLL

2.

J41

VCCD_LVDS_1

H42

VCCD_LVDS_2

CRESTLINE_1p0

Tie to GND 4/24

1.

POWER

CRTPLLA PEGA SMTV

A CK A LVDS

D TV/CRTLVDS

3

VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5

AXD

VCC_AXD_6

VCC_AXD_NCTF

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

VCC_TX_LVDS

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4

PEG

VCC_PEG_5

VCC_RXR_DMI_1
VCC_RXR_DMI_2

DMI

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13

VTT

VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22

VCC_DMI

VCC_HV_1
VCC_HV_2

HV

VTTLF1
VTTLF2
VTTLF3

VTTLF

U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

AT23
AU28
AU24
AT29
AT25
AT30

AR29

B23
B21
A21

AJ50

BK24
BK23
BJ24
BJ23

A43

C40
B40

AD51
W50
W51
V49
V50

AH50
AH51

A7
F2
AH1

C1312

+VCCP

0.47U_0603_10V7K

+1.25VM_AXD

0.47U_0603_10V7K

C1313

1

2

1

C1288

2

1.

1

2

1

+

C1279

2

330U_D2E_2.5VM_R7

0.47U_0603_10V7K

1

C1281

2

1U_0603_10V4Z

1

C1289

2

1

C1300

2

+VCC_PEG

0.47U_0603_10V7K

C1314

1

2

1

C1280

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

C1282

2

R1669
0_0805_5%

1 2

10U_0805_10V4Z

0.1U_0402_16V4Z

1

C1301

2

220U_D2_4VM

1

+

C1308

2

2

2.2U_0805_16V4Z

1

C1283

2

+1.25VM

1

C1302

2

10U_0805_10V4Z

10U_0805_10V4Z

Change value. 9/6

10U_0805_10V4Z

1

1

C1309

C1310

2

2

Intel Design Guide :
If LVDS/SDVO are disable : (P165)

1. VCCTX_LVDS & VCCA_LVDS connect to GND.

2. VCCD_LVDS connect to GND.
If internal VGA is disable : (P174)

3. VCCA_CRTDAC & VSSA_CRTDAC & VCC_SYNC are
connect to GND.

If internal VGA/TV-Out are disable : (P192)

4. VCCDTVDAC , VCCDQTVDAC , VCCATVDAC[A:C] ,
VCCATVBG , VSSATVBG are connect to GND.

5. VCCD_TVO connect to +1.5VS for thermal
sensor.

+V1.25VS_AXF

10U_0805_10V4Z

1

1

C1290

C1291

2

2

R1674
0_0805_5%

1 2

Modify from
22uF to 10uF.
6/24

L22

BLM18PG330SN1_2P

1 2

10U_0805_10V4Z

Del R1679 in 5/03

R1670
0_0603_5%

1 2

1U_0603_10V4Z

+1.25VS_DMI

+1.8V+1.8V_SM_CK

+VCCP

+1.25VS

1 2

0.1U_0402_16V4Z

1

C1293

2

+3VS_HV

+1.25VS

R1672
0_0603_5%

R1676 10_0402_5%

0.1U_0402_16V4Z

1

C1307

R1677 0_0402_5%

2

(Crestline 0.7 Page.9)

1

Del R1668,C1286,C1287 4/30
(Un-used +1.5VS_TVDAC)

+VCCP_D

D57

1 2

1 2

CH751H-40_SC76

21

+VCCP

+3VS

Add in 4/28

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

CRESTLINE(4/6)-PWR

LA-3331P

1

1.0

of

10 59Tuesday, May 15, 2007

5

4

3

2

1

Per DG9.0 P.191 , connect VCC_AXG to GND if don't use

+VCCP

Del R1685 and D58 cause duplicate on P10. 6/28

C1331

10U_0805_10V4Z

C1347

+VCCP

0.1U_0402_16V4Z

C1332

1

2

C1338

1

2

0.1U_0402_16V4Z
C1348

1

2

Change in 4/24

1 2

2

G

Q115

13

D

S

U4F

AB33
AB36
AB37
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37

AJ33

AJ35
AK33
AK35
AK36
AK37
AD33

AJ36
AM35

AL33

AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36

Y32
Y33
Y35
Y36
Y37
T30
T34
T35
U29
U31
U32
U33
U35
U36
V32
V33
V36
V37

AL24

AL26

AL28
AM26
AM28
AM29
AM31
AM32
AM33
AP29
AP31
AP32
AP33

AL29

AL31

AL32
AR31
AR32
AR33

CRESTLINE_1p0

R2051
100K_0402_5% @

CRACK_BGA

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50

VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19

1 2

MCHGND3

Q116

RHU002N06_SOT323@

VCC NCTF

POWER

VCC AXM NCTF

CRACK_BGA

Change in 4/24

13

D

2

G

S

4

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15

VSS NCTF

VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

VSS SCBVCC AXM

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7

R2052
100K_0402_5% @

MCHGND4

RHU002N06_SOT323 @

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

A3
B2
C1
BL1
BL51
A51

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

Q117

MCHGND1
MCHGND3

MCHGND4
MCHGND2

1 2

R132 0_0402_5%
R122 0_0402_5%

R113 0_0402_5%
R111 0_0402_5%

CRACK_BGA

Change in 4/24

13

D

2

G

S

R1686
0_0603_5%

1 2

+1.8V

0.01U_0402_16V7K

1

2

C1335

C1336

2

1

22U_0805_6.3V4Z

1 2
1 2

1 2
1 2

+1.05VM

1

1

+

C1334

C1333

2

2

330U_6.3V_M

22U_0805_6.3V4Z

Del C1339 ~ C1343 in 4/27.

CRACK_BGA 22,34

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

D D

220U_D2_2VK_R9

22U_0805_6.3V4Z

1

C1328

+

2

C C

B B

0.22U_0402_10V4Z
C1344

1

1

2

2

Add in 4/21
Remove in 5/02

+3VS +3VS +3VS +3VS

R2049

A A

100K_0402_5% @

Change in 4/24

1 2

13

Q114

D

2

G

S

MCHGND1

RHU002N06_SOT323 @

0.22U_0402_10V4Z

C1329

1

2

0.22U_0402_10V4Z
C1345

CRACK_BGA

5

0.22U_0402_10V4Z

C1330

1

1

2

2

+1.05VM

10U_0805_10V4Z

C1337

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C1346

1

1

2

2

R2050
100K_0402_5% @

MCHGND2

RHU002N06_SOT323 @

integrated Graphice. 4/27

U4G

AT35

VCC_1

AT34

VCC_2

AH28

VCC_3

AC32

VCC_5

AC31

VCC_4

AK32

VCC_6

AJ31

VCC_7

AJ28

VCC_8

AH32

VCC_9

AH31

VCC_10

AH29

VCC_11

AF32

VCC_12

R30

VCC_13

VCC CORE

POWER

AU32

VCC_SM_1

AU33

VCC_SM_2

AU35

VCC_SM_3

AV33

VCC_SM_4

AW33

VCC_SM_5

AW35

VCC_SM_6

AY35

VCC_SM_7

BA32

VCC_SM_8

BA33

VCC_SM_9

BA35

VCC_SM_10

BB33

VCC_SM_11

BC32

VCC_SM_12

BC33

VCC_SM_13

BC35

VCC_SM_14

BD32

VCC_SM_15

BD35

VCC_SM_16

BE32

VCC_SM_17

BE33

VCC_SM_18

BE35

VCC_SM_19

BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35

BJ32
BJ33

BJ34
BK32
BK33
BK34
BK35

BL33
AU30

W13
W14

AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31

AJ20
AN14

R20
T14

Y12

VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

CRESTLINE_1p0

VCC SMVCC GFX

VCC GFX NCTF

2

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

VCCSM_LF1

AW45

VCCSM_LF2

BC39

VCCSM_LF3

BE39

VCCSM_LF4

BD17

VCCSM_LF5

BD4

VCCSM_LF6

AW8

VCCSM_LF7

AT6

Title

Size Document Number Rev

Custom

Date: Sheet

CRESTLINE((5/6)-PWR/GND

LA-3331P

Del C1325 ~ C1327 in 4/27.

C1351

C1349

C1350

C1352

1

1

1

1

0.22U_0603_10V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.22U_0603_10V7K

2

2

2

2

Compal Electronics, Inc.

1

C1354

C1353

C1355

1

1

1

1U_0603_10V4Z

0.47U_0402_6.3V6K

1U_0603_10V4Z

2

2

2

1.0

of

11 59Tuesday, May 1 5, 2007

5

U4I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

AB20

D D

C C

B B

A A

AB23
AB26
AB28
AB31
AC10
AC13

AC39
AC43
AC47

AD21
AD26
AD29

AD41
AD45
AD49

AD50
AE10

AE14
AF20

AF23
AF24
AF31

AG38
AG43
AG47
AG50

AH40
AH41

AK20
AK21
AK26
AK28
AK31
AK51

AM11
AM13

AM41
AM45

AN38
AN39
AN43

AP48
AP50
AR11

AR39
AR44
AR47

AT10
AT14
AT41
AT49

AU23
AU29

AU36
AU49
AU51
AV39
AV48

AW12
AW16

AC3

AD1

AD3

AD5
AD8

AE6

AG2

AH3

AH7

AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49

AL1

AM3
AM4

AN1

AN5

AN7

AP4

AR2

AR7

AU1

AU3

AW1

VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

CRESTLINE_1p0

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

4

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

3

U4J

C46
C50

C7
D13
D24

D3
D32
D39
D45
D49
E10
E16
E24
E28
E32
E47
F19
F36

F4
F40
F50

G1

G13
G16
G19
G24
G28
G29
G33
G42
G45
G48

G8
H24
H28

H4
H45
J11
J16

J2
J24
J28
J33
J35
J39

K12
K47

K8

L1
L17
L20
L24
L28

L3
L33
L49

M28
M42
M46
M49

M5

M50

M9
N11
N14
N17
N29
N32
N36
N39
N44
N49

N7
P19

P2
P23

P3
P50
R49
T39
T43
T47
U41
U45
U50

V2

V3

CRESTLINE_1p0

VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243

VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286

VSS

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

2

1

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((6/6)-PWR/GND

LA-3331P

1

1.0

of

12 59Tuesday, May 1 5, 2007

5

DDR_A_DQS#[0..7]8

DDR_A_D[0..63]8

DDR_A_DM[0..7]8
DDR_A_DQS[0..7]8
DDR_A_MA[0..13]8

D D

Layout Note:
Place near JP9

+1.8V

1

+

C1548

2

470U_D2_2.5VM_R15

C461

C467

1

1

2

2

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z
C462

C463

1

1

2

2

0.1U_0402_16V4Z

2.2U_0805_16V4Z
C464

1

2

0.1U_0402_16V4Z

C105

C93

1

1

2

2

Add 470uF in 4/25

C C

0.1U_0402_16V4Z

1

1

2

2

C80

+0.9V

0.1U_0402_16V4Z

1

2

C81

C82

RP13 56_0404_4P2R_5%

14
23

RP18 56_0404_4P2R_5%

14
23

RP12 56_0404_4P2R_5%

14
23

RP17 56_0404_4P2R_5%

14
23

RP16 56_0404_4P2R_5%

14
23

RP14 56_0404_4P2R_5%

14
23

RP19 56_0404_4P2R_5%

14
23

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9V

0.1U_0402_16V4Z

1

2

C79

RP11

1 4
2 3

RP7

1 4
2 3

RP15

1 4
2 3

RP10

1 4
2 3

RP9

1 4
2 3

RP8

2 3
1 4

1 2

R2135
56_0402_5%

0.1U_0402_16V4Z

1

2

C78

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

5

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C83

B B

DDR_A_MA5
DDR_A_MA8

DDR_A_MA1
DDR_A_MA3

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_BS#0
DDR_A_MA10

A A

DDR_A_CAS#
DDR_A_WE#

DDR_CS1_DIMMA#
M_ODT1

DDR_A_MA14

Add for using DDR2 2Gb tech. 6/9

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C115

C84

DDR_A_BS#2
DDR_CKE0_DIMMA

DDR_A_MA7
DDR_A_MA6

DDR_A_MA9
DDR_A_MA12

DDR_A_MA4
DDR_A_MA2

DDR_A_MA0
DDR_A_BS#1

M_ODT0
DDR_A_MA13

DDR_CKE1_DIMMA
DDR_A_MA11

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C111

C110

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C95

C91

1

1

2

2

0.1U_0402_16V4Z

1

1

2

2

C112

C113

Layout Note:
Place these resistor
closely JP9,all
trace length Max=1.5"

4

3

+1.8V +1.8V

JP9

1

VREF

3

DDR_A_D4
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D9
DDR_A_D15

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D29
DDR_A_D24

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA7

DDR_A_BS28

DDR_A_BS08

DDR_A_WE#8

DDR_A_CAS#8

DDR_CS1_DIMMA#7

0.1U_0402_16V4Z

1

2

C114

Add 2.2uF and Change
+3VS to +3VM in 4/25

M_ODT17

ICH_SMBDATA14,15,21

ICH_SMBCLK14,15,21

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D37

DDR_A_D36
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D35

DDR_A_D32
DDR_A_D40

DDR_A_D44
DDR_A_DM5
DDR_A_D41

DDR_A_D46
DDR_A_D49

DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D54
DDR_A_D50

DDR_A_D61
DDR_A_D60

DDR_A_DM7
DDR_A_D59

DDR_A_D58

+3VM

C96

1

1

C1546

2

2

2.2U_0603_6.3V6K

2006/02/13 2006/03/10

Compal Secret Data

5

7

9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

0.1U_0402_16V4Z

Deciphered Date

VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

FOX_ASOA426-M4R-TRconn@

SO-DIMM A

REVERSE

Top side

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1

RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

2

V_DDR_MCH_REF

2

DDR_A_D6

4

DDR_A_D0

6
8

DDR_A_DM0

10
12

DDR_A_D5

14

DDR_A_D7

16
18

DDR_A_D13

20

DDR_A_D12

22
24

DDR_A_DM1

26
28
30
32
34

DDR_A_D11

36

DDR_A_D10

38
40

42

DDR_A_D20

44

DDR_A_D21

46
48
50

NC

A11

A7
A6

A4
A2
A0

S0#

NC

2

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_DM2
DDR_A_D23

DDR_A_D22
DDR_A_D28

DDR_A_D25
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D31

DDR_A_D30
DDR_CKE1_DIMMA

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D39
DDR_A_D38

DDR_A_DM4
DDR_A_D34

DDR_A_D33
DDR_A_D45

DDR_A_D43
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D47

DDR_A_D42
DDR_A_D52

DDR_A_D53

DDR_A_DM6
DDR_A_D51

DDR_A_D55
DDR_A_D57

DDR_A_D56
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

R40

R38

10K_0402_5%

10K_0402_5%

12

2.2U_0805_16V4Z
C97

1

2

M_CLK_DDR0 7
M_CLK_DDR#0 7

PM_EXTTS#0 7

DDR_CKE1_DIMMA 7

DDR_A_MA14 7

DDR_A_BS1 8
DDR_A_RAS# 8
DDR_CS0_DIMMA# 7

M_ODT0 7

M_CLK_DDR1 7
M_CLK_DDR#1 7

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

LA-3331P

1

0.1U_0402_16V4Z

1

2

Add for using DDR2
2Gb tech. 6/9

V_DDR_MCH_REF 7,14,45

C92

1

1.0

of

13 59Tuesday, May 1 5, 2007

5

DDR_B_DQS#[0..7]8

DDR_B_D[0..63]8
DDR_B_DM[0..7]8

DDR_B_DQS[0..7]8

DDR_B_MA[0..13]8

D D

Layout Note:
Place near JP34

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C109

C108

1

2

0.1U_0402_16V4Z

1

2

C87

RP34

1 4
2 3

RP35

56_0404_4P2R_5%

1 4
2 3

RP3

56_0404_4P2R_5%

1 4
2 3

RP2

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

RP36

1 4
2 3

RP37

56_0404_4P2R_5%

2 3
1 4

56_0404_4P2R_5%

1 2

C460

1

2

0.1U_0402_16V4Z

1

2

C C

B B

A A

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C86

C85

DDR_B_MA1
DDR_B_MA3

DDR_B_BS#0
DDR_B_MA10

DDR_B_MA0
DDR_B_BS#1

DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_CAS#
DDR_B_WE#

DDR_CS3_DIMMB#
M_ODT3

DDR_B_MA14

R2136
56_0402_5%

1

2

0.1U_0402_16V4Z

1

1

2

2

C88

+0.9V

2.2U_0805_16V4Z

C466

C107

1

2

0.1U_0402_16V4Z

1

2

C89

C90

RP32 56_0404_4P2R_5%

14
23

RP6 56_0404_4P2R_5%

14
23

RP33 56_0404_4P2R_5%

14
23

RP5 56_0404_4P2R_5%

14
23

RP4 56_0404_4P2R_5%

14
23

RP1 56_0404_4P2R_5%

14
23

RP31

14
23

56_0404_4P2R_5%

0.1U_0402_16V4Z
C94

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C477

DDR_B_MA9
DDR_B_MA12

DDR_B_MA7
DDR_CKE3_DIMMB

DDR_B_MA5
DDR_B_MA8

DDR_B_MA6
DDR_B_MA11

DDR_B_MA4
DDR_B_MA2

M_ODT2
DDR_B_MA13

DDR_B_BS#2
DDR_CKE2_DIMMB

0.1U_0402_16V4Z

C476

5/16

5/16

0.1U_0402_16V4Z

C455

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C475

Add for using DDR2 2Gb tech. 6/9

5

4

0.1U_0402_16V4Z
C454

C106

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C473

C474

C472

Layout Note:
Place these resistor
closely JP10,all
trace length Max=1.5"

4

3

+1.8V +1.8V

JP29

1

VREF

3

DDR_B_D1
DDR_B_D0

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D17
DDR_B_D20

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D28

DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB7

DDR_B_BS28

DDR_B_BS08
DDR_B_WE#8

DDR_B_CAS#8

0.1U_0402_16V4Z

1

2

C471

Add 2.2uF and Change
+3VS to +3VM in 4/25

DDR_CS3_DIMMB#7

M_ODT37

ICH_SMBDATA13,15,21

ICH_SMBCLK13,15,21

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D56
DDR_B_D61

DDR_B_DM7
DDR_B_D59

DDR_B_D58

+3VM +3VM

1

1

C453

C1547

2

2

0.1U_0402_16V4Z

2.2U_0603_6.3V6K

2006/02/13 2006/03/10

Compal Secret Data

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2RN-7Fconn@

SO-DIMM B
STANDARD

Bottom side

Deciphered Date

VSS
DQ4
DQ5

VSS
DM0

VSS
DQ6
DQ7

VSS

DQ12
DQ13

VSS
DM1

VSS

CK0

CK0#

VSS

DQ14
DQ15

VSS

VSS

DQ20
DQ21

VSS
DM2

VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

VDD

VDD

BA1

RAS#

S0#
VDD

ODT0

NC/A13

VDD

VSS

DQ36
DQ37

VSS
DM4

VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS

CK1

CK1#

VSS
DM6

VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS

SA0

SA1

2

V_DDR_MCH_REF

2

DDR_B_D5

4

DDR_B_D4

6
8

DDR_B_DM0

10
12

DDR_B_D6

14

DDR_B_D7

16
18

DDR_B_D12

20

DDR_B_D13

22
24

DDR_B_DM1

26
28
30
32
34

DDR_B_D14

36

DDR_B_D15

38
40

42

DDR_B_D21

44

DDR_B_D16

46
48
50

NC

A7
A6

A4
A2
A0

NC

2

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D26

DDR_B_D24DDR_B_D25
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D29

DDR_B_D27
DDR_CKE3_DIMMB

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D39

DDR_B_D38
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53

DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D57
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

10K_0402_5%

12

R34

2.2U_0805_16V4Z

0.1U_0402_16V4Z

1

1

C99

2

2

M_CLK_DDR3 7
M_CLK_DDR#3 7

PM_EXTTS#1 7,47

DDR_CKE3_DIMMB 7

DDR_B_MA14 7

DDR_B_BS1 8
DDR_B_RAS# 8
DDR_CS2_DIMMB# 7

M_ODT2 7

M_CLK_DDR2 7
M_CLK_DDR#2 7

R33

1 2

10K_0402_5%

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA-3331P

1

V_DDR_MCH_REF 7,13,45

C103

Add for using DDR2
2Gb tech. 6/9

Change +3VS t o +3VM in 5/15,
cause OTS 2654 41 and 261307.

of

14 59Tuesday, May 1 5, 2007

1

1.0

5

PCI

SRC

CPU

CLKSEL1

1

1

FSLA

CLKSEL0

MHz

200

166

MHz

1000

100

MHz

33.30

33.3

FSLC1FSLB

CLKSEL2

0

FSB Frequency Selet:

R1716

CPU Driven

D D

(Default)

*

667MHz

800MHz

Stuff

No Stuff

Stuff

No Stuff

Stuff

R1689

R1689

R1694 R1705

No Stuff

+VCCP

FSA

C C

CPU_BSEL05

CPU_BSEL15

B B

R1690 2.2K_0402_5%

R1716 0_0402_5%

12

1 2

R1694 0_0402_5%

CLK_Ra

FSB

1 2

CLK_Rb

+VCCP

R1705

1 2

Del tie to +VCCP.7/28

FSC

CPU_BSEL25

A A

R1730 8.2K_0402_5%

14.31818MHZ_20P_1BX14318BE1A

Y6

2

C138322P_0402_50V8J

1

12

1 2

R1734 0_0402_5%

CLK_Rc

CLK_XTAL_OUT

CLK_XTAL_IN

12

2

C1384

22P_0402_50V8J

1

5

R1734R1694

R1705R1696 R1719 R1737R1726

R1696

R1737R1734

R1716 R1719

R1726

R1737R1734

R1694R1689

R1696 R1716 R1719R1705

Add option for FSB frequency by jumper.11/08
Del jumper(JP62, JP63) in 3/14.

R1689

56_0402_5%@

CLK_Rd

1 2

1 2

R1691 1K_0402_5%

12

R1696

1K_0402_5%@

1K_0402_5%@

1 2

R1713 1K_0402_5%

CLK_PCI_DB33

CLK_PCI_SIO32
CLK_PCI_TCG33
CLK_PCI_EC34

CLK_PCI_PCM27

CLK_PCI_ICH19

MCH_CLKSEL0 7

CLKSATAREQ#21

MCH_CLKSEL1 7

Remove R1722 in 4/24.(Richo don't need 48MHz)

CLK_48M_ICH21

Change from 12.1 to 33
4/30 (Same as Chimay)

CLK_14M_ICH21

CLK_14M_SIO32

1 2

R1731 1K_0402_5%

12

R1737

0_0402_5%@

CLK_14M_KBC34

MCH_CLKSEL2 7

CLK_Rf

Change from +3.3VM_CK505 to +3VS. 6/9

+3VS

R1744
10K_0402_5%

1 2

ITP_EN

R1747

@

10K_0402_5%

1 2

4

+3VM

1 2

R1687 0_1206_5%

R1726

R1700 475_0402_1%

CLKREQB#7

CLK_PCI_DB
CLK_PCI_SIO
CLK_PCI_TCG
CLK_PCI_EC
CLK_PCI_PCM

CLK_PCI_ICH

CLK_48M_ICH

CLK_14M_ICH
CLK_14M_SIO
CLK_14M_KBC

+3VS +3VS

R1745

@

10K_0402_5%

1 2

27_SEL

R1748
10K_0402_5%

1 2

R1701 475_0402_1%

4

+3VM_CK505

1

2

C1359
10U_0805_10V4Z

+1.25VM_CK505

12
12
12

12
1 2
1 2
1 2

1 2

1 2

1 2
1 2
1 2

+1.25VM_CK505

Modify at 5/14.

R1746
10K_0402_5%

1 2

PCI2_TME

R1749

@

10K_0402_5%

1 2

3

Removed C1366~C1368 4/30 (Same as Chimay)

C1360

0.1U_0402_16V4Z

1

2

1

2

C1361

0.1U_0402_16V4Z

C1362

0.1U_0402_16V4Z

1

2

1

2

C1363

0.1U_0402_16V4Z

03/02 change

R170422_0402_5%
R170612_0402_5%
R170812_0402_5%
R170912_0402_5%
R171112_0402_5%

R171422_0402_5%

R172433_0402_1%

R172933_0402_1%
R173233_0402_1%
R173333_0402_1%

+3VM_CK505

CLK_XTAL_IN
CLK_XTAL_OUT

FSA

FSB

FSC

U30

2

VDD_PCI

9

VDD48

16

VDDPLL3

61

VDDREF

39

VDDSRC

55

VDDCPU

12

VDD96_IO

20

VDDPLL3_IO

26

VDDSRC_IO

36

VDDSRC_IO

49

VDDCPU_IO

PCI_CLK0

1

PCI0/CR#_A

PCI_CLK1

3

PCI1/CR#_B

PCI2_TME

4

PCI2/TME

PCI_CLK3

5

PCI3

27_SEL

6

PCI4/27_Select

ITP_EN

7

PCIF5/ITP_EN

60

X1

59

X2

10

USB_48MHZ/FSLA

57

FSLB/TEST MODE

62

REF0/FSLC/TEST_SEL

45

VDDSRC_IO

42

GNDSRC

8

GNDPCI

11

GND48

15

GND

19

GND

52

GNDCPU

23

GNDSRC

29

GNDSRC

58

GNDREF

* Internal Pull-Up Resistor
** Internal Pull-Down Resistor

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

CPU_STOP#

SRC11/CR#_H

SRC11#/CR#_G

SRC7/CR#_F

SRC7#/CR#_E

SRC3/CR#_C

SRC3#/CR#_D

SRC2#/SATA#

SRC1/SE1/27MHz_NonSS

SRC1#/SE2/27MHz_SS

SRC0/DOT96

SRC0/DOT96#

CK_PWRGD/PD#

ICS9LPRS355_TSSOP64

2006/02/13 2006/03/10

SCLK

SDATA

PCI_STOP#

CPU0

CPU0#

CPU1_F

CPU1#_F

SRC8/ITP

SRC8#/ITP#

SRC10#

SRC10

SRC9

SRC9#

SRC6

SRC6#

SRC4

SRC4#

SRC2/SATA

2

C1364

0.1U_0402_16V4Z

1

2

1

C1365

0.1U_0402_16V4Z

2

Install R1688 4/28

Del Q79 in 5/19.

+1.25VM_CK505+1.25VM

R1688
0_1206_5%

12

1

48

NC

64
63

38
37

Del RP49, RP51 ~ R P5 7 from PV build. 3/19

54
53

51
50

R_CPU_XDP

47

R_CPU_XDP#

46

35
34

33
32

30
31

44
43

41
40

27
28

24
25

21
22

17
18

13
14

56

R_CLKREQ#_H
R_CLKREQ#_G

R_CLKREQ#_F
R_CLKREQ#_E

R1710 475_0402_1%
R1712 475_0402_1%

R2067 475_0402_1%
R1721 475_0402_1%

Add in 5/02 for Roberson.
Del in 5/21.

Del in 4/24

2

C1377
10U_0805_10V4Z

R1707 10K_0402_5%

12
12

R1715 10K_0402_5%

R2066 10K_0402_5%

12
12

R1720 10K_0402_5%

Compal Secret Data

Deciphered Date

2

C1378

0.1U_0402_16V4Z

1

2

1 2

1 2

1 2

1 2

1

C1356
C1357
C1358
C1369
C1370
C1371
C1372
C1373
C1374
C1375

12
12
12
12
12
12
12
12
12
12

Del C1376. 5/19

Place close to U30

C1380
10U_0805_10V4Z

1

1

2

C1379

0.1U_0402_16V4Z

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4

CLK_MCH_BCLK 7
CLK_MCH_BCLK# 7

CLK_PCIE_DOCK 36
CLK_PCIE_DOCK# 36

CLKREQG# 26

CLK_PCIE_MCARD 26
CLK_PCIE_MCARD# 26

CLKREQF# 26
CLKREQE# 17

CLK_PCIE_MXM 17
CLK_PCIE_MXM# 17

CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7

CLK_PCIE_ICH 21
CLK_PCIE_ICH# 21

CLK_PCIE_SATA 20
CLK_PCIE_SATA# 20

CK_PWRGD 21

2

ICH_SMBCLK 13,14,21
ICH_SMBDATA 13,14,21

H_STP_PCI# 21
H_STP_CPU# 21

R_CPU_XDP
R_CPU_XDP#

R_CPU_XDP
R_CPU_XDP#

+3VS

CPPE# 36

+3VS

+3VS

Add for Roberson 4/28

+3VS

Title

Size Document Number Rev

LA-3331P

Date: Sheet

C1382

0.1U_0402_16V4Z

1

1

2

2

C1381

0.1U_0402_16V4Z

RP48

0_0404_4P2R_5% @

1 4
2 3

1 4
2 3

RP50

0_0404_4P2R_5% @

In order to take advantage
of the Robson CLKREQ ,
share SRC8 with Robson and
the XDP. 5/21

Cuase layout issue
change all diff pair's
damping to 0404
package RP. 6/3

Compal Electronics, Inc.

CLOCK GENERATOR

1

CLK_48M_ICH

5P_0402_50V8C@

CLK_14M_ICH

4.7P_0402_50V8C@

CLK_PCI_ICH

4.7P_0402_50V8C@

CLK_14M_KBC

4.7P_0402_50V8C@

CLK_14M_SIO

4.7P_0402_50V8C@

CLK_PCI_EC

4.7P_0402_50V8C@

CLK_PCI_TCG

4.7P_0402_50V8C@

CLK_PCI_PCM

4.7P_0402_50V8C@

CLK_PCI_SIO

4.7P_0402_50V8C@

CLK_PCI_DB

5P_0402_50V8C@

CLK_PCIE_NAND 26
CLK_PCIE_NAND# 26

CLK_CPU_XDP 4
CLK_CPU_XDP# 4

of

15 59Tuesday, May 1 5, 2007

1.0

A

CRT Connector

1 1

+5VS

0.1U_0402_16V4Z

1

5

R30651K_0402_5%

1 2

R30851K_0402_5%

1 2

P

A2Y

G

3

M_HSYNC17

M_VSYNC17

2 2

+5VS

C293

1 2

U24
SN74AHCT1G125GW_SOT353-5

4

OE#

5

A2Y

3

Place cloce to MXM connector JP39

L

B

BLUE36

GREEN36

RED36

1

1

C74

C77

2

2

5P_0402_50V8C

C294

1 2

0.1U_0402_16V4Z

HSYNC D_HSYNC

1

P

VSYNC D_ VSYNC

4

OE#

G

U23
SN74AHCT1G125GW_SOT353-5

@

R312 0_0603_5%

1 2

R310 0_0603_5%

1 2

Change value from BK2125LL560-T
0805 to 0_0805. 5/19

1

C71

2

5P_0402_50V8C

5P_0402_50V8C

@

@

5P_0402_50V8C@

R31 0_0805_5%

1 2

1 2

1 2

1

1

2

2

C325

5P_0402_50V8C@

R29 0_0805_5%

R26 0_0805_5%

C326

C

D3

2 1

21

CH491D_SC59

0.1U_0402_16V4Z

C420

RED_R

GREEN_R

BLUE_R

W=40mils

1

2

2.2K_0402_5%

C73

1

2

18P_0402_50V8J@

1.1A_6VDC_FUSE

C75

C76

1

1

2

2

18P_0402_50V8J@

D_HSYNC 36

D_VSYNC 36

D_DDCDATA36

D_DDCCLK36

F1

18P_0402_50V8J@

L

D

+CRTVDD+RCRT_VCC+5VS

JP7

6

11

1
7

12

2
8

13

3
9

14

18

4

19
10
15

5

FOX_DZ11A91-L7conn@

+CRTVDD +CRTVDD

12

12

R446

R445

2.2K_0402_5%

1 3

Q68

D

BSS138_SOT23

Q67
BSS138_SOT23

2

G

1 3

D

S

2

G

Place cloce to MXM connector JP39

BLUE
GREEN
RED

+3VS

R4502.2K_0402_5%

1 2

S

R4492.2K_0402_5%

1 2

E

R666150_0402_1%@

R664150_0402_1%@

R665150_0402_1%@

12

12

12

M_DDCDATA 17

M_DDCCLK 17

+5VS

21

D65
RB411D_SOT23

3 3

R1990 1K_0402_1%

12

R1991
10K_0402_1%

1 2

HDMI_DETECT17

D66

SKS10-04AT_TSMA

4 4

A

2 1

HDMI Connector

L23

1 2

FBML10160808121LMT_0603

1

C1578

330P_0402_50V7K

Add in 8/25.

B

2

R212210K_0402_5%

R212110K_0402_5%

1

C1493

1 2

1 2

Add in 6/5.

HDMIDAT18
HDMICLK18

HDMI_CLK-18

HDMI_CLK+18

HDMI_TX0-18

HDMI_TX0+18

HDMI_TX1-18

HDMI_TX1+18

HDMI_TX2-18

HDMI_TX2+18

Security Classification

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

0.1U_0402_16V4Z

2

C

JP61

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

2005/03/10 2006/03/10

20

GND

21

GND

22

GND

23

GND

TYCO_1775040-6conn@

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

CRT & HDMI

LA-3331P

E

1.0

of

16 59Tuesday, May 1 5, 2007

5

B+

JP5A

1

PWR_SRC

3

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53

55
57
59
61
63
65
67
69
71
73
75
77

79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161

PWR_SRC

5

PWR_SRC

7

PWR_SRC

9

PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC

PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
GND
GND
GND
GND

PEX_RX15#
PEX_RX15
GND
PEX_RX14#
PEX_RX14
GND
PEX_RX13#
PEX_RX13
GND
PEX_RX12#
PEX_RX12
GND
PEX_RX11#
PEX_RX11
GND
PEX_RX10#
PEX_RX10
GND
PEX_RX9#
PEX_RX9
GND
PEX_RX8#
PEX_RX8
GND
PEX_RX7#
PEX_RX7
GND
PEX_RX6#
PEX_RX6
GND
PEX_RX5#
PEX_RX5
GND
PEX_RX4#
PEX_RX4
GND
PEX_RX3#
PEX_RX3
GND
PEX_RX2#
PEX_RX2
GND

5

ACES_88982-28428conn@

R316150_0402_1%

12

R314150_0402_1%

12

12

RUNPWROK

TV-Out Termination/EMI Filter

R317150_0402_1%

C11

1

2

D D

C1579

Del C9
and
replaced
by 2 X
22uF.9/8

C C

B B

A A

0.1U_0603_50V4Z

B+

1

1

C1580

2

2

22U_1210_25V6-M

22U_1210_25V6-M

PEG_RXN15
PEG_RXP15

PEG_RXN14
PEG_RXP14

PEG_RXN13
PEG_RXP13

PEG_RXN12
PEG_RXP12

PEG_RXN11
PEG_RXP11

PEG_RXN10
PEG_RXP10

PEG_RXN9
PEG_RXP9

PEG_RXN8
PEG_RXP8

PEG_RXN7
PEG_RXP7

PEG_RXN6
PEG_RXP6

PEG_RXN5
PEG_RXP5

PEG_RXN4
PEG_RXP4

PEG_RXN3
PEG_RXP3

PEG_RXN2
PEG_RXP2

Place those components as close as

L

MXMIII connector within 500 mils.

MXM_LUMA
MXM_CRMA
MXM_COMP

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN

5VRUN

GND
GND
GND

PRSNT2#

PEX_TX15#

PEX_TX15

GND

PEX_TX14#

PEX_TX14

GND

PEX_TX13#

PEX_TX13

GND

PEX_TX12#

PEX_TX12

GND

PEX_TX11#

PEX_TX11

GND

PEX_TX10#

PEX_TX10

GND

PEX_TX9#

PEX_TX9

GND

PEX_TX8#

PEX_TX8

GND

PEX_TX7#

PEX_TX7

GND

PEX_TX6#

PEX_TX6

GND

PEX_TX5#

PEX_TX5

GND

PEX_TX4#

PEX_TX4

GND

PEX_TX3#

PEX_TX3

GND

PEX_TX2#

PEX_TX2

MXM_LUMA

MXM_CRMA

MXM_COMP

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54

56
58
60
62
64
66
68
70
72
74
76
78

80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162

L

C17

C18

1

1

2

2

82P_0402_50V8J

4

+3VS

1 2

G

Q142

2

MXM_THERM# PWR _GD

+1.8VS +5VS

PEG_M_TXN15
PEG_M_TXP15

PEG_M_TXN14
PEG_M_TXP14

PEG_M_TXN13
PEG_M_TXP13

PEG_M_TXN12
PEG_M_TXP12

PEG_M_TXN11
PEG_M_TXP11

PEG_M_TXN10
PEG_M_TXP10

PEG_M_TXN9
PEG_M_TXP9

PEG_M_TXN8
PEG_M_TXP8

PEG_M_TXN7
PEG_M_TXP7

PEG_M_TXN6
PEG_M_TXP6

PEG_M_TXN5
PEG_M_TXP5

PEG_M_TXN4
PEG_M_TXP4

PEG_M_TXN3
PEG_M_TXP3

PEG_M_TXN2
PEG_M_TXP2

Place cloce to MXM connector JP5

C19

1

2

82P_0402_50V8J

82P_0402_50V8J

+1.8VS

1

2

R303

8.2K_0402_5%@

1 2

Add for leakage issue. 1/12
Change again. 1/15

L8

1 2

CHB1608U301_0603
L9

1 2

CHB1608U301_0603
L7

1 2

CHB1608U301_0603

4

RHU002N06_SOT323

S

C292

4.7U_0805_10V4Z

PWR_GD

+3VS

MXM_CD1# 21,48

C13

1

2

82P_0402_50V8J

Move this from VGA
board to M/B. 2/12

R2204
10K_0402_5%

13

D

CLKREQE#15

VGA_RST#21

ICH_SM_DA4,21,26

ICH_SM_CLK4,21,26

Add R2190 to option G71
& G84.11/8

RHU002N06_SOT323

ADP_PRES24,34,41,42,43,48

C14

C15

1

1

2

2

82P_0402_50V8J

82P_0402_50V8J

3

PEG_RXN[0..15]9

PEG_RXP[0..15]9
PEG_M_TXN[0..15]9
PEG_M_TXP[0..15]9

JP5B

PEG_RXN1

PWR_GD 21,27,34,37,38,46,48

CLK_PCIE_MXM#15

R311

0_0402_5%@

MXM Address:100_1100

R320 0_0402_5%
R319 0_0402_5%

SLP_S3#21,24,29,30,34,36,37,44,45,46,48,49

Q139

D

1 3

G

2

+3VS

M_LUMA 36

M_CRMA 36

M_COMP 36

CLK_PCIE_MXM15

1 2

1 2
1 2

MXM_THERM#21

M_HSYNC16
M_VSYNC16

M_DDCCLK16

M_DDCDATA16

+5VALW

ADP_PRES_Q

Reserve R2110 ,R2190 from SI2
cause G84/G92 don't need them.
1/10

S

R2196

1 2

R2110 0_0402_5%@
R2190 0_0402_5%@
R313 0_0402_5%

HD_DVI_CLK-18

HD_DVI_CLK+18

HDMI_DETECT16

DVI_TX5-18

DVI_TX5+18

DVI_TX4-18

DVI_TX4+18

DVI_TX3-18

DVI_TX3+18

DVI_DETECT36

DVI_CLK-36

DVI_CLK+36

DVI_TX2-36

DVI_TX2+36

DVI_TX1-36

DVI_TX1+36

DVI_TX0-36

DVI_TX0+36

ADP_PRES_Q

8.2K_0402_5%

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PEG_RXP1
PEG_RXN0

PEG_RXP0

MXM_SMBDATA
MXM_SMBCLK

MXM_THERM#

1 2
1 2
1 2

M_RED

M_GRN

12

R10

150_0402_1%

2005/03/10 2006/03/10

Compal Secret Data

12

R2

R11

150_0402_1%

12

Deciphered Date

163

PEX_RX1#

165

PEX_RX1

167

GND

169

PEX_RX0#

171

PEX_RX0

173

GND

175

PEX_REFCLK#

177

PEX_REFCLK

179

CLK_REQ#

181

PEX_RST#

183

RSVD

185

RSVD

187

SMB_DAT

189

SMB_CLK

191

THERM#

193

VGA_HSYNC

195

VGA_VSYNC

197

DDCA_CLK

199

DDCA_DAT

201

IGP_UCLK#

203

IGP_UCLK

205

GND

207

RSVD

209

RSVD

211

RSVD

213

IGP_UTX2#

215

IGP_UTX2

217

GND

219

IGP_UTX1#

221

IGP_UTX1

223

GND

225

IGP_UTX0#

227

IGP_UTX0

229

GND

231

IGP_LCLK#/DVI_B_CLK#

233

IGP_LCLK/DVI_B_CLK

235

DVI_B_HPD/GND

237

RSVD

239

RSVD

241

GND

243

IGP_LTX2#/DVI_B_TX2#

245

IGP_LTX2/DVI_B_TX2

247

GND

249

IGP_LTX1#/DVI_B_TX1#

251

IGP_LTX1/DVI_B_TX1

253

GND

255

IGP_LTX0#/DVI_B_TX0#

257

IGP_LTX0/DVI_B_TX0

259

DVI_A_HPD

261

DVI_A_CLK#

263

DVI_A_CLK

265

GND

267

DVI_A_TX2#

269

DVI_A_TX2

271

GND

273

DVI_A_TX1#

275

DVI_A_TX1

277

GND

279

DVI_A_TX0#

281

DVI_A_TX0

283

GND

CRT Termination/EMI Filter

L4

1 2

HLC0603CSCC39NJT_0603

L5

1 2

HLC0603CSCC39NJT_0603

L2

1 2

HLC0603CSCC39NJT_0603

150_0402_1%

2

PEX_TX1#

PEX_TX0#

TV_C/HDTV_Pr

TV_Y/HDTV_Y

TV_CVBS/HDTV_Pb

VGA_GRN

LVDS_UCLK#

LVDS_UCLK

LVDS_UTX3#

LVDS_UTX3

LVDS_UTX2#

LVDS_UTX2

LVDS_UTX1#

LVDS_UTX1

LVDS_UTX0#

LVDS_UTX0

LVDS_LCLK#

LVDS_LCLK

LVDS_LTX3#

LVDS_LTX3

LVDS_LTX2#

LVDS_LTX2

LVDS_LTX1#

LVDS_LTX1

LVDS_LTX0#

LVDS_LTX0
DDCC_DAT

DDCC_CLK

LVDS_PPEN

LVDS_BL_BRGHT

LVDS_BLEN

DDCB_DAT

DDCB_CLK

ACES_88982-28428conn@

RED_LL

GREEN_LL

BLUE_LLM_BLU

2

GND

PEX_TX1

GND

PEX_TX0

PRSNT1#

GND
GND
GND

VGA_RED

GND
GND

VGA_BLU

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

2V5RUN

GND
3V3RUN
3V3RUN
3V3RUN

C3

1

MXM_CD0#

164

PEG_M_TXN1

166

PEG_M_TXP1

168
170

PEG_M_TXN0

172

PEG_M_TXP0

174

MXM_CD0#

176

MXM_CRMA

178
180

MXM_LUMA

182
184

MXM_COMP

186
188

M_RED

190
192

M_GRN

194
196

M_BLU

198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
258
260
262
264
266
268
270
272
274
276
278
280
282
284

1

1

C7

2

2

18P_0402_50V8J

1

C4

2

4.7U_0805_10V4Z

L1

1 2

HLC0603CSCCR11JT_0603

L6

1 2

HLC0603CSCCR11JT_0603

L3

1 2

HLC0603CSCCR11JT_0603

1

C2

2

18P_0402_50V8J

18P_0402_50V8J

Place those components as close as

L

MXMIII connector within 500 mils.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

LA-3331P

MXM_CD0# 21

+3VS

R305

8.2K_0402_5%@

1 2

M_TXBCLK- 18
M_TXBCLK+ 18

Add for HDMI 4/28

SPDIF_OUT 29

M_TXB2- 18
M_TXB2+ 18

M_TXB1- 18
M_TXB1+ 18

M_TXB0- 18
M_TXB0+ 18

M_TXACLK- 18
M_TXACLK+ 18

M_TXA2- 18
M_TXA2+ 18

M_TXA1- 18
M_TXA1+ 18

M_TXA0- 18
M_TXA0+ 18

M_LCD_DAT 18
M_LCD_CLK 18
M_ENAVDD 18
M_PWM 18
M_ENBLT 18
DVI_DAT 18
DVI_CLK 18

+3VS

+2.5VS

1

Add for long trace
issue.1/11

2

C1594

0.1U_0402_16V4Z

D_RED 36

D_GREEN 36

D_BLUE 36

MXM-HE CONN

1

1.0

of

17 59Tuesday, May 1 5, 2007

5

4

3

2

1

LCD POWER CIRCUITMXM LVDS CONN

B+_LCD

C286

12

0.1U_0603_50V4Z
C287

M_TXA2+17

M_TXA2-17

M_TXA1+17

M_TXA1-17

M_TXA0+17

M_TXA0-17

1

2

0.1U_0402_16V4Z

68P_0402_50V8J

L13

1 2

5

12

HD_DVI_CLK+17
HD_DVI_CLK-17

Add pin43 of U57
bottom pad.6/30

JP3

1

1

2

3

3

4

5

5

6

7

7

8

9

9

10

11

11

12

13

13

14

15

15

16

17

17

18

19

19

20

21

21

22

23

23

24

25

25

26

27

27

28

29

29

30

31

31

32

33

33

34

35

35

36

37

37

38

39

39

40

GND41GND

ACES_87216-4016

conn@

+3VS +3VS

R2118
10K_0402_5%

1 2

DVI_TX3+17
DVI_TX3-17
DVI_TX4+17
DVI_TX4-17
DVI_TX5+17
DVI_TX5-17

DVI_HDMI_R_SEL

S

G

2

S

G

2

D

13

Q123
RHU002N06_SOT323

D

13

Q124
RHU002N06_SOT323

LID_SW#

2
4
6
8
10
12

M_LCD_CLK

14

M_LCD_DAT

16
18
20
22
24
26
28
30
32
34
36
38
40
42

HDMIDAT 16

DVIDAT 36

DVI_HDMI_SEL DVI_HDMI_SEL_G

+3VS

21

D80

SS1040_SOD123

VDD2VDD8VDD16VDD18VDD20VDD30VDD40VDD

3

D0+

4

D0-

6

D1+

7

D1-

11

D2+

12

D2-

14

D3+

15

D3-

9

SEL

VSS1VSS5VSS10VSS13VSS17VSS19VSS21VSS41VSS

VSS

43

LID_SW# 21
ALS_EN 21

+5VS_INV

+3VS

M_LCD_CLK 17
M_LCD_DAT 17

M_TXBCLK+ 17M_TXACLK+17
M_TXBCLK- 17

M_TXB2+ 17
M_TXB2- 17

M_TXB1+ 17
M_TXB1- 17

M_TXB0+ 17
M_TXB0- 17

1 2

U57

42

PI3HDMI412FTZHE

22

D3-_B

23

D3+_B

24

D2-_B

25

D2+_B

26

D1-_B

27

D1+_B

28

D0-_B

29

D0+_B

31

D3-_A

32

D3+_A

33

D2-_A

34

D2+_A

35

D1-_A

36

D1+_A

37

D0-_A

38

D0+_A

39

DVI_HDMI_SEL_G

R2132
10K_0402_5%

Add in 6/5.

D

S

13

G

Q125

2

RHU002N06_SOT323

D

S

13

G

Q126

2

RHU002N06_SOT323

R2111
0_0402_5%

1 2

Add for leakage issue.1/7
Need update the part after

apply ready.1/9

+3VS_D80

HDMI_CLK- 16
HDMI_CLK+ 16
HDMI_TX2- 16
HDMI_TX2+ 16
HDMI_TX1- 16
HDMI_TX1+ 16
HDMI_TX0- 16
HDMI_TX0+ 16

DVI_D_TX5- 36
DVI_D_TX5+ 36
DVI_D_TX4- 36
DVI_D_TX4+ 36
DVI_D_TX3- 36
DVI_D_TX3+ 36

+1.5VS

4

D D

B+

KC FBM-L11-201209-221LMA30T_0805

LCDVDD

M_TXACLK-17

Change pin
size cause
MXM-HE.5/24

C C

DVI_DAT17

DVI_CLK17

B B

+1.5VS

C1584

C1583

1

2

Removed RP44 ~ RP47. 10/18

A A

0.1U_0402_16V4Z

Add C1583, C1584 decoupling for +1.5VS. 10/18

J1

PAD-SHORT 2x2m@

PAD-No SHORT 2x2m@

21

J2

21

R2176 0_0402_5%@

HDMICLK 16

DVICLK 36

M_PWM 17

INV_PWM 34

M_ENAVDD17

+5VS

Change in 8/4.

U61
SN74LVC1G14DCKR_SC70-5

5

V

4

1 2

2

A

Y

NC

G

1

3

Add GPIO extander 6/2.

Change package 7/4.

U59

HDMIEN

DVIEN

R2112 0_0402_5%

1 2

R2113 0_0402_5%

1 2

I/O01VCC
I/O12SDA

3

I/O2
VSS4I/O3

PCA9536DP_TSSOP8

Change design in 6/20.

DVI_HDMI_R_SEL D VI_HDMI_SEL

1

1

C1566

C1565

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R2148 2.21K_0402_1%

1 2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

SCL

R307

100_0402_1%

Q55

2N7002_SOT23

+5VS

8

M_LCD_DAT

7

M_LCD_CLK

6
5

M_ENBLT17

Compal Secret Data

LCDVDD

12

13

D

S

2

Deciphered Date

R315 47K_0402_5%

1 2

2

G

13

Q56
DTC124EK_SC59

1

C1393

0.1U_0402_16V4Z

2

LID_SW#

1
2

R86100K_0402_5%

1 2

C2880.1U_0402_16V4Z

1

2

Function opt i o n , A d d i n 6/5. (Reserved at 6/6)

DVI_HDMI_R_SEL DVI_HDMI_SEL

+3VS

+5VS

U11A
SN74LVC08APW_TSSOP14

14

P

A

3

O

B

G

7

1 2

2

Q1

AO3413_SOT23

D

S

1 3

G

2

R309 1M_0402_5%

1 2

C298 0.047U_0402_16V7K

1 2

C124.7U_0805_10V4Z

1

2

Change
design in
6/20.

R2124

R2123

1.8K_0402_5%

1 2

1 2

R2127

4.53K_0402_1%~D

Q10
DTA114YKA_SC59

47K

10K

2

13

D

2

G

S

R80100K_0402_5%

Size Document Number Rev

Date: Sheet

0_0402_5%

@

1 2

DVIEN HDMIEN

0_0402_5%

R2128

1 2

@

13

+5VS_INV

Q13
BSS138_SOT23

Title

Compal Electronics, Inc.

LCD CONN & Q-Switch & GPIO Ext.

LA-3331P

+5VS +5VS+5VS+3VS

1 2

1 2

R2125

R2129

+3VALWLCDVDD

1

2

0_0402_5%

@

0_0402_5%

@

C2894.7U_0805_10V4Z@

0_0402_5%

R2126

@

1 2

R2130

0_0402_5%

1 2

@

1.0

of

18 59Tuesday, May 1 5, 2007

1

5

+3VS

1 2

R1750 8.2K_0402_5%

1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2

D D

C C

R1751 8.2K_0402_5%
R1752 8.2K_0402_5%
R1753 8.2K_0402_5%

R1754 8.2K_0402_5%
R1755 8.2K_0402_5%
R1756 8.2K_0402_5%
R1757 8.2K_0402_5%

+3VS

R1759 8.2K_0402_5%
R1760 8.2K_0402_5%
R1761 8.2K_0402_5%
R1762 8.2K_0402_5%

R1765 8.2K_0402_5%
R1766 8.2K_0402_5%

R1769 8.2K_0402_5%
R2089 8.2K_0402_5%
R1770 8.2K_0402_5%
R1771 8.2K_0402_5%
R1772 8.2K_0402_5%
R1773 8.2K_0402_5%

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PCI_PIRQE#
PCI_IRQF#

Change net name. 5/10

PCI_PIRQH#
PCI_PIRQG#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#

This pin is OD pin so add PU. 5/16
Reserved R2089. 6/2
Installed R2089. 6/5

PCI_AD[0..31]27

Disconnect to Cardbus
controller. 8/15

4

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#
PCI_PIRQB#

PCI_PIRQC#27
PCI_PIRQD#27

PCI_PIRQC#

PCI_PIRQD#

U10B

D20

AD0

E19
D19
A20
D17
A21
A19
C19
A18
B16
A12
E16
A14
G16
A15

B6

C11

A9
D11
B12
C12
D10

C7
F13
E11
E13
E12

D8

A6
E8

D6

A3

F9
B5

C5
A10

PCI

AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

Interrupt I/F

PIRQA#
PIRQB#
PIRQC#
PIRQD#

ICH8M REV 1.0

Removed R1767 , R2053 5/5.

REQ0#

GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

C/BE0#

C/BE1#

C/BE2#

C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2

PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

3

A4
D7
E18
C18
B19
F18
A11
C10

C17
E15
F16
E17

C8
D9
G6
D16
A7
B7
F10
C16
C9
A17

AG24
B10
G7

F8
G11
F12
B3

PCI_PIRQG#
PCI_PIRQH#

2

Del Modem disable

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#

PCI_REQ2#
PCI_GNT2#
PCI_REQ3#
PCI_GNT3#

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_PLTRST#
CLK_PCI_ICH
PCI_PME#

1 2

R2044 8.2K_0402_5%

PCI_PIRQE#
PCI_IRQF#

R188 0_0402_5%

Chnage desig n t o same as Chimay 5/5.
Chnage design , move LANLINK_STATUS# to GPIO1.
Connect to Richo chip.8/15

function in 6/21.
Add in 6/15.

PCI_REQ2# 27
PCI_GNT2# 27

PCI_CBE#0 27
PCI_CBE#1 27
PCI_CBE#2 27
PCI_CBE#3 27

PCI_IRDY# 27
PCI_PAR 27

PCI_DEVSEL# 27
PCI_PERR# 27

PCI_SERR# 27,34
PCI_STOP# 27
PCI_TRDY# 27
PCI_FRAME# 27

CLK_PCI_ICH 15

+3VALW

12

PCI_PIRQE# 27

PCI_PIRQG# 27

ACCEL_INT 26

T93 PA D

1
2

R1758 0_0402_5%

Change design to

4

+3VALW

1

B

2

A

same as Chimay.
5/10

5

3

+3VALW

5

U37

P

B

Y

A

G

TC7SH08FU_SSOP5@

3

12

R1768 0_0402_5%

1

12

R1763
100K_0402_5%

U55

P

4

Y

G

TC7SH08FU_SSOP5@

12

PCI_RST# 27

Change design to
same as Chimay.
5/10

PLT_RST# 7,20,21,26,32,33

12

R1764
100K_0402_5%

Change design to
same as Chimay.
5/10

A16 swap override Strap

B B

PCI_GNT3#

(According to ICH8 EDS

1.5 P.86)

A A

Low= A16 swap override Enble
High= Default

PCI_GNT3#

Del R2054. 5/12

Place closely pin B10

CLK_PCI_ICH

R1777

10_0402_5% @

C1385

8.2P_0402_50V@

5

12

1 2
1

2

*

R1774

1K_0402_5% @

Boot BIOS Strap

PCI_GNT0# SPI_CS#1

R1775
1K_0402_5%

J15
PAD-SHORT 2x2m@

1

0

1

0

1

1

PCI_GNT0#

12

21

4

Boot BIOS Location

SPI

*

PCI

LPC

SPI_CS1#_R21

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

R1776

1K_0402_5%@

2006/02/13 2006/03/10

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

ICH8(1/4)-PCI/INT

LA-3331P

1

1.0

of

19 59Tuesday, May 1 5, 2007

5

+3VS

GPIO23

R2083 10K_0402_5%@

GATEA20

R1778 10K_0402_5%

KB_RST#

R1780 10K_0402_5%

H_FERR#

R1783 56_0402_5%

H_DPRSTP#
H_DPSLP#

AC97_BITCLK_MDC35

AC97_BITCLK_CODEC29

AC97_SYNC_CODEC29

AC97_RST#_CODEC29

AC97_SDOUT_MDC35

AC97_SDOUT_CODEC29

IDE_LED#23

C139112P_0402_50V8J

R1784 56_0402_5%@
R1785 56_0402_5%@

AC97_SYNC_MDC35

AC97_RST#_MDC30,35

AC97_SDIN029
AC97_SDIN135

R1800

1 2

10M_0402_5%

1

1

2

2

D D

C C

B B

12
12
12

12
12
12

+RTCVCC

C1386
1U_0603_10V4Z

+3VS

R1799 10K_0402_5%

ICH_RTCX1

ICH_RTCX2

C139212P_0402_50V8J

Y7

4

32.768KHZ_12.5P_1TJS125BJ2A251

1

IN

OUT

2

NC3NC

R1786
20K_0402_5%

1 2

AC97_SDOUT_CODEC

12

Reserve pad for test. 5/14

+VCCP

2

CLRP3
SHORT PADS

1 2

1

GLAN_CLK24

LAN_RST24

LAN_RXD024
LAN_RXD124
LAN_RXD224

LAN_TXD024
LAN_TXD124
LAN_TXD224

ENERGY_DET25

+1.5VS

G_BATLED#34

1 2

R1788 24.9_0402_1%

R1791

1 2

R1790

1 2

R1792 33_0402_5%

1 2

R1793 33_0402_5%

1 2

R1794 33_0402_5%

1 2

R1795 33_0402_5%

1 2

R1797 33_0402_5%

1 2

R1798 33_0402_5%

Del D77. 12/20

CLK_PCIE_SATA#15
CLK_PCIE_SATA15

33_0402_5%
33_0402_5%

1 2

CLRP2 SHORT PADS

12

Del 2nd SATA
in 6/1.

R1802

1 2

24.9_0402_1%

Within 500 mils

ICH_RTCX1
ICH_RTCX2

ICH_RTCRST#
SM_INTRUDER#
ICH_INTVRMEN

LAN100_SLP

GLAN_COMP
AC97_BITCLK

AC97_SYNC
AC97RST#

AC97_SDOUT

T80PAD

IDE_LED#

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0_C
SATA_TXP0_C

4

+RTCVCC

R1779 330K_0402_1%

1 2

R1781 470K_0402_5%

1 2

R1782 330K_0402_1%

1 2

U10A

AG25

RTCX1

AF24

RTCX2

AF23

RTCRST#

AD22

INTRUDER#

AF25

INTVRMEN

AD21

LAN100_SLP

B24

GLAN_CLK

D22

LAN_RSTSYNC

C21

LAN_RXD0

B21

LAN_RXD1

C22

LAN_RXD2

D21

LAN_TXD0

E20

LAN_TXD1

C20

LAN_TXD2

AH21

GLAN_DOCK#/GPIO13

D25

GLAN_COMPI

C25

GLAN_COMPO

AJ16

HDA_BIT_CLK

AJ15

HDA_SYNC

AE14

HDA_RST#

AJ17

HDA_SDIN0

AH17

HDA_SDIN1

AH15

HDA_SDIN2

AD13

HDA_SDIN3

AE13

HDA_SDOUT

AE10

HDA_DOCK_EN#/GPIO33

AG14

HDA_DOCK_RST#/GPIO34

AF10

SATALED#

AF6

SATA0RXN

AF5

SATA0RXP

AH5

SATA0TXN

AH6

SATA0TXP

AG3

SATA1RXN

AG4

SATA1RXP

AJ4

SATA1TXN

AJ3

SATA1TXP

AF2

SATA2RXN

AF1

SATA2RXP

AE4

SATA2TXN

AE3

SATA2TXP

AB7

SATA_CLKN

AC6

SATA_CLKP

AG1

SATARBIAS#

AG2

SATARBIAS

ICH8M REV 1.0

RTCLAN / GLAN

CPUPWRGD/GPIO49

IHDA

SATA

LAN100_SLP

SM_INTRUDER#

ICH_INTVRMEN

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

LDRQ1#/GPIO23

LPCCPU

A20GATE

DPRSTP#

STPCLK#

THRMTRIP#

IDE

LDRQ0#

A20M#

DPSLP#

FERR#

IGNNE#

INIT#
INTR

RCIN#

SMI#

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8

DD9
DD10
DD11
DD12
DD13
DD14
DD15

DCS1#
DCS3#

DIOR#

DIOW#

DDACK#

IDEIRQ

IORDY

DDREQ

3

Change from 1 M to 470K. 6/14

Del Kensington support. 10/18

LPC_AD0

E5

LPC_AD1

F5

LPC_AD2

G8

LPC_AD3

F6
C4
G9

GPIO23

E6

GATEA20

AF13
AG26

H_DPRSTP_R#

AF26

H_DPSLP#

AE26

H_FERR#

AD24
AG29
AF27
AE24

AC20

KB_RST#

AH14
AD23

NMI

AG28
AA24

THRMTRIP_ICH#

AE27
AA23

TP8

DA0
DA1
DA2

PD_D0

V1

PD_D1

U2

PD_D2

V3

PD_D3

T1

PD_D4

V4

PD_D5

T5

PD_D6

AB2

PD_D7

T6

PD_D8

T3

PD_D9

R2

PD_D10

T4

PD_D11

V6

PD_D12

V5

PD_D13

U1

PD_D14

V2

PD_D15

U6

PD_A0

AA4

PD_A1

AA1

PD_A2

AB3

PD_CS#1

Y6

PD_CS#3

Y5

PD_IOR#

W4

PD_IOW#

W3

PD_DACK#

Y2

PD_IRQ

Y3

PD_IORDY

Y1

PD_DREQ

W5

LPC_AD[0..3 ] 32,33,34

LPC_FRAME# 32,33,34
LPC_DRQ#0 32

GATEA20 34
H_A20M# 4

H_DPRSTP#

R1787 0_0402_5%

12

H_FERR# 4

H_PWRGOOD 4,5
H_IGNNE# 4
H_INIT# 4

H_INTR 4

KB_RST# 34

H_NMI 4
H_SMI# 4

H_STPCLK# 4

1 2

R1796 24_0402_1%

within 2"

placed within 2"
from ICH8M

R1801 8.2K_0402_5%

1 2

R1803 4.7K_0402_5%

1 2

H_DPRSTP# 5,7,46
H_DPSLP# 5

Add 2nd STAT in 4/19.

+VCCP

12

R1789
56_0402_5%

Del 2nd SATA in 6/1.
Del JP54 , C1387~C1390.6/1

Change PLT_RST_B# to
PLT_RST#. 6/15

change from ODD_RST# to
PLT_RST_B#. 5/19

H_THERMTRIP# 4,7

D35
CH751H-40_SC76

IDE_LED# IDE_DSP#

2 1

+5VS

R499 4.7K_0402_5%@
R503 470_0402_5%

+3VS

PLT_RST#7,19,21,26,32,33

1 2

+5VS

2

12

R51210K_0402_5%

12

PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0

PD_IOW#
PD_IORDY
PD_IRQ
PD_A1
PD_A0
PD_CS#1

SEC_CSEL

SATA CONN

ODD CONN

+5VS
+5VS

OCTEK_CDR-50DU1

conn@

Del U52.6/15
Del C1394~C1397.6/1

JP20

GND
GND

GND

GND

V33
V33

V33
GND
GND
GND

GND

RSVD

GND

V12

V12

V12
GND

OCTEK_SAT-22DN1G_NRconn@

JP13

112
334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950

1

+5VS

C148

C153

C151

24
S1

SATA_TXP0

S2

A+

A­B-

B+

V5
V5
V5

SATA_TXN0

S3
S4

SATA_RXN0

S5

SATA_RXP0

S6
S7

P1
P2
P3
P4
P5
P6
P7
P8
P9

+5VS
P10
P11

P12
P13
P14
P15

23

2
4

PD_D8

6

PD_D9

8

PD_D10

10

PD_D11

12

PD_D12

14

PD_D13

16

PD_D14

18

PD_D15

20

PD_DREQ

22

PD_IOR#

24
26

PD_DACK#

28
30

PDIAG#

32

PD_A2

34

PD_CS#3

36
38
40
42
44
46
48
50

W=80mils

C104 0.1U_0402_16V4Z

1

2

10U_0805_10V4Z

Place component's
closely SATA

L

CONN.(JP20)

+5VS

C98

1

2

10U_0805_10V4Z

Place component's

L

closely ODD CONN.

R509
100K_0402_5%

1 2

+5VS
+5VS

12

+5VS

1

2

0.1U_0402_16V4Z

C100

1

2

0.1U_0402_16V4Z

+5VS

C156

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C101

C102

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Del R1804,R2 0 5 5 ,R2056 in 5/19.

Change to right one.7/26

Follow Intel Reference

+RTCVCC +3VL

design circuit.5/15

R430 0_0402_5%

AC97_BITCLK

R1805

@

10_0402_5%

1 2

1

C1398

10P_0402_25V8K@

2

A A

1

C403
1U_0603_10V4Z

2

1 2

BATT1

45@

CR2032 RTC BATTERY

D32

1

DAN202U_SC70

1 2

L

W=20mils

R423
1K_0402_5%

ZZZ

RTC2RTC1

3
2

PCB-MB

XOR CHAIN ENTRANCE STRAP:RSVD

+3VS

R1806

1K_0402_5%@

AC97_SDOUT_CODEC

12

5

4

JP28

ACES_85204-02001conn@

1122G13G2

4

-+

SATA_RXN0_C

SATA_RXP0_C

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

C175 3900P_0402_50V7K

1 2

C173 3900P_0402_50V7K

1 2

Compal Secret Data

Deciphered Date

SATA_RXN0

2

SATA_TXP0_C SATA_TXP0SATA_RXP0

Title

Size Document Number Rev

Custom

Date: Sheet

C150 3900P_0402_50V7K

1 2

C149 3900P_0402_50V7K

1 2

LL

Near ICH8-M side.Near Device side.

Compal Electronics, Inc.

ICH8(2/4)_LAN,HD,IDE,LPC

LA-3331P

1

SATA_TXN0SATA_TXN0_C

1.0

of

20 59Tuesday, May 1 5, 2007

+3VS

1 2

R2183 10K_0402_5%

1 2

R1808 10K_0402_5%

1 2

R1813 8.2K_0402_5%

1 2

R1816 10K_0402_5%

1 2

R1819 10K_0402_5%

1 2

R1821 8.2K_0402_5%@

1 2

R1822 10K_0402_5%

D D

1 2

R1823 8.2K_0402_5%

1 2

R1824 8.2K_0402_5%@

1 2

R1827 10K_0402_5%

1 2

R2091 8.2K_0402_5%

1 2

R1830 8.2K_0402_5%

1 2

R1835 10K_0402_5%

+3VALW

Add in 5/5.

1 2

R2078 100K_0402_5%

1 2

R1832 10K_0402_5%@

1 2

R1837 10K_0402_5%
R1839 8.2K_0402_5%

1 2

R1840 1K_0402_5%

1 2

R1842 10K_0402_5%

1 2

R1845 10K_0402_5%

1 2

R1847 1K_0402_5%

1 2

R1848 10K_0402_5%

C C

1 2

R2045 10K_0402_5%
R1850 1K_0402_5%@

1 2

R1851 100K_0402_5%

1 2

R2173 100K_0402_5%

Add in 7/28.

10K_0402_5%

PREP#25,29,36

B B

R1866

2.2K_0402_5%

ICH_SM_DA4,17,26

ICH_SM_CLK4,17,26

Del RP38 , RP39. 5/16
Add back RP38 , RP39. 8/23

+3VALW

RP38

10K_1206_8P4R_5%

1 8
2 7
3 6
4 5

1 8

A A

2 7
3 6
4 5

RP39

10K_1206_8P4R_5%

5

NPCI_RST#
SIRQ
PM_CLKRUN#
GPIO39

MCH_ICH_SYNC#

THERM_SCI#
CLKSATAREQ#
GPIO37
GPIO18
GPIO22
GPIO48
DOCK_ID_R
OCP#

GPIO14
CL_RST#1
LID_SW#
ICH_LOW_BAT#

12

PCIE_WAKE#
ICH_RI#
LAN_PHYPC_R
XDP_DBRESET# SPI_CS1#
GPIO26 VGARST#
CB_IN#
ICH_RSVD

12

DPRSLPVR
VRMPWRGD

ICH_SMBDATA13,14,15

ICH_SMBCLK13,14,15

+3VM_LAN +3VS

R1852

USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5

USB_OC#8
USB_OC#9

Add for solve issue
for enable LAN/WLAN
switching, unplug
AC, WLAN will be
disabled on XP OS.
3/30

ME__EC_CLK134

ME__EC_DATA134

Change pull up from
+3VALW to +3VS. 8/28

GPIO20

GPIO20 4

MXM_THERM#17

+3VALW

R1814

10K_0402_5%

H_STP_PCI#15

H_STP_CPU#15

Chnage 2'rd FAN control signal
from GPIO18 to GPIO20.9/8

Del from PV.3/14

Modify in 8/28.

Change to 1K.
(Follow Chimay 8/24)

+3VM

12

12

R205

2.2K_0402_5%

ICH_SMBDATA
ICH_SMBCLK

12

CH751H-40_SC76

+3VS +3VS

12

12

+5VS

VGA_RST#17

5

12

R1853

D60

R1867

2.2K_0402_5%

S

10K_0402_5%

ISO_PREP#

21

Q81
RHU002N06_SOT323

D

ICH_SMB_DATA

13

D

S

ICH_SMB_CLK

G

13

Q82

2

RHU002N06_SOT323

G

2

Del R2157 & modify
net name in 7/31

Add R2207 for isolate from MXM and to
solve power consumption to high when sleep
mode issue. 3/26

8

2.2K_0402_5%
R204

S

+3VM

WLAN

Robson

DOC

+3VS

U11C
SN74LVC08APW_TSSOP14

14

9

P

A

O

10

B

G

7

Q24
RHU002N06_SOT323

D

13

S

G

2

Modify net name. 6/14

VGARST#

U63
SN74AHC1G08DCKR_SC70

R1815
10K_0402_5%

1 2

1 2

1 2

R1854 0_0402_5%@

LAN_PHYPC24

Change option. 8/28

ICH_SMB_DATA

D

ICH_SMB_CLK

13

Q25

G

RHU002N06_SOT323

2

RSMRST_ICH#

PCIE_RXN226
PCIE_RXP226
PCIE_TXN226
PCIE_TXP226

PCIE_RXN426
PCIE_RXP426
PCIE_TXN426
PCIE_TXP426

PCIE_RXN536
PCIE_RXP536
PCIE_TXN536
PCIE_TXP536

GLAN_RXN24
GLAN_RXP24
GLAN_TXN24
GLAN_TXP24

SPI_CLK33
SPI_CS#33
SPI_CS1#33

SPI_CS1#_R19

SPI_SI33

SPI_SO_JP5233

SPI_SO_R33

BT_OFF31

MXM_CD0#17
MXM_CD1#17,48

R2057

0_0402_5%@

1 2

PLT_RST# 7,19,20,26,32,33

4

5

P

SLP_S3#_U63

ICH_SMBCLK
ICH_SMBDATA

+3VM

R1825
10K_0402_5%

Exchange with
LANLINK_STATUS# 8/28.

LAN_PHYPC

CLKSATAREQ#15

4

1 2

1 2

THERM_SCI#

VGATE7,46

O

R1826
10K_0402_5%

IN1
IN2

G

3

R1817 0_0402_5%@
R1820 0_0402_5%@

R1841 0_0402_5%@
R2184 0_0402_5%
R1992 0_0402_5%

Don't need IDE_RESET#. 5/19

ICH_SMB_DATA 26
ICH_SMB_CLK 26

R1807 10K_0402_5%

1 2

C1407 0.1U_0402_16V4Z
C1408 0.1U_0402_16V4Z

R1868 15_0402_5%

1 2

R1869 15_0402_5%

1 2

R2103 15_0402_5%

1 2

R1870 15_0402_5%

1 2

R1871 0_0402_5%

R1844 0_0402_5%

1 2

R2207 0_0402_5%@

1 2

R1873 0_0402_5%@

1 2

D

1 3

+3VALW

4

2

+3VALW

SLP_S3#

1
2

CL_RST#126

LAN_STATUS#

R1829 0_0402_5%

R1833 0_0402_5%@

Reserve in 6/6.

1 2
1 2
1 2

2.2K_0402_5%

12
12

XDP_DBRESET#4

PM_CLKRUN#27,32,33,34

1 2

R1809

LPC_PD#33

PM_BMBUSY#7

12

PCIE_WAKE#26

THERM_SCI#4

RUNSCI_EC#34

ISO_PREP#36
LID_SW#18

Del R1849 in 5/19.

SB_SPKR29

MCH_ICH_SYNC#7

1 2

+3VS

R2068 10K_0402_5% @

RSMRST_ICH# 34

PCIE_C_TXN2

C14050.1U_0402_16V4Z

12

PCIE_C_TXP2

C14060.1U_0402_16V4Z

12

PCIE_C_TXN4

C14020.1U_0402_16V4Z

12

12
12

12

S

Q84

2N7002_SOT23@

G

PCIE_C_TXP4

C14030.1U_0402_16V4Z

12

PCIE_C_TXN5

C15490.1U_0402_16V4Z

12

PCIE_C_TXP5

C15500.1U_0402_16V4Z

12

GLAN_RXN
GLAN_RXP
GLAN_TXN_C
GLAN_TXP_C

SPI_CLK_R
SPI_CS0#_R

SPI_SI_R
SPI_SO_R

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
MXM_CD0#_R
MXM_CD1#_R
USB_OC#8
USB_OC#9

3

12

12

R1810

2.2K_0402_5%

ICH_SMB_CLK
ICH_SMB_DATA
CL_RST#1
ME__EC_CLK1
ME__EC_DATA1

ICH_RI#

XDP_DBRESET#

1 2

R2114 0_0402_5%

R_STP_CPU#

PCIE_WAKE#
SIRQ

SIRQ27,32,33,34

THERM_SCI#
VRMPWRGD
SST_CTL

T65PAD

T84PAD
T66PAD

T83PAD

T68PAD

OCP#
ISO_PREP#
LAN_PHYPC_R

ALS_EN#
GPIO18
GPIO20
GPIO22

CLKSATAREQ#
DOCK_ID_R
GPIO39
GPIO48

SB_SPKR
MCH_ICH_SYNC#
ICH_RSVD

SB_SPKR

P27
P26
N29
N28

M27
M26

L29
L28

K27
K26
J29
J28

H27
H26
G29
G28

F27
F26
E29
E28

D27
D26
C29
C28

C23
B23
E22

D23
F21

AJ19
AG16
AG15
AE15
AF15
AG17
AD12

AJ18
AD14
AH18

OCP#4,48

U10D

PERN1
PERP1
PETN1
PETP1

PERN2
PERP2
PETN2
PETP2

PERN3
PERP3
PETN3
PETP3

PERN4
PERP4
PETN4
PETP4

PERN5
PERP5
PETN5
PETP5

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

SPI_CLK
SPI_CS0#
SPI_CS1#

SPI_MOSI
SPI_MISO

OC0#
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#
OC9#

ICH8M REV 1.0

LANLINK_STATUS#24,25,36

U10C

AJ26

SMBCLK

AD19

SMBDATA

AG21

LINKALERT#

AC17

SMLINK0

AE19

SMLINK1

AF17

RI#

F4

SUS_STAT#/LPCPD#

AD15

SYS_RESET#

AG12

BMBUSY#/GPIO0

AG22

SMBALERT#/GPIO11

AE20

STP_PCI#/GPIO15

AG18

STP_CPU#/GPIO25

AH11

CLKRUN#/GPIO32

AE17

WAKE#

AF12

SERIRQ

AC13

THRM#

AJ20

VRMPWRGD

AJ22

TP7

AJ8

TACH1/GPIO1

AJ9

TACH2/GPIO6

AH9

TACH3/GPIO7

AE16

GPIO8

AC19

GPIO12

AG8

TACH0/GPIO17

AH12

GPIO18

AE11

GPIO20

AG10

SCLOCK/GPIO22

AH25

QRT_STATE0/GPIO27

AD16

QRT_STATE1/GPIO28

AG13

SATACLKREQ#/GPIO35

AF9

SLOAD/GPIO38

AJ11

SDATAOUT0/GPIO39

AD10

SDATAOUT1/GPIO48

AD9

SPKR

AJ13

MCH_SYNC#

AJ21

TP3

ICH8M REV 1.0

low-->default
High -->No boot

PCI-Express

SPI

USB

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

DMI_CLKN
DMI_CLKP

DMI_ZCOMP

DMI_IRCOMP

Direct Media Interface

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBRBIAS#

USBRBIAS

SLP_S3#_U63

S

SATA

SMB

SYS

GPIO

GPIO

MISC

GPIO14

Delete D71,R 3 5 1 & n et A D P _P RES and change design to as
Chimay 6/1.

DMI_RXN0

V27

DMI_RXP0

V26

DMI_TXN0

U29

DMI_TXP0

U28

DMI_RXN1

Y27

DMI_RXP1

Y26

DMI_TXN1

W29

DMI_TXP1

W28

DMI_RXN2

AB26

DMI_RXP2

AB25

DMI_TXN2

AA29

DMI_TXP2

AA28

DMI_RXN3

AD27

DMI_RXP3

AD26

DMI_TXN3

AC29

DMI_TXP3

AC28

CLK_PCIE_ICH#

T26

CLK_PCIE_ICH

T25
Y23

DMI_IRCOMP

Y24

USB20_N0

G3

USB20_P0

G2

USB20_N1

H5

USB20_P1

H4

USB20_N2

H2

USB20_P2

H1

USB20_N3

J3

USB20_P3

J2

USB20_N4

K5

USB20_P4

K4

USB20_N5

K2

USB20_P5

K1

USB20_N6

L3

USB20_P6

L2

USB20_N7

M5

USB20_P7

M4

USB20_N8

M2

USB20_P8

M1

USB20_N9

N3

USB20_P9

N2

USBRBIAS

F2
F3

R2187
10K_0402_5%

G

2

13

D

Q136
RHU002N06_SOT323

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36

GPIO

SATA3GP/GPIO37

Clocks

S4_STATE#/GPIO26

DPRSLPVR/GPIO16

Power MGTController Link

MEM_LED/GPIO24
ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14

WOL_EN/GPIO9

R2077 0_0402_5%

12

AJ12
AJ10
AF11
AG11

AG9

CLK14

G5

CLK48

D3

SUSCLK

AG23

SLP_S3#

AF21

SLP_S4#

AD18

SLP_S5#

AH27
AE23

PWROK

AJ14
AE21

BATLOW#

C2

PWRBTN#

AH20

LAN_RST#

AG27

RSMRST#

E1

CK_PWRGD

E3

CLPWROK

AJ25

SLP_M#

F23

CL_CLK0

AE18

CL_CLK1

F22

CL_DATA0

AF19

CL_DATA1

D24

CL_VREF0

AH23

CL_VREF1

AJ23

CL_RST#

AJ27
AJ24
AF22
AG19

12

DMI_RXN0 7
DMI_RXP0 7
DMI_TXN0 7
DMI_TXP0 7

DMI_RXN1 7
DMI_RXP1 7
DMI_TXN1 7
DMI_TXP1 7

DMI_RXN2 7
DMI_RXP2 7
DMI_TXN2 7
DMI_TXP2 7

DMI_RXN3 7
DMI_RXP3 7
DMI_TXN3 7
DMI_TXP3 7

CLK_PCIE_ICH# 15
CLK_PCIE_ICH 15

R1864 24.9_0402_1%

1 2

USB20_N0 31
USB20_P0 31
USB20_N1 33
USB20_P1 33
USB20_N2 31
USB20_P2 31
USB20_N3 30
USB20_P3 30
USB20_N4 30
USB20_P4 30
USB20_N5 30
USB20_P5 30
USB20_N6 31
USB20_P6 31
USB20_N7 36
USB20_P7 36
USB20_N8 30
USB20_P8 30
USB20_N9 36
USB20_P9 36

1 2

R1875 22.6_0402_1%

LAN_STATUS#

Within 500 mils

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

2

+3VALW+3VALW+3VM_LAN

Add in 11/02.

R1818
10K_0402_5%

1 2

NPCI_RST#
GPIO37

CLK_14M_ICH
CLK_48M_ICH

ICH_SUSCLK

SLP_S3#

GPIO26

DPRSLPVR
ICH_LOW_BAT#

EC_RMRST#
CK_PWRGD_R

PM_SLP_M#

CL_VREF0_ICH
CL_VREF1_ICH

CB_IN#
GPIO14

AMT_ADP_PRES 34

AMT_BI_GPIO34

Confirm to change the
design. 6/2

Within 500 mils

+1.5VS

HDD_HALTLED 23
NPCI_RST# 32,34

CLK_14M_ICH 15
CLK_48M_ICH 15

T64 PAD

1 2

R1836 100_0402_5%

1 2

R1838 0_0402_5%

LAN_WOL_EN 37

USB_OC#0

R2085 10K_0402_5%

USB_OC#1

R2086 10K_0402_5%

MXM_CD0#_R

R1874 10K_0402_5%

MXM_CD1#_R

R1876 22K_0402_5%

M/B(1)
FP

M/B(2)

Audio/B

BT
DOC1

Audio/B
DOC2

Mount on 8/24.

2

1

Place closely pin AC1Place closely pin B2

CLK_48M_ICH

12

R1811

10_0402_5%@

1

C1399

4.7P_0402_50V8C@

2

SLP_S3# 17,24,29,30,34,36,37,44,45,46,48,49
SLP_S4# 37,45
SLP_S5# 37,45

GPIO26 33
PM_PWROK 7,34,46
DPRSLPVR 7,46

D59 CH751H-40_SC76

ON/OFFBTN# 35
LAN_RST# 38

M_PWROK 7,38
PM_SLP_M# 34,37,44,45,49

CL_CLK0 7
CL_CLK1 26

CL_DATA0 7
CL_DATA1 26

CL_RST# 7

XMIT_OFF# 26

Change Design in
6/2.

1 2

1 2
1 2
1 2
1 2

Change design.
8/24

CLK_ENABLE#46

Change USB
assignment.
5/19

ALS_EN#

Size Document Number Rev

Custom

Date: Sheet of

Add this net to control
FPR/USB powe r on S3. 2/12

R1831 10K_0402_5%

1 2

2 1

Modify to same
as Chimay 5/5

RSMRST_ICH#

Chnage
Design. 5/16

Title

CK_PWRGD

R1856
0_0402_5%

+3VALW

2

G

Q80

RHU002N06_SOT323

2

G

12

R2115
10K_0402_5%

Compal Electronics, Inc.

ICH8(3/4)_PM,USB,GPIO

LA-3331P

CK_PWRGD 15

1

2

C1401

0.1U_0402_16V4Z

1

2

C1404

0.1U_0402_16V4Z

J16

2 1

PAD-No SHORT 2x2m

R1862

1K_0402_5%@

1 2
13

D

S

+5VS

R1872
330_0402_5%

1 2
13

D

Q83
RHU002N06_SOT323

S

CLK_14M_ICH

12

R1812

10_0402_5%@

1

C1400

4.7P_0402_50V8C@

2

LOW_BAT# 34

R1834
10K_0402_5%

12

R1843

3.24K_0402_1%

1 2

12

R1846
453_0402_1%

+3VALW

R1855

3.24K_0402_1%

1 2
12

R1858
453_0402_1%

1 2

R2182 10K_0402_5%

1 2

R1863 0_0402_5%@

1 2

R1865 0_0402_5%

C1576

0.1U_0402_16V4Z @

Add for find
tune
timing.(glich
issue 7/28)

ALS_EN 18

1

+3VL

+3VM

Change
to same
as
Chimay
in 8/2.

CABLE_DETECT 25

PWR_GD17,27,34,37,38,46,48

CK_PWRGD

VRMPWRGD

1

2

21 59Tuesday, May 1 5, 2007

1.0

5

+RTCVCC

20 mils

ICH_V5REF_RUN

R1610

100_0402_5%

1

C1212

2

+1.5VS

0.1U_0402_16V4Z

C122410U_0805_6.3V6M

1

2

+5VS

10U_0805_6.3V6M

12

+1.5VSL

1

2

ICH_V5REF_SUS

40 mils

1

1

+

C1412

C1411220U_D2_4VM

2

2

10U_0805_6.3V6M

+3VS

21

D55
CH751H-40_SC76

1

C1190
1U_0603_10V4Z

2

Chnage to 1uF. 5/02

1U_0603_10V4Z

+1.5VS

1U_0603_10V4Z

1

C1220

2

T30
T31

1 2

+1.5VS

C1225

CHB1608U301_0603

2.2U_0603_10V6K

1

1

C1413

C1414

2

2

10U_0805_6.3V6M

2.2U_0603_6.3V4Z

20 mils

+1.5VS

1

C1213

2

1

C1216

2

VCC_LAN1_05_INT_ICH_1
VCC_LAN1_05_INT_ICH_2

C1228

L19

1

2

4.7U_0805_10V4Z

1

R1611

10_0402_5%

0.1U_0402_16V4Z

1

C14090.1U_0402_16V4Z

2

12

+1.5VS

+3VALW+5VALW

C1223

C14100.1U_0402_16V4Z

2

D D

C C

B B

A A

+1.5VS

L16

1 2

20 mils

+1.5VS

CHB1608U301_0603

5

CHB1608U301_0603

1

C1211

2

1U_0603_10V4Z

1

C1219

2

0316 change design

L18

1 2

21

D56
CH751H-40_SC76

ICH_V5REF_SUS ICH_V5REF_RUN

1

C1200

0.1U_0402_16V4Z

2

L21

1 2

CHB1608U301_0603

+1.5VS

0.1U_0402_16V4Z

+3VM

1

2

+1.5VSAPL

+1.5VS

+1.5VSPL
+1.5VSL

+3VS

4

AD25

AA25
AA26
AA27
AB27
AB28
AB29

W25

AG7

AC10

W23

A16

T7

G4

D28
D29
E25
E26
E27
F24
F25
G24
H23
H24
J23
J24
K24
K25
L23
L24

L25
M24
M25
N23
N24
N25

P24

P25
R24
R25
R26
R27

T23

T24

T27

T28

T29
U24
U25

V23

V24

V25

Y25

AJ6
AE7

AF7
AH7

AJ7
AC1

AC2
AC3
AC4
AC5

AC9
AA5

AA6
G12

G17

H7

AC7
AD7

D1

F1
L6

L7
M6
M7

F17

G18

F19

G20

A24
A26

A27
B26
B27
B28

B25

U10F

VCCRTC
V5REF[1]

V5REF[2]
V5REF_SUS
VCC1_5_B[01]

VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]

VCCSATAPLL
VCC1_5_A[01]

VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]

VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]

VCC1_5_A[11]
VCC1_5_A[12]

VCC1_5_A[13]
VCC1_5_A[14]

VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]

VCC1_5_A[18]
VCC1_5_A[19]

VCCUSBPLL
VCC1_5_A[20]

VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]

VCC1_5_A[25]
VCCLAN1_05[1]

VCCLAN1_05[2]
VCCLAN3_3[1]

VCCLAN3_3[2]
VCCGLANPLL
VCCGLAN1_5[1]

VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]

VCCGLAN3_3

ICH8M REV 1.0

CORE

VCCA3GP ATXARX

VCCP_COREVCCPSUSVCCPUSB

IDE

PCI

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2]
VCCSUS3_3[01]
VCCSUS3_3[02]

VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]

USB CORE

VCCSUS3_3[06]
VCCSUS3_3[07]

VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]

GLAN POWER

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]

V_CPU_IO[1]
V_CPU_IO[2]

VCCSUSHDA

VCCCL3_3[1]
VCCCL3_3[2]

VCCDMIPLL
VCC_DMI[1]

VCC_DMI[2]

VCC3_3[01]
VCC3_3[02]
VCC3_3[03]

VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]

VCCHDA

VCCCL1_05

VCCCL1_5

A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

R29
AE28

AE29
AC23

AC24
AF29
AD2
AC8

AD8
AE8
AF8

AA3
U7
V7
W1
W6
W7
Y7

A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11

AC12
AD11
J6

AF20
AC16
J7
C3
AC18

AC21
AC22
AG20
AH28

P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6

G22
A22
F20

G21

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+VCCP

T28
T29

VCCSUS1_5_ICH_1
VCCSUS1_5_ICH_2

VCCCL1_05_ICH

+3VM

3

Add in 4/21

R2058
100K_0402_5%@

1

1

C1193

C1192

2

2

0.1U_0402_16V4Z

0.1U_0402_16V7K

L17

VCCDMIPLL

+3VS

+3VS

1

C1207

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C1208

2

T17
T18

+3VALW

1

C1222

4.7U_0603_6.3V6K

2

1

C1198

2

1

2

1

2

0.1U_0402_16V4Z

T19

1

C1229

2

1 2

1

C1199

2

10U_0805_6.3V6M

0.01U_0402_16V7K

1

C1201
22U_0805_6.3V4Z

2

+3VS

(SATA)

C1206

0.1U_0402_16V4Z

+3VS

0.1U_0402_16V4Z

1

C1209

C1210

2

+3VALW

1

1

C1217

2

2

1U_0603_10V4Z@

CHB1608U301_0603

+1.25VS

0.1U_0402_16V4Z

C1218

2006/02/13 2006/03/10

ICHGND1

RHU002N06_SOT323 @

R2059
100K_0402_5%@

+1.5VS

ICHGND2

@

RHU002N06_SOT323

+3VS

(DMI)

1

C1205

0.1U_0402_16V4Z

2

+3VALW

1

C1215

0.1U_0402_16V4Z

2

Add in 4/21

R2060
100K_0402_5%@

ICHGND3

RHU002N06_SOT323 @

R2061
100K_0402_5%@

ICHGND4

RHU002N06_SOT323@

Compal Secret Data

Deciphered Date

+3VS

+3VS

1 2

2

G

Q118

+3VS

1 2

2

G

Q119

+VCCP

4.7U_0603_6.3V6M
C1202

1

2

1

C1214

0.1U_0402_16V4Z

2

+3VS

1 2

2

G

Q120

+3VS

1 2

2

G

Q121

Change in 4/24Change in 4/24Change in 4/24Change in 4/24

13

D

S

13

D

S

0.1U_0402_16V4Z

13

D

S

13

D

S

2

CRACK_BGA

CRACK_BGA

Remove in 5/02

0.1U_0402_16V4Z

C1203

1

2

Remove in 5/02

CRACK_BGA

CRACK_BGA

2

C1204

1

2

1

U10E

A23

VSS[001]

A5

VSS[002]

AA2

VSS[003]

AA7

VSS[004]

A25

VSS[005]

AB1

VSS[006]

AB24

VSS[007]

AC11

VSS[008]

AC14

VSS[009]

AC25

VSS[010]

AC26

VSS[011]

AC27

VSS[012]

AD17

VSS[013]

AD20

VSS[014]

AD28

VSS[015]

AD29

VSS[016]

AD3

VSS[017]

AD4

VSS[018]

AD6

VSS[019]

AE1

VSS[020]

AE12

VSS[021]

AE2

VSS[022]

AE22

VSS[023]

AD1

VSS[024]

AE25

VSS[025]

AE5

VSS[026]

AE6

VSS[027]

AE9

VSS[028]

AF14

VSS[029]

AF16

VSS[030]

AF18

VSS[031]

AF3

VSS[032]

AF4

VSS[033]

AG5

VSS[034]

AG6

VSS[035]

AH10

VSS[036]

AH13

VSS[037]

AH16

VSS[038]

AH19

VSS[039]

AH2

VSS[040]

AF28

VSS[041]

AH22

VSS[042]

AH24

VSS[043]

AH26

VSS[044]

AH3

VSS[045]

AH4

VSS[046]

AH8

VSS[047]

AJ5

VSS[048]

B11

VSS[049]

B14

VSS[050]

B17

VSS[051]

B2

VSS[052]

B20

VSS[053]

B22

VSS[054]

B8

VSS[055]

C24

VSS[056]

C26

VSS[057]

C27

VSS[058]

C6

VSS[059]

D12

VSS[060]

D15

VSS[061]

D18

VSS[062]

D2

VSS[063]

D4

VSS[064]

E21

VSS[065]

E24

VSS[066]

E4

VSS[067]

E9

VSS[068]

F15

VSS[069]

E23

VSS[070]

F28

VSS[071]

F29

VSS[072]

F7

VSS[073]

G1

VSS[074]

E2

VSS[075]

G10

VSS[076]

G13

VSS[077]

G19

VSS[078]

G23

VSS[079]

G25

VSS[080]

G26

VSS[081]

G27

VSS[082]

H25

VSS[083]

H28

VSS[084]

H29

VSS[085]

H3

VSS[086]

H6

VSS[087]

J1

VSS[088]

J25

VSS[089]

J26

VSS[090]

J27

VSS[091]

J4

VSS[092]

J5

VSS[093]

K23

VSS[094]

K28

VSS[095]

K29

VSS[096]

K3

VSS[097]

K6

VSS[098]

ICH8M REV 1.0

CRACK_BGA 11,34

Title

Size Document Number Rev

Custom

LA-3331P

Date: Sheet

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

Compal Electronics, Inc.

ICH8(4/4)_POWER&GND

VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]

K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

1

ICHGND1

ICHGND2

ICHGND3

ICHGND4

1 2

1 2

1 2

1 2

22 59Tuesday, May 1 5, 2007

of

R138

0_0402_5%

R139

0_0402_5%

R140

0_0402_5%

R141

0_0402_5%

1.0

5

4

3

2

1

+5VS +3VS

12

47K

R221

1.74K_0402_1%

D D

Modify to add 5/5

C C

Wireless LED

WL/BT_LED35

BT_LED31

BT_LED

WL_LED

LTST-S110TBKT-5A

BLUE LED

BT_LED

WL_LED

R199 100K_0402_5%

R95 100K_0402_5%

Del R2109. 6/14
Add the kill circuit.5/25

1 2

1 2

21

D28

13

D

2

G

S

13

D

2

G

S

10K

1 3

2

Q34
DTA114YKA_SC59

Mini-PCIE Card LED

Q35
2N7002_SOT23

Q36
2N7002_SOT23

WL_LED

WL_LED# 26

AMBER_BATLED#34

GREEN_BATLED#34

AMBER_BATLED#

GREEN_BATLED#

Battery LED

19-22UYSYGC/S530-A2/TR8_ G/Y

2

+3VL

47K

10K

1 3

12

D30

AMBER

Q44
DTA114YKA_SC59

+3VL

47K

10K

2

R233
255_0402_1%

21

+3VL

Q45
DTA114YKA_SC59

1 3
12

R234
255_0402_1%

34

GREEN

R212

0_0402_5%@

1 2

10K

2

HDD LED

+3VS

47K

1 3

12

D27

Q42
DTA114YKA_SC59

+3VS

47K

10K

2

R243
255_0402_1%

21

Q46
DTA114YKA_SC59

1 3
12

R242
255_0402_1%

34

GREENAMBER

13

D

HDD_HALTLED21

R211
100K_0402_5%

2

G

12

IDE_LED#20

Q41
2N7002_SOT23

S

HDD_STP#

IDE_LED#

19-22UYSYGC/S530-A2/TR8_ G/Y

Update design. 5/14
Reserved Space for Kensington 4/27
Removed Kensington 10/18.

Change net name.6/13

STB_R_LED#34,36

47K

10K

Q38
DTA114YKA_SC59

2

GREEN

D29

3

1 3
12

R222
360_0402_5%

21

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

LEDS & Kensington

LA-3331P

1

1.0

of

23 59Tuesday, May 1 5, 2007

STB_LED35

B B

POWER LED

17-21SYGC/S530-E1/TR8_GRN

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

+3VM +3VM_LAN

ACBS support :
Mount Q85, R2072.
Remove Q87, Q88, R1877.

D D

LAN_PHYPC21

ADP_PRES17,34,41,42,43,48

SLP_S3#17,21,29,30,34,36,37,44,45,46,48,49

C C

1/2

2

G

R1878
1M_0402_5%

1 2

R1879
100K_0402_5%

1 2

13

D

Q86

2

BSS138_SOT23

G

S

1 2

Q87

RHU002N06_SOT323@

13

D

Q88

RHU002N06_SOT323 @

S

R2072 0_0402_5%

13

D

S

2

G

Del R1887 , R1888 per Intel recommend. 5/14

R1881

1.4K_0402_1%

LANLINK_STATUS#
LAN_ACT#

2

2

1

1

C1582

C1581

B B

680P_0402_50V7K

680P_0402_50V7K

Modify design same as Chimay 5/5

1 2

Reserved for EMI request. 9/12
Mount at 11/08.

Chimay leave this pin as NC. 5/5
Removed R1981

A A

EMI request to add for 150MHz/200MHz
issue close to R1894.1/4

5

GLAN_CLK20

LANLINK_STATUS#21,25,36

LAN_MDI0P25

LAN_MDI0N25

LAN_MDI1P25

LAN_MDI1N25

LAN_MDI2P25

LAN_MDI2N25

LAN_MDI3P25

LAN_MDI3N25

C1589

2

1

2

C1416

1

LAN_RST20
LAN_TXD020

LAN_TXD120
LAN_TXD220

LAN_RXD020
LAN_RXD120
LAN_RXD220

GLAN_RXP21
GLAN_RXN21

GLAN_TXP21
GLAN_TXN21

+3VM_LAN

470P_0402_50V7K

1000P_0402_50V7K

LAN_ACT#25,36

C1590

2

1

4

R1877
0_1206_5%@

1 2

S

G

2

820P_0402_25V7K

4

D

13

Q85
SI2301BDS_SOT23

Close to U25

R1880
33_0402_5%

GLAN_RXP_C

1 2

GLAN_RXN_C

1 2

LAN_KBIAS_P
LAN_KBIAS_N

LANLINK_STATUS#
LAN_ACT#

IEEE_TEST_P
IEEE_TEST_N

12

1 2

R1892
100_0402_5%

GLANCLK

1 2

C1429

0.1U_0402_16V7K

C1430 0.1U_0402_16V7K

1 2

R1886 0_0402_5%@

R1890

1.4K_0402_1%

1

C1415
10U_0805_10V4Z

2

E2
E3
D1

F3
F1

D3
D2
C1

H2
J2

J4
H4

G7

H7

A4
B4
A5

B8
B9

D9
D8

F9
F8

H8
H9

A7
B7

J6
J7

E7
E6

B5
A6

C5
B6

3

+3VM_LAN

R2137 0.68_2010_5%

1 2

Follow Design
Guide in 6/11.

Y8

25MHZ_20P_1BG25000CK1A

1 2

2

C1422
27P_0402_50V8J

1

U25

JKCLK-JCLK
JRSTSYNC
JTXD0

JTXD1
JTXD2

JRXD0
JRXD1
JRXD2

GLAN_TXP-NC
GLAN_TXN-NC

GLAN_RXP-NC
GLAN_RXN-NC

KBIAS_P-RBIAS100
KBIAS_N-RBIAS10

LED0-LINK_UP_N
LED1-ACT_LED_N
LED2-SPEED_LED_N

MDI_PLUS[0]-TDP
MDI_MINUS[0]-TDN

MDI_PLUS[1]-RDP
MDI_MINUS[1]-RDN

MDI_PLUS[2]-NC
MDI_MINUS[2]-NC

MDI_PLUS[3]-NC
MDI_MINUS[3]-NC

IEEE_TEST_P-NC
IEEE_TEST_N-NC

RSVD_J6-NC
RSVD_J7-NC

RBIAS_P-NC
RBIAS_N-NC

RSVD_B5-NC
RSVD_A6-ADV10/LAN_DIS_N

RSVD_C5-NC
TEST_EN

RU82566MM B1 Q883 BGA 81P

T69 PAD
T71 PAD

+3VM_LAN

XTAL1
XTAL2

LCI

GLCI

MDI

1 2

R1895

200_0402_5%@

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

NIC startup issue, add
R2195(0ohm).12/21

1 2

R2195 30_0402_1%

2

C1423
27P_0402_50V8J

1

H6

XTAL2-X2H5XTAL1-X1

VSSA[15]-VSSA2

VSSA[03]-VSSR

VDD1P0[03]-VCCA
VDD1P0[02]-VCCT

VDD1P0[01]-VCCR

VCCF1P0-VCC

VCCFC1P0-VCC

VCC3P3[02]-VCCP

VCC3P3[01]-VCC

VCC1P8[04]-NC
VCC1P8[03]-NC
VCC1P8[02]-NC
VCC1P8[01]-NC

VCC1P0-VCCA2

JTAG

V1P0_OUT-NC

THERM_D_P-NC

JTAG_TCK-ISOL_TCKG1JTAG_TDI-ISOL_TIH1JTAG_TDO-TOUTG3JTAG_TMS-ISOL_EXEC

THERM_D_N-NC

G2

1 2

2006/02/13 2006/07/26

VSSA[17]-NC
VSSA[16]-NC

VSSA[14]-VSS

VSSA[13]-NC
VSSA[12]-VSS
VSSA[11]-VSS
VSSA[10]-VSS
VSSA[09]-VSS
VSSA[08]-VSS
VSSA[07]-VSS
VSSA[06]-VSS
VSSA[05]-VSS
VSSA[04]-VSS

VSSA[02]-NC
VSSA[01]-VSS

VSS[04]-VSS
VSS[03]-VSSP

VSS[02]-VSS

VSS[01]-NC

VCC[02]
VCC[01]

CTRL_10-NC

CTRL_18-NC

R1894

200_0402_5%@

2

C1431

1

4.7U_0805_10V4Z

LAN_CTRL_18

XTAL1

XTAL2

J9
J8
J5
J3
J1
G9
G8
G6
F6
E9
D6
C9
C8
C7
C6
A9
A8
F4
E1
C4
A1

F7
E8
D7

E5

H3
F2

B3

G5
F5
D5
C2

G4
E4

D4
B1

C3
B2

A2
A3

+3VM_LAN

T70PAD
T72PAD

Compal Secret Data

Q89
BCP69_SOT223

3

2

1

C1432

C1433

1

2

10N_0603_50V7K

0.1U_0402_16V4Z

EMI request to ad d for 150MHz/200MHz
issue close to U25.1/4

Cause something wrong , add 1V
supply back. 5/14

+V1.0M_LAN_R

1 2

R1883 0_0603_5%

+3.3V_LAN

+1.8VM_LAN

R1889 0_0603_5%

1 2

+V1.0_OUT

LAN_CTRL_18

LAN_THERM_D_P
LAN_THERM_D_N

R2092 10K_0402_5%

1 2

R1893 0_0402_5%@

Deciphered Date

4
2

1

C1587

2

1

R1884
0_0603_5%

1 2

R1885
0_0603_5%

1 2

R2090

0_0603_5%@

1 2

2

2

C1434

1

+3.3V_LAN

470P_0402_50V7K

12

2

0.1U_0402_16V4Z

C1588

2

1

+1.8VM

1

C1435

2

820P_0402_25V7K

+V1.0M_LAN

+3VM_LAN

+1.8VM

+V1.0_OUT

+3VM_LAN

Add in 5/24.

Remove Q90 and C1 436 ~ C1440. 3/28

10U_0805_6.3V6M

Change design 5/01 (Follow Chimay)
Change design . 5 /1 4(Intel check result)

Reserve in 5/16.

C1424

C1564

2

2

1

1

10U_0805_10V4Z

Add in 5/17.(Follow
DG P.430)

Title

Size Document Number Rev

Date: Sheet

1

+V1.0M_LAN_R

C1426

Add in 5/17.(Follow
DG P.430)

C1562

1

2

C1563

1

2

10U_0805_10V4Z

C1418

C1417

2

2

1

1

10U_0805_10V4Z

4.7U_0603_6.3V6K

C1561

1

2

C1419

2

1

0.1U_0402_16V4Z

C1428

2

2

1

1

10U_0805_10V4Z

0.1U_0402_16V4Z

470P_0402_50V7K

+1.8VM

C1421

C1420

2

2

1

1

0.1U_0402_16V4Z

820P_0402_25V7K

470P_0402_50V7K

Removed +V1.0 M_ LA N 5/01 (Follow Chimay)

Cause something

+V1.0M_LAN

C1425

C1427

2

2

1

1

0.1U_0402_16V4Z

470P_0402_50V7K

4.7U_0603_6.3V6K

wrong , add 1V
supply back.
5/14

Compal Electronics, Inc.

Intel 82566 Nineveh

LA-3331P

1

of

24 59Tuesday, May 1 5, 2007

EMI request to change C1421 to 680P

and close to U25. 1/5

1.0

5

LAN_MDI0N

+1.8VM

LAN_MDI0P

TRM_CT

12

C348

0.1U_0402_16V7K

D D

C345

0.1U_0402_16V7K

C346

0.1U_0402_16V7K

C347

0.1U_0402_16V7K

C C

LAN_MDI1N

+1.8VM

LAN_MDI1P
TRM_CT

12

LAN_MDI2N

+1.8VM

LAN_MDI2P
TRM_CT

12

LAN_MDI3N MDO3-

+1.8VM

LAN_MDI3P
TRM_CT

12

T22

12

TD4-

11

TD4+

10

TCT4

9

TD3-

8

TD3+

7

TCT3

6

TD2-

5

TD21+

4

TCT2

3

TD1-

2

TD1+

1

TCT1

24HST1041A-3_24P

SI2 Note : Change to Delta S/N SP050003R10.

1:1

1:1

1:1

1:1

Layout Notice : Place
termination as close as
Intel 82566 as possible

MX4-

MX4+
MCT4

MX3-

MX3+
MCT3

MX2-

MX2+
MCT2

MX1-

MX1+
MCT1

13

14
15
16

17
18
19

20
21
22

23
24

MDO0-

MDO0+
MCT0
MDO1-

MDO1+
MCT1
MDO2-

MDO2+
MCT2

MDO3+
MCT3

4

R323
75_0402_1%

R318
75_0402_1%

R322
75_0402_1%

R321
75_0402_1%

12

12

12

12

C301
1000P_1808_3KV7K

1 2

C302
1000P_1808_3KV7K

1 2

3

LAN ENERGY DET

LAN_MDI0P

C1442 0.01U_0402_16V7K

LAN_MDI1P

C1443 0.01U_0402_16V7K

12

12

CAP closed to LAN_MDIO bus

R1899
10K_0402_5%

1 2

1 2

R1901
10K_0402_5%

12

R1902

Intel design c hange WW44.11/6
Design chnage fr om HP pe r In te l' s request from 1.4K to 1.87K.12/18

100K_0402_5%

1

C1444

2

2

Change power from +1.8VM

+3VM

to +3VM. 6/5

12

R1896

12

10P_0402_50V8J

100K_0402_5%

ED_ACT
ED_VREF

R1903

1.87K_0402_1%

12

R1897

200K_0402_5%

@

1

IN+

3

IN-

12

R1898

5

2

1.5K_0402_5%

P

4

O

G

U39
LMV331IDCKRG4_SC70-5~D

1 2

R1900 0_0402_5%

1

C1441

0.1U_0402_16V7K

2

1

ENERGY_DET 20

C363 0.1U_0402_16V4Z

1 2

C362 0.1U_0402_16V4Z

1 2

C361 0.1U_0402_16V4Z

1 2

C360 0.1U_0402_16V4Z

1 2

B B

3/28

R2208 300_0402_5%

LAN_ACT#24,36

LANLINK_STATUS#21,24,36

A A

1 2

R2209 300_0402_5%

1 2

R389 49.9_0402_1%

1 2

R388 49.9_0402_1%

1 2

R387 49.9_0402_1%

1 2

R386 49.9_0402_1%
R385 49.9_0402_1%
R384 49.9_0402_1%
R383 49.9_0402_1%
R382 49.9_0402_1%

V_3P3_LAN_LED +3VM_LAN V_3P3_LAN_LED

1 2

1 2

1 2

1 2

1 2

L24 FBMA-10-100505-151T_0402

1 2

R13 FBMA-10-100505-151T_0402

1 2

R12 FBMA-10-100505-151T_0402

1 2

MDO3+36
MDO3-36
MDO2+36
MDO2-36
MDO1+36
MDO1-36
MDO0+36
MDO0-36

CABLE_DETECT21

LAN_MDI0N 24
LAN_MDI0P 24
LAN_MDI1N 24
LAN_MDI1P 24
LAN_MDI2N 24
LAN_MDI2P 24
LAN_MDI3N 24
LAN_MDI3P 24

To RJ-45 CONN.

L

Keep JP4.1/2/3 at least 10mils

V_3P3_LAN_LED_R
LAN_ACT#_R

C10

LANLINK_STATUS#_R

1

2

MDO3+
MDO3­MDO2+
MDO2­MDO1+
MDO1­MDO0+
MDO0-

0.1U_0402_16V4Z

EMI request :

1. Add L24 and C1591.

2. Change R12~R13 to FBMA-10-100505-151T_0402.

3. Add R2208, R 22 09 to ha ve current limit for E-star. 3/28

JP4

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

ACES_87212-1400conn@

V_3P3_LAN_LED_R

1

C1591
680P_0402_50V7K

2

R380
100K_0402_5%

PREP#21,29,36

D

S

13

Q64

2

FDN338P_SOT23

13

D

Q63
2N7002_SOT23

S

20 mil20 mil

12

G

2

G

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Magnetic & RJ45/RJ11

LA-3331P

1

1.0

of

25 59Tuesday, May 1 5, 2007

A

B

C

Modify in 9/6.

D

+3VS_WLAN

E

+1.5VS+3VS

+3VALW

C493

1

0.01U_0402_16V7K

2

C492

1

0.1U_0402_16V4Z

2

C489

1

4.7U_0805_10V4Z

2

C494

1

2

C491

0.1U_0402_16V4Z

1

2

Change U6 to same as Chimay. 7/27

C167

0.01U_0402_16V7K

1

0.01U_0402_16V7K

2

C214

1

0.01U_0402_16V7K

2

C217

1

0.1U_0402_16V4Z

2

C171

1

4.7U_0805_10V4Z

2

ACCELEROMETER

1 1

ACCEL_INT19

ICH_SM_DA4,17,21

+3VS_ACL_IO

ICH_SM_CLK4,17,21

+3VS_ACL

2 2

+3VS +3VS_ACL

12

R48 10K_0402_5%

12

R50
0_0402_5%

L

+3VS_ACL_IO

D11
CH751H-40_SC76

2 1

U6

1

INT/RDY

2

SDD

3

SDA/SDI/SPC

4

VDD_IO

5

SCL/SPC

6

CS

7

NC

8

CK

LIS3LV02DL-TR _LGA16

Must be pl aced in the center of the system.

R55
0_0603_5%

1 2

GND

RES

GND

VDD

RES

VDD

RES

GND

16

R43

0_0402_5%

15

1 2

14

13

12

11

R44

0_0402_5%

10

1 2

9

R45
0_0402_5%

1 2

+3VS_ACL_IO

+3VS_ACL

1

C121

2

+3VS_ACL

1

C135

2

0.1U_0402_16V4Z

Mini-Express Card

JP30

PCIE_WAKE#21

CH_DATA31

CH_CLK31

CLKREQG#15

CLK_PCIE_MCARD#15

CLK_PCIE_MCARD15

R546 0_0402_5%

PCIE_RXN221
PCIE_RXP221

PCIE_TXN221

PCIE_TXP221

1 2

R547 0_0402_5%

1 2

Add in 7/26.

CL_CLK121
CL_DATA121
CL_RST#121

10U_0805_6.3V6M

R1982 0_0402_5%
R1983 0_0402_5%
R1984 0_0402_5%

Del net STB_R_LED#(pin47) &
NUM_LED#(pin49).6/19

12
12
12

T90 PAD
T91 PAD

PCIE_C_RXN2
PCIE_C_RXP2

+3VS_WLAN

T92 PAD

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

FOX_AS0B226-S40N-7F

conn@

H29

HOLE_MC

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

GND2

H28

HOLE_MC

1

1

T85PAD
T86PAD
T87PAD
T88PAD
T89PAD

XMIT_D_OFF#
PLT_RST#

WW_LED#
WL_LED#
WP_LED#

WW_LED#

R497 0_0402_5%@

WP_LED#

R500 0_0402_5%@

Add to prevent le akage issue in 8/24.

CH751H-40_SC76

Chnage Design , Del R92 , R104 , R112 , Q17. 5/16

Del +3VL from JP30 pin 45. 6/15
Del net of JP30 pin 8, 10, 12, 14, 16, 17, 19, 51. 6/15

Del resistors & bypass all net as shown in below picture. 5/24

J12

2 1

PAD-SHORT 2x2m

J11

2 1

PAD-No SHORT 2x2m

ICH_SMB_CLK 21
ICH_SMB_DATA 21

WL_LED# 23

1 2
1 2

2 1

D78

PLT_RST# 7,19,20,21,32,33

+1.5VS

+3VM

+3VALW

WL_LED#

XMIT_OFF#XMIT_D_OFF#

R2158
0_1206_5%

1 2

XMIT_OFF# 21

+3VS+3VS_WLAN

Add in 4/27.

3 3

Rerserve from PV build. 3/23

CLKREQF#15

CLK_PCIE_NAND#15

CLK_PCIE_NAND15

PCIE_RXN421
PCIE_RXP421

PCIE_TXN421
PCIE_TXP421

Add in 5/16. (Close to JP59)

+3VS +3VS +1.5VS

4 4

1

1

C1555

C1554

C1553

2

2

0.01U_0402_16V7K

0.01U_0402_16V7K

@

@

NAND mini Card(Robson support)

JP59

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

R2064 0_0402_5%@

1 2

R2065 0_0402_5%@

1 2

1

2

0.01U_0402_16V7K

@

A

1

1

C1556

2

0.1U_0402_16V4Z

@

1

C1557

C1558

2

2

4.7U_0805_10V4Z

@

@

PCIE_C_RXN4
PCIE_C_RXP4

1

1

C1559

C1560

2

2

0.1U_0402_16V4Z

0.01U_0402_16V7K

4.7U_0805_10V4Z

@

@

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

FOX_AS0B226-S40N-7F

conn@

+3VS +1.5VS

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

GND2

B

PLT_RST#

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Mini-Card/Mini-NAND/Accelerometer

LA-3331P

E

of

26 59Tuesday, May 1 5, 2007

1.0

5

Change in 4/19

+SC_PWR

D D

PCI_AD[0..31]19

PCI_CBE#[0..3]19

C C

B B

X2

1

E/D

2

GND

30.0MHz/100ppm

Layout :

Please add GND shield 4/27

12

1

2

PCI_RST#19

PWR_GD17,21,34,37,38,46,48

+3VS

4

VCC

XOUT

TCO-787RH3@

1 2

0.1U_0402_16V4Z@

3

CLK_PCI_PCM

R2023

10_0402_5%@

C1538

15P_0402_50V8J@

1 2

R2029
0_0402_5%

R2030 0_0402_5%@

PCI_PIRQC#19
PCI_PIRQD#19
PCI_PIRQE#19
PCI_PIRQG#19

C1540

SIRQ21,32,33,34

PCM_SPK29

Not Use EEPROM
R2041,R2042,R2043 Install

PCI_AD[0..31]
PCI_CBE#[0..3]

PCI_FRAME#19

PCI_TRDY#19

R2026
100_0402_5%

1 2

PCI_IRDY#19

PCI_STOP#19

PCI_DEVSEL#19

PCI_PERR#19

PCI_SERR#19,34
PCI_REQ2#19
PCI_GNT2#19

CLK_PCI_PCM15

12

PM_CLKRUN#21,32,33,34

R2033 0_0402_5%
R2034 0_0402_5%
R2035 0_0402_5%
R2036 0_0402_5%

SM_CD#28

R2037 0_0402_5%

PCM_SPK SPK

PCI_PAR19

1 2
1 2
1 2
1 2

1 2

C1586 1U_0402_6.3V4Z

12

R2038
10K_0402_5%

R2083,U51,C1541 Un-install

Use EEPROM
R2083,R2042,R2043,U51,C1541 Install
R2041 Un-install

A A

+3VS

R2194 100K_0402_5%

1 2

R2079 10K_0402_5%

1 2

R2076 10K_0402_5%

1 2
1 2
1 2
1 2
1 2
1 2
1 2

R2032 10K_0402_5%
R2040 10K_0402_5%
R2041 22K_0402_5%
R2042 10K_0402_5%
R2043 10K_0402_5%
R2088 100K_0402_5%

SPK
SMELWP#
SM_CD#
PCI_PME853#
HWSPND#
PCM_SPK
1394_CLK
1394_DAT
GRST#

5

SMELWP# 28

4

1

1

2

2

C1515

C1514

0.1U_0402_16V4Z

2.2U_0805_16V4Z

A4

J19

K19

F5

VCC_MD3V

G5

VCC_SC

GND10

M19

L15

VCC_3V2

VCC_3V3

VCC_3V1

R5C853

GND6

GND7

GND8

GND9

T10

V10

R10

W10

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

PCI_IDSELPCI_AD22

CLK_PCI_PCM
PRST#
GRST#

PCI_PME853#

Add by Richo 5/4

1394_DAT
1394_CLK
SM_CD#
SMELWP#

HWSPND#

1 2

U16B

M2

AD31

M1

AD30

N5

AD29

N4

AD28

N2

AD27

N1

AD26

P5

AD25

P4

AD24

R4

AD23

R2

AD22

R1

AD21

T2

AD20

T1

AD19

U2

AD18

U1

AD17

V1

AD16

T7

AD15

V7

AD14

W7

AD13

R8

AD12

T8

AD11

V8

AD10

W8

AD9

R9

AD8

V9

AD7

W9

AD6

T11

AD5

V11

AD4

W11

AD3

T12

AD2

V12

AD1

W12

AD0

P2

C/BE3#

W2

C/BE2#

W6

C/BE1#

T9

C/BE0#

V6

PAR

V3

FRAME#

W4

TRDY#

V4

IRDY#

V5

STOP#

T5

DEVSEL#

P1

IDSEL

W5

PERR#

T6

SERR#

M4

REQ#

M5

GNT#

K1

PCICLK

L4

PCIRST#

G2

GBRST#

L5

CLKRUN#

G4

RI_OUT#/PME#

J2

INTA#

K4

INTB#

K2

INTC#

L2

INTD#

G1

UDIO5

H5

UDIO4

H4

UDIO3

H2

UDIO2

H1

UDIO1

J4

UDIO0/SRIRQ#

F2

HWSPND#

F1

SPKROUT#

R5C853

Pop noise:

Add R2194(100Kohm) and C1586(1uF).
Change R2038 to 10Kohm and R2041 to 22Kohm.

1394_CLK
1394_DAT

+3VS

4

C1541

1 2

0.1U_0402_16V4Z@

U51

8

VCC

7

WP

6

SCL

5

SDA

AT24C02N-10SU-2.7_SO8@

GND

1

A0

2

A1

3

A2

4

E14

R6

E13

VCC_RIN2

VCC_ROUT1L1VCC_ROUT2

GND1J1GND2J5GND3K5GND4E9GND5

R12

VCC_RIN1

VCC_ROUT

W3

R11

VCC_PCI1

VCC_PCI2

VCC_PCI3

AGND5

AGND6

A15

B15

D14

3

AVCC_PHY3V1
AVCC_PHY3V2
AVCC_PHY3V3
AVCC_PHY3V4

REXT
VREF

TPBIAS0

TPBN0
TPBP0

TPAN0
TPAP0

TEST1
TEST2

AGND1A9AGND2B9AGND3D9AGND4

CPS

FIL0

NC1
NC2
NC3
NC4
NC5
NC6

1

1

2

2

C1511

C1510

0.01U_0402_16V7K

1

1

2

2

C1516

C1517

0.1U_0402_16V4Z

E10
E11
A17
B17

D11

A16

XI

B16

XO

A14
B14
D13

D12

A13
B13

A12
B12

E12
D10
A11
B11
A10
B10

F4
R7

1

1

2

2

C1513

C1512

0.01U_0402_16V7K

C1518

0.1U_0402_16V4Z

Layout : With GND shield. 4/27

R2022 10K_0402_1%
C1535 0.01U_0402_16V7K

0.47U_0603_10V7K

0.47U_0603_10V7K

1

1

1

2

2

2

C1519

0.1U_0402_16V4Z

AVCC_PHY

XIN

12

XOUT

1 2

XTPBIAS0

XTPB0­XTPB0+

XTPA0­XTPA0+

Place those components as
close to R5C853.

C1521

C1520

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Close to Pin
A17 & E10.

1

2

C1528

C1527

1000P_0402_50V7K

C1533 10P_0402_50V8K

1 2

X1

24.576MHz_16P_3XG-24576-43E1
C1534 10P_0402_50V8K

1 2

12

1

2

1

2

Layout :
With GND shield.

C1522

0.1U_0402_16V4Z

C1529

1000P_0402_50V7K

1

1

2

2

C1523

0.1U_0402_16V4Z

1

1

2

2

C1530

0.1U_0402_16V4Z

56.2_0603_1%

270P_0603_50V8J

2

1

2

C1524

0.1U_0402_16V4Z

1

2

C1531

0.1U_0402_16V4Z

12

R2024

R2027

C1539

12/21.

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/06 2007/02/06

Compal Secret Data

Deciphered Date

2

1

1

Close to Pin F5, J19 & K19. Close to Pin W3, R11, R12.

2

C1525

10U_0805_10V4Z

0.1U_0402_16V4Z

L20

1 2

FBML10160808121LMT_0603

1

2

C1532

10U_0805_10V4Z

0.1U_0402_16V4Z

C1536

0.33U_0603_16V4Z

12

R2025

56.2_0603_1%

12

1

2

1

2

56.2_0603_1%

12

R2028

56.2_0603_1%

12

R2031

5.1K_0603_1%

Size Document Number Rev

Custom

Date: Sheet

Title

1

2

LA-3331P

1

2

C1526

10U_0805_10V4Z

+3VS

C1537

0.01U_0402_16V7K

Compal Electronics, Inc.

RICOH R5C853 (1/2)

1

+3VS

JP17

1

XTPB0-

2

XTPB0+

3

XTPA0-

4

XTPA0+

5

GND

6

GND

7

GND

8

GND

AMP_440168-2conn@

1.0

of

27 59Tuesday, May 1 5, 2007

5

Change in 4/19

U16A

J18

CADR25/CAD19

J15

CADR24/CAD17

K16

CADR23/CFRAME#

L16

CADR22/CTRDY#

L18

CADR21/CDEVSEL#

M16

CADR20/CSTOP#

N19

CADR19

N16

CADR18

P16

CADR17/CAD16

L19

CADR16/CCLK

K15

CADR15/CIRDY#

N18

CADR14/CPERR#

N15

CADR13/CPAR

K18

CADR12/CCBE2#

R18

CADR11/CAD12

U19

CADR10/CAD9

R19

CADR9/CAD14

P15

CADR8/CCBE1#

J16

CADR7/CAD18

H15

CADR6_CAD20

H18

CADR5/CAD21

G15

CADR4/CAD22

G18

CADR3/CAD23

F15

CADR2/CAD24

F18

CADR1/CAD25

E16

CADR0/CAD26

U18

CDATA15/CAD8

W18

CDATA14

V17

CDATA13/CAD6

V16

CDATA12/CAD4

V15

CDATA11/CAD2

B19

CDATA10/CAD31

C18

CDATA9/CAD30

D18

CDATA8/CAD28

W17

CDATA7/CAD7

W16

CDATA6/CAD5

W15

CDATA5/CAD3

T15

CDATA4/CAD1

R14

CDATA3/CAD0

C19

CDATA2

D19

CDATA1/CAD29

E19

CDATA0/CAD27

T19

OE#/CAD11

M15

WE#/CGNT#

T18

CE2#/CAD10

V19

CE1#/CCBE0#

F16

REG#/CCBE3#

H19

RESET/CRST#

G16

WAIT#/CSERR#

A18

WP/CCLKRUN#

M18

RDY/CINT#

F19

BVD2/CAUDIO

E18

BVD1/CSTSCHG

H16

VS2#/CVS2

R16

VS1#/CVS1

D15

CD2#/CCD2#

T14

CD1#/CCD1#

G19

INPACK#/CREQ#

P18

IORD#/CAD13

P19

IOWR#/CAD15

V14

USBDP

W14

USBDM

R5C853

U50

1

GND

2
3
4

OUT

IN

OUT
OUT

IN

OC#

EN#

TPS2061IDGN_MSOP8~N

+S1_VPP

1

C1507
10U_0805_10V4Z

2

R5C853

MEDIA_3VCC +3VS

8
7
6
5

1 2

R2019 10K_0402_5%

1

C1508

0.1U_0402_16V4Z

2

Reserved for ETD test. 8/31

+3VS

1 2

13

D

S

S1_A25
S1_A24
S1_A23
S1_A22
S1_A21
S1_A20
S1_A19
S1_A18
S1_A17
S1_A16S1_A16_C
S1_A15
S1_A14
S1_A13
S1_A12
S1_A11
S1_A10
S1_A9
S1_A8
S1_A7
S1_A6
S1_A5
S1_A4
S1_A3
S1_A2
S1_A1
S1_A0

S1_D15
S1_D14
S1_D13
S1_D12
S1_D11
S1_D10
S1_D9
S1_D8
S1_D7
S1_D6
S1_D5
S1_D4
S1_D3
S1_D2
S1_D1
S1_D0

S1_OE#
S1_WE#
S1_CE2#
S1_CE1#
S1_REG#
S1_RST
S1_WAIT#
S1_WP
S1_RDY#
S1_BVD2
S1_BVD1
S1_VS2
S1_VS1
S1_CD2#
S1_CD1#
S1_INPACK#

S1_IORD#
S1_IOWR#

+3VS

Q112
2N7002_SOT23

1

C1506

0.1U_0402_16V4Z

2

5

D D

R1997
33_0402_5%

1 2

Close to Pin L19
within 100mils.

C C

B B

R2016
100K_0402_5%

SD_PWRON

2

R2021
100K_0402_5%

A A

G

1 2

Near to JP23

+S1_VCC

1

C1505
10U_0805_10V4Z

2

R2047
100K_0402_5%

S1_CD1#

S1_CD2#

S1_RST

4

VPPEN1

VPPEN0
VCC3EN#
VCC5EN#

SCCD#

SCIO

SCSENSE

SCCLK

SCRST
SCVCC5EN#
SCVCC3EN#

MDIO19
MDIO18

MDIO17
MDIO16
MDIO15
MDIO14
MDIO13
MDIO12
MDIO11
MDIO10

MDIO09
MDIO08
MDIO07
MDIO06
MDIO05
MDIO04
MDIO03
MDIO02
MDIO01
MDIO00

MEDIA_3VCC

0.1U_0402_16V4Z

1 2

1 2

C1503 270P_0402_50V7K

1 2

C1504 270P_0402_50V7K

1 2

C1509 0.01U_0402_16V7K@

4

Add per
Richo's
recommend ,
cause enable
XD. 5/5

VPPEN1

W13

VPPEN0

V13

VCC3EN#

T13

VCC5EN#

R13

SC_CD#

C1

SC_DATA

D1
E1

SC_CLK_R

C2

SC_RST

D2

SCVCC5EN#

E2

SCVCC3EN#

E4

SDCMD_SMALE

E8

SMCLE

D8

SDD3_SMD7

B8

SDD2_SMD6

A8

SDD1_SMD5

E7

SDD0_SMD4

D7

MSD3_SDD3_SMD3

B7

MSD2_SDD2_SMD2

A7

MSD1_SDD1_SMD1

E6

MSD0_SDD0_SMD0

D6

CLK_R

B6
A6
D5
B5
A5
B4
B3
A3
A2
B1

1 2

R2004 10_0402_5%

MSBS_SDCMD_SMWE#

R2205 0_0402_5%

1 2

SMELWP#
SD_PWRON
SDWP#_SMCE#_SMRB#
SM_CE#

SD_CD#

SM_CD#27

+3VS

+SC_PWR

12

12

R1993100K_0402_5%

R199410K_0402_5%

R1998 10K_0402_5%

R1999 10_0402_5%

12

1 2

T94 PA D

SM_CD#

SC_CLK

1

C1498

0.01U_0402_16V7K

2

Layout :
With GND shield.

MSCLK_SDCLK_SMELWP#

SMELWP# 27

Removd R2046 , D70 as
Richo recommend.5/9

D67 1SS355_SOD323
D69 1SS355_SOD323

1 2

Modify design after check with Richo 5/5

JP24

34

SM-D0 / XD-D0

33

SM-D1 / XD-D1

32

SM-D2 / XD-D2

31

SM-D3 / XD-D3

21

SM-D4 / XD-D4

22

SM-D5 / XD-D5

23

SM-D6 / XD-D6

24

SM-D7 / XD-D7

35

SM_WP-IN / XD_WP-IN

43

SM-WP-SW

36

#SM_-WE / XD_-WE

37

#SM-ALE / XD-ALE

25

SM-LVD

3

SM-CD-SW

29

SM_-VCC / XD_-VCC

26

#SM_R/-B / XD_R/-B

27

#SM_-RE / XD_-RE

28

#SM_-CE / XD_-CE

30

#SM_-CD

2

SM-CD-COM

38

SM-CLE / XD-CLE

45

GND

46

GND

conn@

Connect JP24 dummy net to
GND per EMI request. 6/16

TAITW_R007-010-N3

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R2020

1 2

33_0402_5%@

C1502

MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
SDD0_SMD4
SDD1_SMD5
SDD2_SMD6
SDD3_SMD7

SMELWP#
SMWP

MSBS_SDCMD_SMWE#

SDCMD_SMALE MSD0_SDD0_SMD0

SM_CD

SDWP#_SMCE#_SMRB#
MSCLK_SDCLK_SMELWP#

1

SM_CE#
SM_CD#

2

SMCLE

3

+3VS

1

VCC3EN#
VCC5EN#

2

C1494

+5VS

1

2

C1495

100K_0402_5%

VPPEN0
VPPEN1

SCVCC3EN#
SCVCC5EN#

+SC_PWR

Layout :
With GND shield.

1

C1499
6P_0402_50V8K

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Add T94 & R2205 for Pre-PV test. 2/14

12
12

D721SS355_SOD323

5 IN 1 CONN

3

XD_CD#

XD_CD#MSINS_CD#

SD_DAT3

11

SD-DAT3

12

SD-DAT2

6

SD-DAT1

7

SD-DAT0

5

SD-WP-SW

10

SD-CMD

8

SD_CLK

9

SD-VCC

4

N/C

42

SD-CD-SW

41

SD-CD-COM

15

MS-DATA0

14

MS-DATA1

16

MS-DATA2

18

MS-DATA3

19

MS-SCLK

17

MS-INS

13

MS-BS

20

MS-VCC

40

XD-VCC

39

XD-CD

1

GND

44

GND

2006/02/06 2007/02/06

R2012 0_0402_5%

SD_DAT2
SD_DAT1
SD_DAT0
SDWP#_SMCE#_SMRB#

R2017 0_0402_5%
R2018 0_0402_5%

MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
MSCLK_SDCLK_SMELWP#
MSINS_CD#
MSBS_SDCMD_SMWE#

1 2

R2013 0_0402_5%

1 2

R2014 0_0402_5%

1 2

R2015 0_0402_5%

1 2

1 2
1 2

SD_CD#

XD_CD#

C1543

0.1U_0402_16V4Z

Compal Secret Data

Deciphered Date

R2000

12

1

2

2

U19

10

AVCC3IN

6

AVCC5IN

2

AVCC3_EN

1

AVCC5_EN

4

AEN0

3

AEN1

11

BVCC3IN

15

BVCC5IN

19

BVCC3_EN

20

BVCC5_EN

17

BEN0

18

BEN1

12

R5534V-E2-FB_SSOP20~N
R2001
100K_0402_5%

+S1_VPP

+S1_VCC

MSD3_SDD3_SMD3
MSD2_SDD2_SMD2
MSD1_SDD1_SMD1
MSD0_SDD0_SMD0

MSBS_SDCMD_SMWE#
MSCLK_SDCLK_SMELWP#

R2039

1 2

1

2

1

C1542

0.1U_0402_16V4Z

2

150K_0402_1%

MEDIA_3VCC

C1544

2.2U_0603_6.3V6K

MEDIA_3VCC

Close to JP24 Pin40

2

1

+S1_VCC

7

AVCCOUT

8

AVCCOUT

Slot A
Power
Supply

Slot B
Power
Supply

9

AVPPOUT

TST

BVCCOUT
BVCCOUT

BVPPOUT

GND

S1_CD2#
S1_WP
S1_D10
S1_D2
S1_D9
S1_D1

S1_D8
S1_D0
S1_BVD1
S1_A0
S1_BVD2
S1_A1
S1_REG#

S1_A2
S1_INPACK#
S1_A3
S1_WAIT#
S1_A4
S1_RST
S1_A5

S1_VS2
S1_A6
S1_A25
S1_A7
S1_A24
S1_A12
S1_A23

S1_A15
S1_A22 SC_CLK
S1_A16_C

S1_RDY#
S1_A21
S1_WE#

S1_A20
S1_A14
S1_A19
S1_A13
S1_A18
S1_A8
S1_A17

S1_A9
S1_IOWR#
S1_A11
S1_IORD#
S1_OE#
S1_VS1
S1_A10

S1_CE2#
S1_CE1#
S1_D15
S1_D7
S1_D14
S1_D6
S1_D13

S1_D5
S1_D12
S1_D4
S1_D11
S1_D3
S1_CD1#

Title

Size Document Number Rev

Custom

Date: Sheet

+S1_VPP

5

+5VS

+SC_PWR

13
14

12

16

JP23

1

GND

2

GND

3

CD2#

4

WP

5

D10

6

D2

7

D9

8

D1

9

GND

10

D8

11

D0

12

STSCHG#

13

A0

14

SPKR#

15

A1

16

REG#

17

GND

18

A2

19

INPACK#

20

A3

21

WAIT#

22

A4

23

RESET

24

A5

25

GND

26

VS2#

27

A6

28

A25

29

A7

30

A24

31

A12

32

A23

33

GND

34

A15

35

A22

36

A16

37

A52/A18/VCCP

38

NONE

39

A51/A17/VCC

40

READY

41

A21

42

WE#

43

GND

44

A20

45

A14

46

A19

47

A13

48

A18

49

A8

50

A17

51

GND

52

A9

53

IOWR#

54

A11

55

IORD#

56

OE#

57

VS1#

58

A10

59

GND

60

CE2#

61

CE1#

62

D15

63

D7

64

D14

65

D6

66

D13

67

GND

68

D5

69

D12

70

D4

71

D11

72

D3

73

CD1#

74

GND

75

GND

154

GND

156

GND

158

GND

Connect JP23 dummy net to
GND per EMI request. 6/16

SCVCC3EN#
SCVCC5EN#

NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE

GND
NONE
NONE
NONE
NONE
NONE
NONE
NONE

GND
NONE
NONE
NONE
NONE

I/O
NONE
NONE

GND

VCC
NONE
NONE
NONE
NONE

RST

DET2

GND

VPP

CLK
NONE

GND
NONE
NONE

DET1

RFU4

NONE

GND

RFU8
NONE
NONE
NONE
NONE
NONE
NONE

GND
NONE
NONE
NONE
NONE
NONE
NONE
NONE

GND
NONE
NONE
NONE
NONE
NONE
NONE
NONE

GND
NONE
NONE
NONE
NONE
NONE
NONE

GND

GND

GND

GND

GND

TYCO_1123088-1_LTconn@

Compal Electronics, Inc.

RICOH R5C853 (2/2)

LA-3331P

1

+3VS

12

12

R1996

R1995

100K_0402_5%

100K_0402_5%

+SC_PWR

1

1

C1496

C1497

2

2

10U_0805_10V4Z

0.1U_0402_16V4Z

76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96

SC_DATA

97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
153
155
157

+SC_PWR

SC_RST

SC_CD#

1.0

of

28 59Tuesday, May 1 5, 2007

A

VDDA_CODEC

12

R287
10K_0402_5%

PCM_SPK27

1 1

R288
10K_0402_5%

SB_SPKR21

13

D

2

G

S

VDDA_CODEC

12

13

D

2

G

S

C276

0.1U_0402_16V4Z

1 2

Q48
2N7002_SOT23

C279

0.1U_0402_16V4Z

1 2

Q51
2N7002_SOT23

B

R277
150K_0402_1%

1 2

1 2

R279
150K_0402_1%

1 2

C264 0.1U_0402_16V4Z

R28310K_0402_5%12C2690.01U_0402_16V7K

2

1

C

MONO_IN_HD

D

+5VAMP

1

+

C198
22U_B_10V

2

2

C193
1U_0603_10V4Z

1

E

SLP_S3#17,21,24,30,34,36,37,44,45,46,48,49

2

C194
100P_0402_50V8J

1

R198 0_1206_5%

1 2

Place R198 between DGND
& AGND & close to U21

F

U17
MIC5205YM5_SOT23-5

1

IN

OUT

3

EN

ADJ

2

GND

C205

0.01U_0402_16V7K

G

VDDA_CODEC

12

R213

2

1

49.9K_0402_1%

12

R206
143K_0402_1%

5
4

C21322U_B_10V

1

+

1

C216

2

0.1U_0402_16V4Z

2

H

VDDA_CODEC +3VS

2 2

C283 1U_0603_10V4Z

1 2

C270 1U_0603_10V4Z

INT_MIC30

DLINE_IN_L36

DLINE_IN_R36

3 3

R290 6.04K_0402_1%
R289 2K_0402_5%
R291 6.04K_0402_1%
R292 2K_0402_5%

Change them in 3/19 to improve
audio quality per HP request.

1 2
1 2

12
12

Place close to U14

12

C545 0.1U_0805_25V7M

12

C259 0.1U_0805_25V7M

12

4 4

C206 0.1U_0805_25V7M

12

C284 0.1U_0805_25V7M

R219 0_1206_5%@

12

Add for HDMI
to MXM Conn
4/27

DLINE_IN_R_L
DLINE_IN_R_R

VDDA_CODEC

R297 2.67K_0402_1%

R236 2.2K_0402_5%

AC97_RST#_CODEC20

AC97_SYNC_CODEC20

AC97_SDOUT_CODEC20

1 2

C274 1U_0603_10V4Z

1 2

C275 1U_0603_10V4Z

1 2

MIC130
MIC230

1 2

1 2

EAPD30,34

SPDIF_OUT17

C265

1

2

0.1U_0402_16V4Z

1 2

C272 1U_0603_10V4Z

1 2

C273 1U_0603_10V4Z

R284 0_0402_5%@

L11

1 2

FBM-L10-160808-301-T_0603

R2206

4.7K_0402_5%

1 2

Add R2206 per HP request.
2/14

GNDAGND

A

B

C

C224

C225

1

1

2

2

0.1U_0402_16V4Z

T48PAD
T44PAD

INT_MICL_C
INT_MICR_C
DLINE_IN_RC_L
DLINE_IN_RC_R

T47PAD
T45PAD
T46PAD

MIC1_C
MIC2_C
SENSE_A

SENSE_B

12

C222

C266

1

2

2

1

38

U21

10U_1206_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

AVDD125AVDD2

14

AUX_L

15

AUX_R

16

MIC3

17

MIC4

23

LINE_IN_L

24

LINE_IN_R

18

CD_L

20

CD_R

19

CD_GND

21

MIC1

22

MIC2

13

SENSEA

34

SENSEB

11

RESET#

10

SYNC

5

SDATA_OUT

47

EAPD

48

SPDIFO

4

DVSS1

7

DVSS2

AD1981HDJSTZ-REEL_LQFP48

Security Classification

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

DVDD11DVDD2

LINE_OUT_L

LINE_OUT_R

MONO_OUT
HP_LOUT_L
HP_LOUT_R

BIT_CLK

SDATA_IN

GPIO_0
GPIO_1
GPIO_2
GPIO_3

VREF

MIC_BIAS_B

MIC_BIAS_C

MIC_BIAS_F

MIC_BIAS_D

PCBEEP

AVSS1
AVSS2

Issued Date

+3VS_CODEC

9

35
36
37
39
41

C247 10P_0402_25V8K

6
8

AC97_SDIN0_CODEC

43

PIN44

44
2
3

AUD_REF

27

CODEC_REF

28

AFILT1

29

AFILT2

30

AFILT4

32

MONO_IN_HD

12

AFILT3

31

N/C

PIN33

33

N/C

PIN40

40

N/C

45

NC

46

NC

26

PIN42

42

C239

C251

1

1

2

2

0.1U_0402_16V4Z

1 2

R248 10_0402_5%@

R226 4.7K_0402_5%@
R224 4.7K_0402_5%@

1 2

R218 10K_0402_5%
R241 4.7K_0402_5%@

1 2

PAD

T36
T37 PA D

2005/03/10 2006/03/10

R225
0_0805_5%

1 2

C238

1

2

10U_1206_16V4Z

0.1U_0402_16V4Z

LINE_OUTL 30
LINE_OUTR 30

T33 PA D

L_HP 30
R_HP 30

AC97_BITCLK_CODEC 20

12

R252 33_0402_5%

12
12

T41 P AD
T43 PA D
T42 PA D
T38 PA D

T40 PA D
T39 PA D
T34 PA D

E

SENSE_A

1U_0603_10V4Z

C249 10P_0402_25V8K@

1 2

12

PREP# 21,25,36

Chnage in 6/16.

1

C256
1U_0603_10V4Z

2

Compal Secret Data

Deciphered Date

C282

AC97_SDIN0 20

PORT_A_SNS 30

1

C250

0.1U_0402_16V4Z

2

F

R293 39.2K_0402_1%

1 2

R294 20K_0402_1%

1 2

SENSE_A_C

1 2

R286 10K_0402_1%

1

2

Q52

2N7002_SOT23

SENSE_A_A 30
SENSE_A_B 30

VDDA_CODEC

12

R296

13

D

2

G

S

R295

100K_0402_5%

Title

Size Document Number Rev

LA-3331P

Date: Sheet

G

10K_0402_5%@

12

1

C285

0.1U_0603_50V4Z

2

LINE_IN_ SENSE

LINE_IN_SENSE 36

Compal Electronics, Inc.

AC97 CODEC AD1981HD

29 59Tuesday, May 1 5, 2007

H

of

1.0

A

1

L_SPK+
L_SPK­R_SPK+
R_SPK-

D18

2

3

C160100P_0402_50V8J

1

2

PACDN042_SOT23~D@

1 1

2 2

1

D19

PACDN042_SOT23~D@

2

3

C162100P_0402_50V8J

C161100P_0402_50V8J

1

1

2

2

LINE_OUTR29

LINE_OUTL29

SLP_S3#17,21,24,29,34,36,37,44,45,46,48,49

EAPD29,34

A_SD34

C163100P_0402_50V8J

1

2

JP19

1

1

2

2

3

3

4

4

E&T_3801-04conn@

C261

0.1U_0402_16V4Z

LINE_C_OUTR LINE_C_R_OUTR

1 2

C260

0.1U_0402_16V4Z

LINE_C_OUTL LINE_C_R_OUTL

1 2

R203 10K_0402_5%

1 2

R649 0_0402_5%

1 2

12

R650

1K_0402_5%@

R272
10K_0402_5%

1 2

R270
10K_0402_5%

1 2

B

AMP. FOR INTERNAL SPEAKER

+5VAMP+5VALW

12

8

18

VDD

PVDD1

PGND1

PGND211PGND315PGND4

6

C246

1

2

10U_1206_6.3V6M

@

BIAS

PVDD2

OUTR+

OUTR-

OUTL+

OUTL-

NC1
NC2
NC3
NC4

MAX9710ETP_QFN20

20

C248

C240

1

1

2

2

1U_0603_10V4Z

0.1U_0402_16V4Z

@

L

C262 1U_0603_10V4Z

2

R257 16.5K_0402_1%

R_SPK+

7

R_SPK-

9

R256 16.5K_0402_1%

L_SPK+

19

L_SPK-

17

3
10
13
16

C252

1

+

2

150U_D_6.3VM@

U20

5

INR

1

INL

4

MUTE

14

SHDN

EP

21

R271
0_0402_5%

2

G

1

C20810U_1206_6.3V6M@

2

10 dB

10 dB

13

D

S

2

G

R220
0_1206_5%

1 2

12

Q40
2N7002_SOT23

13

D

S

Q39
2N7002_SOT23

C

Keep 10 mil width

1 2

1 2

1 2

10 dB

10 dB

AC97_RST#_MDC20,35

RST# Control Delay Circuit

LINE_C_R_OUTR

LINE_C_R_OUTL

D

C191 100U_D2_6.3VM

R_HP29

10K_0402_5%

1 2

R2162

R2164
1K_0402_5%

1 2

C1575

0.047U_0402_16V7K

L_HP29

+

1 2

+5VS+3VS

12

330K_0402_1%

R2163

ANTI_DELAY

13

D

Q133

2

2N7002_SOT23

G

S

2

1

ANTI POP Circuit

+

C192 100U_D2_6.3VM

1 2

ANTI_DELAY

R2159 0_0402_5% @

Q131

BSS138_SOT23

D

1 3

R2160
10K_0402_5%

1 2

R2165 0_0402_5% @

BSS138_SOT23

R2166
10K_0402_5%

1 2

1 2

S

G

2

1

C1574

4.7U_0603_6.3V6K

2

1 2

Q134

D

S

1 3

G

2

Q132
BSS138_SOT23

D

S

13

G

2

(Add in 7/26)

Q135
BSS138_SOT23

D

S

G

2

E

HP_R_JACK

R2161
10K_0402_5%

1 2

13

HP_L_JACK

R2167
10K_0402_5%

1 2

To Audio / USB Board CONN

3 3

VDDA_CODEC VDDA_CODECVDDA_CODEC

PORT_A_SNS29

SENSE_A_A29

2N7002_SOT23

4 4

13

D

2

G

Q49

S

Q50
2N7002_SOT23

DOCK_HPS#36

A

12

R285
100K_0402_5%

13

D

2

G

S

1

C281

0.1U_0603_25V7K_V1

2

Q47
2N7002_SOT23

12

R278
100K_0402_5%

13

D

S

2

G

1

C278

2.2U_0603_6.3V6K

2

B

R273
100K_0402_5%

1 2

SENSE_A_B29

Q37
2N7002_SOT23

12

R258
100K_0402_5%

DLINE_OUT_L

13

D

MIC_SENSE

2

G

S

C188

0.1U_0402_16V4Z

+5VALW

1

2

USB20_N321
USB20_P321

USB20_N421
USB20_P421

DLINE_OUT_L36

DLINE_OUT_R36

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

R1986 0_0402_5%

1 2

R1987 0_0402_5%

1 2

R162 0_0402_5%
R170 0_0402_5%

DLINE_OUT_L
HP_R_JACK

HP_L_JACK

Change them from

56.2 to 60.4 ohm.
2/28

2005/03/10 2006/03/10

12
12

Compal Secret Data

USB20_N3_R
USB20_P3_R

USB20_N4_R
USB20_P4_R

R207 60.4_0603_1%

12

R217 60.4_0603_1%

12

Deciphered Date

Change type 4/19.

JP25

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15

ACES_87216-3006

D

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
GND31GND

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

32

Add modify in 2/12.

USB20_N5_R
USB20_P5_R

USB20_N8_R
USB20_P8_R

R174 0_0402_5%

1 2

R180 0_0402_5%

1 2

R1988 0_0402_5%
R1989 0_0402_5%

+5VALW+5VALW

R2198 0_0402_5% @

VDDA_CODEC

Title

Size Document Number Rev

Date: Sheet

12
12

12

MIC_SENSE

Compal Electronics, Inc.

AMP & Audio Jack

LA-3331P

USB20_N5 21
USB20_P5 21

USB20_N8 21
USB20_P8 21

S4_STATE 31,33

SLP_S5 36,37

INT_MIC 29
MIC2 29MIC129

SLP_S5_R 31,33

E

1.0

of

30 59Tuesday, May 1 5, 2007

5

4

3

2

1

USB CONNECTOR 1

USB20_N2 21
USB20_P2 21

USB_VCCUSB_VCC

Change it to
SGA00002B00 330uF
with same footprint.

1

1

1

C1220.1U_0402_16V4Z

C1231000P_0402_50V7K

C126330U 6.3V M

3/31

+

2

2

2

Del C118, C498, C499 at 3/28.

USB20_N021
USB20_P021

D D

R53
0_0402_5%

USB20_N0_R

12

USB20_P0_R

12

R57
0_0402_5%

2

3

D12

PACDN042_SOT23~D@

1

JP16

1

VCC

VCC

2

D0-

3

D0+

D1+

4

VSS

VSS

G210G1

12

TYCO_1-1734062-1

conn@

R51

5

USB20_N2_R

6

D1-

USB20_P2_R

7
8

9

G311G4

0_0402_5%

12

12

R52
0_0402_5%

2

3

PACDN042_SOT23~D@

D10

1

(2A,100mils ,Via NO.=4)

+5VALW

+5VALW USB_VCC

C C

C137

4.7U_0805_10V4Z

1

2

SLP_S5_R30,33

S4_STATE30,33

Add option in 2/12.

U35

1

GND

2

IN

3

IN

4

EN#

G548A2P1U_SO8

8

OUT

7

OUT

6

OUT

OC#

5

USB_OC#

Del J13, R49 from 3/28.

Add in 8/2.

R2175
10K_0402_5%

1 2

BT Connector

JP18

1
2

USB20_P6_R

3

USB20_N6_R

4
5
6
7
8

B B

ACES_87212-0800conn@

1

C140
1U_0603_10V4Z

2

R70 47K_0402_5%

BT_OFF21

1 2

R85 0_0402_5%
R87 0_0402_5%

R674 1K_0402_5%@
R677 1K_0402_5%@

Change value. 5/10
Reserve R674,R677

cause BlueFlame
co-existance
issue. 6/14

12

R69
100K_0402_5%

12
12

1 2
1 2

Q12
SI2301BDS_SOT23

S

D

13

G

2

C138

1

2

+3VAUX_BT

Del D16. 3/28

+3VAUX_BT+3VALW

C1430.1U_0402_16V4Z

C1424.7U_0805_10V4Z

C1440 .01U_0402_16V7K

1

1

1

2

2

2

USB20_P6 21
USB20_N6 21
BT_LED 23
CH_DATA 26

CH_CLK 26

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.1U_0402_16V4Z

RV to Install. 5/10

2005/03/10 2006/03/10

3

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

USB I/O & BT Connector

LA-3331P

1

1.0

of

31 59Tuesday, May 1 5, 2007

A

B

C

D

E

RP29

DCD#1

1 8

RI#1

2 7

CTS#1

3 6

DSR#1

1 1

RP30

10K_1206_8P4R_5%
R428 10K_0402_5%

1 2

R437 10K_0402_5%

1 2

Change design. 6/15

+3VS

2 2

+3VS

3 3

R8

1 2

10K_0402_5%

R422

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

R435

R436

R429

R438

18
27
36
45

1 2

0_0402_5%

SW_EXPCRD_RST#

SIO_GPIO12
SIO_GPIO10
SIO_GPIO44
SIO_GPIO43

CARD_ID#

R421

PID0

PID1

SIO_GPIO11

SIO_GPIO40

SIO_IRQ

SIO_DPIO45

NPCI_RST#21,34

PLT_RST#7,19,20,21,26,33

+3VS

EXPCRD_RST# 36

R431 0_0402_5%

1 2

R432 0_0402_5%@

1 2

R433 10K_0402_5%

1 2

1 2

+3VS

R417 10K_0402_5%

High : Compal MXM
Low : Standard MXM

LPC_AD020,33,34
LPC_AD120,33,34
LPC_AD220,33,34
LPC_AD320,33,34

LPC_FRAME#20,33,34

LPC_DRQ#020

PM_CLKRUN#21,27,33,34

CLK_PCI_SIO15

SIRQ21,27,33,34

CLK_14M_SIO15

SER_SHD36

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#
LPC_DRQ#0

SIO_RST#
SIO_PD#

CLK_PCI_SIO
SIRQ
SIO_PME#

CLK_14M_SIO
SIO_GPIO40

PID0
PID1
SIO_GPIO43
SIO_GPIO44
SIO_DPIO45
CARD_ID#
SER_SHD
SIO_GPIO10
SIO_GPIO11
SIO_GPIO12
SIO_IRQ

SW_EXPCRD_RST#

10
12
13
14

15
16

17
18

19
20
21

6
9

23
24
25
27
28
29
30
31
32
33
34
35
36
40

8
22
43
52

4 5

4.7K_1206_8P4R_5%

IRRX

R427 1K_0402_5%

1 2

U29

LAD0
LAD1
LAD2
LAD3

LFRAME#
LDRQ#

PCI_RESET#
LPCPD#

LPC I/F

CLKRUN#
PCI_CLK
SER_IRQ
IO_PME#

CLK14

CLOCK

GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45

GPIO

GPIO46
GPIO47
GPIO10
GPIO11/SYSOPT
GPIO12/IO_SMI#
GPIO13/IRQIN1
GPIO14/IRQIN2
GPIO23

VSS
VSS

POWER

VSS
VSS

LPC47N217_STQFP64

Base I/O Address

0 = 02Eh
1 = 04Eh*

12

R434

10_0402_5%@

1

C410

18P_0402_50V8K

@

2

+3VS

RXD1

TXD1
DSR1#
RTS1#
CTS1#
DTR1#

RI1#

SERIAL I/F

DCD1#

IRRX2

FIR

IRTX2

IRMODE/IRRX3

INIT#

SLCTIN#

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

SLCT

PE

BUSY

PARALLEL I/F

ACK#

ERROR#

ALF#

STROBE#

VTR
VCC
VCC
VCC
VCC

CLK_14M_SIOCLK_PCI_SIO

12

R420

10_0402_5%@

1

C399

10P_0402_25V8K

@

2

+5VS

21

D31
CH751H-40_SC76

RXD1 36

RXD1

62
63
64
1
2
3
4
5

37
38
39

41
42
44
46
47
48
49
50
51
53
55
56
57
58
59
60
61

7
11
26
45
54

R403 1K_0402_5%

TXD1

DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

IRRX

LPTINIT#
LPTSLCTIN#
LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7
LPTSLCT
LPTPE
LPTBUSY
LPTACK#
LPTERR#
LPTAFD#
LPTSTB#

C3910.1U_0402_16V4Z

1

2

C3970.1U_0402_16V4Z

1

2

1 2

TXD1 36
DSR#1 36
RTS#1 36
CTS#1 36
DTR#1 36
RI#1 36
DCD#1 36

LPTINIT# 36
LPTSLCTIN# 36
LPD0 36
LPD1 36
LPD2 36
LPD3 36
LPD4 36
LPD5 36
LPD6 36
LPD7 36
LPTSLCT 36
LPTPE 36
LPTBUSY 36
LPTACK# 36
LPTERR# 36
LPTAFD# 36
LPTSTB# 36

C3830.1U_0402_16V4Z

1

2

+3VS

C4014.7U_0805_10V4Z

1

2

LPD3
LPD2
LPD1
LPD0

LPD7
LPD6
LPD5
LPD4

LPTACK#
LPTBUSY
LPTPE
LPTSLCT

LPTSTB#
LPTAFD#
LPTERR#

LPTSLCTIN#

LPTINIT#

+5VS_PRN

RP28

1 8
2 7
3 6
4 5

4.7K_1206_8P4R_5%
RP27

1 8
2 7
3 6
4 5

4.7K_1206_8P4R_5%
RP26

1 8
2 7
3 6
4 5

4.7K_1206_8P4R_5%
RP25

1 8
2 7
3 6
4 5

4.7K_1206_8P4R_5%

R414

4.7K_0402_5%

1 2

R418

4.7K_0402_5%

1 2

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

SUPER I/O LPC47N217

LA-3331P

E

1.0

of

32 59Tuesday, May 1 5, 2007

5

4

3

2

+3VS

+3VALW

1

Finger printer

Add change per request for FPR resume in S3. 2/12

Q140

D D

C C

RHU002N06_SOT323

S

G

R2200
10K_0402_5%

D

1 2

13

2

R2202
0_0402_5%

12

USB20_N121
USB20_P121

PACDN042_SOT23~D@

Q141
FDN338P_SOT23

D

S

USB20_N1_PWR

13

G

2

S4_STATE 30,31

GPIO26 21

R46 0_0402_5%
R47 0_0402_5%

2

3

D9

1

Change connector to same as JP58 per
ME request. 12/18

R2201

0_0402_5% @

12
12

+3VS+3VALW+5VALW

12

USB20_N1_PWR
USB20_N1_R
USB20_P1_R

1

C124

0.1U_0402_16V4Z

2

JP15

1

1

2

2

3

3

4

4

E&T_3801-04conn@

LPC_PD#21

TPM1.2 on board

R402 10K_0402_5%

1 2

R401 0_0402_5%

R379

4.7K_0402_5%@

R375

0_0402_5%

+3VS

12

12

12

C365 18P_0402_50V8J

32.768KHZ_12.5P_1TJS125BJ2A251
C341 18P_0402_50V8J

C392
10P_0402_50V8K@

Del R397. 6/5

5

10

19

VSB

VDD

VDD

VDD

GPIO

GPIO2

TEST1

TESTB1/BADD

NC
NC
NC

GND

GND

GND

GND

SLB 9635 TT 1.2_TSSOP28

4

11

18

1

C350

2

0.1U_0402_16V4Z

TPM_GPIO

6

TPM_GPIO2

2

Base I/O Address
0 = 02Eh
1 = 04Eh*

8
9

3
12
1

R390
0_0402_5%

R378

4.7K_0402_5%

12

4.7K_0402_5%@

+3VS+3VS

12

T23PAD
T24PAD

12

R377

1

C349

2

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
PLT_RST#

SIRQ21,27,32,34

CLK_PCI_TCG15

R415 10_0402_5%@

1

IN

4

OUT

12

TPM_XTALO
TPM_XTALI

TPM_XTALI

12

R394
10M_0402_5%

TPM_XTALO

12

PM_CLKRUN#21,27,32,34

12

Y5

2

NC

3

NC

12

0.1U_0402_16V4Z

C393

2

26
23
20
17
22
16
28
27
21

15

14
13

0.1U_0402_16V4Z

U26

LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
LPCPD#
SERIRQ
LCLK

CLKRUN#

7

PP

XTALO
XTALI/32K IN

C394

2

0.1U_0402_16V4Z

24

SLB 9635 TT 1.2

25

1

1

# Change SPI ROM to 8Mbit(SA00001JX00) from SI2.

BIOS ROM

C1445

0.1U_0402_16V4Z

20mils

B B

SPI_CS#21
SPI_CLK21

+3VM

SPI_CLK

SPI_SI21

SPI_SI
SPI_CS# SPI_CS#_JP52

SPI_HOLD#_0 SPI_HOLD#_1

1 2

R2181 0_0402_5%@

Del in 3/14.

20mils

+3VM

R2170

SPI_CLK_JP52
SPI_SI_JP52

A A

Add in 7/27.

0_0402_5%

1 2
1 2

R2171

0_0402_5%

SPI_CS1#21

SPI_CLK

SPI_CS1# SPI_CS1#_JP52

5

1 2

R1906 3.3K_0402_5%

R1904 47_0402_5%

1 2

R1905 47_0402_5%

1 2

R2169 0_0402_5%

1 2

C1567

0.1U_0402_16V4Z

1 2

R2104 3.3K_0402_5%@

R2105 47_0402_5%@

1 2

R2106 47_0402_5%@

1 2

R2172 0_0402_5%

1 2

Del in 3/14.

20mils

+3VM

R1907 3.3K_0402_5%@

+3VM

20mils

1

2

1

2

Modify net name to correct
SPI bus routing.7/28

1 2

SPI_WP#

SPI_HOLD#_0

SPI_CS#
SPI_CLK_0
SPI_SI_0

+3VM

20mils

SPI_WP#

SPI_HOLD#_1

SPI_CS1#
SPI_CLK_1
SPI_SI_1

SPI_WP#

U14

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

WIESO_G6179-100000_8P

U58

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

SST25LF080A_SO8-200mil@

R2108 0_0402_5%

4

VSS

Q

VSS

Q

1 2

4

2

4

2

@

SST25LF080A_SO8-200mil

SPI_SO_L0

1 2

R1291 15_0402_5%

Del in 3/14.

SPI_SO_L1 SPI_SO_RSPI_SI

1 2

R2107 15_0402_5%@

&U14

SPI_SO_R

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SPI_SO_R 21

3

2005/03/10 2006/03/10

Compal Secret Data

LPC Debug Port

Connect pin3 & 23
together and pin 24
to GND in 6/29.

NUM_LED#

+3VL

R2168

12

100K_0402_5%

CLK_PCI_DB15

LPC_FRAME#20,32,34

PLT_RST#7,19,20,21,26,32
LPC_AD020,32,34

LPC_AD120,32,34
LPC_AD220,32,34
LPC_AD320,32,34

STB_LED#34
CAPS_LED#34
NUM_LED#34

VCC1_PWRGD34,38

SPI_SO_JP5221

Add in 7/24.

Deciphered Date

2

Change from +3VL to +3VS. 6/9

Removed +3VS. 6/13

B+

JP52

1

Ground

2

LPC_PCI_CLK

3

Ground

4

LPC_FRAME#

5

+V3S

6

LPC_RESET#

7

+V3S

8

LPC_AD0

9

LPC_AD1

10

LPC_AD2

11

LPC_AD3

12

VCC_3VA

13

PWR_LED#

14

NUM_LED#

SPI_CLK_JP52
SPI_CS#_JP52
SPI_SI_JP52

SPI_HOLD#_0
SPI_CS1#_JP52

Title

Size Document Number Rev

Date: Sheet

CAPS_LED#

15

NUM_LED#

16

VCC1_PWRGD

17

SPI_CLK

18

SPI_CS#

19

SPI_SI

20

SPI_SO

21

SPI_HOLD#

22

Reserved

23

Reserved

24

Reserved

ACES_87216-2404_24P

conn@

Compal Electronics, Inc.

TCG/BIOS ROM/PS2/SW LPC DEBUG

LA-3331P

1.0

of

33 59Tuesday, May 1 5, 2007

1

5

NPCI_RST#21,32

PWR1

1

C1446

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1 2

R1928

2M_0402_5%@

1

IN

1

2

2

C1456 18P_0402_50V8J

Y9

ADP_EN 48

TP_DATA35

KBD_CLK36

KBD_DATA36

PS2_CLK36

PS2_DATA36

LPC_AD320,32,33
LPC_AD220,32,33
LPC_AD120,32,33
LPC_AD020,32,33

ADP_PS148

12

C1449

TP_CLK35

PM_RSMRST#

BAV99S_SOT363@

R2146

1

2

SIRQ21,27,32,33

+RTCVCC

R2178
0_0402_5%

@

R2179

0_0402_5%@

1 2
1 2

R2197
0_0402_5%

1U_0603_10V4Z@

R1937 0_0402_5%@

2.2K_0402_5%@

1 2

1

C1448

0.1U_0402_16V4Z

2

KSO[0..13]35

Pin3 250 : KSO12/OUT8/KBRST

KSI[0..7]35

PM_CLKRUN#21,27,32,33

CLK_PCI_EC15

RUNSCI_EC#21

LPC_FRAME#20,32,33

R1930
120K_0402_5%

4

+3VL

OUT

1

NC3NC

2

C1457 18P_0402_50V8J

1. in case +3VL is over budget. 8/24

2. Change +3VALW to +3VL & add option to
GND. 2/6

PM_PWROK7,21,46

+3VALW

R2145 4.7K_0402_5%@

+3VL

+RTCVCC

+3VL

D D

+5VS

C C

+3VS

B B

32K_CLK

A A

R1908 0_0603_5%

R1910 0_0603_5%@

Change Design
in 12/18.

RP40

1 8
2 7
3 6
4 5

10K_1206_8P4R_5%

RP41

1 8
2 7
3 6
4 5

10K_1206_8P4R_5%

1 2

R1916 10K_0402_5%

1 2

R1920 10K_0402_5%

RP43

1 8
2 7
3 6
4 5

10K_1206_8P4R_5%

1 2

R1925 10K_0402_5%

To improve layout trace for
EMI, remove R1929, C1455. 3/28

Removed R1939 , cause power
team has removed VR_ON
signal. 6/23

Removed R1985 in 4/19
Removed R1935 in 6/2

R1934 0_0402_5%

1 2

12

12

KSI0
KSI3
KSI2
KSI1

KSI7
KSI6
KSI5
KSI4

TP_CLK

TP_DATA

KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA

RUNSCI_EC#

Change from PLT_RST#
to NPCI_RST#. 6/9

32.768KHZ_12.5P_1TJS125BJ2A251

Add for DG1.0. 6/14
Modify at 10/27.(will mount if

timing issue)
Modify to meet DG1.1.10/30

5

4

1

C1450

0.1U_0402_16V4Z

KSO[0..13]

C1458

1 2

12

D73B

2

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

TP_CLK
TP_DATA
KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA

CLK_PCI_EC
RUNSCI_EC#

CRY1
CRY2

12

C1459

1

2

0.1U_0402_16V4Z

@

2

1

R2144 0_0402_5%

1 2

Q128
MMBT3906_SOT23@

3

E

4

5

2

3

6

4

0.1U_0402_16V4Z

U18

21

KSO0

20

KSO1

19

KSO2

18

KSO3

17

KSO4

16

KSO5

13

KSO6

12

KSO7

10

KSO8

9

KSO9

8

KSO10

7

KSO11

6

KSO12/GPIO00/KBRST

5

KSO13/GPIO18

29

KSI0

28

KSI1

27

KSI2

26

KSI3

25

KSI4

24

KSI5

23

KSI6

22

KSI7

35

IMCLK

36

IMDAT

38

KCLK

40

KDAT

41

EMCLK

42

EMDAT

55

CLKRUN#

57

SER_IRQ

54

PCI_CLK

76

EC_SCI#

51

LAD[3]

50

LAD[2]

48

LAD[1]

46

LAD[0]

52

LFRAME#

53

LRESET#

45

LPCPD#/GPIO23

70

XTAL1

71

XTAL2

68

VCC0

C

1

B

2

D73A

1

BAV99S_SOT363@

1

C1451

4.7U_0805_10V4Z

2

NC94NC95NC96NC97NC

Power Mgmt/SIRQ

LPC
Bus

NC1NC2NC3NC30NC31NC32NC33NC34NC43NC

PGD_IN

+3VL

1

C1452

2

PWR1

14

127NC128

106

VCC139VCC158VCC184VCC1

VCC1

Keyboard/Mouse Interface

SMSC_1070_TQFP-128P

AGND

VSS11VSS37VSS47VSS56VSS

VSS82VSS

72

44

104

117

AGND FILTER

C1460 0.1U_0402_16V4Z

1 2

RSMRST_ICH# 21

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

R1909 0_0402_5%@

R1911 0_0402_5%

1

C1447

2

0.1U_0402_16V4Z

119

49

15

CAP

VCC1

VCC2

General Purpose I/O Interface

Access Bus Interface

24MHZ_OUT/GPIO19/WINDMON

Miscellaneous

NC62NC63NC64NC65NC66NC

67

Del R2140 , R2143. 6/15

3

2

+3VL

R2062

100K_0402_5%@

1 2

PM_SLP_M# 21,37,44,45,49

A_SD 30
EAPD 29,30

10U_0805_10V4Z1070@

12

AMT_ADP_PRES 21

+3VL

12

R1913
10K_0402_5%

I2C_DAT 35
I2C_CLK 35

ME__EC_DATA1 21
ME__EC_CLK1 21

+3VL

C1453

1

2

KBC_PWR_ON 43
GREEN_BATLED# 23

BATSELB_A# 42
INV_PWM 18

FAN_PWM 4
CHGCTRL 41,42

THM_MBAY# 47
ON/OFFBTN_KBC# 35

LOW_BAT# 21
KSO14 35
KSO15 35

CRACK_BGA 11,22

T75PAD

BATCON 42
THM_MAIN# 47

NUM_LED# 33

1 2

Add in 5/25. (Follow ANG3.0)

AB1A_DATA 47
AB1A_CLK 47

AB1B_DATA 47
AB1B_CLK 47

1 2

Add in 5/25. (Follow ANG3.0)

PGD_IN 46
PWR_GD 17,21,27,37,38,46,48
VCC1_PWRGD 33,38
ADP_PS0 48

1 2

ADP_ID 48
AMBER_BATLED# 23
STB_LED# 33
CAPS_LED# 33

R2142 0_0402_5%@

1 2

2

3

U60

P5G

Y

4

2

Add in 7/28.

I2C_INT 35

Same as Chimay. (6/26)

CLK_14M_KBC15

B1A

D61
CH751H-40_SC76

D62 C H751H-40_SC76

KSO17 35

CAPS_LED#

+3VS

AMT_BI_GPIO 21

INV_PWM

PCI_SERR# 19,27

124

OUT0

125
123

122
121
120
118

107

GPIO01

79

GPIO02

80

GPIO03

81
83

85
86
87

88
89
90
91
92
101
102

103
105
4
74

GPIO27

111
112

109
110

73
108

59

CLOCKI

75
60
78

PWRGD

77
61

69

TEST PIN

116
113
115
114

Compal Secret Data

Change
Design
in 6/2.

R2063 0_0402_5%

1 2

R2116 0_0402_5%

1 2

R2117 0_0402_5%

1 2

+3VL

R2180
10K_0402_5%

1 2

GREEN_BATLED#

KBRST#
INV_PWM

PM_RSMRST#
CRACK_BGA
EC_GPIO9

AB2A_DATA

R1918 330_0402_5%

AB2A_CLK
AB2B_DATA
AB2B_CLK

EC_GPIO27

Pin50 250 -- 24MHz_Out

Pin52 250 -- XOSEL

1 2

R1919 330_0402_5%

1 2

R1921 0_0402_5%

1 2

R1922 0_0402_5%

1 2

THM_MAIN#
A20M

R1923 10K_0402_5%

NUM_LED#

R2101 0_0402_5%

2 1

D63

CH751H-40_SC76

AB1A_DATA
AB1A_CLK

AB1B_DATA
AB1B_CLK

R2174 330_0402_5%

1 2

EA#

R2102 0_0402_5%

CLK_14M_KBC
32K_CLK
PGD_IN
PWR_GD
VCC1_PWRGD

TEST

R1927 300_0402_5%

STB_LED#
CAPS_LED#

Change R2138 to 100K. 6/15

Install R2142 if debug
card is no used.

+3VL +3VL+3VL

Add in 6/13 for debug port.

12

R2139

10K_0402_5%

TC7SH08FU_SSOP5

Deciphered Date

PWR_GD

12

12

Add in 8/24.

100

126

GPIO2893GPIO2998GPIO3099GPIO31

GPIO32

OUT1/IRQ8#

OUT7/SMI#

OUT8/KBRST

OUT9/PWM2
OUT10/PWM0
OUT11/PWM1

GPIO04/KSO14
GPIO05/KSO15

GPIO07/PWM3

GPIO08/RXD

GPIO09/TXD

GPIO11/AB2A_DATA

GPIO12/AB2A_CLK

GPIO13/AB2B_DATA

GPIO14/AB2B_CLK
GPIO15/FAN_TACH1
GPIO16/FAN_TACH2

GPIO17/A20M

GPIO20/PS2CLK
GPIO21/PS2DAT

GPIO24/KSO16

AB1A_DATA

AB1A_CLK

AB1B_DATA

AB1B_CLK

PGM Strap/GPIO25

EA Strap#/GPIO26/KSO17

32KHZ_OUT/GPIO22

RESET_OUT#/GPIO06

VCC1_PWRGD

DMS_LED#/GPIO10

BAT_LED#

PWR_LED#/8051TX

FDD_LED#/8051RX

KBC1070_VTQFP128

STB_LED# STB_R_LED#

2006/02/13 2006/07/26

1

Add in 12/20 pe r HP's request.

21

+3VL

1 2

R2192

GREEN_BATLED#

KB_RST# 20

CRACK_BGA

100K_0402_5%

THM_MAIN#
ADP_PS1
EC_GPIO27

G_BATLED#20

R2193
1K_0402_5%

D

S

13

1 2

G

Q137

2

2N7002_SOT23

13

D

Q138

2

2N7002_SOT23

G

S

1 2

R1914 210K_0402_1%

1 2

R1915 100K_0402_5%@

1 2

R1917 100K_0402_5%

1 2

R2131 100K_0402_5%

Add in 6/5.

RP42

4.7K_1206_8P4R_5%

AB1A_CLK

1 8

AB1A_DATA

2 7

AB1B_CLK

3 6

21

GATEA20 20

SLP_S3# 17,21,24,29,30,36,37,44,45,46,48,49
KSO16 35
ADP_PRES 17,24,41,42,43,48

AB1B_DATA

EA#

R1940 1K_0402_5%

PGD_IN

1 2

R2177

100K_0402_5%

4 5

12

Add in 8/23.

Del R1926 , R19 31~R1932 , R1933 ,
R1936 , R193 8 , J17. 6/7

R1924

CLK_14M_KBC

+3VL

12

R2138

100K_0402_5%

12

R2141

10K_0402_5%

1

C1568

0.1U_0402_16V4Z

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

LA-3331P

10_0402_5% @

1 2

STB_R_LED# 23,36

LPC47N1021

C1454

10P_0402_25V8K @

1 2

of

34 59Tuesday, May 1 5, 2007

1

+3VL

+3VL

+3VL

1.0

SWITCH BOARD.

I2C_CLK34
I2C_DAT34
I2C_INT34

WL/BT_LED23

1 2

AC97_SDOUT_MDC
AC97_SYNC_MDC

AC97_SDIN1_MDC

1

C220

2

AC97_SDOUT_MDC20

AC97_SYNC_MDC20

AC97_SDIN120

AC97_RST#_MDC20,30

R239 33_0402_5%

Power button

+3VL

12

R167

ON/OFF#36

ON/OFF#

C177
1U_0603_10V4Z

100K_0402_5%

2

A

1

2

Change to single gate. 5/9

Modify at 10/5.

+3VL+3VS

Del PLT_RST#.12/18

12

12

JP1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

10

10

ACES_87212-10G0

conn@

12

R2069

4.7K_0402_5%

10K_0402_5%

R2071

R2070

4.7K_0402_5%

MDC 1.5 Conn.

JP26

1

1

3

3

5

5

7

7

9

9

11

1

2

11

GND13GND14GND15GND16GND17GND

2

G

+3VS

1

1

C204

C223

2

2

4.7U_0805_10V4Z@

0.1U_0402_16V4Z

1000P_0402_50V7K

+3VL

5

U53
SN74LVC1G14DCKR_SC70-5

V

4

1 2

Y

NC

1

R172

G

100K_0402_5%

3

C183
1U_0603_10V4Z

STB_LED23

G11119

12

G12

+3VS

Connect pin2 to +3VS
for future modems.

ACES_88020-12101conn@

+3VL

2

2

4

4

6

6

8

8

10

10

12

12

18

Add ESD
diode(D79).1/4

12

PACDN042_SOT23~D
R163
100K_0402_5%

13

D

Q29

S

2N7002_SOT23

Change SC1B751V005 to SC1H751H010
to unified spec. 3/26

11/07

R209

10_0402_5%@

3

D79

ON/OFFBTN_KBC# 34

R179 100K_0402_5%

21

D23 CH751H-40_SC76

AC97_BITCLK_MDC 20

1 2

12

C221

10P_0402_25V8K@

STB_LED
ON/OFF#

2

1

1 2

ON/OFFBTN# 21

+3VALW

INT_KBD CONN.

KSO[0..17]34
KSI[0..7]34

KSO0
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO14
KSO11
KSO12
KSO1
KSO17
KSO13
KSO15
KSO16
KSI2
KSI3
KSI6
KSI4
KSI1
KSI5
KSI0
KSI7

Del Modem disable
function(Del
R2147). 6/21.

JP58

1

1

2

2

3

3

4

4

E&T_3801-04conn@

Update to 18x8 an ge lfire keyboard matrix

KSO0
KSO2
KSO3
KSO4

KSO5
KSO6
KSO7
KSO8

KSO9
KSO10
KSO14
KSO11

CP1

4 5
3
2

100P_1206_8P4C_50V8

CP2

4 5
3
2

100P_1206_8P4C_50V8

CP3

4 5
3
2

100P_1206_8P4C_50V8

KSO[0..17]
KSI[0..7]

JP12

A1
A2
A3
A4
A5
A6
A7
A8

A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30

conn@

FOX_GB1SV301-160K-7F

6
7
81

6
7
81

6
7
81

1

1

31

2

2

32

3

3

33

4

4

34

5

5

35

6

6

36

7

7

37

8

8

38

9

9

39

10

10

40

11

11

41

12

12

42

13

13

43

14

14

44

15

15

45

16

16

46

17

17

47

18

18

48

19

19

49

20

20

50

21

21

51

22

22

52

23

23

53

24

24

54

25

25

55

26

26

56

27

27

57

28

28

58

29

29

59

30

30

60

KSO12
KSO1
KSO17
KSO13

KSO15
KSO16
KSI2
KSI3

KSI6
KSI4
KSI1
KSI5

KSI0
KSI7

KSO0
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO14
KSO11
KSO12
KSO1
KSO17
KSO13
KSO15
KSO16
KSI2
KSI3
KSI6
KSI4
KSI1
KSI5
KSI0
KSI7

Chnage Connector to
new. 8/31

CP4

4 5
3

6

2

7

CP5

4 5
3
2

CP6

4 5
3
2

CP7

4 5
3
2

81

6
7
81

6
7
81

6
7
81

100P_1206_8P4C_50V8

100P_1206_8P4C_50V8

100P_1206_8P4C_50V8

100P_1206_8P4C_50V8

TrackPoint CONN. T/P BOARD.

+5VS

SP_DATA
SP_CLK

JP14

ACES_87212-0800conn@

1
2
3
4
5
6
7
8

1

C490

0.1U_0402_16V4Z

2

SP_DATA

JP11

8
6
4
2

7

7

8
6
4
2

E&T_6700-Q08N-00Rconn@

SP_CLK

5

5

3

3

1

1

+5VS +5VS

1

+5VS

C116

0.1U_0402_16V4Z

2

TP_DATA34

TP_CLK34

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

MDC/KBD/ON_OFF/LID

LA-3331P

of

35 59Tuesday, May 1 5, 2007

1.0

A

DOCK CONN. 184PIN

Change L14 from SM010020720 to SM010008E10.

L14 SMB3025500YA_2P

1 1

ON/OFF#35

D_VSYNC16

D_HSYNC16

D_DDCDATA16

D_DDCCLK16

D_RED DOCK_RED

2 2

3 3

4 4

D_GREEN

DVI_DETECT17

R1941 0_0402_5%

1 2

R1942 0_0402_5%

1 2

R1943 0_0402_5%

1 2

M_COMP17
M_CRMA17

M_LUMA17

LINE_IN_SENSE29
ACOCP_EN#48

LPTSTB#32
LPTAFD#32

LPTERR#32

A

1000P_0402_50V7K

MDO2+25
MDO2-25

MDO0+25
MDO0-25

LAN_ACT#_DOCK PWR_LED
LANLINK_STATUS#_DOCK

DCD#132

RI#132
DTR#132
CTS#132
RTS#132
DSR#132

TXD132
RXD132

C314

DOCK_GRN
DOCK_BLUD_BLUE

1

2

172

12

JP27A

G1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45

100

18

101

19

102

20

103

21

104

22

105

23

106

24

107

25

108

26

109

27

110

28

111

29

112

30

113

31

114

32

115

33

116

34

117

35

118

36

119

37

120

38

121

39

122

40

123

41

124

42

125

43

126

44

127

45

JAE_SP03-14588-PCL03conn@

B

DOCKVINVIN

1

C305
1000P_0402_50V7K

2

173

P1

DETECT

83

83

84

84

85

85

86

86

87

87

88

88

89

89

90

90

91

91

92

92
93
94
95
96
97
98
99

93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127

R346 10K_0402_5%

DOCK_ADP_SIGNAL

Add for dual channel
DVI.5/15

1 2

DOCKVIN

MDO3+ 25
MDO3- 25

MDO1+ 25
MDO1- 25

SLP_S5#_5R

DVICLK 18

DVIDAT 18

DVI_TX2- 17
DVI_TX2+ 17

DVI_TX1- 17
DVI_TX1+ 17

DVI_CLK- 17
DVI_CLK+ 17

DVI_TX0- 17
DVI_TX0+ 17

DVI_D_TX5- 18

DVI_D_TX5+ 18

DVI_D_TX4- 18

DVI_D_TX4+ 18

Place them close to U1/U2/U3

D_RED RED

R7

1 2
1 2
1 2

0_0402_5%@

GREEN

0_0402_5%@

BLUE

0_0402_5%@

D_GREEN
D_BLUE

B

R5
R6

SLP_S530,37

Q62
2N7002_SOT23

1 2

R299 1K_0402_1%

C

+5VALW

12

R357
100K_0402_5%

SLP_S5#_5R

13

D

2

G

S

USB20_N721
USB20_P721
USB20_N921
USB20_P921

ADP_SIGNAL

D_RED17

RED16

D_GREEN17

GREEN16

D_BLUE17

BLUE16

ISO_PREP#21

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

13

D

S

1U_0603_10V6K

@

C6

0.1U_0402_16V4Z

1 2

ISO_PREP#

C5

0.1U_0402_16V4Z

1 2

D_GREEN
GREEN

ISO_PREP#

C8

0.1U_0402_16V4Z

1 2

ISO_PREP#

C

Q77

2N7002_SOT23@

1 2

2

R671 22K_0402_5%@

G

1

C546

2

LPTSLCTIN#32

R301 0_0402_5%
R300 0_0402_5%
R304 0_0402_5%
R298 0_0402_5%

SER_SHD32

EXPCRD_RST#32

+3VS

U1

5

+3VS

+3VS

VCC

1

A

2

B

4

OE

3

GND

FSA66P5X_SC70-5

U2

5

VCC

1

A

2

B

4

OE

3

GND

FSA66P5X_SC70-5

U3

5

VCC

1

A

2

B

4

OE

3

GND

FSA66P5X_SC70-5

D_RED
RED

D_BLUE
BLUE

2006/02/13 2006/07/26

PREP#

LPTACK#32

LPTBUSY32

LPTPE32

LPTSLCT32

LPD732
LPD632
LPD532
LPD432
LPD332
LPD232
LPD132
LPD032

LPTINIT#32

USB20_N7_R

12

USB20_P7_R

12

USB20_N9_R

12

USB20_P9_R

12

SER_SHD

EXPCRD_RST#

Compal Secret Data

DETECT

Deciphered Date

D

JP27B

46

46

47

47

48

48

49

49

50

50

51

51

52

52

53

53

54

54

55

55

56

56

57

57

58

58

59

59

60

60

61

61

62

62

63

63

64

64

65

65

66

66

67

67

68

68

69

69

70

70

71

71

72

72

73

73

74

74

75

75

76

76

77

77

78

78

79

79

80

80

81

81

82

82

176

GND

169

GND

175

GND

179

GND

181

GND

177

GND

165

G2

166

RING

JAE_SP03-14588-PCL03conn@

Modify in 5/03

+3VM_LAN

D

128

128

129

129

130

130

131

131

132

132

133

133

134

134

135

135

136

136

137

137

138

138

139

139

140

140

141

141

142

142

143

143

144

144

145

145

146

146

147

147

148

148

149

149

150

150

151

151

152

152

153

153

154

154

155

155

156

156

157

157

158

158

159

159

160

160

161

161

162

162

163

163

164

164

178

GND

180

GND

182

GND

174

GND

171

GND

170

GND

167

P2

168

TIP

R372 10K_0402_5%

E

RJ11 Pass Through to Docking

DOCK_MOD_RING
DOCK_MOD_TIP

DVI_D_TX3- 18

DVI_D_TX3+ 18

KBD_DATA 34
KBD_CLK 34
CPPE# 15
PS2_DATA 34
PS2_CLK 34
DOCK_HPS# 30

DLINE_IN_L 29
DLINE_IN_R 29

DLINE_OUT_L 30
DLINE_OUT_R 30

PCIE_TXP5 21
PCIE_TXN5 21

PCIE_R_RXP5
PCIE_R_RXN5

VA_ON#

+5VS

DOCK_MOD_TIPDOCK_MOD_RING

12

2

G

2

G

R3 0_0402_5%

1 2

R4 0_0402_5%

1 2

CLK_PCIE_DOCK 15
CLK_PCIE_DOCK# 15
PREP# 21,25,29

12

R302
1K_0402_5%

C1

1 2

22U_0805_6.3V4Z@

LAN_ACT#_DOCK

13

D

Q58
2N7002_SOT23

S

LANLINK_STATUS#_DOCK

13

D

Q59
2N7002_SOT23

S

Change net name.6/13

STB_R_LED#23,34

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

LA-3331P

JP2

1
2

ACES_85205-0200conn@

1

C291

0.1U_0402_16V4Z

2

LAN_ACT# 24,25

LANLINK_STATUS# 21,24,25

2

G

SLP_S3#17,21,24,29,30,34,37,44,45,46,48,49

Docking CONN.

E

+3VALW

12

13

D

S

PCIE_RXP5 21
PCIE_RXN5 21

R352
10K_0402_5%

PWR_LED

Q61
2N7002_SOT23

of

36 59Tuesday, May 1 5, 2007

1.0

A

+3VALW to +3VM Transfer

+1.25VM to +1.25VS Transfer

1

C1461

1 1

10U_0805_10V4Z

2

+3VALW to +3VS Transfer

R1945
330K_0402_5%

2 2

SLP_S3

Wrong net name 5/9.

U40
SI4800DY_SO8

8

S

D

7

S

D

6

S

D

5

G

D

RUNON

B+

12

1

C1470
10U_0805_10V4Z

2

12

J18
SHORT PADS

13

D

Q92

2

RHU002N06_SOT323

G

S

1
2
3
4

RUNON

+1.25VS+1.25VM

1

2

C1462

U43
SI4800DY_SO8

8

D

7

D

6

D

5

D

12

R1950
470_0402_5%

1

C1473

0.01U_0402_25V7Z

2

0.1U_0402_16V4Z

S
S
S

G

1

C1463
10U_0805_10V4Z

2

+3VS+3VALW

1
2
3
4

No install from 2/14.

1

1

2

2

C1471

C1472

10U_0805_10V4Z

0.1U_0402_16V4Z

Discharge circuit-2 for V-M

+5VALW to +5VS Transfer

S
S
S
G

RUNON

1
2
3
4

+0.9V

2

G

+5VS+5VALW

1

2

C1478

0.1U_0402_16V4Z

12

R1955
470_0402_5%

13

D

Q100

S

RHU002N06_SOT323

1

C1479
10U_0805_10V4Z

2

SLP_S3

+3VS

2

G

12

R1956
470_0402_5%

13

D

Q101

S

RHU002N06_SOT323

U45
SI4800DY_SO8

8

D

7

D

6

1

2

3 3

5

C1477
10U_0805_10V4Z

D
D

Discharge circuit-1

R1961

0_0402_5%@

SLP_S5

1 2

SLP_S4

1 2

R1962
0_0402_5%

Change to same as Chimay. 6/2

4 4

B

R1947
100K_0402_5%

BSS138_SOT23

PM_SLP_M#21,34,44,45,49

LAN_WOL_EN21

+1.25VM

12

R1952
470_0402_5%

13

D

2

SLP_S530,36

Q96
RHU002N06_SOT323

G

S

SLP_S5

2

G

SLP_S3

Q97
RHU002N06_SOT323

PWR_GD 17,21,27,34,38,46,48

C

B+

C1464

2

G

13

D

Q95
BSS138_SOT23

S

R1953
470_0402_5%

SLP_S3#17,21,24,29,30,34,36,44,45,46,48,49SLP_S5#21,45

+5VS

2

G

12

10U_0805_10V4Z

13

D

Q91
BSS138_SOT23

S

LAN_WOL_EN#LAN_WOL_EN#LAN_WOL_EN#

Q99
RHU002N06_SOT323

SLP_S3 SLP_S4

Q94
RHU002N06_SOT323

12

R1959
470_0402_5%

13

D

Q104

S

RHU002N06_SOT323

+3VALW

12

Q93

2

+5VALW

2

LAN_WOL_EN#

13

D

G

S

R2203

100K_0402_5%

R1951
100K_0402_5%@

Q98
RHU002N06_SOT323

12

R1948
100K_0402_5%

13

D

S

+1.5VS +1.8V

12

R1957
470_0402_5%

13

D

G

Q102

S

RHU002N06_SOT323

R1944
100K_0402_5%

+3VALW

12

2

G

12

+1.05VM

12

13

D

2

G

S

Removed +2.5VS discharge
circuit. 5/9

SLP_S3

+3VALW +3VM

U41

8
7
6

1

5

2

12

R1949
470_0402_5%

1

C1545

0.01U_0402_25V7Z

2

+3VM

12

R1954
470_0402_5%

13

D

2

G

S

+3VL +3VL

12

R1946
100K_0402_5%

13

D

2

G

S

Add discharge circuit
for +1.8VS. 5/10

+1.8VS

12

R1958
470_0402_5%

13

SLP_S3 SLP_S5

D

2

G

S

1

S

D

2

S

D

3

S

D

4

G

D

SI4800DY_SO8

PM_SLP_M

SLP_S4#21,45

Change to same
as Chimay. 6/2

Q103

RHU002N06_SOT323

Q113
RHU002N06_SOT323

SLP_S4

1

C1465

2

0.1U_0402_16V4Z

R2119
0_0402_5%

1 2
1 2

R2120

0_0402_5%@

1

C1466
10U_0805_10V4Z

2

12

13

D

2

G

S

2

G

D

R2048
100K_0402_5%

12

R1960
470_0402_5%

13

D

Q105

S

RHU002N06_SOT323

UNUSE GATE :

+3VL

14

P

9

O8I

G

U15D
SN74LVC14APWLE_TSSOP14

7

+3VL

U15E

14

SN74LVC14APWLE_TSSOP14

P

11

O10I

G

7

Add in 1/10 for MXM power rail.

U62

APL5508-25DC-TRL_SOT89-3

2

IN

OUT

1

2

C1593

1U_0603_10V4Z

Change U42 t o Q , cause no
need such power consumption
of +1.8VS. 6/9

GND

1

+1.8V to +1.8VS Transfer

+1.8V +1.8VS

C1467

1U_0603_10V4Z

C1483 0.1U_0402_16V4Z

+VCCP +1.5VS

C1484 0.1U_0402_16V4Z

+1.5VS

C1485 0.1U_0402_16V4Z

+3VS

U11B
SN74LVC08APW_TSSOP14

14

4

P

A

5

B

G

7

+3VS

14

12

P

A

13

B

G

7

SN74LVC08APW_TSSOP14

+2.5VS+3VS

3

1

2

1

2

Q127

SI2306DS-T1 1N_SOT23

D

1 3

G

2

RUNON

1 2

1 2

1 2

E

6

O

U11D

11

O

C1592

4.7U_0805_10V4Z

S

1

C1468
1U_0603_10V4Z

2

+VCCP+VCC_CORE

+1.8V

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/13 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

DC/DC Circuits

LA-3331P

E

1.0

of

37 59Tuesday, May 1 5, 2007

C1585

0.1U_0402_16V4Z

1 2

21

+1.25VS

VCCP_POK49

CH751H-40_SC76

DDR_PGOOD

D74

+5VS

+3VS

1 2

R2191 1K_0402_1%

R1964 10K_0402_5%

R1965 232K_0402_1%

R1968 150K_0402_1%

1 2

21

R2156 10K_0402_5%

D75

CH751H-40_SC76

R1969

49.9K_0402_1%

12

12

12

12

Add for auto
shutdown
issue.12/19

1.24VREF

1

C1486
1000P_0402_50V7K

2

Del R1975 , R1967 , R1972 , R1975 , R2087. 6/23

DDR_PGOOD

M_PROK49

+3VM

D76 CH751H-40_SC76
R2151 10K_0402_5%
R2152 76.8K_0402_1%

Same as Chimay in 6/29.

1 2
1 2

21

12

R1977

56.2K_0402_1%

R1966 20K_0402_5%

R1974 20K_0402_5%

12

R2150
10K_0402_5%

12

1.24VREF_393

12

1.24VREF_393

1

2

Del R1976, C1487. 3/28

1

C1488
1000P_0402_50V7K

2

R1963
1M_0402_5%

12

+5VALW

8

U47A

3

P

+

1

2

-

C1569
1000P_0402_50V7K

O

G

LM393M_SO8

4

J19 SHORT PADS

Change LMV331 to LM393. 3/28

R1970
1M_0402_5%

12

+5VALW

8

U47B

5

P

+

7

O

6

-

G

LM393M_SO8

4

1 2

+3VALW

+3VS

12

R2149
10K_0402_5%

12

R1971
10K_0402_5%

PWR_GD 17,21,27,34,37,46,48

M_PWROK 7,21

KBC Power OK

+3VL+3VL

12

R1979
100K_0402_5%

1

C1489

0.1U_0402_16V4Z

2

Del U54 and con nect to U15. 12/19
Del Q106 and connect to U15, del R1978 and reserve C1577.

U15A

14

SN74LVC14APWLE_TSSOP14

P

1

O2I

G

7

+3VL

U15F

14

SN74LVC14APWLE_TSSOP14

P

13

O12I

G

7

1

C1577

100P_0402_50V8J@

2

VCC1_PWRGD 33,34

+0.9V

R2155 3.3K_0402_5%

Change to same as Chimay (Del
R2080 , R1980 , R2082. 6/23
Modify to same as Chimay 5/5

C1490

0.1U_0402_16V4Z

+3VM

R2081 120K_0402_5%

Change from +3VM_LAN to
+3VM.1/5

12

12

+3VALW

12

R2153
10K_0402_5%

C

Q130

2

B

MMBT3904_SOT23

E

3 1

+3VL

Need be tune to 10msec time delay

1

Reversed & install in 6/15.

2

14

P

3

O4I

G

U15B

7

SN74LVC14APWLE_TSSOP14

1.8PGOOD45

D64
CH751H-40_SC76

2 1

1 2

R1981
100K_0402_1%

R2154 0_0402_5%

+3VL

1

2

14

P

5

G

U15C
SN74LVC14APWLE_TSSOP14

7

C1492

0.1U_0603_50V4Z

O6I

1

2

12

2

G

C1491

0.1U_0402_16V4Z

H30
HOLEA

FM1

CF1

1

1

M2
HOLEA

1

H31
HOLEA

1

FM2

FM3

1

CF2

CF3

1

1

DDR_PGOOD

13

D

Q129
RHU002N06_SOT323

S

1

1

LAN_RST# 21

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/05/26 2006/07/26

Compal Secret Data

Deciphered Date

H32
HOLEA

1

1

1

H3
HOLEA

1

FM4

CF4

1

1

H11
HOLEA

1

H1
HOLEA

1

FM5

CF5

H12
HOLEA

H25
HOLEA

1

1

1

CPU

H2
HOLEA

1

1

FM6

CF6

H23
HOLEA

1

H26
HOLEA

1

H21
HOLEA

H4
HOLEA

1

1

CF7

1

H6

H5
HOLEA

H16
HOLEA

1

1

Title

Size Document Number Rev

Date: Sheet

H8

HOLEA

HOLEA

1

H13
HOLEA

1

1

H18
HOLEA

1

1

CF11

1

H10
HOLEA

1

1

CF9

Compal Electronics, Inc.

LA-3331P

H19
HOLEA

1

CF12

1

H14
HOLEA

1

POK CKT

H20
HOLEA

CF8

H9
HOLEA

1

H27
HOLEA

1

1

1

H17
HOLEA

CF10

H15
HOLEA

1

H24
HOLEA

1

1

1.0

of

38 59Tuesday, May 1 5, 2007

5

D D

4

3

2

1

AC

Adapter

in

C C

VIN

LM358
Thermal
Protector

+1.25VM

SWITCHADP_EN#

MAINPWON

ENBL2 ENBL1

VL

PM_SLP_M#

+3VALWP 3A

B+ B+

MAS8734A

APL5912
LDO
(1.05V)

+1.25VM

DC/DC
(3V/5V)

SLP_S3#

+1.05VMP 1A

APL5912
LDO
(1.05V)

+5VS

+1.05VCCP 4.7A

VCC S HDN#

PWR_GD

+5VALWP 4.5A

VIN

ISL6260&ISL6208
DC/DC
(CPU_CORE)

BQ24703
Charger

B+

MAX8743
DC/DC
(1.25V/1.5V)

+1.5VSP 4A

CPU_CORE
( 44A)

B B

Battery

BATSELB_A

SLP_S3#

ENBL1/ENBL2

+1.25V_VMP 7.4A

+5VALWP

Selector
Circuit

BATSELB_A#

Battery A
8 Cell

Battery B
8 Cell

B+

TPS51116
DC/DC

VCC

+1.8VP 7A

(+1.8VP/+0.9VSP)

SWITCH

A A

5

BATT

SWITCHSWITCH

4

Battery
Connector
A

BATT_A

BATT_B

Battery
Connector

SLP_S3#/SLP_S5#

S3/S5

+0.9VP 2A

B

Title

POWER BLOCK DIAGRAM

Size Document Number Re v

Date: Sheet

3

2

of

39 59Tuesday, May 15, 2007

1

A

1 1

B

C

D

PJP13

3

GND1

4

GND2

6

GND_1

7

GND_2

8

GND_3

9

GND_4

FOX_JPD113E-LB103-7F

2 2

3 3

SINGAL

PWR1

PWR2

5

1

2

ADP_SIGNAL

ADPIN

12

PC1

100P_0402_50V8J

C8B BPH 853025_2P

12

PC2
1000P_0402_50V7K

PL1

1 2

PC3

100P_0402_50V8J

12

12

PC4

1000P_0402_50V7K

VIN

12

PR1

15K_0402_5%@

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

C

Title

Size Document Number R e v

Custom
Date: Sheet

Compal Electronics, Inc.

DCIN

LA-3331P

D

40 59Tuesday, May 15, 2007

of

A

B

C

D

1 1

2 2

3 3

4 4

PQ6
DTA144EUA_SC70

47K

1 2

PR16 47K_0402_5%

PC10

VIN

PQ4
AO4407_SO8

1
2
3 6

PR444

220K_0402_5%

2

G

P2

PC138

12

12

PR14
200K_0402_5%

0.1U_0603_16V7K

13

D

PQ120

S

RHU002N06_SOT323

PR20
150K_0402_5%

1 2

PD33

1N4148_SOD80

ADP_EN# 48

12

ACDET

4

12

13

47K

2

BATCAL#48

1 2

47P_0402_50V8J

1 2

12

PR44

100K_0603_1%

2.15K_0402_1%

1 2

12

PR240

VL

3

+

2

-

PR49

12.4K_0603_0.1%

12

12

PR62

PR55
130K_0402_1%

12

PC26

10K_0603_1%

22P_0402_25V8K

1 2

8

5

P

+

6

-

G

4

PR67

1 2

33K_0402_1%

4

REF

5

ANODE

LMV431ACM5X_SOT23-5

A

CHGLIM48

CHGCTRL34,42

PR42

330K_0402_5%

8

PU5A

P

1

O

G

LM393DG_SO8

4

PR56
1M_0402_5%

PU5B

7

O

LM393DG_SO8

VL

PU6

CATHODE

NC
NC

P2

8
7

5

PR31

1 2

191K_0402_1%

3
2
1

8
7

5

ACDRV#

ADP_PRES

12

AC_CHG

1.24VREF

PR45

PQ5

AO4407_SO8

4

PR17

0_0402_5%

1 2

@

PQ124

RHU002N06_SOT323

2

G

PR18

0_0402_5%@

1 2

AC_CHG

12

PC15

1 2

1U_0603_6.3V6M

+3VL

+3VL

12

5

PU4

10K_0402_1%

SN74LVC1G17DBVR_SOT23-5

P

2

O4I

NC

G

3

+3VL

12

PC24

0.1U_0402_16V7K

@

ACDET

12

PR63

47K_0402_1%

@

RHU002N06_SOT323

1
2
36

12

PR21
200K_0402_5%

12

PR22
150K_0402_5%

13

D

S

PR19

0_0402_5%

1 2

+3VL

PR35

137K_0402_1%

12

PC20

1U_0603_6.3V6M

PC22

0.1U_0402_10V6K

1

PQ12

2

G

AC_CHG 42

P4

PR372

0.015_2512_1%

1 2

12

PR338
100_0402_1%

1 2

PC198

1U_0603_6.3V6M

1 2

PR339
1K_0402_1%

PR29

1K_0402_1%

ALARM

PR32

100K_0402_5%

BQ24703VREF

12

PR36

100K_0402_1%

12

12

PC18

PR41

4.7U_0805_6.3V6K

80.6K_0402_1%

ADP_PRES 17,24,34,42,43,48

+3VL

12

PR52

4.7K_0402_5%
PR58

1 2

100K_0402_5%

12

PQ13

2

G

13

13

D

S

12

12

PC21

150P_0402_50V8J

BQ24703VREF

PR61
100_0402_5%

D

RHU002N06_SOT323

S

B+

PL2

FBM-L11-322513-151LMAT_1210

1 2

ACN 48

PU2

8

ACN

9

ACP

26

ACDET

5

ENABLE

28

ACSEL

19

ALARM

BATDRV#

2

SRSET

3

ACSET
ACPRES27VHSP

13

IBAT

4

VREF

7

COMP

10

NC1

11

NC2

BQ24703RHDR_QFN28_5X5

12

PR43
150_0402_1%

12

12

PC23

4.7U_0805_10V6K

ALARM 42

B

ACDRV#

VCC

PWM#

SRN

BATP

BATSET

BATDEP

GND

BATT

P2

PR15

0_0402_5%

1 2

PQ3
AO4407_SO8

1
2
3 6

4

8
7

5

CHG_B+

PR26

0_0402_5%

12

PC14

4

1U_0805_25V4Z

DH_CHG

3

PQ8

S1S2S

G

FDS4435_SO8

D8D7D6D

5

LX_CHG

1 2

16UH_SIL1045R-160_4.1A_30%

12

PD8
EC31QS04

PL3

12

SRP

NC4
NC3

12

12

PC11

PC12

10U_1206_25V6M

RLZ16B_LL34

ACDRV#

25
22
21
16
15
12
24

18

VS

20
29

TP

6
1
17
23
14

12

4.7U_1206_25V6K
PD6

2 1

SE_CHG+

SE_CHG-

BATTBATT

12

PR47

12

PR51

154K_0402_1%

12

12

PR59

PC25

20K_0402_1%

300K_0603_0.1%

12

PR50

31.6K_0603_0.1%

12

12

PR439
24K_0603_0.5%

100P_0402_50V8J

PC205

470P_0402_50V7K

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

C

PR33

0.015_1206_1%

1 2

PR38

3K_0402_1%

PC19

1 2

0.1U_0402_16V7K

BATT

12

PR39

3K_0402_1%

12

PC16

PC17

10U_1206_25V6M

10U_1206_25V6M

12

CV=16.8V (8 CELLS LI-ION)
CC=3.73A when duty f or CHGCTRL is 100%

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

LA-3331P

Charger

D

of

41 59Tuesday, May 1 5, 2007

A

4

B

C

D

+3VL

1 1

+3VL

ALARM41

PR70

BATSELB_A

BATSELB_A#

2 2

PC28

1 2

1000P_0402_50V7K

PC30

1 2

1000P_0402_50V7K

PQ17

PR72

1 2

22K_0402_5%

PR73

1 2

PQ18

22K_0402_5%

RHU002N06_SOT323

13

2

G

13

2

G

47K_0402_5%

1 2

D

RHU002N06_SOT323

S

D

S

RHU002N06_SOT323

PQ19

13

D

S

5

PU8

1

P

INB

2

INA

G

74LVC1G02_04_SOT353

3

2

ADP_PRES 17,24,34,41,43,48

G

4

O

+3VL

1

5

PU9

P

NC

4

A2Y

G

SN74LVC1G14DCKR_SC70-5

3

1

INB

2

INA

+3VL

5

1

PU10

BATSELB_A#34

BATSELB_A#

+3VL

+3VL

12

3 3

CHGCTRL

,41

PR408

1K_0402_5%

PC221

12

1 2

1000P_0402_50V7K

PC220

0.047U_0402_16V7K

12

PR407

1 2

470K_0402_1%

2

G

PD14

1N4148_SOD80

PR83

1 2

470K_0402_1%

13

D

S

PQ110

RHU002N06_SOT323

5

1

PU12

P

NC

4

A2Y

G

SN74LVC1G14DCKR_SC70-5

3

AC_CHG41

P

NC

4

A2Y

G

SN74LVC1G14DCKR_SC70-5

3

PR84

10K_0402_1%

1 2

RHU002N06_SOT323

ADP_PRES

BATSELB_A

PQ30

S

G

2

12

PC197

220P_0402_50V7K

PR82

1 2

220K_0402_5%

BATSELB_A#

D

13

+3VL

PD17

CFET_A

2
3

RB715F_SOT323

1

12

4 4

CFET_B

5

PU14

P

2

O4I

1

NC

G

SN74LVC1G17DBVR_SOT23-5

3

BATCON 34

12

PC27

5

PU7

P

4

O

G

@

74LVC1G02_04_SOT353

3

+3VL

5

1

P

IN1

O

2

IN2

G

PU11

SN74AHC1G08DCKR_SC70

3

+3VL

5

1

P

IN1

O

2

IN2

G

PU13

SN74AHC1G08DCKR_SC70

3

0.1U_0402_10V6K

4

4

BATT_B

RHU002N06_SOT323

PQ16

S

G

+3VL

PR78

1 2

10K_0402_5%

PQ26

BATT_IN

RHU002N06_SOT323

PR88

1 2

10K_0402_5%

CFET_B

BATT_IN

BATT_A

D

13

2

CFET_A

2

G

PQ34

2

G

PD9

2
3

RB715F_SOT323

PQ23

2

G

13

D

S

13

D

S

1

BATT

12

PR74
470K_0402_5%

2

12

PR76

1 2

10K_0402_5%

13

D

RHU002N06_SOT323

S

BATT

12

PR81
470K_0402_5%

2

12

PR87

1 2

10K_0402_5%

13

D

PQ31

2

RHU002N06_SOT323

G

S

RHU002N06_SOT323

PR68

1 2

100_0402_5%

1

PQ21

PMBT2222A_SOT23-3

3

PD12

1N4148_SOD80

1

PQ29

3

PD16

1N4148_SOD80

RHU002N06_SOT323

12

PC29

0.1U_0603_50V4Z

PR75
470K_0402_5%

1 2

PMBT2222A_SOT23-3

PR85

1 2

470K_0402_5%

D

1 3

12

PR71

1.5M_0402_5%

PD13

B540C_SMC
PQ24

AO4407_SO8

1
2
3 6

1
2
3 6

PQ15

S

G

2

21

4

PQ27

AO4407_SO8

4

PD15

B540C_SMC

PR69

1 2

0_0402_5%

PD11
RLZ6.2C_LL34

2 1

RHU002N06_SOT323

RHU002N06_SOT323

8
7

5

8
7

5

21

RHU002N06_SOT323

RHU002N06_SOT323

8
7

5

8
7

5

BATT_IN

PD10
1N4148_SOD80

1 2

PQ20

2

PQ22

2

PQ25

AO4407_SO8

PQ28

AO4407_SO8

PQ32

PQ33

BATT_IN

BATT_IN

G

G

4

4

2

G

2

G

13

D

S

13

D

12

S

1
2
36

1
2
36

PR77

4.7K_0402_5%

12

PR79
470K_0402_5%

12

PR80
470K_0402_5%

BATT_A

BATT_B

12

PR86

4.7K_0402_5%

13

D

S

13

D

S

PR237

100K_0402_5%

A

B

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Battery selector

LA-3331P

D

of

42 59Tuesday, May 1 5, 2007

5

4

3

2

1

B+

12

PL4

FBM-L11-322513-151LMAT_1210

D D

B++

12

12

PC44

PC45

10U_1206_25V6M

2200P_0402_50V7K

10UH_SIL1045RA-100PF_4.5A_30%

PL6

AO4916_SO8

1

D2

2

D2

D1/S2/K

3

G1

D1/S2/K

4

D1/S2/K

S1/A

PQ38

1 2

PC36

0.1U_0603_50V4Z

DH_5V_2

8

G2

7
6
5

12

LX_5V

+5VALWP

C C

2VREF_1999

1

+

2

PC199

150U_B2_6.3VM_R35M

B B

1 2

1 2

PR410

@10.2K_0402_1%

PR411

0_0402_5%

PR414

47K_0402_5%

B++

12

12

VL

PC224

0.1U_0603_25V7K

PR413

499K_0603_1%

12

12

0_0402_5%

1 2

ADP_PRES17,24,34,41,42,48

MAINPWON

PC223

0.1U_0603_16V7K

RHU002N06_SOT323

PR416

MAINPWON 47

PR104

0_0402_5%

1 2

LX_5V 48

1 2

10K_0402_5%@

PQ39

PR412

13

D

S

BST_5B

PR415

@0_0402_5%

1 2

PR451

+3VL

PR107

100K_0402_5%

2

G

D

S

1 2

BST5A

DH_5V_1

DL_5V

2VREF_1999

1 2

300K_0402_5%

12

13

ADP_PRES

2

G

PQ40

RHU002N06_SOT323

PR409
0_0402_5%

12

PC222

3

1

CHP202U_SC70

VL

1

2

PC227

4.7U_0805_10V4Z
PU37

14

BST5

16

DH5

15

LX5

19

DL5

21

OUT5

9

FB5

1

N.C.

6

SHDN#

4

ON5

3

ON3

12

SKIP#

8

REF

0.22U_0603_10V7K

13

D

S

RHU002N06_SOT323

2

PD41

B++

18

2

G

PQ41

LD05

KBC_PWR_ON34

1 2

12

0.1U_0603_50V4Z

PC228

13

20

17

V+

VCC

TON

PGOOD

GND

PRO#

LDO3

23

10

25

1

2

PC225

1 2

4.7U_0805_10V4Z

BST3B

VL

12

PC230

0.1U_0603_16V7K

PR424

47_0402_5%

2VREF_1999

12

PC229

1U_0805_16V7K

5

ILIM3

11

ILIM5

28

BST3

26

DH3

24

DL3

27

LX3

22

OUT3

7

FB3

2

MAX8734AEEI+_QSOP28

+3VLP

PR417
0_0402_5%

1 2

1 2

PR418

PR419

499K_0402_1%

1 2

220K_0402_1%

1 2

PR425

0_0402_5%

PR420

220K_0402_1%

PR421

499K_0402_1%

1 2

BST3A

DH_3.3V_1

PC231

0.1U_0603_50V4Z

1 2

B++

12

12

PC33

PC34

2200P_0402_50V7K

DH_3.3V_2

12

PR100
0_0402_5%

SI4800BDY_SO8

DL_3.3V

4.7U_1206_25V6K

PQ37

LX_3.3V

5

D8D7D6D

S1S2S3G

4

5

D8D7D6D

SI4800DY_SO8
PQ123

S1S2S3G

4

12

PL5

4.7UH_SIQB74B-4R7PF_4A_20%

+3VALWP

1 2

1 2

PR422

@3.57K_0402_1%

PR423

0_0402_5%

1

+

PC39

2

150U_B2_6.3VM_R45

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

3.3VALW/5VALW

LA-3331P

1

of

43 59Tuesday, May 1 5, 2007

A

B

C

D

MAX8743_B+

12

12

PC57

4.7U_1206_25V6K

CHP202UPT_SOT323-3

PC192

0.1U_0603_50V4Z

1 2

PD39

PR342

1

PD31

2

3

BST_1.25V_1

1 2

BST_1.25V_2

PR330

0_0402_5%

12

PR331
0_0402_5%

DH_1.25V_1
LX_1.25V LX_1.5V

MAX8743EEI+T_QSOP28~N

12

VCC_MAX8743

PC201

0.001U_0402_50V7M

@

PQ79
SI4800BDY_SO8

PC189

2200P_0402_50V7K

DH_1.25V_2

DL_1.25V

1 2

1SS355_SOD323

1 2

0_0402_5%

1 1

5

D8D7D6D

S1S2S3G

D8D7D6D

S1S2S3G

4

5

4

PL22

+1.25VMP

1

12

+

PC191

2

2 2

330U_2V_M_R15M

PR257

10K_0402_1%

3.3UH_PCMB104E-3R3MS_11A_20%

PC145

12

4.7U_0805_6.3V6K
PR329

2.61K_0402_1%

12

12

SI4810DY_SO8

PQ78

PM_SLP_M#21,34,37,45,49

3 3

0_0402_5%

1U_0805_50V4Z

PC190

PC194

0.1U_0603_50V4Z

PU28

25
26
27

24
28

1
2

11

0_0402_5%

@

PR328

12

BST1
DH1
LX1

DL1
CS1

OUT1
FB1

ON1

PR265

12

OVP

8

12

PR268

0_0402_5%

1 2

12

4

1U_0805_16V7K

V+

GND

23

20_0603_5%

VCC_MAX8743

PC195

22

VCC

SKIP

6

2VREF

12

12

PR332

9

VDD

UVP

BST2

DH2
LX2
DL2
CS2

OUT2

FB2

ON2

PGOOD

TON

ILIM2
ILIM1

REF

PR262

10

20K_0402_1%

PR263

0_0402_5%

12

PC147

0.22U_0603_10V7K

+5VALW

BST_1.5V_1

21
19

18
17
20
16

15
14
12

7
5

13
3

12
12

PR266

100K_0402_1%

12

BST_1.5V_2

PR327

0_0402_5%

1 2

DH_1.5V_1

12

PC186

4.7U_1206_16V4Z

PR333
0_0402_5%

1 2

0_0402_5%

12

PR267

100K_0402_1%

PC144

0.1U_0603_50V4Z

12

DH_1.5V_2

DL_1.5V

12

PR319

PQ86

SI4800BDY_SO8

5

D8D7D6D

S1S2S3G

4

5

D8D7D6D

S1S2S3G

4

3.3UH_SIQB74B-3R3PF_5.9A_20%

SI4800DY_SO8
PQ122

PD40

1SS355_SOD323

PR340
0_0402_5%

12

PC200

0.001U_0402_50V7M

@

PL21

1 2

12

12

PL23

FBM-L11-322513-151LMAT_1210

12

12

PC188

2200P_0402_50V7K

12

12

PR258

5.1K_0402_1%

PR261

10K_0402_1%

12

PC203

SLP_S3# 17,21,24,29,30,34,36,37,45,46,48,49

B+

4.7U_1206_25V6K

PC185

+1.5VSP

1

+

2

220U_B2_2.5VM

1.5VSP/ +1 .25VMP

PJP1

+1.5VSP

+1.8VP

+1.25VMP

4 4

+0.9VP

1 2

PAD-OPEN 3x3m
PJP3

PAD-OPEN 4x4m

1 2

PJP5

PAD-OPEN 4x4m

1 2

PJP12

PAD-OPEN 4x4m

1 2

PJP7

1 2

PAD-OPEN 3x3m

+1.5VS

(4A,160mils ,Via NO.=8)

(7A,280mils ,Via NO.= 14)

+1.8V

(7.4A,300mils ,Via NO.= 15)

+1.25VM

(2A,80mils ,Via NO.= 4)

+0.9V

A

+5VALWP

+3VALWP

+3VLP

PJP2

1 2

PAD-OPEN 4x4m
PJP4

1 2

PAD-OPEN 4x4m

PJP6

2 1

PAD-OPEN 2x2m

B

+5VALW

(4.5A,180mils ,Via NO.= 9) (4.7A,180mils ,Via NO.= 9)

+3VALW

(3A,120mils ,Via NO.= 6)

(100mA,20mils ,Via NO.= 1)

+3VL

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.05V_VCCP +VCCP

+1.05VMP

2005/03/10 2006/03/10

PJP14

1 2

PAD-OPEN 4x4m

PJP15

2 1

PAD-OPEN 2x2m

Compal Secret Data

Deciphered Date

C

(1A,40mils ,Via NO.= 2)

+1.05VM

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

1.5VS/1.25VMP

LA-3331P

D

of

44 59Tuesday, May 1 5, 2007

5

D D

4

3

2

1

DDR_B+

+1.8V

12

12

PR242

0_1206_5%

1

VLDOIN

12

12

PC127

10U_0805_10V4Z

C C

+0.9VP

V_DDR_MCH_REF7,13,14

+5VALWP

B B

A A

12

PC129
22U_1206_6.3V6M

PR324

0_0402_5%

1 2

PC128

10U_0805_10V4Z

12

PC130

0.033U_0402_16V7K

2

VTT

3

VTTGND

4

VTTSNS

5

GND

6

MODE

7

VTTREF

8

COMP

9

VDDQSNS

10

VDDQSET

TPS51116_HTSSOP20

PU27

VBST

DRVH

DRVL

PGND

V5IN

PGOOD

BST_1.8V_1 BST_1.8V_2

20

DH_1.8V_1

19

18

LL

17

16

15

CS

14

13

12

S5

11

S3

0_0402_5%

1 2

0_0402_5%

1 2

LX_1.8V

DL_1.8V

12

PC136

0.001U_0402_50V7M@

PR231

PR230

12

PC122

4.7U_0805_10V6K

PR234
0_0402_5%@

PR314

0_0402_5%

PR236

0_0402_5%@

PR323

0_0402_5%@

PR450

0_0402_5%

12

PC137

0.001U_0402_50V7M@

PC121

0.1U_0603_50V4Z

1 2

DH_1.8V_2

12

PC123

0.001U_0402_50V7M

12

12

12

12

12

12

5

D8D7D6D

PQ63

S1S2S3G

SI4800BDY_SO8

4

PL16

2.2UH_PCMC063T-2R2MN_8A_20%

1 2

5

D8D7D6D

SI4810DY_SO8
PQ64

S1S2S3G

4

PR233

20K_0603_1%

PR232

3_0402_5%

12

SLP_S5# 21,37

SLP_S4# 21,37

SLP_S3# 17,21,24,29,30,34,36,37,44,46,48,49

SLP_S4# 21,37

PR436

100K_0402_5%

1 2

PR437

0_0402_5%

1 2

PM_SLP_M# 21,34,37,44,49

+3VALW

1.8PGOOD 38

12

PC125

2200P_0402_50V7K

+5VALWP

PL15

FBM-L11-322513-151LMAT_1210

PC124
10U_1206_25V6M

1

+

2

PC204

12

220U_D2_4VM

12

PC133

12

12

22P_0402_50V8J

12

B+

+1.8VP

PR388
@0_0402_5%

1 2

PR389

0_0402_5%

14.7K_0603_0.1%
PR238

10K_0603_0.1%
PR239

+1.8V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/10 2006/03/10

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

2

Date: Sheet

Compal Electronics, Inc.

1.8V/0.9VS

LA-3331P

45 59Tuesday, May 15, 2007

1

of

8

7

6

5

4

3

2

1

+CPU_B+

H H

+CPU_B+

PR269
10_0603_5%

G G

+5VS

10_0603_5%

PR273

1 2

PR291

PR296

12

PC180

12

12
12
12
12

0_0402_5%

12

PR304

12

12

12

12

12

12

PC168

PR299
0_0402_5%

12

PC158

1U_0603_10V6K

NTC

12

12

12

5.11K_0603_1%

F F

PC184

NTC

12

0.01U_0402_16V7K

H_PROCHOT#4,47

E E

CPU_VID05
CPU_VID15
CPU_VID25
CPU_VID35
CPU_VID45
CPU_VID55
CPU_VID65

H_DPRSTP#5,7,20

DPRSLPVR7,21

D D

SLP_S3#

9

H_PSI#5

PGD_IN34

CLK_ENABLE#21

PWR_GD17,21,27,34,37,38,48

PR279

4.22K_0603_1%

0.015U_0402_16V7K

147K_0402_1%

12

0_0402_5%
0_0402_5%

0_0402_5%

0_0402_5%

VCCSENSE5

+VCC_CORE

PR315

100_0402_1%

C C

B B

VSSSENSE5

PR316

100_0402_1%

12

12

PR298

180_0603_1%

12

PC179

1 2

220P_0402_25V8K

1800P_0402_50V7K

PR278

12

PC164

12

PR282

12

PR284

12

PR286

12

PR289

PR292

0_0402_5%

PR295 0_0402_5%

PR445 0_0402_5%@

1000P_0402_50V7K

PC173

1 2

1 2

PC176

0.022U_0402_16V7K

PR277

0_0402_5%

PH2
470KB_0402_5%_ERTJ0EV474J

PR281

0_0402_5%

PR283

0_0402_5%

PR285

0_0402_5%

PR288

0_0402_5%

12

499_0402_1%

12

PR294

12

12

0_0402_5%

PC167

1000P_0402_50V7K

PR300

1.2K_0402_1%

51K_0603_1%

1000P_0402_50V7K
PR307

6.98K_0402_1%

1 2

12

0.01U_0402_25V7K
PC156

19

20

18

VSS

VDD

4

VR_TT#

3

RBIAS

5

NTC

6

SOFT

PU31

28

VID0

29

VID1

30

VID2

31

VID3

32

VID4

33

VID5

34

VID6

37

DPRSTP#

36

DPRSLPVR

1

PSI#

2

PGD_IN

38

CLK_EN#

35

VR_ON

12

VSEN

13

RTN

11

VDIFF

ISL6260CRZ-T_QFN40_6X6

10

FB

9

COMP

8

VW

41

TP

DROOP

14

PR310

12

PC183

12

330P_0402_50V7K

+3VS

39

VIN

3V3

PWM1

ISEN1

PWM2

ISEN2

FCCM

PWM3

ISEN3

OCSET

VSUM

DFB15VO

1K_0402_1%

PR275

1.91K_0603_1%

1 2

1 2

40

PGOOD

27

23

26

22

24

25

21

7

17

16

VO

PR311

12

PR326
0_0402_5%

VSUM

12

PR303

4.53K_0402_1%

PWM1

ISEN1

PWM2

ISEN2

0_0402_5%

PC178

0.22U_0603_16V7K

PR312

1 2

PM_PWROK 7,21,34

VGATE 7,21

12

+5VS

11.5K_0402_1%

PC177

1 2

1000P_0402_50V7K

12

12

0.1U_0402_16V7K

PC182

PR297

PH3

12

12

PR301

3K_0402_1%

12

PR308

1K_0402_1%

@

10KB_0603_5%_ERTJ1VR103J

+5VS

12

PC154

1U_0603_10V6K

+5VS

12

PC163

PU30

5

VCC

6

FCCM

2

PWM

3

GND

ISL6208CRZ-T_QFN 8

1U_0603_10V6K

PU32

5

VCC

6

FCCM

2

PWM

3

GND

ISL6208CRZ-T_QFN8

BOOT

UGATE

PHASE
LGATE

BOOT
UGATE
PHASE

LGATE

1
8
7
4

0_0402_5%

BST_CPU1_1

DH_CPU1
LX_CPU1

BST_CPU2_1

1

DH_CPU2

8

LX_CPU2

7
4

PR270

DL_CPU1

PR280

0_0402_5%

DL_CPU2

12

BST_CPU1_2

0.22U_0603_16V7K

1 2

12

BST_CPU2_2

0.22U_0603_16V7K

1 2

PC155

PC165

3 5

241

PQ81

IRF7832PBF_SO8

PQ84

PC248

PQ80
SI7840DP-T1-E3_SO8

5

D8D7D6D

S1S3G

S

4

2

3 5

241

5

D8D7D6D

S1S3G

S

4

2

IRF7832PBF_SO8

12

12

PC244

10U_1206_25V6M

22U_1210_25V6M@

@

5

D8D7D6D

PQ82

S1S3G

S

4

2

IRF7832PBF_SO8

PQ83
SI7840DP-T1-E3_SO8

5

D8D7D6D

S1S3G

S

4

2

PC243

22U_1210_25V6M@

PC240

PC159

PQ85

12

PC150

0.01U_0402_50V4Z

PR446

1 2
12

680P_0603_50V8J

12

PC160

0.01U_0402_50V4Z

IRF7832PBF_SO8

PC241

680P_0603_50V8J

12

12

PC152

PC151

10U_1206_25V6M

2200P_0402_50V7K

P_0.36H_ETQP4LR36WFC_24A_20%

1 2

PR272

10K_0402_1%

4.7_1206_5%

1 2

PR274

5.11K_0402_1%

1 2

VSUM

12

12

PC162

PC161

10U_1206_25V6M

2200P_0402_50V7K

PR447

10K_0402_1%

1 2

1 2

4.7_1206_5%

12

PR293

5.11K_0402_1%

1 2

VSUM

PL24

FBMA-L18-453215-900LMA90T_1812

1 2

PC157

12

PR317

@

0_0402_5%

PL20

0.22U_0603_16V7K

@

PC242

100U_25V_M

12

PC166

PR318

0_0402_5%

1

+

2

12

12

12

12

PC153

10U_1206_25V6M

PL19

0.22U_0603_16V7K

+CPU_B+

12

10U_1206_25V6M

P_0.36H_ETQP4LR36WFC_24A_20%

1 2

PR290

PC247

22U_1210_25V6M@

PR271
10_0402_1%

1 2

VO

B+

12

PC245

22U_1210_25V6M@

PR287
10_0402_1%

1

12

+

2

+VCC_CORE

+VCC_CORE

PC196

68U_25V_M

12

PC246

22U_1210_25V6M@

1 2

VO

A A

8

7

6

5

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

4

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

3

Compal Electronics, Inc.

Title

Size Docu me n t N u m ber Re v

C

LA-3331P

Date: Sheet

2

CPU_CORE

of

46 59Tuesday, M ay 1 5, 2007

1

A

B

C

D

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C

1 1

PCN2

1

BATT+

SMD
SMC

RES

GND

TYCO_C-1746706_6P

2 2

TS

2
3
4
5

6

100_0402_5%

EC_SMD_A

EC_SMC_A

PR188

12

PR189

100_0402_5%

3
2

3
2

PD27

12

@SM05_SOT23

PR186
1K_0402_5%

12

PD43 SM24_SOT23@

1

2

3

1

PD26
SM24_SOT23@

1

12

PC104
1000P_0402_50V7K

THM_MAIN# 34

12

PC105

0.01U_0402_50V4Z

0.22U_0603_10V7K

BATT_A

PC107

CPU

12

Recovery at 43 +-3 degree C

+5VS

12

PH1

10K_TH11-3H103FT_0603_1%

PR190
15K_0603_1%

+5VS

12

PR192

2.55K_0603_1%

1 2
1 2

PR191
150K_0402_1%

PR193

150K_0402_1%

12

Vref

12

PC108
1000P_0402_50V7K

PR185

47K_0402_1%

1 2

5

+

6

-

8

PU21B

P

0

G

LM358ADR_SO8

4

MAINPWON 43

13

D

7

2

G

S

PQ56
RHU002N06_SOT323

EC_SMD_A1

EC_SMC_A1

PCN3

3 3

1

BATT+

SUYIN_20163S-06G1-K

4 4

SMD
SMC

GND

B/I
TS

EC_SMD_B

2

EC_SMC_B

3

AB/I_B

4

TS_B

5
6

PR200

100_0402_5%

PR194

1K_0402_5%

PR197
1K_0402_5%

PD20

1 2

3

12

100_0402_5%

2

@SM05_SOT23

EC_SMD_B1

EC_SMC_B1

12

PR201

12

1 2

PR195

210K_0402_1%

1

AB1A_DATA 34
AB1A_CLK 34

+3VL

BATT_B

2

3

PD19
SM24_SOT23@

1

12

PC109
1000P_0402_50V7K

THM_MBAY# 34

AB1B_DATA 34
AB1B_CLK 34

12

PC110

0.01U_0402_50V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

+5VS

PR426

47K_0402_1%

1 2

+5VS

12

PC106

0.1U_0402_10V6K
PU21A

3

Vref

2

LM358ADR_SO8

RAM

12

PC233

0.22U_0603_10V7K

12

PH4

10K_TH11-3H103FT_0603_1%

12

PR430

2.55K_0603_1%

PR429
15K_0603_1%

1 2

PH4 under RAM botten side :

RAM thermal protection at 90 +-3 degree C
Recovery at 43 +-3 degree C

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

C

PR448

12

0_0402_5%

PR449

12

0_0402_5%

8

P

+

1

0

-

G

4

Title

Size Document Number R e v

Custom
Date: Sheet of

@

13

D

2

G

S

PQ111
RHU002N06_SOT323

Compal Electronics, Inc.

BATTERY CONN

LA-3331P

D

PM_EXTTS#1 7,14

H_PROCHOT# 4,46

47 59Tuesday, May 15, 2007

5

4

3

2

1

D

S

G

2

12

220K_0402_5%

2

G

ADP_PRES

of

+5VS

12

PR384

220K_0402_5%

PD36

CH355PT_SOD323-2

1 2
13

D

S

PQ107

RHU002N06_SOT323

21

+3VS

+3VS

12

PR363
10K_0402_5%

+3VS

12

PR364
10K_0402_5%

PQ105

NDS0610_SOT23

1 3

PR387

LX_5V 43

ADP_PS0 34

ADP_PS1 34

48 59Tuesday, May 15, 2007

D D

8

PU24A

3

P

+

1

0

2

-

G

LM358ADR_SO8

4

PR210

1 2

0_0402_5%

PR209

12

PC118

1U_0805_50V4Z

C C

ADP_SIGNAL

B B

VIN

12

PR344
100K_0402_1%

PR346
1M_0402_5%

1 2

12

PR345
10K_0603_1%

PQ100

12

RHU002N06_SOT323@

13

D

A A

PR367

0_0402_5%

S

MXM_CD1# 17,21

2

G

12

12

PR348

100K_0402_1%

PR349

10K_0402_1%

PR347
226K_0402_1%

VIN

12

PR381

40.2K_0402_1%

12

12

0_0402_5%

B+

12

P4

1 2

10K_0402_1%

12

PC119

12

NDS0610_SOT23

S

PR391
287K_0402_1%@

1 2

PR213

2.2U_0603_6.3V6K

PR226
0_0402_5%

PQ96

D

G

2

5

+

6

-

PR211

6.81K_0402_1%

1 2

PR214

100K_0603_0.5%

4

REF

5

ANODE

ADP_PRES 17,24,34,41,42,43

13

VIN

8

PU33A

3

P

+

O

2

-

G

LM393DG_SO8

4

PR350

1M_0402_5%

1 2

8

PU33B

P

7

O

G

LM393DG_SO8

4

5
6

1 2

0.027U_0603_16V7K

PU26

3

CATHODE

2

NC

1

NC

LMV431ACM5X_SOT23-5

2

B

PR373

1 2

124K_0402_1%

E

+3VALW

12

1

12

PR351

47K_0402_5%

PD34

1 2

1N4148_SOD80

ADP_EN# 41

8

PU24B

P

+

0

-

G

LM358ADR_SO8

4

PC116

C

PQ102
MMBT3904_SOT23

3 1

PR354
10K_0402_5%

ADP_ID 34

VIN

12

PR352

220K_0402_5%

2

G

12

PR368

220K_0402_5%

1 2

7

MMBT3906_SOT23

12

PR220

7.87K_0402_1%

12

PR222

215_0603_1%

PD38

CH355PT_SOD323-2

SLP_S3#17,21,24,29,30,34,36,37,44,45,46,49

2

G

+3VALW

12

PR353

47K_0402_5%

13

D

PQ97
RHU002N06_SOT323

S

Security Classification

PR212
0_0402_5%

PQ59

2

12

BATCAL# 41

13

D

PQ121

S

RHU002N06_SOT323

ADP_EN 34

12

PR216

2K_0402_5%

E

3

B

1

12

C

12

PR249

3.9K_0402_5%

PR224

100K_0402_5%

1 2

PR252

3.9K_0402_5%

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PR251

330K_0402_5%

12

8

PU25B

5

P

+

7

O

6

-

G

LM393DG_SO8

4

PR206

1 2

0_0402_5%

CH751H-40PT_SOD323-2@

PWR_GD 17,21,27,34,37,38,46

12

PC206
3900P_0402_50V7K

CHGLIM41

2

B

E

2005/03/10 2006/03/10

+3VS

12

PR377

10K_0402_5%

PD30

21

12

PR390

PR227

1 2

PR225
100K_0402_5%

@

47K_0402_5%

470K_0402_5%

12

PC207
1U_0603_10V6K

ACN 41

1 2

C

PQ62
MMBT3904_SOT23

3 1

Compal Secret Data

Deciphered Date

12

PR207
133K_0402_1%

12

PR218

80.6K_0402_1%

13

D

2

G

S

PR355

470K_0402_5%

12

12

12

12

+5VS

8

3

+

2

-

4

12

PC117

0.01U_0603_16V7K

PR223

1 2

0_0402_5%

PQ61
RHU002N06_SOT323

12

PC202

0.1U_0805_50V7M

+3VS

PR356

71.5K_0402_1%

PR357
21K_0402_1%

PR358

3.48K_0402_1%

2

PR208

1 2

100K_0402_5%

PU25A

P

1

O

G

LM393DG_SO8

1 2

PR217
200K_0603_1%

OCP# 4,21

ACOCP_EN#36

CH751H-40PT_SOD323-2

+5VS

12

PR378
10K_0402_5%

VIN

47K

PR385

150K_0402_5%

PR380

1 2

1K_0402_5%

1M_0402_5%

PR359

10K_0402_5%

1 2

PR361

21K_0402_1%

1 2

1 2

1M_0402_5%

1 2

Title

Size Document Number R e v

Custom

LA-3331P

Date: Sheet

PD21

21

1

7

12

12

PD22

PC115

1U_0805_16V7K

PR221
10_0402_5%

CH751H-40PT_SOD323-2

PQ108

DTA144EUA_SC70

13

47K

2
12

1 2

PR360

PR362

12

PR383

221K_0603_1%

ADP_SIGNAL

PD37
1N4148_SOD80

PD35

1 2

1N4148_SOD80

+5VS

8

PU34A

3

P

+

O

2

-

G

LM393DG_SO8

4

+5VS

8

PU34B

5

P

+

O

6

-

G

LM393DG_SO8

4

Compal Electronics, Inc.

ADP_OCP

1

5

,

D D

+5VALW

12

PC234
1U_0603_6.3V6M

6

VCCP_POK38

30,34,36,37,44,45,46,48

C C

SLP_S3#

1 2

PR431

0_0402_5%

0.01U_0402_16V7K@

1 2

PR433

0_0402_5%

PC238

PU38

7

POK

8

EN

12

APL5912-KAC-TRL_SO8

5

VIN

9

VIN

VCNTL

3

VOUT

4

VOUT

2

FB

GND

1

47K_0402_1%

150K_0402_1%

PR434

PR435

12

12

4

12

PC235
27P_0402_50V8J

+1.25VM

12

PC236
10U_1206_6.3V6M

+1.05V_VCCP

12

PC237
22U_1206_6.3V6M

3

2

1

+5VALW

+3VL

12

B B

M_PROK38

1 2

PR402

0_0402_5%

PM_SLP_M#21,34,37,44,45

0.01U_0402_16V7K@

A A

5

@

1 2

PR403

0_0402_5%

PC239

PR404
10K_0402_1%

PU36

7

POK

8

EN

12

APL5912-KAC-TRL_SO8

12

PC216
1U_0603_6.3V6M

6

5

VIN

9

VIN

VCNTL

3

VOUT

4

VOUT

2

FB

GND

1

150K_0402_1%

PR405

47K_0402_1%

PR406

12

12

4

12

PC217
27P_0402_50V8J

+1.25VM

12

12

PC219
22U_1206_6.3V6M

PC218
10U_1206_6.3V6M

+1.05VMP

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

+1.05V_VCCP/+1.05VMP

LA-3331P

1

of

49 59Tuesday, May 1 5, 2007

5

4

Version Change List ( P. I. R. List ) for Power Circuit

3

2

1

Item

D D

1

Title

41HPCharger

Date

5/9

Request
Owner

Issue Description

Remove PQ91,PD32,PR376

Solution Description

Remove PQ91,PD32,PR376

PU12 Change from SN74LVC1G17DBVR_SOT23-5 to

Rev.Page#

Rev.

SN74LVC1G14DCKR_SC70-5

Battery Selector

42

2

5/9

HP

Modify battery selector design.

Add new location PC220 as 0.047uF
Add new location PC221 as 1000PF
Add new location PR407 as 470K ohm.
Add new location PR408 as 1K ohm.

3

2.5VALW/1.5VS/

44

4

C C

5

1.05VCCP

BATTERY CONN

47

ADP_OCP

48

5/9 HP
5/9 Compal

Compal
Thermal

5/9

team

5/9

HP6

Modify 3.3VALW/5VALW solution

Change solution from TPS51020 to MAX8734A

Remove 2.5VALW, H/W no need! Remove PU20, PC72, PC73

Add RAM thermal protection schematic.

Modify ADP_OCP design

Add new location PH4,PC233,PR430,PR429,PR426,PQ111

Delete PR379,PQ103,PQ104,PR386,PR382,PQ106

3.3VALW/5VALW

43

Swap location PC33, PC44

3.3VALW/5VALW

43

5/9

Compal7

Modify 3.3VALW/5VALW location for layout.

Swap location PC34, PC45
Swap location PQ37, PQ38, PL5 PL6, PR100, PR104, PC39 , PC199.

1.25VM/1.5VS

44

8

B B

9
10

11
12

13
14

A A

15

1.05V_VCCP/

49

1.05VS

45
41 HP

42
47

45
46

1.8V/0.9VS
Charger

Battery selector

BATTERY CONN

1.8V/0.9VS
CPU_CORE HP request.

5

5/29
5/29

6/2
6/6

6/6
6/6

6/7
6/21

Compal
Compal

HP

HP
HP

HP
HP

Layout concern. Modify 1.05V_VCCP/1.25VM solution

Layout concern.

HP request to follow Chimay.

Modify 1.05V_VCCP/1.25VM solution.
Modify 1.8V/0.9VS schematic.

HP request ! Modify Charger schematic.
HP request ! Modify selector schematic.

HP request ! Modify main battery power in schematic.

At S3 mode, 0.9V need exist, so connect PR242 to 1.8V Mod ify PR242 connect to 1.8V

Modify PU31.35 pin connect to SLP_S3#, originally is connect to VR_ON.

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/28 2007/02/28

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Changed-List History-1

LA-3331P

1

50 59Tuesday, May 1 5, 2007

of

0.5

5

4

Version Change List ( P. I. R. List ) for Power Circuit

3

2

1

Item

D D

41HPCharger

16

47

17

43/44

18

41 Charger

19

Title

BATTERY CONN

Date

5/9

9/7

03/29 Compal

20 03/30 Compal

C C

04/0221
04/0222

04/02

Request
Owner

Compal

Compal11/1

Compal
Compal

Compal23
Compal04 /0224
Compal04 /0225

Issue Description

Solution Description

Change PQ114 to BSS138. Change PQ114 to BSS138.

Intel Document for the DDR Module Thermal Diode design

Dual N MOSFET has failure rate at other project,
to reduce Dual N MOS useage.

Rese rve s om e c om pon en t s fo r EP A. Res erve PR21, PR 22, PQ124 and PR19.

DFx request m odify footprint to prevent shift issue.

For ADP OCP setting.

For ADP OCP setting.
For ADP OCP setting.
For ADP OCP setting.

Change the PQ111.1 connection from H_PROCHOT# to PM_EXTTS#1

Change 3V, 1.5V solution, to single N Mos FET solution.

Modify PD10,PD12,PD14,PD16,PD33,PD34,PD35,PD37(SC11N414880) footprint from SOD80 to LL34.

Unistall Un install PR1, PR17 and PR18.And install PR19,PR21,PR22,PQ124.For Energy star

Change PC116 from 0.22U_0603_16V_X7R to 0.027U_0603_16V_X7R.

Change PR222 from 422 ohm 1% to 215 ohm 1%.

Change PC117 form 0.027U_0603_16V_X7R to 0.01U_0603_16V_X7R.

Change PR217 from 604K_0603_1% to 200K_0603_1%

Rev.Page#

B B

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/28 2007/02/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

Changed-List History-1

LA-3331P

1

51 59Tuesday, May 1 5, 2007

0.5

of

5

4

Version Change List ( P. I. R. List ) for HW Circuit

3

2

1

Item Issue DescriptionDate

26

1

D D

2 4 GIGA LAN

2

Title

Mini Express Card

Owner

7/3

Compal

7/4 Compal

H28 & H29 size different. Change H28 size to same as H29. 0. 2
BOM Leverage to Chimay.

Solution Description

Chnage Y8 to 25MHz_20P_1BG 25000CK1A
(Same as Chimay)

1 8 GPI O Extender

3
4
5
6
7
8
9

Capacitive I2C34
FSB SEL15
RTC Conn20

33

NUM_LED#

30

Head Phone Add circuit for this issueANTI-POP noise

26

WLAN Add R2158 connect to +3VS and connect to JP30 pin

7/4 Compal
7/27 H P
7/27 H P
7/26 Compal
7/25 Compal
7/26

HP

7/27

Use wrong package with BOM (U59). Correct the package. 0. 2

Change R1918, R1919 & add R2174 to 330 ohm. 0. 2
No good for layout quality. 0.2
Wrong Package 0.2

Del R1719, R1726.

Change JP28 from SP02000D000 to SP02000D700.
System auto re-boot Add R2168 pull up to 3VL. 0. 2

Rev.Page#

0.2

0.2

0.2

2,39,41,52 , pin37,43 connect to GND.

Request

C C

B B

18

10
11
12
13
14
15
16
17
18
19
20

Quick Switch
21 CPU Clock
1 8 Quick Switch
06 VCCP
21 CL_VREF1_ICH
31 USB
1 8 Quick Switch
38 Power Good
21 Power Good
07 C lock
2 7 CardBus Controller

7/26

Compal
7/28 Compal/HP
7/28 Compal
8/1 Compal
8/2 Compal
8/2 Compal
8/3HPHP
8/4 Compal
8/7 Compal
8/11 Compal
8/15. Compal

Wrong package for PCB foot print (U57). 0.2Correct the package.

Add R2173 & reserve C1576.VRMPWRGD has glich to cause wrong CPU clk. 0. 2

Channel A & B will twist togeter as current layout. Swap Channel A & B on schematic. 0. 2

Delete C1570 ~ C1573 0. 2
Wrong pull high to +3VM.(R1855) Change pull up to +3VALW.
No pull up resistor for USB power switch OC pin. Add R2175 and pull up to +5VALW.

0.2

0.2

Add U61 and Rese rved R2176 for Q-switch select pin. 0 . 2
VCC1_PWRGD has glich when power on. Reserve C1577 on PWRGD to GND. 0. 2
CLK_ENABLE# has glich when power on. Change R1862 from 330ohm to 1K ohm. 0 . 2
CLK_MCH_3GPLL/CLK_ MCH_3GPLL# reversed. Correct CLK_MCH_3GPLL/CLK_MCH_3GPLL#. 0. 3
Easy confl ict with other device that use same IRQ. Chnag e connect from PCI_PIRQB# to PCI_PIRQG#. 0 .3

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/28 2007/02/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

HW Changed-List History-1

LA-3331P

1

52 59Tuesday, May 1 5, 2007

1.0

of

5

4

Version Change List ( P. I. R. List ) for HW Circuit

3

2

1

Item Issue DescriptionDate

07 C lock

1

D D

2 7 CardBus Controller

2

21 USB

3

34 PGD_IN

4

3 4 EC VCC0(PIN 68)

5

34

6

3 3 SPI ROM

7

26 MINI Card

8

2 1 Power Sequency

9

21 GPI O26

10

21 GPI O17

11

C C

B B

21 STP_CPU#

12

2 1 XDP_DB RESET#

13

21 SPI_CS1#

14

17 MXM-HE

15

17 HDMI

16

21 GPI O12

17

2 1 GPIO1 & GPIO11

18

2 8 Card bus ETD test May some issue with ETD test. Reserved C1509. 0. 3

19

3 5 KBD Connector

20

10 L22

21

2 6 Wireless LAN

22

07

23

04, 21 Second FAN

24

1 7 MXM power B+

25

2 4 LAN Connector

26

Title

8/11 Compal
8/15 Compal
8/23 Compal
8/23 H P
8/24 H P

EC Leverage Chimay SI schematic. Add D77, R2180 and connect D77 pin2 to U10 pinAE10.

8/24 H P
8/24 H P
8/24 H P
8/24 H P
8/24 H P
8/24 H P
8/24 H P
8/24 H P
8/24 H P
8/24 H P
8/25 H P

8/28 H P
8/28 H P

Owner

CLK_MCH_3GPLL/CLK_ MCH_3GPLL# reversed. Correct CLK_MCH_3GPLL/CLK_MCH_3GPLL#. 0. 3
Easy confl ict with other device that use same IRQ. Chnag e connect from PCI_PIRQB# to PCI_PIRQG#. 0 .3
System easy hang-up when plug USB2.0 device. Separate fr om pull up resistor of U10 for these pins. 0. 3
Leverage Chimay SI schematic. Add R2177(100K) pull down to GND.
+3VL may over budget. Add R2178, R2179(RV) for option the power source.

Debug card asserts hold, can't assert both SPI ROM. Add R2181 to connect SPI_HOLD#0 and SPI_HOLD#1.
May leakage issue from WLAN card. Add D78 to prevent this issue.
There is a shoot when power on of this pin. Reserve R1 862 and add R2182(10K) pull up to PWR_GD.
Default is input can't floating. Ad d a pull up R2183(10K) to +3VS.
Default is input can't floating. Mak e R2115 from RV to mount.
Can't into C3 status. Mount R1829.
Leverage Chimay SI schematic. Change R1847 to 1K.
Only need one 4MB BIOS chip. Add R2184(0 ohm) for BOM option.
Need High performace VGA card. Chnage MXM -III to MXM-HE.
BOM change. Change R1990 to 1K, R1991 to 10K and add L23, C1578.

Add BOM option for SPI_CS1#.
Net Change. Exchnage OCP#(To GPIO1)&LANLINK_STATUS#(To GPIO11)

8/31 H P
8/31 H P
9/6 HP
9/6 HP

CRESTLINE Change Chip version from A0 to B0.

9/6 HP
9/7 Compal
9/8 Compal
9/12 Compal

To meet HP 2007 platform defined. Chnage JP12 from 26pin to 30pin. 0. 3
BLM18PG221SN1 impedence is 221ohm@100MHz. BLM18PG330SN1 impedence is 33ohm@100MHz. 0.3
Connect C217, C171, C493 to wrong power. Connect C217, C171, C493 from +3VS to +3VS_WLAN. 0. 3

Thermal team ask to add control for second FAN.
Delete C9 cause not enough space to placement. ADD C1579, C1580(1210 size) to replace C9.
EMI issue for LANLINK_STATUS#, LAN_ACT#.

Solution Description

Change connect of R1845.2 from LAN_PHYPC to

LAN_PHYPC_R.

Mount R2134.

Add R2185, R2186 and use GPIO20 to control FAN.

ADD C1581, C1582(0402 size) per EMI request.

Rev.Page#

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

Request

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/28 2007/02/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

HW Changed-List History-2

LA-3331P

1

53 59Tuesday, May 1 5, 2007

1.0

of

5

4

Version Change List ( P. I. R. List ) for HW Circuit

3

2

1

Item Issue DescriptionDate

20, 34

1

D D

21 SM Bus

2

3 5 Function Connector

3

20, 23

4

18 Quick-Switch

5

18 Quick-Switch

6

34 KBC Debug port

7

3 4 RUMRST# timing

8

3 4 RUMRST# timing

9

3 4 VCC1 Power

10

21 LANSTATUS#

11

C C

31 USB Switch

12

30 Audio

13

25 LAN

14

24

15

1 7 MXM Connector

16

4 Thermal Senser

17

35 MDC

18

1 5 FSB Freq Selecter

19

Title

BATTERY LED

Kensington support

LAN Connector

Owner

10/2

HP
10/3 Compal
10/5 HP

10/18 HP
10/18 N vidia
10/18 HP
10/18

HP

10/18 HP
10/18 HP
11/02 HP
11/02 HP
11/03 Compal
11/03 HP
11/06 Intel
11/06

Compal
11/08 HP
11/08 HP
11/08 HP
11/09 HP

GREEN_BATLED# keep high when AC/DC exist. Change connection between SB & EC. 0. 4
SM Bus connection is not correct. Correct connection of SM bus and reserved R1817, R1820. 0. 4
Wireless LED always on. Make change of JP1, pin1-> +3VL, pin2 -> +3VS. 0. 4
Removed Kensington support. Remove JP60, Q122, R2084. 0 . 4
We will change Quick switch to PI3HDMI412FT-A Don't need pull up, removed RP44 ~ RP47. 0.4
Don't have decoupling for U57 1.5VS. Add C1583, C1584. 0. 4
Don't need use JP55, JP56 for debug. Removed JP55, J P56 from SI1. 0. 4
It may don't need these circuit. Reserve them at SI1.(Install R2144, RV : Q128, D73, R2145~2146) 0. 4
It different to desgn guide 1.1. Change R2145 to 4.7k, pull up to +3VALW and connect to Q128 base pin.
Chnage Design. Chnage VCC1 pow er option to +3VALW or +RTCVCC. 0 .4
System auto power on after plug AC in. Add Q136 to isolation U10 directly li nk to NIC, and add PU R2187. 0.4
Don't need dual layout for USB power switch. Remove U7, U36. 0. 4
To pass Vista test of Audio. Change R207, R217 from 15ohm to 56.2ohm. 0.4
Intel Santa Rosa Platform Message of the WW44 Change R1903 from 3.92Kohm to 1.4Kohm.
EMI issue for LANLINK_STATUS#, LAN_ACT#.
Need BO M option of SLP_S3# for use G71 or G84.
Abita will chnage to new Thermal senser in the future.
Implement new MDC future.
Need HW option for 667MHz or 800MHz Add JP62, JP63 and install R1689,R1696,R1705,R1737

20

3 7 M-Power discharge

21
22

B B

11/10 Compal

It's wrong connection of discharge control circuit. 0. 4

Solution Description

Mount C1581, C1582 --> 680pF(0402).
Add R2190(0ohm).
Add R2188, R2189(0ohm).
Connect JP26.2 to +3VS.

and reserve R1694,R1716,R1734.

Correct Q97, Q98, Q99 pin2 connect to LAN_WOL_EN#.

Rev.Page#

0.4

0.4

0.4

0.4

0.4

0.4

23
24
25
26

Request

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/28 2007/02/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

HW Changed-List History-3

LA-3331P

1

54 59Tuesday, May 1 5, 2007

1.0

of

5

4

Version Change List ( P. I. R. List ) for HW Circuit

3

2

1

Item Issue DescriptionDate

33

1

D D

34 KBC

2

35 PLTRST/CBB

3

38 KBC Power good

4

2 5 LAN ENERGY DET

5

38 PWR_GD

6

34 KBC

7

Title

FP Connector

Owner

12/18
12/18

Compal

HP
12/18 HP
12/19 HP
12/19 Intel
12/19 HP
12/20 HP

ME ask to change FP connector. Change FP connector(JP15) to same as JP58. 0 . 5
System can't power on.(PWR1 connect to +3VALW) PWR1 will modify connect to +3VL(R1908.2).
Capacitive Button Board may not need PLTRST. Disconnect PLT_RST# from JP1.3.
VCC1_PWRGD have glich when plug AC/DC power. Del U54 , Q106 and R1978, replace by U15.
Intel request chnage value of R1903. Change R1903 from 1.4K to 1.87Kohm.
Ripple noise to cause system auto shutdown issue. Add C1585(0.1uF) and R2191(1Kohm).
Current design may possible to damage the KBC. Change design to add Q137, Q138(2N7002) and R2192(100Kohm),

Solution Description

R2193(1Kohm).

2 7 Card bus Controller

8

24 NIC

9

24 ACBS

10

C C

3 5 Power Buttom

11

24 NIC

12

12/21 Compal
12/21 Intel
01/02 Intel
01/04 Compal
01/05 Compal

There is pop noise when plug some PCMCIA card. Add R2194 and C1586 and change value for R2038 and R2041.
82566MM may have start-up issue with Crystal. Modify layout and add R2195(0ohm).
To enable iAMT and support ACBS. Mount Q85 and R2072 but remove Q87~Q88 and R1877.
ESD test is not good for Switch board. Add ESD diode(D79) to M/B and add ME solution.
EMI test is fail from NIC. Add C1587~C1590, L24 and change C1421 to 820pF,

Rev.Page#

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

R12~R13 to FBMA-10-100505-151T.

Request

38 LAN Reset

13

18 Quick-Switch 01/07

14
15

MXM 01/ 1037

16
17

MXM 01/ 12

01/05 HP

HP

HP

01/11MXM37 Reserve C1594(0.1uF) close to pin.

HP

HP

HP request to modify. Change this power rail from +3VM_LAN to +3VM.
There is leakage issue of Q-Switch. Add D80 for this issue.
MXM board need external +2.5VS power rail. Add U62, C1592, C1593 for this issue.

2.5VS for MXM is too long.
Leakage issue from MXM pin211(ADP_PRES) 37 Add Q139(RHU002N06) & R2196(8.2K).

18
19
20

B B

21
22

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

23
24
25
26

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/28 2007/02/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

HW Changed-List History-4

LA-3331P

1

55 59Tuesday, May 1 5, 2007

1.0

of

5

4

Version Change List ( P. I. R. List ) for HW Circuit

3

2

1

Item Issue DescriptionDate

30

1

D D

3 4 KBC VCC0 Can't power on and AC power LED always light.

2

33

3
4
5

29 Card reader

6

17

7

3 0 USB Connector

8

2 1 THERM_SCI#

9

Title

USB Connector

02/07

Owner

Compal

Not need 40 pin connector for USB/Audio connector. Change JP25 from 40pin to 30 pin. 0. 6

02/07 Compal

FPR/USB S3/S4
WOL control
SPDIF

02/12
02/1437HP
02/1429HP

HP

02/14 HP

MXM thermal pin Isolation MXM_THERM# and PWR_GD use MOSFET. Add Q142 and R2204 for the m odify.

HP02/14
02/28 HP

Change control method for FPR/USB power in S3/S4. Add R2198, R2200~R2202, Q140~Q141.
Add 100K pull up for LAN_WOL_EN. Add R2203(100Kohm).
HP request to add 4.7K pull down on SPDIF out. Add R2206(4.7Kohm).
Need reserve some test point. Add R2205(0ohm) and T94.

Couple mV over the 150mV GS limits. Change R207, R217 from 56.2 ohm to 60.4 ohm.

02/28 HP

Solution Description

Change R2179 connect to +3VL, and add option R2197 to GND.

Remove R1854 from BOM list.HP request to design change.

10
11

C C

12

Rev.Page#

0.6

0.6

0.6

0.6

0.6

0.6

0.6

0.6

0.6

0.6

0.6

13
14
15
16
17
18
19
20
21

Request

22

B B

23
24
25
26

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/28 2007/02/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

HW Changed-List History-5

LA-3331P

1

56 59Tuesday, May 1 5, 2007

1.0

of

5

4

Version Change List ( P. I. R. List ) for HW Circuit

3

2

1

Item Issue DescriptionDate

15

1

D D

1 5 FSB selecter Remove FSB selection function.

2

29

3

20 GPU Thermal

4

2 6 NAND Card

5
6

38 POK CKT

7

24 NIC power

8

31 USB Port

9

10

3 4 KBC Clock

11

C C

2 1 LAN/WLAN Switch

12

Title

Clock Gen

OC6#/GPIO3021

BT

Owner

03/19
03/19
03/19
03/19
03/23

HP

HP

HP

HP

HP

HP

HP03/23
03/28 Compal
03/28 Compal
03/28 Compal
03/28 Compal
03/28 Compal
03/30 HP

Remove 0hom damping of differential clock pair. 0. 8

Remove JP62, JP63, Reserve R1689, R1696, R1705, R1737, install R1694, R1716, R1734.
To improve audio quality of docking.Audio Codec
Design change for MXM board.
Don't need this function for MP. Reserve R2064, R2065, C1553 ~ C1560.
This pin is not long use for MXM. Reserve R2207 for isolation. 0 . 8
For schematic leverage to Chimay. Change LMV331(U47,U48) to LM393(U47), and remove R1976, C1487
Don't need +V1.0M_LAN power regulator. Remove Q90, C1436 ~ C1440. 0. 8
To correct sch ematic and make layout smooth. Remove C118, C498, C499, R49 and change C126 to 330uF. 0 . 8
To make layout smoothly. Remove D16. 0 .831
To make layout smoothly and EMI request. R emove R19 29, C1455.
Unplug AC, WLAN will be disabled on XP OS. Add U63 for slove leakage issue of enable ACBS.

Solution Description

Remove RP49, RP51~RP57, reserve RP48.

Change R290~R291 to 6.04K and R289, R292 to 2K.
Reserve R1854.

Rev.Page#

0.8

0.8

0.8

0.8

0.8

0.8

13
14
15
16
17
18
19
20
21

Request

22

B B

23
24
25
26

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/28 2007/02/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

HW Changed-List History-6

LA-3331P

1

57 59Tuesday, May 1 5, 2007

1.0

of

5

4

Version Change List ( P. I. R. List ) for HW Circuit

3

2

1

Item Issue DescriptionDate

11

1

D D

2 2 SB Crack detect

2

22

3

36

4

1 4 DDR DIMM B

5

Title

NB Crack detect

05/02
05/02
05/02
05/14
5/15

Owner

HP
HP
HP
HP
HP

Reserve BGA crack detect function
Reserve BGA crack detect function
To improve ICH_V5REF_RUN of SB.Audio Codec
To prevent crack issue for L14Easy crack issue Change L14 material to SM010008E10.
To solve OTS issue OTS 26 5441 and 261307.

Solution Description

Remove Q114~Q117, R2049~R2052, install R111, R113, R122, R132.
Remove Q118~Q121, R2058~R2061, install R138~R141.
Change C1190 from 0.1uF to 1uF.

Change R33 pin2 connect to +3VM. 1 .0

Rev.Page#

1.0

1.0

1.0

1.0

6
7
8

9
10
11

Request

C C

12
13
14
15
16
17
18
19
20
21
22

B B

23
24
25
26

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/28 2007/02/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

HW Changed-List History-7

LA-3331P

1

58 59Tuesday, May 1 5, 2007

1.0

of

5

4

3

2

1

+3VALW

D D

PM_SLP_M

U41

VIN

B+

PQ5

page 41

ACDRV#

C C

PU37

page 43

(Control +1.5VSP turn on)

MAINPWON

KBC_PWR_ON

SLP_S3#

PU28

page 44

(Control +1.25VMP turn on)

(Control PU27 turn on)

B B

PM_SLP_M#

SLP_S4#

PU27

page 45

+3VALWP

PL5

PL6

+5VALWP

+1.5VSP

PL21

PL22

+1.25VMP

+1.8VP

PL16

V_DDR_MCH_REF
+0.9VP

PJP4

PJP2

PJP1

PJ5 , 12

PJP3

+0.9V

U43

+5VALW

U45

+1.5VS

+1.25VM

U40

+1.8V

Q127

RUNON

RUNON

+1.8VS

RUNON

RUNON

+3VM

+3VS

+5VS

+1.25VS

PU38

PU36

SLP_S3#

+1.05V_VCCP

VCCP_POK

PM_SLP_M#

+1.05VMP

M_PROK

+VCCP

PJP14

+1.05VM

PJP15

PJP7

1.8PGOOD

CLK_ENABLE#

+VCC_CORE

PM_PWROK
VGATE

PU31

A A

5

4

page 46

PGD_IN
SLP_S3#

PL20

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Power Map

Size Docum e n t N u mb er Re v

C

LA-3331P

Date: Sheet

1

of

59 59Tuesday, M ay 1 5, 2007

1.0