HP LA-3331P Schematics

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Merom uFCPGA with Intel
Crestline_PM+ICH8-M core logic

3 3

2007-05-15

REV:1.0

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/04/13 2006/06/30

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-3331P

E

1.0

of

159Tuesday, May 1 5, 2007

A

Compal confidential

File Name : LA-3331P

B

C

D

E

ABITA

Thermal Sensor

1 1

LCD conn

page 18

ADM1032ARMZ

page 4

Mobile Merom

uFCPGA-478 CPU

page 4,5,6

CK505

Clock Generator
ICS9LPRS355

page 15

Fan Control

MXM III
Connector

page 17

page 4

PCI-E x 16

H_A#(3..35)
H_D#(0..63)

Intel Crestline MCH

FCBGA 1299

FSB

667/800MHz 1.05V

DDR2 667MHz 1.8V

Dual Channel

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

page 13,14

CRT & HDMI

page 16 page 7,8,9,10,11,12

2 2

CRT & DVI-D OUT
AV & SV OUT

page 36

PCI-E BUS

Intel ICH8-M

10/100/1000 LAN

Intel 82566MM

page 24

RJ45/11 CONN

3 3

page 25

Mini-Card

page 26

CardBus Controller

Rico R5C583

page 27,28

Slot 0/Smart Card

1394 port

6in1 Slot

LED

page 33

RTC CKT.

page 20

Power OK CKT.

page 38

4 4

Power On/Off CKT.

page 35

TPM1.2

SLB9635TT

page 33 page 33

Touch Pad CONN.

TrackPoint CONN.

DC/DC Int erface CKT.

page 37

A

B

PCI BUS

LPC BUS

SMSC KBC 1070

page 34

page 19,20,21,22

Security Classification

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DMI X4

mBGA-676

Int.KBD

Issued Date

C

SPI

SPI ROM

ST M25P32

page 32

COM1

( Docking )

2006/02/13 2006/03/10

USB2.0

Azalia

SATA Master

PATA Slave

SMSC Super I/O

LPC47N217

LPT

( Docking )

Compal Secret Data

Deciphered Date

USB x2
(Docking)

page 36

FingerPrinter AES1610
USBx1

page 33

USB conn x 2(For I/O)
BT Conn USB x 1

page31

MDC V1.5

page 35

Audio CKT

AD1981HD

page 29

SATA HDD Connector

page 23

PATA ODD Connector

page 23

Title

Size Document Number Rev

Custom

D

Date: Sheet

daughter board

MAX9710

AMP & Audio Jack

Docking CONN.

*RJ-45(LED*2)
*RJ-11(Pass Through)
*CRT
*COMPOSITE Video Out
*S-VIDEO OUT
*DVI-D
*LINE IN
*LINE OUT
*PCI-E x2
*Serial Port
*Parallel Port
*PS/2 x2
*USB x2
*DC JACK

Compal Electronics, Inc.

Block Diagram

LA-3331P

E

USB x 4

page 30

of

259Tuesday, May 1 5, 2007

1.0

A

Voltage Rails

+5VS

+3VM
+1.25VM
+1.05VM

O

OO
O
O

X

X

power
plane

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

O MEANS ON X MEANS OFF

LDO3
LDO5

O

O
O
O

O

X

+5VALW
+3VALW

PCI Devices

1 1

EXTERNAL

CARD BUS & 1394

DMA Channel
DMA0
DMA1
DMA2
DMA3
DMA4
DMA5
DMA6
DMA7

USB PORT#

0
1
2
3
4
5
6
7
8
9

IDSEL# REQ/GNT# PIRQ
AD22 2 C,D,E,G

Device
MODEM / LAN
ECP
FLOPPY DISK
AUDIO
(Cascade)
Unused
Unused
Unused

Destination

M/B

Finger Printer

M/B

On Audio Board

On Audio Board

On Audio Board

Blut Tooth

Docking

On Audio Board

Docking

+5V+B
+1.8V

+3VS
+1.8VS

+0.9V

+1.5VS
+1.25VS
+CPU_CORE
+VCCP

O

OO

OO
O
O

X

X

O

X

XX

X

X

XX

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2006/02/13 2006/03/10

IRQ

0
1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

17

18

19

20

21
22
23

Compal Secret Data

Deciphered Date

Device

System Timer

Keyboard

N/A

Serial port (COM2),LAN/Modem

Serial port (COM1)

Audio/VGA

Floppy

Parallel port

System CMOS/R eal-time clock

Microsoft ACPI

N/A,Momem,LAN

Mass strorage co nt ro l/ PCI simple communication control

synactic PS2 port GlidePAD

Numeric Data Process

Primary IDE interface,HDD

Secondary IDE innterface,CD-ROM

Mobile Intel C re st li ne Express Chipset Family
Microsoft UAA Bu s D ri ve r for High Definition Audio
Intel 82801H ( I C H 8 F a m i ly ) PCI Express Root Port -27D0
Broadcom Net X t r e me Gigabit Ethernet

Intel 82801H ( I C H 8 F a m i ly ) PCI Express Root Port - 27D2
Broadcom 802.11b/g WLAN
Intel 82801H ( I C H8 F a m i ly ) USB Universal Host Controll
Intel 82801H ( I C H8 F a m i ly ) USB Universal Host Controll
Ricoh R5C853 C ardbus Control
Ricoh R5C853 I nt eg ra tes FlashMedia Control
Ricoh R5C853 G em co re based SmartCard Control
Intel 82801H ( I C H 8 F a m i ly ) PCI Express Root Port - 27D6
Intel 82801H ( I C H8 F a m i ly ) USB Universal Host Controll

Intel 82801H ( I C H8 F a m i ly ) USB Universal Host Controll
Intel 82801H ( IC H8 Fa mi ly )USB2 Enhanced Host Controll

Intel 82801H ( I C H8 F a m i ly ) USB Universal Host Controll

SDA Standard C om pl ia nt SD Host Controller

HP Mobile Data Protection Sensor

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-3331P

359Tuesday, May 15, 2007

1.0

of

5

4

3

2

1

1
2
3

GND
GND

1
2
3

R443

1 2

1K_0402_5%@

G1
G2

R24
10K_0402_5%

+3VS

+VCCP

CLK_CPU_XDP# 15

H_RESET#
XDP_DBRESET#

THERM_SCI# 21

4
5

0413 add

ITP-XDP Connector

Change to same as
Chimay 4/6

JP31

1

TP_BPM#5

T95

TP_BPM#4

D D

H_A#[3..16]7

H_ADSTB#07

H_REQ#07
H_REQ#17
H_REQ#27
H_REQ#37
H_REQ#47

C C

B B

A A

H_A#[17..35]7

H_ADSTB#17

H_A20M#20

H_FERR#20

H_IGNNE#20
H_STPCLK#20

H_INTR20

H_NMI20
H_SMI#20

H_ADSTB#0
H_REQ#0

H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

JP8A

J4

ADDR GROUP 0 ADDR GROUP 1

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

Merom Ball-out Rev 1aconn@

DEFER#

CONTROL

RESET#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA
THERMDC

ICH

THERMTRIP#

H CLK

BCLK[0]
BCLK[1]

RESERVED

ADS#
BNR#
BPRI#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

PRDY#
PREQ#

TCK
TDO

TMS

TRST#

DBR#

TDI

H1
E2
G5

H5
F21
E1

F1
D20

B3
H4
C1

F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

H_ADS#
H_BNR#
H_BPRI#

H_DEFER#
H_DRDY#
H_DBSY#

H_BR0#
H_IERR#

H_INIT#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

H_HIT#
H_HITM#

XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#

XDP_DBRESET#

H_PROCHOT#

H_THERMTRIP#

CLK_CPU_BCLK
CLK_CPU_BCLK#

R1613 56_0402_5%

Cut them but reserve TP for
ESD request. 5/8

R2188 0_0402_5%

1 2

R2189 0_0402_5%

1 2

H_ADS# 7
H_BNR# 7

H_BPRI# 7

H_DEFER# 7
H_DRDY# 7
H_DBSY# 7

H_BR0# 7

12

H_INIT# 20
H_LOCK# 7
H_RESET# 7

H_RS#0 7

H_RS#1 7

H_RS#2 7

H_TRDY# 7

H_HIT# 7
H_HITM# 7

XDP_BPM#0_TP
XDP_BPM#1_TP
XDP_BPM#2_TP
XDP_BPM#3_TP
XDP_BPM#4_TP
XDP_BPM#5

XDP_DBRESET# 21

R1614 68_0402_5%

H_THERMTRIP# 7,20

CLK_CPU_BCLK 15
CLK_CPU_BCLK# 15

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

T101
T102
T103
T104
T105

12

+VCCP

H_PROCHOT# 46,47

+VCCP

H_THERMDA
H_THERMDC

H_PWRGOOD5,20 CLK_CPU_XDP 15

Removed at 5/30.(Follow
Chimay)

H_PROCHOT# OCP#

T96

TP_BPM#3

T97

TP_BPM#2

T98

TP_BPM#1

T99

R442
1K_0402_5%

12

R1616

56_0402_5%@

C

TP_BPM#0

H_PWRGOOD_R

12

XDP_HOOK1

XDP_TCK

OCP# 21,48

T100

Cut them but reserve TP
for ESD request. 5/8

C539 0.1U_0402_16V4Z

+VCCP

12

B

2

E

3 1

Q78

MMBT3904_SOT23@

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-Aconn@

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

Thermal Sensor ADM1032ARMZ

C69

0.1U_0402_16V4Z

1 2

C68 2200P_0402_50V7K

+3VS

1 2

R25 10K_0402_5%

PWM Fan & System Fan Control circuit

Change to sa m e as Chimay 4/6

FAN_PWM34

Will Reserved R2186 if
don't use 2'rd FAN.
9/8

Add in 9/6.
Change to
GPIO20. 9/8

THERM#

GPIO2021

GND1
OBSFN_C0
OBSFN_C1

GND3

GND5

GND7
OBSFN_D0
OBSFN_D1

GND9

GND11

GND13

GND15

TD0

TRST#

TDI

TMS

GND17

+3VS

2

1

H_THERMDA
H_THERMDC

THERM#

1
2

1 2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

1
2
3

ADM1032ARMZ-2REEL_MSOP8

+3VS

U31

5

TC7SH00FU_SSOP5

P

INB

O

INA

G

3

R2186
0_0402_5%

R2185
10K_0402_5%

Add in 9/7.

XDP_DBRESET#_R

1 2

Change value in 5/02

XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5
XDP_HOOK1
XDP_TRST#
XDP_TCK

CLK_CPU_XDP
CLK_CPU_XDP#

H_RESET#_R
XDP_DBRESET#_R

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE

R524 54.9_0402_1%

1 2

R523 54.9_0402_1%

1 2

R525 54.9_0402_1%

1 2

R526 54.9_0402_1%

1 2

R1612 54.9_0402_1%@

1 2

R521 51_0402_1%

1 2

R522 54.9_0402_1%

1 2

This shall place near CPU

+VCCP+VCCP

R441 1K_0402_1%

1 2

R444 200_0402_1%

R191
0_0402_5%

1 2

12

Place R191 within 200ps (~1") to CPU

ICH_SM_CLK17,21,26

ICH_SM_DA17,21,26

U5

VDD
D+

SDATA

ALERT#

D­THERM#4GND

4

12

SCLK

1 2

ICH_SM_CLK
ICH_SM_DA

Address:100_1100

ICH_SM_CLK

8

ICH_SM_DA

7

THERM_SCI#

6
5

Change conne c tor type from
4pin to 3 pin. 6/8
Change pin connection 4/25

conn@

ACES_85205-03001

1
2
3

4
5

1
2

3
conn@

ACES_85204-03001

R1615

+5VS

0_0402_5%@

+5VS

JP6

JP53

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Merom(1/3)-AGTL+/XDP

LA-3331P

1

1.0

of

459Tuesday, May 15, 2007

5

4

3

2

1

Correct net name 4/27

H_D#[0..15]7

D D

H_DSTBN#07
H_DSTBP#07

H_DINV#07

H_D#[16..31]7

C C

layout note: Route TEST3 & TEST5 traces on
ground referenced layer to the TPs

H_DSTBN#17
H_DSTBP#17

H_DINV#17

R1619 1K_0402_5%@

1 2

R1620 1K_0402_5%@

1 2

C1231 0.1U_0402_16V4Z@

1 2

CPU_BSEL015
CPU_BSEL115
CPU_BSEL215

T49
T50

T51

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

V_CPU_GTLREF

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

CPU_BSEL CPU_BSEL2 CPU_BSEL1

166

B B

200

V_CPU_GTLREF

01

0

+VCCP

12

R1626
1K_0402_1%

12

R1628
2K_0402_1%

AD26

AF26

JP8B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#
GTLREF

C23

TEST1

D25

TEST2

C24

TEST3
TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Merom Ball-out Rev 1aconn@

DATA GRP 0

DATA GRP 1

MISC

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#

DATA GRP 2DATA GRP 3

D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

COMP0
COMP1
COMP2
COMP3

CPU_BSEL0

1

1

0

H_D#[32..47] 7

H_DSTBN#2 7
H_DSTBP#2 7
H_DINV#2 7
H_D#[48..63] 7

H_DSTBN#3 7
H_DSTBP#3 7
H_DINV#3 7

H_DPRSTP# 7,20,46
H_DPSLP# 20

H_DPWR# 7

H_PWRGOOD 4,20
H_CPUSLP# 7

H_PSI# 46

12

R1621

54.9_0402_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.

R1622

27.4_0402_1%

12

R1623

12

R1624

54.9_0402_1%

12

27.4_0402_1%

+VCC_CORE +VCC_CORE

Correct net name 6/16

AA10
AA12
AA13
AA15
AA17
AA18
AA20

AC10
AB10
AB12
AB14
AB15
AB17
AB18

A7

A9
A10
A12
A13
A15
A17
A18
A20

B7

B9
B10
B12
B14
B15
B17
B18
B20

C9
C10
C12
C13
C15
C17
C18

D9
D10
D12
D14
D15
D17
D18

E7

E9
E10
E12
E13
E15
E17
E18
E20

F7

F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9

AB9

JP8C

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

Merom Ball-out Rev 1a

conn@

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

R1617 0_0402_5%

G21
V6

R1618 0_0402_5%

J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

.

+VCC_CORE

VCCSENSE

VSSSENSE

1 2

1 2

Close to CPU pin
within 500mils.

R1627
100_0402_1%

R1629
100_0402_1%

+VCCP

12
12

1

+

2

CPU_VID0 46
CPU_VID1 46
CPU_VID2 46
CPU_VID3 46
CPU_VID4 46
CPU_VID5 46
CPU_VID6 46

VCCSENSE 46

VSSSENSE 46

C1230
330U_D2E_2.5VM_R7

1

2

C1232

Near pin C26

Length match
within 25 mils.
The trace

+1.5VS

1

2

C1233

10U_0805_10V4Z

0.01U_0402_16V7K

Near pin B26

width/space/other
is 20/7/25.

VCCSENSE

VSSSENSE

Close to CPU pin AD26
within 500mils.

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Merom(2/3)-AGTL+/PWR

LA-3331P

1

1.0

of

559Tuesday, May 15, 2007

5

Place these capacitors on L8
(North side,Secondary Layer)

4

+VCC_CORE

1

C412
10U_0805_6.3V6M

2

1

C413
10U_0805_6.3V6M

2

1

C414
10U_0805_6.3V6M

2

3

1

C415
10U_0805_6.3V6M

2

1

C416
10U_0805_6.3V6M

2

1

C417
10U_0805_6.3V6M

2

2

1

C425
10U_0805_6.3V6M

2

1

C479
10U_0805_6.3V6M

2

1

D D

C C

B B

JP8D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

conn@

P6

VSS[082]

P21

VSS[083]

P24

VSS[084]

R2

VSS[085]

R5

VSS[086]

R22

VSS[087]

R25

VSS[088]

T1

VSS[089]

T4

VSS[090]

T23

VSS[091]

T26

VSS[092]

U3

VSS[093]

U6

VSS[094]

U21

VSS[095]

U24

VSS[096]

V2

VSS[097]

V5

VSS[098]

V22

VSS[099]

V25

VSS[100]

W1

VSS[101]

W4

VSS[102]

W23

VSS[103]

W26

VSS[104]

Y3

VSS[105]

Y6

VSS[106]

Y21

VSS[107]

Y24

VSS[108]

AA2

VSS[109]

AA5

VSS[110]

AA8

VSS[111]

AA11

VSS[112]

AA14

VSS[113]

AA16

VSS[114]

AA19

VSS[115]

AA22

VSS[116]

AA25

VSS[117]

AB1

VSS[118]

AB4

VSS[119]

AB8

VSS[120]

AB11

VSS[121]

AB13

VSS[122]

AB16

VSS[123]

AB19

VSS[124]

AB23

VSS[125]

AB26

VSS[126]

AC3

VSS[127]

AC6

VSS[128]

AC8

VSS[129]

AC11

VSS[130]

AC14

VSS[131]

AC16

VSS[132]

AC19

VSS[133]

AC21

VSS[134]

AC24

VSS[135]

AD2

VSS[136]

AD5

VSS[137]

AD8

VSS[138]

AD11

VSS[139]

AD13

VSS[140]

AD16

VSS[141]

AD19

VSS[142]

AD22

VSS[143]

AD25

VSS[144]

AE1

VSS[145]

AE4

VSS[146]

AE8

VSS[147]

AE11

VSS[148]

AE14

VSS[149]

AE16

VSS[150]

AE19

VSS[151]

AE23

VSS[152]

AE26

VSS[153]

A2

VSS[154]

AF6

VSS[155]

AF8

VSS[156]

AF11

VSS[157]

AF13

VSS[158]

AF16

VSS[159]

AF19

VSS[160]

AF21

VSS[161]

A25
AF25

VSS[163]

Merom Ball-out Rev 1a

.

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

1

C411
10U_0805_6.3V6M

C441
10U_0805_6.3V6M

C442
10U_0805_6.3V6M

+VCCP

1

C437

0.1U_0402_10V6K

2

C481
10U_0805_6.3V6M

2

1

C423
10U_0805_6.3V6M

2

1

C435
10U_0805_6.3V6M

2

Removed C434 at 4/18

Removed C1570 ~ C1573 , cause FSB Common clock have move to bottom side.8/1

1

C480
10U_0805_6.3V6M

2

1

C432
10U_0805_6.3V6M

2

1

C436
10U_0805_6.3V6M

2

1

C486
10U_0805_6.3V6M

2

1

C422
10U_0805_6.3V6M

2

1

C443
10U_0805_6.3V6M

2

No istall C67 , C125 at 2007/03/23.

South Side Secondary

+VCC_CORE

1

C409

+

2

330U_D2E_2.5VM_R9

1

C421

0.1U_0402_10V6K

2

1

C67

+

2

@

330U_D2E_2.5VM_R9

C408

1

C429

0.1U_0402_10V6K

2

1

+

2

330U_D2E_2.5VM_R9

1

C418
10U_0805_6.3V6M

2

1

C446
10U_0805_6.3V6M

2

1

C444
10U_0805_6.3V6M

2

North Side Secondary

1

C66

+

2

1

C438

0.1U_0402_10V6K

2

1

C117

+

2

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

1

2

1

+

C125
330U_D2E_2.5VM_R9

2

C428

0.1U_0402_10V6K

1

C482
10U_0805_6.3V6M

2

1

C424
10U_0805_6.3V6M

2

1

C427
10U_0805_6.3V6M

2

@

1

C433

0.1U_0402_10V6K

2

1

C483
10U_0805_6.3V6M

2

1

C445
10U_0805_6.3V6M

2

1

C426
10U_0805_6.3V6M

2

1

C484
10U_0805_6.3V6M

2

1

C485
10U_0805_6.3V6M

2

1

C431
10U_0805_6.3V6M

2

ESR <= 1.5m ohm
Capacitor > 1980uF

Place these inside
socket cavity on L8
(North side
Secondary)

Mid Frequence Decoupling

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Merom(3/3)-GND&Bypass

LA-3331P

1

1.0

of

659Tuesday, May 15, 2007

5

AD12

AC14
AD11
AC11

AE11
AH12

AH13

H_RCOMP

W10

AJ14

M10
N12

AE3
AD9
AC9
AC7

AB2
AD7
AB1

AC6
AE2
AC5
AG3

AH8
AE9

AH5
AE7

AE5
AH2

E2

G2
G7
M6
H7
H3
G4

F3
N8
H2

N9
H5

P13

K9
M2

Y8

V4
M3

J1
N5
N3
W6
W9
N2

Y7

Y9

P4
W3
N1

Y3

AJ9

AJ5
AJ6
AJ7

AJ2
AJ3

B3
C2

W1
W2

B6

E5

B9

A9

U4A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

H_CPURST#
H_CPUSLP#

H_AVREF
H_DVREF

CRESTLINE_1p0

+VCCP

12

R1645

12

R1651

221_0603_1%

1

2

100_0402_1%

HOST

H_SWNGH_VREF

0.1U_0402_16V4Z

C1241

H_ADSTB#_0
H_ADSTB#_1

H_DEFER#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1

H_REQ#_2
H_REQ#_3

H_REQ#_4

H_D#[0..63]5

D D

C C

+VCCP

12

12

R1638

R1639

54.9_0402_1%

54.9_0402_1%

H_RESET#4

H_CPUSLP#5

B B

Layout Note:
H_RCOMP / H_VREF / H_SWNG

trace width and spacing is 18/20

+VCCP

12

1K_0402_1%

R1644

12

A A

R1649

2K_0402_1%

1

2

C1240

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWNG
H_RCOMP

H_SCOMP
H_SCOMP#

H_VREF

12

R1650

24.9_0402_1%

0.1U_0402_16V4Z

Near B3 pinwithin 100 mils from NB

5

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#
H_DBSY#

H_DRDY#

H_HIT#
H_HITM#

H_LOCK#
H_TRDY#

H_RS#_0
H_RS#_1
H_RS#_2

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

K5
L2
AD13
AE13

M7
K3
AD2
AH11

L7
K2
AC2
AJ10

M14
E13
A11
H13
B12

E12
D7
D8

4

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

V_DDR_MCH_REF13,14,45

H_A#[3..35] 4

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BR0# 4
H_DEFER# 4
H_DBSY# 4
CLK_MCH_BCLK 15
CLK_MCH_BCLK# 15
H_DPWR# 5
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4

H_DINV#0 5
H_DINV#1 5
H_DINV#2 5
H_DINV#3 5

H_DSTBN#0 5
H_DSTBN#1 5
H_DSTBN#2 5
H_DSTBN#3 5

H_DSTBP#0 5
H_DSTBP#1 5
H_DSTBP#2 5
H_DSTBP#3 5

H_REQ#0 4
H_REQ#1 4
H_REQ#2 4
H_REQ#3 4
H_REQ#4 4

H_RS#0 4
H_RS#1 4
H_RS#2 4

VGATE21,46

PM_PWROK21,34,46

H_THERMTRIP#4,20

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

SMRCOMP_VOH

Change SN to
SD034301180(LF
part). 5/12

SMRCOMP_VOL

Add for using DDR2 2Gb tech. 6/9

PM_EXTTS#013

PM_EXTTS#114,47

R1484 0_0402_5%
R1483 0_0402_5%@

PLT_RST#19,20,21,26,32,33

Mount R2134.9/6

Reserve R2134 for Cresline A0.
Install R2134 from Cresline B0.

V_DDR_MCH_REF

1

2

C1239

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V

2

2

2.2U_0603_10V6K

2.2U_0603_10V6K

1K_0402_1%@

1K_0402_1%@

C1235

1

0.01U_0402_25V7K

1

C1237

2

0.01U_0402_25V7K

DDR_A_MA1413
DDR_B_MA1414

PM_EXTTS#0

PM_EXTTS#1

CLKREQB#

MCH_CLKSEL015
MCH_CLKSEL115
MCH_CLKSEL215

PM_BMBUSY#21

H_DPRSTP#5,20,46

1 2
1 2

3

12

R1630
1K_0402_1%

12

R1631

3.01K_0402_1%

12

R1632
1K_0402_1%

T52
T53

CFG59

T54

CFG79
CFG89
CFG99

T55

T56

CFG129
CFG139

T57

T58

CFG169

T59

T60

CFG199
CFG209

C1234

1

1

C1236

2

12
12

R1640 100_0402_5%
R2134 0_0402_5%

+1.8V

12

R1643

12

R1646

U4B

P36

RSVD1

P37

RSVD2

R35

RSVD3

N35

RSVD4

AR12

RSVD5

AR13

RSVD6

AM12

RSVD7

AN13

RSVD8

J12

RSVD9

AR37

RSVD10

AM36

RSVD11

AL36

RSVD12

AM37

RSVD13

D20

RSVD14

H10

RSVD20

B51

RSVD21

BJ20

RSVD22

BK22

RSVD23

BF19

RSVD24

BH20

RSVD25

BK18

RSVD26

BJ18

RSVD27

BF23

RSVD28

BG23

RSVD29

BC23

RSVD30

BD24

RSVD31

BJ29

RSVD32

BE24

RSVD33

BH39

+3VS

R1635

12

10K_0402_5%

R1636

12

10K_0402_5%

R1637

12

10K_0402_5%

PAD
PAD

PAD

PAD
PAD

PAD
PAD

PAD
PAD

PWROK

DPRSLPVR21,46

CFG3
CFG4

CFG6

CFG10
CFG11

CFG14
CFG15

CFG17
CFG18

PM_EXTTS#0
PM_EXTTS#1

PLT_RST#_R

2006/02/13 2006/03/10

RSVD34

AW20

RSVD35

BK20

RSVD36

C48

RSVD37

D47

RSVD38

B44

RSVD39

C44

RSVD40

A35

RSVD41

B37

RSVD42

B36

RSVD43

B34

RSVD44

C34

RSVD45

P27

CFG_0

N27

CFG_1

N24

CFG_2

C21

CFG_3

C23

CFG_4

F23

CFG_5

N23

CFG_6

G23

CFG_7

J20

CFG_8

C20

CFG_9

R24

CFG_10

L23

CFG_11

J23

CFG_12

E23

CFG_13

E20

CFG_14

K23

CFG_15

M20

CFG_16

M24

CFG_17

L32

CFG_18

N33

CFG_19

L35

CFG_20

G41

PM_BM_BUSY#

L39

PM_DPRSTP#

L36

PM_EXT_TS#_0

J36

PM_EXT_TS#_1

AW49

PWROK

AV20

RSTIN#

N20

THERMTRIP#

G36

DPRSLPVR

BJ51

NC_1

BK51

NC_2

BK50

NC_3

BL50

NC_4

BL49

NC_5

BL3

NC_6

BL2

NC_7

BK1

NC_8

BJ1

NC_9

E1

NC_10

A5

NC_11

C51

NC_12

B50

NC_13

A50

NC_14

A49

NC_15

BK2

NC_16

CRESTLINE_1p0

Compal Secret Data

Deciphered Date

2

DDR MUXINGCLK

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CFGRSVD

DMI

PM

GRAPHICS VID

ME

NC

SDVO_CTRL_DATA

Connect to GND 4/25 (DG9.0 P.190)

MISC

2

SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4

SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4

SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF_0
SM_VREF_1

DPLL_REF_CLK

DPLL_REF_CLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

NC in 4/24

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#
CL_VREF

SDVO_CTRL_CLK

CLK_REQ#

ICH_SYNC#

TEST_1
TEST_2

1

For Crestline: 20ohm

AV29
BB23
BA25
AV23

AW30
BA23
AW25
AW23

BE29
AY32
BD39
BG37

BG20
BK16
BG16
BE13

BH18
BJ15
BJ14
BE16

BL15
BK14

BK31
BL31

AR49
AW4

SMRCOMP
SMRCOMP#

SMRCOMP_VOH
SMRCOMP_VOL

V_DDR_MCH_REF

For Calero: 80.6ohm

M_CLK_DDR0 13
M_CLK_DDR1 13
M_CLK_DDR2 14
M_CLK_DDR3 14

M_CLK_DDR#0 13
M_CLK_DDR#1 13
M_CLK_DDR#2 14
M_CLK_DDR#3 14

DDR_CKE0_DIMMA 13
DDR_CKE1_DIMMA 13
DDR_CKE2_DIMMB 14
DDR_CKE3_DIMMB 14

DDR_CS0_DIMMA# 13
DDR_CS1_DIMMA# 13
DDR_CS2_DIMMB# 14
DDR_CS3_DIMMB# 14

M_ODT0 13
M_ODT1 13
M_ODT2 14
M_ODT3 14

R1633 20_0402_1%
R1634 20_0402_1%

12
12

Del in 4/24

B42
C42
H48
H47

K44
K45

AN47
AJ38
AN42
AN46

AM47
AJ39
AN41
AN45

AJ46
AJ41
AM40
AM44

AJ47
AJ42
AM39
AM43

E35
A39
C38
B39
E36

AM49
AK50
AT43
AN49

CL_VREF

AM50

H35
K36

CLKREQB#

G39
G40

A37
R32

R1647

20K_0402_5%

Title

Size Document Number Rev

Custom

Date: Sheet

Correct the net name.8/11

CLK_MCH_3GPLL 15
CLK_MCH_3GPLL# 15

DMI_TXN0 21
DMI_TXN1 21
DMI_TXN2 21
DMI_TXN3 21

DMI_TXP0 21
DMI_TXP1 21
DMI_TXP2 21
DMI_TXP3 21

DMI_RXN0 21
DMI_RXN1 21
DMI_RXN2 21
DMI_RXN3 21

DMI_RXP0 21
DMI_RXP1 21
DMI_RXP2 21
DMI_RXP3 21

+1.25VM_AXD

Closed to AM50 pin

12

12

R1648
0_0402_5%

CL_CLK0 21
CL_DATA0 21
M_PWROK 21,38
CL_RST# 21

C1238

0.1U_0402_16V4Z

CLKREQB# 15
MCH_ICH_SYNC# 21

12

R1641
1K_0402_1%

12

1

R1642
392_0402_1%

2

Compal Electronics, Inc.

CRESTLINE(1/6)-AGTL+/DMI/DDR2

LA-3331P

759Tuesday, May 1 5, 2007

1

+1.8V

1.0

of

5

D D

DDR_A_D[0..63]13

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8

DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AR43

AW44

BA45
AY46
AR41
AR45
AT42

AW47

BB45
BF48
BG47

BJ45
BB47
BG50
BH49
BE45

AW43

BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40

AW40

AT39

AW36
AW41

AY41
AV38
AT38
AV13
AT13

AW11

AV11
AU15
AT11
BA13
BA11
BE10
BD10

BG10

AW9

AM8
AN10

AM9
AN11

BD8
AY9

BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3

AT9
AN9

U4D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

CRESTLINE_1p0

DDR SYSTEM MEMORY A

SA_BS_0
SA_BS_1
SA_BS_2

SA_CAS#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_RAS#

SA_RCVEN#

SA_WE#

4

BB19
BK19
BF29

BL17
AT45

BD44
BD42
AW38
AW13
BG8
AY5
AN6

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16

BE18
AY20

BA19

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

SA_RCVEN#

DDR_A_BS0 13
DDR_A_BS1 13
DDR_A_BS2 13

DDR_A_CAS# 13 DDR_B_CAS# 14
DDR_A_DM[0..7] 13

DDR_A_DQS[0..7] 13

DDR_A_DQS#[0..7] 13

DDR_A_MA[0..14] 7,13

DDR_A_RAS# 13

T62

DDR_A_WE# 13

3

DDR_B_D[0..63]14

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8

DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AP49

AR51
AW50
AW51

AN51

AN50

AV50

AV49

BA50

BB50

BA49

BE50

BA51

AY49

BF50

BF49

BL43
BK47
BK49
BK43
BK42

BJ41

BL41

BJ37

BJ36
BK41

BJ40

BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12

BJ10

BK10

BJ50
BJ44
BJ43

BG1

BL9
BK5
BL5
BK9

BJ8
BJ6
BF4
BH5

BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

2

U4E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

CRESTLINE_1p0

1

AY17

SB_BS_0

BG18

SB_BS_1

BG36

SB_BS_2

BE17

SB_CAS#
SB_DM_0

SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

DDR SYSTEM MEMORY B

AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13

AV16
AY18

BC17

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6

DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

SB_RCVEN#

DDR_B_RAS# 14

T61

DDR_B_WE# 14

DDR_B_BS0 14
DDR_B_BS1 14
DDR_B_BS2 14

DDR_B_DM[0..7] 14

DDR_B_DQS[0..7] 14

DDR_B_DQS#[0..7] 14

DDR_B_MA[0..14] 7,14

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((2/6)-DDR2 A/B CH

LA-3331P

1

of

859Tuesday, May 1 5, 2007

1.0

5

4

3

2

1

Strap Pin Table

010 = FSB 800MHz

CFG[2:0] FSB Freq select

D D

Tie to GND 4/24

C C

B B

Tie to GND 4/24

U4C

J40
H39
E39
E40
C37
D35
K40

L41
L43
N41
N40
D46
C45
D44
E42

G51
E51
F49

G50
E50
F48

G44
B47
B45

E44
A47
A45

E27
G27
K27

F27
J27
L27

M35

P33

H32
G32
K29
J29
F29
E29

K33
G35
F33
C32
E33

CRESTLINE_1p0

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2

TVA_DAC
TVB_DAC
TVC_DAC

TVA_RTN
TVB_RTN
TVC_RTN

TV_DCONSEL_0
TV_DCONSEL_1

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

LVDS

TV VGA

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_10

PEG_RX_11

PEG_RX_12

PEG_RX_13

PEG_RX_14

PEG_RX_15

PEG_TX#_0

PEG_TX#_1

PEG_TX#_2

PEG_TX#_3

PEG_TX#_4

PEG_TX#_5

PEG_TX#_6

PEG_TX#_7

PEG_TX#_8

PEG_TX#_9
PEG_TX#_10

PCI-EXPRESS GRAPHICS

PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_10

PEG_TX_11

PEG_TX_12

PEG_TX_13

PEG_TX_14

PEG_TX_15

PEGCOMP trace width and
spacing is 18/25 mils.

N43
M43

J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41

J50

PEG_RX_0

L50

PEG_RX_1

M47

PEG_RX_2

U44

PEG_RX_3

T49

PEG_RX_4

T41

PEG_RX_5

W45

PEG_RX_6

W41

PEG_RX_7

AB50

PEG_RX_8

Y48

PEG_RX_9

AC45
AC41
AH47
AG49
AH45
AG42

N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44

M45

PEG_TX_0

T38

PEG_TX_1

T46

PEG_TX_2

N50

PEG_TX_3

R51

PEG_TX_4

U43

PEG_TX_5

W42

PEG_TX_6

Y47

PEG_TX_7

Y39

PEG_TX_8

AC38

PEG_TX_9

AD47
AC50
AD43
AG39
AE50
AH43

PEGCOMP

PEG_RXP15
PEG_RXP14
PEG_RXP13
PEG_RXP12
PEG_RXP11
PEG_RXP10
PEG_RXP9
PEG_RXP8
PEG_RXP7
PEG_RXP6
PEG_RXP5
PEG_RXP4
PEG_RXP3
PEG_RXP2
PEG_RXP1
PEG_RXP0

PEG_RXN15
PEG_RXN14
PEG_RXN13
PEG_RXN12
PEG_RXN11
PEG_RXN10
PEG_RXN9
PEG_RXN8
PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_RXN4
PEG_RXN3
PEG_RXN2
PEG_RXN1
PEG_RXN0

PEG_TXP15
PEG_TXP14
PEG_TXP13
PEG_TXP12
PEG_TXP11
PEG_TXP10
PEG_TXP9
PEG_TXP8
PEG_TXP7
PEG_TXP6
PEG_TXP5
PEG_TXP4
PEG_TXP3
PEG_TXP2
PEG_TXP1
PEG_TXP0

PEG_TXN15
PEG_TXN14
PEG_TXN13
PEG_TXN12
PEG_TXN11
PEG_TXN10
PEG_TXN9
PEG_TXN8
PEG_TXN7
PEG_TXN6
PEG_TXN5
PEG_TXN4
PEG_TXN3
PEG_TXN2
PEG_TXN1
PEG_TXN0

+VCCP

R1652

24.9_0402_1%

1 2

PEG_RXP[0..15] 17

PEG_RXN[0..15] 17

C1242 0.1U_0402_16V4Z
C1243 0.1U_0402_16V4Z
C1244 0.1U_0402_16V4Z
C1245 0.1U_0402_16V4Z
C1246 0.1U_0402_16V4Z
C1247 0.1U_0402_16V4Z
C1248 0.1U_0402_16V4Z
C1249 0.1U_0402_16V4Z
C1250 0.1U_0402_16V4Z
C1251 0.1U_0402_16V4Z
C1252 0.1U_0402_16V4Z
C1253 0.1U_0402_16V4Z
C1254 0.1U_0402_16V4Z
C1255 0.1U_0402_16V4Z
C1256 0.1U_0402_16V4Z
C1257 0.1U_0402_16V4Z

C1258 0.1U_0402_16V4Z
C1259 0.1U_0402_16V4Z
C1260 0.1U_0402_16V4Z
C1261 0.1U_0402_16V4Z
C1262 0.1U_0402_16V4Z
C1263 0.1U_0402_16V4Z
C1264 0.1U_0402_16V4Z
C1265 0.1U_0402_16V4Z
C1266 0.1U_0402_16V4Z
C1267 0.1U_0402_16V4Z
C1268 0.1U_0402_16V4Z
C1269 0.1U_0402_16V4Z
C1270 0.1U_0402_16V4Z
C1271 0.1U_0402_16V4Z
C1272 0.1U_0402_16V4Z
C1273 0.1U_0402_16V4Z

PEG_M_TXP15
PEG_M_TXP14
PEG_M_TXP13
PEG_M_TXP12
PEG_M_TXP11
PEG_M_TXP10
PEG_M_TXP9
PEG_M_TXP8
PEG_M_TXP7
PEG_M_TXP6
PEG_M_TXP5
PEG_M_TXP4
PEG_M_TXP3
PEG_M_TXP2
PEG_M_TXP1
PEG_M_TXP0

PEG_M_TXN15
PEG_M_TXN14
PEG_M_TXN13
PEG_M_TXN12
PEG_M_TXN11
PEG_M_TXN10
PEG_M_TXN9
PEG_M_TXN8
PEG_M_TXN7
PEG_M_TXN6
PEG_M_TXN5
PEG_M_TXN4
PEG_M_TXN3
PEG_M_TXN2
PEG_M_TXN1
PEG_M_TXN0

PEG_M_TXP[0..15] 17

PEG_M_TXN[0..15] 17

Removed J14 4/27

CFG5 (DMI select)

CFG6

CFG7 (CPU Strap)

CFG8 (Low power PCIE)

CFG9

(PCIE Graphics Lane Reversal)

CFG[11:10]

CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

SDVO_CTRLDATA

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

CFG57

CFG77

CFG87

CFG97

CFG127

CFG137

CFG167

CFG[17:3] have internal pull up
CFG[19:18] have internal pull down

CFG197

A A

CFG207

011 = FSB 667MHz
Others = Reserved

0 = DMI x 2
1 = DMI x 4

*

Reserved

0 = Reserved
1 = Mobile CPU

*

0 = Normal mode
1 = Low Power mode

0 = Reverse Lane
1 = Normal Operation

Reserved
00 = Reserved

01 = XOR Mode Enabled
10 = All Z Mode Enabled

11 = Normal Operation

ReservedCFG[15:14]

0 = Disabled
1 = Enabled

*

ReservedCFG[18:17]

0 = No SDVO Device Present
1 = SDVO Device Present

0 = Normal Operation

(Lane number in Order)

1 = Reverse Lane

0 = Only PCIE or SDVO is operational.
1 = PCIE/SDVO a r e o p e r a t ing simu.

R1653 4.02K_0402_1%~D@

1 2

R1654 4.02K_0402_1%~D@

1 2

R1655 4.02K_0402_1%~D@

1 2

R1656 4.02K_0402_1%~D@

1 2

R1657 4.02K_0402_1%~D@

1 2

R1658 4.02K_0402_1%~D@

1 2

R1661 4.02K_0402_1%~D@

1 2

R1662

1 2

1 2

4.02K_0402_1%~D@

4.02K_0402_1%~D@

R1663

*
*

(Default)

*

+3VS

*

*

*

Change Value
form 2.2K to

4.02K.

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((3/6)-VGA/LVDS/TV

LA-3331P

1

of

959Tuesday, May 1 5, 2007

1.0

5

D D

+1.25VM_HPLL+1.25VM

R1664

0_0805_5%

1 2

Modify from
22uF to 10uF.
6/24

+1.25VM +1.25VM_MPLL

R1667
0_0805_5%

C C

+1.25VS

BLM18PG121SN1D_0603

Add regarding
DG1.0 (page

466). 6/8

B B

1 2

Modify from
22uF to 10uF.
6/24

L15

1 2

R2133

Add in 4/24

C1294

+1.5VS

C1321

1_0603_1%

1 2

10U_0805_10V4Z

1

2

10U_0805_10V4Z

1

2

1

C1276

2

1

1

C1284

C1285

2

2

10U_0805_10V4Z

+1.25VS_PEGPLL

0.1U_0402_16V4Z

1

C1295

2

0.1U_0402_16V4Z
C1323

C1322

1

2

Del R1665,R1666,C1274,C1275,C1277,C1278
4/27

10U_0805_10V4Z

Tied to GND after HP
confirm with Intel. 6/15

+3VS

1

+

2

150U_D_6.3VM

12

R1671
0_0603_5%

C1292

0.1U_0402_16V4Z

R1673
0_0805_5%

1 2

C1297

22U_0805_6.3V4Z

1

C1311

2

12

+1.25VM_A_SM_CK

1

C1303

2

+1.25VS_PEGPLL

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.25VM

R1675 0_0603_5%

5.

0.022U_0402_16V7K

1

+1.25VM_HPLL

2

C1296

4

Connect to GND 4/27
(DG0.9 P.191)

+3VS_PEG_BG

1

2

1

C1298

4.7U_0805_6.3V6K

2

1

C1304

2

22U_0805_6.3V4Z

Change net in 5/02 (DG0.9 P.174)

+1.25VM_A_SM

1

2

1

C1305

2

1U_0603_10V4Z

1U_0402_6.3V4Z

1

C1552

2

0.1U_0402_16V4Z

C1299

1

C1306

2

1

2

1U_0603_10V4Z

0.1U_0402_16V4Z

U4H

J32

3.

4.

VCCSYNC

A33

VCCA_CRT_DAC_1

B33

VCCA_CRT_DAC_2

A30

VCCA_DAC_BG

B32

VSSA_DAC_BG

B49

VCCA_DPLLA

H49

VCCA_DPLLB

AL2

VCCA_HPLL

AM2

VCCA_MPLL

A41

VCCA_LVDS

B41

VSSA_LVDS

K50

VCCA_PEG_BG

K49

VSSA_PEG_BG

U51

VCCA_PEG_PLL

AW18

VCCA_SM_1

AV19

VCCA_SM_2

AU19

VCCA_SM_3

AU18

VCCA_SM_4

AU17

VCCA_SM_5

AT22

VCCA_SM_7

AT21

VCCA_SM_8

AT19

VCCA_SM_9

AT18

VCCA_SM_10

AT17

VCCA_SM_11

AR17

VCCA_SM_NCTF_1

AR16

VCCA_SM_NCTF_2

BC29

VCCA_SM_CK_1

BB29

VCCA_SM_CK_2

C25

VCCA_TVA_DAC_1

B25

VCCA_TVA_DAC_2

C27

VCCA_TVB_DAC_1

B27

VCCA_TVB_DAC_2

B28

VCCA_TVC_DAC_1

A28

VCCA_TVC_DAC_2

M32

VCCD_CRT

L29

VCCD_TVDAC

N28

VCCD_QDAC

AN2

VCCD_HPLL

U48

VCCD_PEG_PLL

2.

J41

VCCD_LVDS_1

H42

VCCD_LVDS_2

CRESTLINE_1p0

Tie to GND 4/24

1.

POWER

CRTPLLA PEGA SMTV

A CK A LVDS

D TV/CRTLVDS

3

VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5

AXD

VCC_AXD_6

VCC_AXD_NCTF

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

VCC_TX_LVDS

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4

PEG

VCC_PEG_5

VCC_RXR_DMI_1
VCC_RXR_DMI_2

DMI

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13

VTT

VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22

VCC_DMI

VCC_HV_1
VCC_HV_2

HV

VTTLF1
VTTLF2
VTTLF3

VTTLF

U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

AT23
AU28
AU24
AT29
AT25
AT30

AR29

B23
B21
A21

AJ50

BK24
BK23
BJ24
BJ23

A43

C40
B40

AD51
W50
W51
V49
V50

AH50
AH51

A7
F2
AH1

C1312

+VCCP

0.47U_0603_10V7K

+1.25VM_AXD

0.47U_0603_10V7K

C1313

1

2

1

C1288

2

1.

1

2

1

+

C1279

2

330U_D2E_2.5VM_R7

0.47U_0603_10V7K

1

C1281

2

1U_0603_10V4Z

1

C1289

2

1

C1300

2

+VCC_PEG

0.47U_0603_10V7K

C1314

1

2

1

C1280

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

C1282

2

R1669
0_0805_5%

1 2

10U_0805_10V4Z

0.1U_0402_16V4Z

1

C1301

2

220U_D2_4VM

1

+

C1308

2

2

2.2U_0805_16V4Z

1

C1283

2

+1.25VM

1

C1302

2

10U_0805_10V4Z

10U_0805_10V4Z

Change value. 9/6

10U_0805_10V4Z

1

1

C1309

C1310

2

2

Intel Design Guide :
If LVDS/SDVO are disable : (P165)

1. VCCTX_LVDS & VCCA_LVDS connect to GND.

2. VCCD_LVDS connect to GND.
If internal VGA is disable : (P174)

3. VCCA_CRTDAC & VSSA_CRTDAC & VCC_SYNC are
connect to GND.

If internal VGA/TV-Out are disable : (P192)

4. VCCDTVDAC , VCCDQTVDAC , VCCATVDAC[A:C] ,
VCCATVBG , VSSATVBG are connect to GND.

5. VCCD_TVO connect to +1.5VS for thermal
sensor.

+V1.25VS_AXF

10U_0805_10V4Z

1

1

C1290

C1291

2

2

R1674
0_0805_5%

1 2

Modify from
22uF to 10uF.
6/24

L22

BLM18PG330SN1_2P

1 2

10U_0805_10V4Z

Del R1679 in 5/03

R1670
0_0603_5%

1 2

1U_0603_10V4Z

+1.25VS_DMI

+1.8V+1.8V_SM_CK

+VCCP

+1.25VS

1 2

0.1U_0402_16V4Z

1

C1293

2

+3VS_HV

+1.25VS

R1672
0_0603_5%

R1676 10_0402_5%

0.1U_0402_16V4Z

1

C1307

R1677 0_0402_5%

2

(Crestline 0.7 Page.9)

1

Del R1668,C1286,C1287 4/30
(Un-used +1.5VS_TVDAC)

+VCCP_D

D57

1 2

1 2

CH751H-40_SC76

21

+VCCP

+3VS

Add in 4/28

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

CRESTLINE(4/6)-PWR

LA-3331P

1

1.0

of

10 59Tuesday, May 15, 2007

5

4

3

2

1

Per DG9.0 P.191 , connect VCC_AXG to GND if don't use

+VCCP

Del R1685 and D58 cause duplicate on P10. 6/28

C1331

10U_0805_10V4Z

C1347

+VCCP

0.1U_0402_16V4Z

C1332

1

2

C1338

1

2

0.1U_0402_16V4Z
C1348

1

2

Change in 4/24

1 2

2

G

Q115

13

D

S

U4F

AB33
AB36
AB37
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37

AJ33

AJ35
AK33
AK35
AK36
AK37
AD33

AJ36
AM35

AL33

AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36

Y32
Y33
Y35
Y36
Y37
T30
T34
T35
U29
U31
U32
U33
U35
U36
V32
V33
V36
V37

AL24

AL26

AL28
AM26
AM28
AM29
AM31
AM32
AM33
AP29
AP31
AP32
AP33

AL29

AL31

AL32
AR31
AR32
AR33

CRESTLINE_1p0

R2051
100K_0402_5% @

CRACK_BGA

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50

VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19

1 2

MCHGND3

Q116

RHU002N06_SOT323@

VCC NCTF

POWER

VCC AXM NCTF

CRACK_BGA

Change in 4/24

13

D

2

G

S

4

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15

VSS NCTF

VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

VSS SCBVCC AXM

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7

R2052
100K_0402_5% @

MCHGND4

RHU002N06_SOT323 @

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

A3
B2
C1
BL1
BL51
A51

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

Q117

MCHGND1
MCHGND3

MCHGND4
MCHGND2

1 2

R132 0_0402_5%
R122 0_0402_5%

R113 0_0402_5%
R111 0_0402_5%

CRACK_BGA

Change in 4/24

13

D

2

G

S

R1686
0_0603_5%

1 2

+1.8V

0.01U_0402_16V7K

1

2

C1335

C1336

2

1

22U_0805_6.3V4Z

1 2
1 2

1 2
1 2

+1.05VM

1

1

+

C1334

C1333

2

2

330U_6.3V_M

22U_0805_6.3V4Z

Del C1339 ~ C1343 in 4/27.

CRACK_BGA 22,34

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

D D

220U_D2_2VK_R9

22U_0805_6.3V4Z

1

C1328

+

2

C C

B B

0.22U_0402_10V4Z
C1344

1

1

2

2

Add in 4/21
Remove in 5/02

+3VS +3VS +3VS +3VS

R2049

A A

100K_0402_5% @

Change in 4/24

1 2

13

Q114

D

2

G

S

MCHGND1

RHU002N06_SOT323 @

0.22U_0402_10V4Z

C1329

1

2

0.22U_0402_10V4Z
C1345

CRACK_BGA

5

0.22U_0402_10V4Z

C1330

1

1

2

2

+1.05VM

10U_0805_10V4Z

C1337

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C1346

1

1

2

2

R2050
100K_0402_5% @

MCHGND2

RHU002N06_SOT323 @

integrated Graphice. 4/27

U4G

AT35

VCC_1

AT34

VCC_2

AH28

VCC_3

AC32

VCC_5

AC31

VCC_4

AK32

VCC_6

AJ31

VCC_7

AJ28

VCC_8

AH32

VCC_9

AH31

VCC_10

AH29

VCC_11

AF32

VCC_12

R30

VCC_13

VCC CORE

POWER

AU32

VCC_SM_1

AU33

VCC_SM_2

AU35

VCC_SM_3

AV33

VCC_SM_4

AW33

VCC_SM_5

AW35

VCC_SM_6

AY35

VCC_SM_7

BA32

VCC_SM_8

BA33

VCC_SM_9

BA35

VCC_SM_10

BB33

VCC_SM_11

BC32

VCC_SM_12

BC33

VCC_SM_13

BC35

VCC_SM_14

BD32

VCC_SM_15

BD35

VCC_SM_16

BE32

VCC_SM_17

BE33

VCC_SM_18

BE35

VCC_SM_19

BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35

BJ32
BJ33

BJ34
BK32
BK33
BK34
BK35

BL33
AU30

W13
W14

AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31

AJ20
AN14

R20
T14

Y12

VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

CRESTLINE_1p0

VCC SMVCC GFX

VCC GFX NCTF

2

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

VCCSM_LF1

AW45

VCCSM_LF2

BC39

VCCSM_LF3

BE39

VCCSM_LF4

BD17

VCCSM_LF5

BD4

VCCSM_LF6

AW8

VCCSM_LF7

AT6

Title

Size Document Number Rev

Custom

Date: Sheet

CRESTLINE((5/6)-PWR/GND

LA-3331P

Del C1325 ~ C1327 in 4/27.

C1351

C1349

C1350

C1352

1

1

1

1

0.22U_0603_10V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.22U_0603_10V7K

2

2

2

2

Compal Electronics, Inc.

1

C1354

C1353

C1355

1

1

1

1U_0603_10V4Z

0.47U_0402_6.3V6K

1U_0603_10V4Z

2

2

2

1.0

of

11 59Tuesday, May 1 5, 2007

5

U4I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

AB20

D D

C C

B B

A A

AB23
AB26
AB28
AB31
AC10
AC13

AC39
AC43
AC47

AD21
AD26
AD29

AD41
AD45
AD49

AD50
AE10

AE14
AF20

AF23
AF24
AF31

AG38
AG43
AG47
AG50

AH40
AH41

AK20
AK21
AK26
AK28
AK31
AK51

AM11
AM13

AM41
AM45

AN38
AN39
AN43

AP48
AP50
AR11

AR39
AR44
AR47

AT10
AT14
AT41
AT49

AU23
AU29

AU36
AU49
AU51
AV39
AV48

AW12
AW16

AC3

AD1

AD3

AD5
AD8

AE6

AG2

AH3

AH7

AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49

AL1

AM3
AM4

AN1

AN5

AN7

AP4

AR2

AR7

AU1

AU3

AW1

VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

CRESTLINE_1p0

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

4

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

3

U4J

C46
C50

C7
D13
D24

D3
D32
D39
D45
D49
E10
E16
E24
E28
E32
E47
F19
F36

F4
F40
F50

G1

G13
G16
G19
G24
G28
G29
G33
G42
G45
G48

G8
H24
H28

H4
H45
J11
J16

J2
J24
J28
J33
J35
J39

K12
K47

K8

L1
L17
L20
L24
L28

L3
L33
L49

M28
M42
M46
M49

M5

M50

M9
N11
N14
N17
N29
N32
N36
N39
N44
N49

N7
P19

P2
P23

P3
P50
R49
T39
T43
T47
U41
U45
U50

V2

V3

CRESTLINE_1p0

VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243

VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286

VSS

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

2

1

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

CRESTLINE((6/6)-PWR/GND

LA-3331P

1

1.0

of

12 59Tuesday, May 1 5, 2007

5

DDR_A_DQS#[0..7]8

DDR_A_D[0..63]8

DDR_A_DM[0..7]8
DDR_A_DQS[0..7]8
DDR_A_MA[0..13]8

D D

Layout Note:
Place near JP9

+1.8V

1

+

C1548

2

470U_D2_2.5VM_R15

C461

C467

1

1

2

2

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z
C462

C463

1

1

2

2

0.1U_0402_16V4Z

2.2U_0805_16V4Z
C464

1

2

0.1U_0402_16V4Z

C105

C93

1

1

2

2

Add 470uF in 4/25

C C

0.1U_0402_16V4Z

1

1

2

2

C80

+0.9V

0.1U_0402_16V4Z

1

2

C81

C82

RP13 56_0404_4P2R_5%

14
23

RP18 56_0404_4P2R_5%

14
23

RP12 56_0404_4P2R_5%

14
23

RP17 56_0404_4P2R_5%

14
23

RP16 56_0404_4P2R_5%

14
23

RP14 56_0404_4P2R_5%

14
23

RP19 56_0404_4P2R_5%

14
23

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9V

0.1U_0402_16V4Z

1

2

C79

RP11

1 4
2 3

RP7

1 4
2 3

RP15

1 4
2 3

RP10

1 4
2 3

RP9

1 4
2 3

RP8

2 3
1 4

1 2

R2135
56_0402_5%

0.1U_0402_16V4Z

1

2

C78

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

5

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C83

B B

DDR_A_MA5
DDR_A_MA8

DDR_A_MA1
DDR_A_MA3

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_BS#0
DDR_A_MA10

A A

DDR_A_CAS#
DDR_A_WE#

DDR_CS1_DIMMA#
M_ODT1

DDR_A_MA14

Add for using DDR2 2Gb tech. 6/9

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C115

C84

DDR_A_BS#2
DDR_CKE0_DIMMA

DDR_A_MA7
DDR_A_MA6

DDR_A_MA9
DDR_A_MA12

DDR_A_MA4
DDR_A_MA2

DDR_A_MA0
DDR_A_BS#1

M_ODT0
DDR_A_MA13

DDR_CKE1_DIMMA
DDR_A_MA11

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C111

C110

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C95

C91

1

1

2

2

0.1U_0402_16V4Z

1

1

2

2

C112

C113

Layout Note:
Place these resistor
closely JP9,all
trace length Max=1.5"

4

3

+1.8V +1.8V

JP9

1

VREF

3

DDR_A_D4
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D9
DDR_A_D15

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D29
DDR_A_D24

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA7

DDR_A_BS28

DDR_A_BS08

DDR_A_WE#8

DDR_A_CAS#8

DDR_CS1_DIMMA#7

0.1U_0402_16V4Z

1

2

C114

Add 2.2uF and Change
+3VS to +3VM in 4/25

M_ODT17

ICH_SMBDATA14,15,21

ICH_SMBCLK14,15,21

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D37

DDR_A_D36
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D35

DDR_A_D32
DDR_A_D40

DDR_A_D44
DDR_A_DM5
DDR_A_D41

DDR_A_D46
DDR_A_D49

DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D54
DDR_A_D50

DDR_A_D61
DDR_A_D60

DDR_A_DM7
DDR_A_D59

DDR_A_D58

+3VM

C96

1

1

C1546

2

2

2.2U_0603_6.3V6K

2006/02/13 2006/03/10

Compal Secret Data

5

7

9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

0.1U_0402_16V4Z

Deciphered Date

VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

FOX_ASOA426-M4R-TRconn@

SO-DIMM A

REVERSE

Top side

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1

RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

2

V_DDR_MCH_REF

2

DDR_A_D6

4

DDR_A_D0

6
8

DDR_A_DM0

10
12

DDR_A_D5

14

DDR_A_D7

16
18

DDR_A_D13

20

DDR_A_D12

22
24

DDR_A_DM1

26
28
30
32
34

DDR_A_D11

36

DDR_A_D10

38
40

42

DDR_A_D20

44

DDR_A_D21

46
48
50

NC

A11

A7
A6

A4
A2
A0

S0#

NC

2

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_DM2
DDR_A_D23

DDR_A_D22
DDR_A_D28

DDR_A_D25
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D31

DDR_A_D30
DDR_CKE1_DIMMA

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D39
DDR_A_D38

DDR_A_DM4
DDR_A_D34

DDR_A_D33
DDR_A_D45

DDR_A_D43
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D47

DDR_A_D42
DDR_A_D52

DDR_A_D53

DDR_A_DM6
DDR_A_D51

DDR_A_D55
DDR_A_D57

DDR_A_D56
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

R40

R38

10K_0402_5%

10K_0402_5%

12

2.2U_0805_16V4Z
C97

1

2

M_CLK_DDR0 7
M_CLK_DDR#0 7

PM_EXTTS#0 7

DDR_CKE1_DIMMA 7

DDR_A_MA14 7

DDR_A_BS1 8
DDR_A_RAS# 8
DDR_CS0_DIMMA# 7

M_ODT0 7

M_CLK_DDR1 7
M_CLK_DDR#1 7

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

LA-3331P

1

0.1U_0402_16V4Z

1

2

Add for using DDR2
2Gb tech. 6/9

V_DDR_MCH_REF 7,14,45

C92

1

1.0

of

13 59Tuesday, May 1 5, 2007

5

DDR_B_DQS#[0..7]8

DDR_B_D[0..63]8
DDR_B_DM[0..7]8

DDR_B_DQS[0..7]8

DDR_B_MA[0..13]8

D D

Layout Note:
Place near JP34

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C109

C108

1

2

0.1U_0402_16V4Z

1

2

C87

RP34

1 4
2 3

RP35

56_0404_4P2R_5%

1 4
2 3

RP3

56_0404_4P2R_5%

1 4
2 3

RP2

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

RP36

1 4
2 3

RP37

56_0404_4P2R_5%

2 3
1 4

56_0404_4P2R_5%

1 2

C460

1

2

0.1U_0402_16V4Z

1

2

C C

B B

A A

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C86

C85

DDR_B_MA1
DDR_B_MA3

DDR_B_BS#0
DDR_B_MA10

DDR_B_MA0
DDR_B_BS#1

DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_CAS#
DDR_B_WE#

DDR_CS3_DIMMB#
M_ODT3

DDR_B_MA14

R2136
56_0402_5%

1

2

0.1U_0402_16V4Z

1

1

2

2

C88

+0.9V

2.2U_0805_16V4Z

C466

C107

1

2

0.1U_0402_16V4Z

1

2

C89

C90

RP32 56_0404_4P2R_5%

14
23

RP6 56_0404_4P2R_5%

14
23

RP33 56_0404_4P2R_5%

14
23

RP5 56_0404_4P2R_5%

14
23

RP4 56_0404_4P2R_5%

14
23

RP1 56_0404_4P2R_5%

14
23

RP31

14
23

56_0404_4P2R_5%

0.1U_0402_16V4Z
C94

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C477

DDR_B_MA9
DDR_B_MA12

DDR_B_MA7
DDR_CKE3_DIMMB

DDR_B_MA5
DDR_B_MA8

DDR_B_MA6
DDR_B_MA11

DDR_B_MA4
DDR_B_MA2

M_ODT2
DDR_B_MA13

DDR_B_BS#2
DDR_CKE2_DIMMB

0.1U_0402_16V4Z

C476

5/16

5/16

0.1U_0402_16V4Z

C455

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C475

Add for using DDR2 2Gb tech. 6/9

5

4

0.1U_0402_16V4Z
C454

C106

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C473

C474

C472

Layout Note:
Place these resistor
closely JP10,all
trace length Max=1.5"

4

3

+1.8V +1.8V

JP29

1

VREF

3

DDR_B_D1
DDR_B_D0

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D17
DDR_B_D20

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D28

DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB7

DDR_B_BS28

DDR_B_BS08
DDR_B_WE#8

DDR_B_CAS#8

0.1U_0402_16V4Z

1

2

C471

Add 2.2uF and Change
+3VS to +3VM in 4/25

DDR_CS3_DIMMB#7

M_ODT37

ICH_SMBDATA13,15,21

ICH_SMBCLK13,15,21

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D56
DDR_B_D61

DDR_B_DM7
DDR_B_D59

DDR_B_D58

+3VM +3VM

1

1

C453

C1547

2

2

0.1U_0402_16V4Z

2.2U_0603_6.3V6K

2006/02/13 2006/03/10

Compal Secret Data

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2RN-7Fconn@

SO-DIMM B
STANDARD

Bottom side

Deciphered Date

VSS
DQ4
DQ5

VSS
DM0

VSS
DQ6
DQ7

VSS

DQ12
DQ13

VSS
DM1

VSS

CK0

CK0#

VSS

DQ14
DQ15

VSS

VSS

DQ20
DQ21

VSS
DM2

VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

VDD

VDD

BA1

RAS#

S0#
VDD

ODT0

NC/A13

VDD

VSS

DQ36
DQ37

VSS
DM4

VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS

CK1

CK1#

VSS
DM6

VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS

SA0

SA1

2

V_DDR_MCH_REF

2

DDR_B_D5

4

DDR_B_D4

6
8

DDR_B_DM0

10
12

DDR_B_D6

14

DDR_B_D7

16
18

DDR_B_D12

20

DDR_B_D13

22
24

DDR_B_DM1

26
28
30
32
34

DDR_B_D14

36

DDR_B_D15

38
40

42

DDR_B_D21

44

DDR_B_D16

46
48
50

NC

A7
A6

A4
A2
A0

NC

2

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D26

DDR_B_D24DDR_B_D25
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D29

DDR_B_D27
DDR_CKE3_DIMMB

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D39

DDR_B_D38
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53

DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D57
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

10K_0402_5%

12

R34

2.2U_0805_16V4Z

0.1U_0402_16V4Z

1

1

C99

2

2

M_CLK_DDR3 7
M_CLK_DDR#3 7

PM_EXTTS#1 7,47

DDR_CKE3_DIMMB 7

DDR_B_MA14 7

DDR_B_BS1 8
DDR_B_RAS# 8
DDR_CS2_DIMMB# 7

M_ODT2 7

M_CLK_DDR2 7
M_CLK_DDR#2 7

R33

1 2

10K_0402_5%

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA-3331P

1

V_DDR_MCH_REF 7,13,45

C103

Add for using DDR2
2Gb tech. 6/9

Change +3VS t o +3VM in 5/15,
cause OTS 2654 41 and 261307.

of

14 59Tuesday, May 1 5, 2007

1

1.0

5

PCI

SRC

CPU

CLKSEL1

1

1

FSLA

CLKSEL0

MHz

200

166

MHz

1000

100

MHz

33.30

33.3

FSLC1FSLB

CLKSEL2

0

FSB Frequency Selet:

R1716

CPU Driven

D D

(Default)

*

667MHz

800MHz

Stuff

No Stuff

Stuff

No Stuff

Stuff

R1689

R1689

R1694 R1705

No Stuff

+VCCP

FSA

C C

CPU_BSEL05

CPU_BSEL15

B B

R1690 2.2K_0402_5%

R1716 0_0402_5%

12

1 2

R1694 0_0402_5%

CLK_Ra

FSB

1 2

CLK_Rb

+VCCP

R1705

1 2

Del tie to +VCCP.7/28

FSC

CPU_BSEL25

A A

R1730 8.2K_0402_5%

14.31818MHZ_20P_1BX14318BE1A

Y6

2

C138322P_0402_50V8J

1

12

1 2

R1734 0_0402_5%

CLK_Rc

CLK_XTAL_OUT

CLK_XTAL_IN

12

2

C1384

22P_0402_50V8J

1

5

R1734R1694

R1705R1696 R1719 R1737R1726

R1696

R1737R1734

R1716 R1719

R1726

R1737R1734

R1694R1689

R1696 R1716 R1719R1705

Add option for FSB frequency by jumper.11/08
Del jumper(JP62, JP63) in 3/14.

R1689

56_0402_5%@

CLK_Rd

1 2

1 2

R1691 1K_0402_5%

12

R1696

1K_0402_5%@

1K_0402_5%@

1 2

R1713 1K_0402_5%

CLK_PCI_DB33

CLK_PCI_SIO32
CLK_PCI_TCG33
CLK_PCI_EC34

CLK_PCI_PCM27

CLK_PCI_ICH19

MCH_CLKSEL0 7

CLKSATAREQ#21

MCH_CLKSEL1 7

Remove R1722 in 4/24.(Richo don't need 48MHz)

CLK_48M_ICH21

Change from 12.1 to 33
4/30 (Same as Chimay)

CLK_14M_ICH21

CLK_14M_SIO32

1 2

R1731 1K_0402_5%

12

R1737

0_0402_5%@

CLK_14M_KBC34

MCH_CLKSEL2 7

CLK_Rf

Change from +3.3VM_CK505 to +3VS. 6/9

+3VS

R1744
10K_0402_5%

1 2

ITP_EN

R1747

@

10K_0402_5%

1 2

4

+3VM

1 2

R1687 0_1206_5%

R1726

R1700 475_0402_1%

CLKREQB#7

CLK_PCI_DB
CLK_PCI_SIO
CLK_PCI_TCG
CLK_PCI_EC
CLK_PCI_PCM

CLK_PCI_ICH

CLK_48M_ICH

CLK_14M_ICH
CLK_14M_SIO
CLK_14M_KBC

+3VS +3VS

R1745

@

10K_0402_5%

1 2

27_SEL

R1748
10K_0402_5%

1 2

R1701 475_0402_1%

4

+3VM_CK505

1

2

C1359
10U_0805_10V4Z

+1.25VM_CK505

12
12
12

12
1 2
1 2
1 2

1 2

1 2

1 2
1 2
1 2

+1.25VM_CK505

Modify at 5/14.

R1746
10K_0402_5%

1 2

PCI2_TME

R1749

@

10K_0402_5%

1 2

3

Removed C1366~C1368 4/30 (Same as Chimay)

C1360

0.1U_0402_16V4Z

1

2

1

2

C1361

0.1U_0402_16V4Z

C1362

0.1U_0402_16V4Z

1

2

1

2

C1363

0.1U_0402_16V4Z

03/02 change

R170422_0402_5%
R170612_0402_5%
R170812_0402_5%
R170912_0402_5%
R171112_0402_5%

R171422_0402_5%

R172433_0402_1%

R172933_0402_1%
R173233_0402_1%
R173333_0402_1%

+3VM_CK505

CLK_XTAL_IN
CLK_XTAL_OUT

FSA

FSB

FSC

U30

2

VDD_PCI

9

VDD48

16

VDDPLL3

61

VDDREF

39

VDDSRC

55

VDDCPU

12

VDD96_IO

20

VDDPLL3_IO

26

VDDSRC_IO

36

VDDSRC_IO

49

VDDCPU_IO

PCI_CLK0

1

PCI0/CR#_A

PCI_CLK1

3

PCI1/CR#_B

PCI2_TME

4

PCI2/TME

PCI_CLK3

5

PCI3

27_SEL

6

PCI4/27_Select

ITP_EN

7

PCIF5/ITP_EN

60

X1

59

X2

10

USB_48MHZ/FSLA

57

FSLB/TEST MODE

62

REF0/FSLC/TEST_SEL

45

VDDSRC_IO

42

GNDSRC

8

GNDPCI

11

GND48

15

GND

19

GND

52

GNDCPU

23

GNDSRC

29

GNDSRC

58

GNDREF

* Internal Pull-Up Resistor
** Internal Pull-Down Resistor

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

CPU_STOP#

SRC11/CR#_H

SRC11#/CR#_G

SRC7/CR#_F

SRC7#/CR#_E

SRC3/CR#_C

SRC3#/CR#_D

SRC2#/SATA#

SRC1/SE1/27MHz_NonSS

SRC1#/SE2/27MHz_SS

SRC0/DOT96

SRC0/DOT96#

CK_PWRGD/PD#

ICS9LPRS355_TSSOP64

2006/02/13 2006/03/10

SCLK

SDATA

PCI_STOP#

CPU0

CPU0#

CPU1_F

CPU1#_F

SRC8/ITP

SRC8#/ITP#

SRC10#

SRC10

SRC9

SRC9#

SRC6

SRC6#

SRC4

SRC4#

SRC2/SATA

2

C1364

0.1U_0402_16V4Z

1

2

1

C1365

0.1U_0402_16V4Z

2

Install R1688 4/28

Del Q79 in 5/19.

+1.25VM_CK505+1.25VM

R1688
0_1206_5%

12

1

48

NC

64
63

38
37

Del RP49, RP51 ~ R P5 7 from PV build. 3/19

54
53

51
50

R_CPU_XDP

47

R_CPU_XDP#

46

35
34

33
32

30
31

44
43

41
40

27
28

24
25

21
22

17
18

13
14

56

R_CLKREQ#_H
R_CLKREQ#_G

R_CLKREQ#_F
R_CLKREQ#_E

R1710 475_0402_1%
R1712 475_0402_1%

R2067 475_0402_1%
R1721 475_0402_1%

Add in 5/02 for Roberson.
Del in 5/21.

Del in 4/24

2

C1377
10U_0805_10V4Z

R1707 10K_0402_5%

12
12

R1715 10K_0402_5%

R2066 10K_0402_5%

12
12

R1720 10K_0402_5%

Compal Secret Data

Deciphered Date

2

C1378

0.1U_0402_16V4Z

1

2

1 2

1 2

1 2

1 2

1

C1356
C1357
C1358
C1369
C1370
C1371
C1372
C1373
C1374
C1375

12
12
12
12
12
12
12
12
12
12

Del C1376. 5/19

Place close to U30

C1380
10U_0805_10V4Z

1

1

2

C1379

0.1U_0402_16V4Z

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4

CLK_MCH_BCLK 7
CLK_MCH_BCLK# 7

CLK_PCIE_DOCK 36
CLK_PCIE_DOCK# 36

CLKREQG# 26

CLK_PCIE_MCARD 26
CLK_PCIE_MCARD# 26

CLKREQF# 26
CLKREQE# 17

CLK_PCIE_MXM 17
CLK_PCIE_MXM# 17

CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7

CLK_PCIE_ICH 21
CLK_PCIE_ICH# 21

CLK_PCIE_SATA 20
CLK_PCIE_SATA# 20

CK_PWRGD 21

2

ICH_SMBCLK 13,14,21
ICH_SMBDATA 13,14,21

H_STP_PCI# 21
H_STP_CPU# 21

R_CPU_XDP
R_CPU_XDP#

R_CPU_XDP
R_CPU_XDP#

+3VS

CPPE# 36

+3VS

+3VS

Add for Roberson 4/28

+3VS

Title

Size Document Number Rev

LA-3331P

Date: Sheet

C1382

0.1U_0402_16V4Z

1

1

2

2

C1381

0.1U_0402_16V4Z

RP48

0_0404_4P2R_5% @

1 4
2 3

1 4
2 3

RP50

0_0404_4P2R_5% @

In order to take advantage
of the Robson CLKREQ ,
share SRC8 with Robson and
the XDP. 5/21

Cuase layout issue
change all diff pair's
damping to 0404
package RP. 6/3

Compal Electronics, Inc.

CLOCK GENERATOR

1

CLK_48M_ICH

5P_0402_50V8C@

CLK_14M_ICH

4.7P_0402_50V8C@

CLK_PCI_ICH

4.7P_0402_50V8C@

CLK_14M_KBC

4.7P_0402_50V8C@

CLK_14M_SIO

4.7P_0402_50V8C@

CLK_PCI_EC

4.7P_0402_50V8C@

CLK_PCI_TCG

4.7P_0402_50V8C@

CLK_PCI_PCM

4.7P_0402_50V8C@

CLK_PCI_SIO

4.7P_0402_50V8C@

CLK_PCI_DB

5P_0402_50V8C@

CLK_PCIE_NAND 26
CLK_PCIE_NAND# 26

CLK_CPU_XDP 4
CLK_CPU_XDP# 4

of

15 59Tuesday, May 1 5, 2007

1.0

A

CRT Connector

1 1

+5VS

0.1U_0402_16V4Z

1

5

R30651K_0402_5%

1 2

R30851K_0402_5%

1 2

P

A2Y

G

3

M_HSYNC17

M_VSYNC17

2 2

+5VS

C293

1 2

U24
SN74AHCT1G125GW_SOT353-5

4

OE#

5

A2Y

3

Place cloce to MXM connector JP39

L

B

BLUE36

GREEN36

RED36

1

1

C74

C77

2

2

5P_0402_50V8C

C294

1 2

0.1U_0402_16V4Z

HSYNC D_HSYNC

1

P

VSYNC D_ VSYNC

4

OE#

G

U23
SN74AHCT1G125GW_SOT353-5

@

R312 0_0603_5%

1 2

R310 0_0603_5%

1 2

Change value from BK2125LL560-T
0805 to 0_0805. 5/19

1

C71

2

5P_0402_50V8C

5P_0402_50V8C

@

@

5P_0402_50V8C@

R31 0_0805_5%

1 2

1 2

1 2

1

1

2

2

C325

5P_0402_50V8C@

R29 0_0805_5%

R26 0_0805_5%

C326

C

D3

2 1

21

CH491D_SC59

0.1U_0402_16V4Z

C420

RED_R

GREEN_R

BLUE_R

W=40mils

1

2

2.2K_0402_5%

C73

1

2

18P_0402_50V8J@

1.1A_6VDC_FUSE

C75

C76

1

1

2

2

18P_0402_50V8J@

D_HSYNC 36

D_VSYNC 36

D_DDCDATA36

D_DDCCLK36

F1

18P_0402_50V8J@

L

D

+CRTVDD+RCRT_VCC+5VS

JP7

6

11

1
7

12

2
8

13

3
9

14

18

4

19
10
15

5

FOX_DZ11A91-L7conn@

+CRTVDD +CRTVDD

12

12

R446

R445

2.2K_0402_5%

1 3

Q68

D

BSS138_SOT23

Q67
BSS138_SOT23

2

G

1 3

D

S

2

G

Place cloce to MXM connector JP39

BLUE
GREEN
RED

+3VS

R4502.2K_0402_5%

1 2

S

R4492.2K_0402_5%

1 2

E

R666150_0402_1%@

R664150_0402_1%@

R665150_0402_1%@

12

12

12

M_DDCDATA 17

M_DDCCLK 17

+5VS

21

D65
RB411D_SOT23

3 3

R1990 1K_0402_1%

12

R1991
10K_0402_1%

1 2

HDMI_DETECT17

D66

SKS10-04AT_TSMA

4 4

A

2 1

HDMI Connector

L23

1 2

FBML10160808121LMT_0603

1

C1578

330P_0402_50V7K

Add in 8/25.

B

2

R212210K_0402_5%

R212110K_0402_5%

1

C1493

1 2

1 2

Add in 6/5.

HDMIDAT18
HDMICLK18

HDMI_CLK-18

HDMI_CLK+18

HDMI_TX0-18

HDMI_TX0+18

HDMI_TX1-18

HDMI_TX1+18

HDMI_TX2-18

HDMI_TX2+18

Security Classification

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

0.1U_0402_16V4Z

2

C

JP61

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

2005/03/10 2006/03/10

20

GND

21

GND

22

GND

23

GND

TYCO_1775040-6conn@

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

CRT & HDMI

LA-3331P

E

1.0

of

16 59Tuesday, May 1 5, 2007

5

B+

JP5A

1

PWR_SRC

3

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53

55
57
59
61
63
65
67
69
71
73
75
77

79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161

PWR_SRC

5

PWR_SRC

7

PWR_SRC

9

PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC

PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
GND
GND
GND
GND

PEX_RX15#
PEX_RX15
GND
PEX_RX14#
PEX_RX14
GND
PEX_RX13#
PEX_RX13
GND
PEX_RX12#
PEX_RX12
GND
PEX_RX11#
PEX_RX11
GND
PEX_RX10#
PEX_RX10
GND
PEX_RX9#
PEX_RX9
GND
PEX_RX8#
PEX_RX8
GND
PEX_RX7#
PEX_RX7
GND
PEX_RX6#
PEX_RX6
GND
PEX_RX5#
PEX_RX5
GND
PEX_RX4#
PEX_RX4
GND
PEX_RX3#
PEX_RX3
GND
PEX_RX2#
PEX_RX2
GND

5

ACES_88982-28428conn@

R316150_0402_1%

12

R314150_0402_1%

12

12

RUNPWROK

TV-Out Termination/EMI Filter

R317150_0402_1%

C11

1

2

D D

C1579

Del C9
and
replaced
by 2 X
22uF.9/8

C C

B B

A A

0.1U_0603_50V4Z

B+

1

1

C1580

2

2

22U_1210_25V6-M

22U_1210_25V6-M

PEG_RXN15
PEG_RXP15

PEG_RXN14
PEG_RXP14

PEG_RXN13
PEG_RXP13

PEG_RXN12
PEG_RXP12

PEG_RXN11
PEG_RXP11

PEG_RXN10
PEG_RXP10

PEG_RXN9
PEG_RXP9

PEG_RXN8
PEG_RXP8

PEG_RXN7
PEG_RXP7

PEG_RXN6
PEG_RXP6

PEG_RXN5
PEG_RXP5

PEG_RXN4
PEG_RXP4

PEG_RXN3
PEG_RXP3

PEG_RXN2
PEG_RXP2

Place those components as close as

L

MXMIII connector within 500 mils.

MXM_LUMA
MXM_CRMA
MXM_COMP

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN

5VRUN

GND
GND
GND

PRSNT2#

PEX_TX15#

PEX_TX15

GND

PEX_TX14#

PEX_TX14

GND

PEX_TX13#

PEX_TX13

GND

PEX_TX12#

PEX_TX12

GND

PEX_TX11#

PEX_TX11

GND

PEX_TX10#

PEX_TX10

GND

PEX_TX9#

PEX_TX9

GND

PEX_TX8#

PEX_TX8

GND

PEX_TX7#

PEX_TX7

GND

PEX_TX6#

PEX_TX6

GND

PEX_TX5#

PEX_TX5

GND

PEX_TX4#

PEX_TX4

GND

PEX_TX3#

PEX_TX3

GND

PEX_TX2#

PEX_TX2

MXM_LUMA

MXM_CRMA

MXM_COMP

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54

56
58
60
62
64
66
68
70
72
74
76
78

80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162

L

C17

C18

1

1

2

2

82P_0402_50V8J

4

+3VS

1 2

G

Q142

2

MXM_THERM# PWR _GD

+1.8VS +5VS

PEG_M_TXN15
PEG_M_TXP15

PEG_M_TXN14
PEG_M_TXP14

PEG_M_TXN13
PEG_M_TXP13

PEG_M_TXN12
PEG_M_TXP12

PEG_M_TXN11
PEG_M_TXP11

PEG_M_TXN10
PEG_M_TXP10

PEG_M_TXN9
PEG_M_TXP9

PEG_M_TXN8
PEG_M_TXP8

PEG_M_TXN7
PEG_M_TXP7

PEG_M_TXN6
PEG_M_TXP6

PEG_M_TXN5
PEG_M_TXP5

PEG_M_TXN4
PEG_M_TXP4

PEG_M_TXN3
PEG_M_TXP3

PEG_M_TXN2
PEG_M_TXP2

Place cloce to MXM connector JP5

C19

1

2

82P_0402_50V8J

82P_0402_50V8J

+1.8VS

1

2

R303

8.2K_0402_5%@

1 2

Add for leakage issue. 1/12
Change again. 1/15

L8

1 2

CHB1608U301_0603
L9

1 2

CHB1608U301_0603
L7

1 2

CHB1608U301_0603

4

RHU002N06_SOT323

S

C292

4.7U_0805_10V4Z

PWR_GD

+3VS

MXM_CD1# 21,48

C13

1

2

82P_0402_50V8J

Move this from VGA
board to M/B. 2/12

R2204
10K_0402_5%

13

D

CLKREQE#15

VGA_RST#21

ICH_SM_DA4,21,26

ICH_SM_CLK4,21,26

Add R2190 to option G71
& G84.11/8

RHU002N06_SOT323

ADP_PRES24,34,41,42,43,48

C14

C15

1

1

2

2

82P_0402_50V8J

82P_0402_50V8J

3

PEG_RXN[0..15]9

PEG_RXP[0..15]9
PEG_M_TXN[0..15]9
PEG_M_TXP[0..15]9

JP5B

PEG_RXN1

PWR_GD 21,27,34,37,38,46,48

CLK_PCIE_MXM#15

R311

0_0402_5%@

MXM Address:100_1100

R320 0_0402_5%
R319 0_0402_5%

SLP_S3#21,24,29,30,34,36,37,44,45,46,48,49

Q139

D

1 3

G

2

+3VS

M_LUMA 36

M_CRMA 36

M_COMP 36

CLK_PCIE_MXM15

1 2

1 2
1 2

MXM_THERM#21

M_HSYNC16
M_VSYNC16

M_DDCCLK16

M_DDCDATA16

+5VALW

ADP_PRES_Q

Reserve R2110 ,R2190 from SI2
cause G84/G92 don't need them.
1/10

S

R2196

1 2

R2110 0_0402_5%@
R2190 0_0402_5%@
R313 0_0402_5%

HD_DVI_CLK-18

HD_DVI_CLK+18

HDMI_DETECT16

DVI_TX5-18

DVI_TX5+18

DVI_TX4-18

DVI_TX4+18

DVI_TX3-18

DVI_TX3+18

DVI_DETECT36

DVI_CLK-36

DVI_CLK+36

DVI_TX2-36

DVI_TX2+36

DVI_TX1-36

DVI_TX1+36

DVI_TX0-36

DVI_TX0+36

ADP_PRES_Q

8.2K_0402_5%

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PEG_RXP1
PEG_RXN0

PEG_RXP0

MXM_SMBDATA
MXM_SMBCLK

MXM_THERM#

1 2
1 2
1 2

M_RED

M_GRN

12

R10

150_0402_1%

2005/03/10 2006/03/10

Compal Secret Data

12

R2

R11

150_0402_1%

12

Deciphered Date

163

PEX_RX1#

165

PEX_RX1

167

GND

169

PEX_RX0#

171

PEX_RX0

173

GND

175

PEX_REFCLK#

177

PEX_REFCLK

179

CLK_REQ#

181

PEX_RST#

183

RSVD

185

RSVD

187

SMB_DAT

189

SMB_CLK

191

THERM#

193

VGA_HSYNC

195

VGA_VSYNC

197

DDCA_CLK

199

DDCA_DAT

201

IGP_UCLK#

203

IGP_UCLK

205

GND

207

RSVD

209

RSVD

211

RSVD

213

IGP_UTX2#

215

IGP_UTX2

217

GND

219

IGP_UTX1#

221

IGP_UTX1

223

GND

225

IGP_UTX0#

227

IGP_UTX0

229

GND

231

IGP_LCLK#/DVI_B_CLK#

233

IGP_LCLK/DVI_B_CLK

235

DVI_B_HPD/GND

237

RSVD

239

RSVD

241

GND

243

IGP_LTX2#/DVI_B_TX2#

245

IGP_LTX2/DVI_B_TX2

247

GND

249

IGP_LTX1#/DVI_B_TX1#

251

IGP_LTX1/DVI_B_TX1

253

GND

255

IGP_LTX0#/DVI_B_TX0#

257

IGP_LTX0/DVI_B_TX0

259

DVI_A_HPD

261

DVI_A_CLK#

263

DVI_A_CLK

265

GND

267

DVI_A_TX2#

269

DVI_A_TX2

271

GND

273

DVI_A_TX1#

275

DVI_A_TX1

277

GND

279

DVI_A_TX0#

281

DVI_A_TX0

283

GND

CRT Termination/EMI Filter

L4

1 2

HLC0603CSCC39NJT_0603

L5

1 2

HLC0603CSCC39NJT_0603

L2

1 2

HLC0603CSCC39NJT_0603

150_0402_1%

2

PEX_TX1#

PEX_TX0#

TV_C/HDTV_Pr

TV_Y/HDTV_Y

TV_CVBS/HDTV_Pb

VGA_GRN

LVDS_UCLK#

LVDS_UCLK

LVDS_UTX3#

LVDS_UTX3

LVDS_UTX2#

LVDS_UTX2

LVDS_UTX1#

LVDS_UTX1

LVDS_UTX0#

LVDS_UTX0

LVDS_LCLK#

LVDS_LCLK

LVDS_LTX3#

LVDS_LTX3

LVDS_LTX2#

LVDS_LTX2

LVDS_LTX1#

LVDS_LTX1

LVDS_LTX0#

LVDS_LTX0
DDCC_DAT

DDCC_CLK

LVDS_PPEN

LVDS_BL_BRGHT

LVDS_BLEN

DDCB_DAT

DDCB_CLK

ACES_88982-28428conn@

RED_LL

GREEN_LL

BLUE_LLM_BLU

2

GND

PEX_TX1

GND

PEX_TX0

PRSNT1#

GND
GND
GND

VGA_RED

GND
GND

VGA_BLU

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

2V5RUN

GND
3V3RUN
3V3RUN
3V3RUN

C3

1

MXM_CD0#

164

PEG_M_TXN1

166

PEG_M_TXP1

168
170

PEG_M_TXN0

172

PEG_M_TXP0

174

MXM_CD0#

176

MXM_CRMA

178
180

MXM_LUMA

182
184

MXM_COMP

186
188

M_RED

190
192

M_GRN

194
196

M_BLU

198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
258
260
262
264
266
268
270
272
274
276
278
280
282
284

1

1

C7

2

2

18P_0402_50V8J

1

C4

2

4.7U_0805_10V4Z

L1

1 2

HLC0603CSCCR11JT_0603

L6

1 2

HLC0603CSCCR11JT_0603

L3

1 2

HLC0603CSCCR11JT_0603

1

C2

2

18P_0402_50V8J

18P_0402_50V8J

Place those components as close as

L

MXMIII connector within 500 mils.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

LA-3331P

MXM_CD0# 21

+3VS

R305

8.2K_0402_5%@

1 2

M_TXBCLK- 18
M_TXBCLK+ 18

Add for HDMI 4/28

SPDIF_OUT 29

M_TXB2- 18
M_TXB2+ 18

M_TXB1- 18
M_TXB1+ 18

M_TXB0- 18
M_TXB0+ 18

M_TXACLK- 18
M_TXACLK+ 18

M_TXA2- 18
M_TXA2+ 18

M_TXA1- 18
M_TXA1+ 18

M_TXA0- 18
M_TXA0+ 18

M_LCD_DAT 18
M_LCD_CLK 18
M_ENAVDD 18
M_PWM 18
M_ENBLT 18
DVI_DAT 18
DVI_CLK 18

+3VS

+2.5VS

1

Add for long trace
issue.1/11

2

C1594

0.1U_0402_16V4Z

D_RED 36

D_GREEN 36

D_BLUE 36

MXM-HE CONN

1

1.0

of

17 59Tuesday, May 1 5, 2007

5

4

3

2

1

LCD POWER CIRCUITMXM LVDS CONN

B+_LCD

C286

12

0.1U_0603_50V4Z
C287

M_TXA2+17

M_TXA2-17

M_TXA1+17

M_TXA1-17

M_TXA0+17

M_TXA0-17

1

2

0.1U_0402_16V4Z

68P_0402_50V8J

L13

1 2

5

12

HD_DVI_CLK+17
HD_DVI_CLK-17

Add pin43 of U57
bottom pad.6/30

JP3

1

1

2

3

3

4

5

5

6

7

7

8

9

9

10

11

11

12

13

13

14

15

15

16

17

17

18

19

19

20

21

21

22

23

23

24

25

25

26

27

27

28

29

29

30

31

31

32

33

33

34

35

35

36

37

37

38

39

39

40

GND41GND

ACES_87216-4016

conn@

+3VS +3VS

R2118
10K_0402_5%

1 2

DVI_TX3+17
DVI_TX3-17
DVI_TX4+17
DVI_TX4-17
DVI_TX5+17
DVI_TX5-17

DVI_HDMI_R_SEL

S

G

2

S

G

2

D

13

Q123
RHU002N06_SOT323

D

13

Q124
RHU002N06_SOT323

LID_SW#

2
4
6
8
10
12

M_LCD_CLK

14

M_LCD_DAT

16
18
20
22
24
26
28
30
32
34
36
38
40
42

HDMIDAT 16

DVIDAT 36

DVI_HDMI_SEL DVI_HDMI_SEL_G

+3VS

21

D80

SS1040_SOD123

VDD2VDD8VDD16VDD18VDD20VDD30VDD40VDD

3

D0+

4

D0-

6

D1+

7

D1-

11

D2+

12

D2-

14

D3+

15

D3-

9

SEL

VSS1VSS5VSS10VSS13VSS17VSS19VSS21VSS41VSS

VSS

43

LID_SW# 21
ALS_EN 21

+5VS_INV

+3VS

M_LCD_CLK 17
M_LCD_DAT 17

M_TXBCLK+ 17M_TXACLK+17
M_TXBCLK- 17

M_TXB2+ 17
M_TXB2- 17

M_TXB1+ 17
M_TXB1- 17

M_TXB0+ 17
M_TXB0- 17

1 2

U57

42

PI3HDMI412FTZHE

22

D3-_B

23

D3+_B

24

D2-_B

25

D2+_B

26

D1-_B

27

D1+_B

28

D0-_B

29

D0+_B

31

D3-_A

32

D3+_A

33

D2-_A

34

D2+_A

35

D1-_A

36

D1+_A

37

D0-_A

38

D0+_A

39

DVI_HDMI_SEL_G

R2132
10K_0402_5%

Add in 6/5.

D

S

13

G

Q125

2

RHU002N06_SOT323

D

S

13

G

Q126

2

RHU002N06_SOT323

R2111
0_0402_5%

1 2

Add for leakage issue.1/7
Need update the part after

apply ready.1/9

+3VS_D80

HDMI_CLK- 16
HDMI_CLK+ 16
HDMI_TX2- 16
HDMI_TX2+ 16
HDMI_TX1- 16
HDMI_TX1+ 16
HDMI_TX0- 16
HDMI_TX0+ 16

DVI_D_TX5- 36
DVI_D_TX5+ 36
DVI_D_TX4- 36
DVI_D_TX4+ 36
DVI_D_TX3- 36
DVI_D_TX3+ 36

+1.5VS

4

D D

B+

KC FBM-L11-201209-221LMA30T_0805

LCDVDD

M_TXACLK-17

Change pin
size cause
MXM-HE.5/24

C C

DVI_DAT17

DVI_CLK17

B B

+1.5VS

C1584

C1583

1

2

Removed RP44 ~ RP47. 10/18

A A

0.1U_0402_16V4Z

Add C1583, C1584 decoupling for +1.5VS. 10/18

J1

PAD-SHORT 2x2m@

PAD-No SHORT 2x2m@

21

J2

21

R2176 0_0402_5%@

HDMICLK 16

DVICLK 36

M_PWM 17

INV_PWM 34

M_ENAVDD17

+5VS

Change in 8/4.

U61
SN74LVC1G14DCKR_SC70-5

5

V

4

1 2

2

A

Y

NC

G

1

3

Add GPIO extander 6/2.

Change package 7/4.

U59

HDMIEN

DVIEN

R2112 0_0402_5%

1 2

R2113 0_0402_5%

1 2

I/O01VCC
I/O12SDA

3

I/O2
VSS4I/O3

PCA9536DP_TSSOP8

Change design in 6/20.

DVI_HDMI_R_SEL D VI_HDMI_SEL

1

1

C1566

C1565

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R2148 2.21K_0402_1%

1 2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/03/10 2006/03/10

SCL

R307

100_0402_1%

Q55

2N7002_SOT23

+5VS

8

M_LCD_DAT

7

M_LCD_CLK

6
5

M_ENBLT17

Compal Secret Data

LCDVDD

12

13

D

S

2

Deciphered Date

R315 47K_0402_5%

1 2

2

G

13

Q56
DTC124EK_SC59

1

C1393

0.1U_0402_16V4Z

2

LID_SW#

1
2

R86100K_0402_5%

1 2

C2880.1U_0402_16V4Z

1

2

Function opt i o n , A d d i n 6/5. (Reserved at 6/6)

DVI_HDMI_R_SEL DVI_HDMI_SEL

+3VS

+5VS

U11A
SN74LVC08APW_TSSOP14

14

P

A

3

O

B

G

7

1 2

2

Q1

AO3413_SOT23

D

S

1 3

G

2

R309 1M_0402_5%

1 2

C298 0.047U_0402_16V7K

1 2

C124.7U_0805_10V4Z

1

2

Change
design in
6/20.

R2124

R2123

1.8K_0402_5%

1 2

1 2

R2127

4.53K_0402_1%~D

Q10
DTA114YKA_SC59

47K

10K

2

13

D

2

G

S

R80100K_0402_5%

Size Document Number Rev

Date: Sheet

0_0402_5%

@

1 2

DVIEN HDMIEN

0_0402_5%

R2128

1 2

@

13

+5VS_INV

Q13
BSS138_SOT23

Title

Compal Electronics, Inc.

LCD CONN & Q-Switch & GPIO Ext.

LA-3331P

+5VS +5VS+5VS+3VS

1 2

1 2

R2125

R2129

+3VALWLCDVDD

1

2

0_0402_5%

@

0_0402_5%

@

C2894.7U_0805_10V4Z@

0_0402_5%

R2126

@

1 2

R2130

0_0402_5%

1 2

@

1.0

of

18 59Tuesday, May 1 5, 2007

1