HP HP6531s Schematics

S-SERIES

Zygo(D) & Zodiac(D) & Ikon

PV_Build (A01)

2008.04.02

CHANGE NO.

DRAWER DESIGN CHECK RESPONSIBLE

FILE NAME :

REVDATE

P/N

EE

3

XXXX-XXXXXX-XX

XXXXXXXXXXXX

DATE

POWER

DATE

TITLE

VER : SIZE

A3

INVENTEC

S-SERIES - Discrete

CODESIZE =

DOC. NUMBER

CS

SHEET

OF

154

REV

A011310A21614

Table Of Contents

Page

5- DC & Battery Charger. 6- Select & Battery CONN. 7- System Power (+V3A/+V5A).

8- System Power (+V1.8/+VCCP) .

9- Graphic Power (+VDD_CORE & +VPCIE). 10- System Power (+V1.5S) . 11- CPU Power (+VCC_CORE).

12- DDR Termination Voltage(+V0.9S). 13- Power (Sleep: +V5S/+V3S/+V1.8S).

14- Power (Sequence).

Page

15- Clock Generator. 16- CPU Penryn-1. 17- CPU Penryn-2.

18- CPU Penryn-3. 19- XDP & Thermal & Fan. 20- N/B Cantiga-1.

21- N/B Cantiga-2. 22- N/B Cantiga-3. 23- N/B Cantiga-4.

24- N/B Cantiga-5. 25- N/B Cantiga-6. 26- DDR2-DIMM0.

27- DDR2-DIMM1. 28- DDR2-DAMPING. 29- VGA CONN.

30- LCM CONN. 31- S/B ICH9-1. 32- S/B ICH9-2.

33- S/B ICH9-3. 34- S/B ICH9-4. 35- S/B ICH9-5.

Page

36- 15" ODD Extend/B. 37- HDD & ODD CONN&Accelerometer. 38- USB CONN. 39- KBC & BIOS ROM. 40- Internal Keyboard & TouchPad CONN. 41- Audio CODEC & Earphone & Speaker. 42- Audio MIC & MDC CONN.

43- Giga LAN controller. 44- Magnetic & RJ45 CONN.

45- Mini Card(WLAN/Robson)/BT/UWB/Web-CAM. 46- New Card & 4 in 1 Card (SD/MMC/MS/XD). 47- LEDs & Buttons & SW/B.

48- Screws / Crack testing circuit. 49- AMD M82SE-1. 50- AMD M82SE-2.

51- AMD M82SE-3. 52- AMD M82SE-4.

53- Video RAM-1 (GDDR2). 54- Video RAM-2 (GDDR2).

CHANGE by

Drawer_Name

31-Mar-2008

INVENTEC

TITLE

S-SERIES - Discrete

SIZE REV

CODE

CS

SHEET

DOC. NUMBER

OF

254

A3

A011310A21614

V-RAM

LCM VGA

P.53

P.30

P.29

DDR2 400

LVDS

CRT

AMD M82S

P.49

PCI_EXPRESS

Penryn

(uFCPGA)

FSB 1067.800/667

Cantiga

PM45

(1329 FCBGA)

DMI

P.20-25

SATA

P.16

DDR2 667

HDD & Fixed ODD

(PC2-5300)

DDR II _SODIMM0

P.26

DDR II _SODIMM1

P.27

P.37

MAIN BATT

6 Cell

System Charger &

DC/DC System power

Clock Generator

ICS9LPRS397

P.15

4 IN 1 CONN

P.46

USB0

CONN

USB1

CONN

USB2

(NewCard)

USB3

Card Reader

ALCOR_AU6371

USB4

CONN

USB5

CONN

USB6

BlueTooth

CONN

USB10

Web CAM

CONN

P.38

P.46

P.38

P.45

Accelerometer

STMicro LIS302DL

MDC V1.5

CONN

P.42

RJ11

-phone

SMBUS

P.37

USB I/F

Audio CODEC

ADI_1984A

MIC

Headphone

-phone

P.41

ICH9-M

676 mBGA

IHDA

P.41

Speaker

P.41

P.31-35

SPI

LPC

KBC

SMSC KBC1091

Keyboard

P.40

TouchPad

PCIE I/F

P.39

P.40

SPI_1091

System

BIOS

P.36

UWB

CONN

(PCIE1)

P.45

Mini Card

CONN

(WLAN 802.11 a/b/g/n)

(PCIE-2)

P.45

New Card

CONN

(PCIE3+USB2)

P.46

Giga LAN

Marvell

88E8072

(PCIE-6)

RJ45

P.43

Mini Card

CONN

Robson

(PCIE-4)

CHANGE by

Drawer_Name

P.44

31-Mar-2008

INVENTEC

TITLE

S-SERIES - Discrete

SIZE CODE

A3

DOC. NUMBER

1310A21614 A01

CS

SHEET

REV

OF

543

BATSELB

AC_AND_CHG

CHGCTRL_3

Adapter

(90W)

LIMIT_SIGNAL

Selector

(Discrete)

+VBATR

+VBDC

OCP

Charger

(BQ24740)

+VBATA

BATCON

ADP_EN OCP_OC# ADP_PS0 ADP_PS1

CHGCTRL_3

ADP_PRES

AC_AND_CHG

Main Battery

ADP_PRES

KBC_PW_ON

SLP_S4#_3R

SLP_S3#_3R

5/3.3V

(TPS51120)

IO POWER

(TPS51124)

+V1.8

+V5A +V3A

+V5AL +V3AL

V1.8_PG

VCCP_PG

+VCCP

(7A)

(5A)

(9.1A)

SLP_S3#_3R

SLP_S4#_3R

SLP_S3#_3R

LR

(G2997)

LR

(APL5913)

+V5S

+V3S

+V3_LAN

+V0.9S

M_VREF

+V1.5S

V1.5S_PG

+V1.8S

SLP_S3#_3R

PWR_GOOD_3

PM_DPRSLPVR

PSI#

H_DPRSTP#

ATI

GPU POWER

(TPS51511)

IMVP VI

(ADP3208)

+VDD_CORE +VPCIE

VGA_PG

+VCC_CORE

PM_PWROK

CHANGE by

INVENTEC

TITLE

S-SERIES - Discrete

CODE

CS

SHEET

DOC. NUMBER

454

SIZE

31-Mar-2008Drawer_Name

A3

REV

A011310A21614

OF

+VADPBL

5-,6-

ADP_EN#

1

2

+VBDC

Q1031

AM4825P_AP

8

D

7 6 54

14-

CHENKO_LL4148_2P

R1217

15K_5%

2VREF

7-,14-

R38

14.3K_1%

+VADPBL

5-,6-

R1222

12

100K_1%

S

G

D1017

21

1

R35

100K_1%

2

1

R39

8.25K_1%

2

1

2

5-,6-

R1225

12

100K_1%

23.7K_1%

R1207

12

24K_1%

1 2 3

R1223

R1218

220K_5%

R1226

100K_5%

C25

12

0.22uF_16v

C500

0.1uF_16v

1

C1275

2

Q1032

3

D

1

G

S

2

SSM3K7002F

12

R37

12

270K_5%

+V5AL

5-,7-,14-

8

3

U1-A

+

OUT

2

-

ON_LM393DR2G_SOP_8P

4

R40

1M_5%

12

+V5AL

5-,7-,14-

8

5

+

OUT

6

4

+V5AL

12

1 2 3

1

2

+VADP

14-

C1279

C1277

1

2

0.1uF_16v

1

2

1

U1-B

7

ON_LM393DR2G_SOP_8P

5-,7-,14-

1IN+ GND 1IN-

2

10pF_50v

R1219

220K_5%

14-

BATCAL#

+V3AL

5-,6-,7-,14-,31-,39-,40-,45-,47-

R36

22K_5%

12

6-

AC_AND_CHG

1

C26

0.1uF_16v

2

R1208

12

100K_5%

R1224

12

1M_5%

5

Vcc+

U1026

TI_LMV321IDBVR_SOT23_5P

4

OUT

NFM60R30T222

0.1uF_25v

D1016

SSM14_1A40V

2

Q1030

8

D

7 6 5

G

AM4825P_AP

6-,39-,43-

1

G

SSM3K7002F

1

G

L1028

1

2

3

4

C1278

1

12

S

2 3

47K_5%

4

ADPDRV# ADP_PRES

12

47K_5%

CHGCTRL_3

6-,39-

+V3AL

5-,6-,7-,14-,31-,39-,40-,45-,47-

2

R41

10K_5%

1

Q3

3

D

S

2

7-,13-,14-,19-,30-,32-,33-,34-,43-,45-,47-

5-

ADPDRV#

VCTRL_3

3

D

Q1026

S

SSM3K7002F

2

C1280

1

2

10pF_50v

0.1uF_25v

LIMIT_SIGNAL

R1220

1

R1221

4.7K_5%

2

5-

R43

R6

294K_1%

12

R5

200K_1%

SLP_S3#_3R

7-,8-,9-,10-,12-,13-,14-,32-,39-,41-,43-,46-

+V3A

39-

DC JACK

5-,14-

C31

1uF_25v

1

C5

2

1uF_6.3v

2

CELLS

1

R44

453K_1%

2

R46

422K_1%

12

1

R48

1M_1%

2

JACK1004 1 2 3 4 5

789

6

FOX_JPD113D_LBA21_7F_9P

+VBAT

6-

0.01_1%_1W

12

R42

12

300K_5%

R1205

BQREF

R1

12

39-

0_5%

R2

100K_5%

1uF_6.3v

1

C33

2

1uF_6.3v

BQREF

7-,8-,9-,11-,13-,30-,39-

+VBATR

R1216

12

20K_5%

1

2

5-

1

2

1

C32

2

5-

ICS

5-

LIMIT_SIGNAL

5-,14-

C30

12

1uF_25v

U2

2

ACN

3

ACP

5

ACDET

9

AGND

13

EXTPWR

16

SRSET

6

ACSET

10

VREF

8

IADSLP

21

DPMDET

4

LPMD

20

CELLS

1

CHGEN

11

VDAC

12

VADJ

15

IADAPT

TI_BQ24740_QFN_28P

5-

1

C6

100pF_50v

2

R52

12

165K_1%

R51

105K_1%

PVCC

HIDRV

PH

BTST

REGN

LODRV

PGND

SRP

SRN

BAT

LPREF

ISYNSET

PowerPad

ICS

C35

0.22uF_16v

1

2

R50

100_5%

12

VBIAS

28

26

25

27

24

C28

1

1uF_10v

2

23

22

19

18

17

7

14

29

1

2

12

R53

12

10K_5%

TI_LMV321IDBVR_SOT23_5P

D1009 Q1023

BSS84_3P

CHENKO_LL4148_2P

3

2

S

D

G

1

14-

C29

12

1uF_25v

D1BAT54

13

C4

1 2

0.1uF_25v

R7

33K_5%

5-,13-,14-,19-,29-,32-,34-,37-,40-,41-

U1024

1

1IN+

Vcc+

2

GND

3

1IN-

OUT

2

1

C1272

0.1uF_25v

1

2

C27

12

0.1uF_16v

C1274

4.7uF_25v1

5

4

R47

3.9K_1%

1 2

C1271

4.7uF_25v

ON_LM339DR2G_SOP_14P

+V5S

C36

0.1uF_10v

1 2

1

R49

2K_1%

2

2 D1010

CHENKO_LL4148_2P

1

R45

12

100K_5%

1

C34

1

2

3900pF_16v

C1273

4.7uF_25v

1 2

FAIR_FDMS9620S_MLP_8P

3

C

1

B

E

2

D_MMST3904

Q1029

Q1

1

Q2

8

Drawer_Name

R114

330K_5%

R115

3.9K_5%

Q1024

1

2

1

2

2 3 4 9

10

5 6 7

+V5S

5-,13-,14-,19-,29-,32-,34-,37-,40-,41-

U1022-A

3

5

+

2

OUT

4

12

OCP_OC

L1027

PCMB0603T_8R2MS

12

1

C1252

2

4.7uF_25v

31-Mar-2008

+V3S

11-,13-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,43-,45-,46-,47-,48-,50-,51-

1

R117

R113

133K_1%

10K_5%

2

1

R116

2

80.6K_1%

0.027uF_10v

2

D1007

21

CHENKO_LL4148_2P

14-

Q1017

3

D

G

1

S

2

SSM3K7002F

12

10K_5%

12

100K_5%

3

U1022-B

7

+

1

OUT

6

-

ON_LM339DR2G_SOP_14P

12

C1247

604K_1%

11-,14-,39-,49-,50-

32-

R1198

R1200

R1199

PWR_GOOD_3

OCP_OC#

OCP

+VBDCR

R1215

0.01_1%_1W

12

1

C1270

2

4.7uF_25v

R3

0_5%

1 2

INVENTEC

TITLE

SIZE

A3

1

R4

0_5%

2

C2

0.033uF_16v

2

1

Kevin sense

C1

C3

1 2

1uF_25v

S-SERIES - Discrete

DC & Battery Charger

CODE REVDOC. NUMBER

CS

SHEET

554

OFCHANGE by

+VBDC

1 2

5-,6-

C1251

4.7uF_25v

1 2

A011310A21614

C1269

4.7uF_25v

+VBDC +VBATA

5-,6-

6-

+V3AL

5-,6-,7-,14-,31-,39-,40-,45-,47-

CHGCTRL_3

CHENKO_LL4148_2P

C1250

1000pF_50v

5-,39-

2

D1008

1

2

C1249

0.047uF_10v

R1202

12

1K_5%

1

R1203

470K_5%

2

1 2

1

G

+V3AL

5-,6-,7-,14-,31-,39-,40-,45-,47-

1

R1201

470K_5%

2

5

24

3

D

S

2

Q1018

SSM3K7002F

AC_AND_CHG

U1023

74HC1G14GV

ADP_PRES

5-

5-,39-,43-

+VADPBL

5-

R1206

12

3K_5%

1

R1204

10K_5%

2

MMGZ2548B

Q1019

SSM3K7002F

3

2

D

S

G

1

+VBAT

5-

D1011

1

2

+V3AL

5-,6-,7-,14-,31-,39-,40-,45-,47-

12

R10

220K_5%

+VBATA

6-

CHENKO_LL4148_2P

Q1025

1

S

2 3 4

G

AM4825P_AP

D1012

21

+VBDC

5-,6-

8

D

7 6 5

R18

12

1.5M_5%

+V3AL

5-,6-,7-,14-,31-,39-,40-,45-,47-

SSM3K7002F

Q1028

8

D

7 6 5

AM4825P_AP

Q1022

G

1

SSM3K7002F

3

D

G

1

S

2

G

Q1020

1

R13

10K_5%

1

R16

2

1

3

D1013

BAV99

2

+V3AL

5

2

3

10K_5%

2

1

3

2

D1015

5-,6-,7-,14-,31-,39-,40-,45-,47-

U1027

4

39-

74HC1G14GV

R15

1

2

BAV99

BATCON

100_5%

1 12

100_5%

3

R14

10K_5%

1

S

2 3

1

4

3

D

S

Q1021

2

D

1

G

S

R8

2

470K_5%

1

R9

4.7K_5%

2

6-

3

SSM3K7002F

2

1 2

CFET#

C7

OPEN

SDA_MAIN

SCL_MAIN

THM_MAIN#

D2015

6-

CFET#

21

CHENKO_LL4148_2P

+V3AL

5-,6-,7-,14-,31-,39-,40-,45-,47-

D1014

BAV99

+V3AL

5-,6-,7-,14-,31-,39-,40-,45-,47-

39-

1

R500

220K_5%

2

3939-

1

R12

100K_5%

2

SYN_200046MR006G100ZU_6P

R17

2

R11

12

1K_5%

C81

2

470pF_50v

C1281

1 2

0.1uF_16v

MAIN BATT

CN1015

1

2

3

4

5

6

C9

1 2

0.1uF_25v

6CELL#

7

8

R501

12

0_5%_OPEN

CHANGE by

Drawer_Name

2-Apr-2008

INVENTEC

TITLE

S-SERIES - Discrete

Selector & Battery CONN & Extend/B

SIZE

A3

CODE

CS

SHEET

DOC. NUMBER

OF

654

REV

A011310A21614

KBC_PW_ON

VCC1_POR#_3

39-

SSM3K7002F

14-,39-

SSM3K7002F

R366

17.4K_1%

Q1036

1

Q1037

1

+V5AL

5-,7-,14-

12

330K_5%

3

D

G

S

D

G

S

2 3

2

R365

7.32K_1%

SSM3K7002F

1212

51120GND

R1243

Q1038

1

G

12

R1242

0_5%_OPEN

3

D

S

2

5-,8-,9-,11-,13-,30-,39-

2VREF

C416

1000pF_50v

51120GND

1 2

5-,7-,14-

+VBATR+VBATR

7-

R1074

12

0_5%

12

51120GND

7.32K_1%

R367

30K_1%

R364

12

+V3A

5-,13-,14-,19-,30-,32-,33-,34-,43-,45-,47-

C1058

1uF_10v

+VBATR

7-

C387

1 2

4.7uF_25v

L1008

CYNTEC_PCMC063_3R3

C1068

1

12

330uF_4v

2

12

1 2

C386

4.7uF_25v

RSMRST#

S1_D2

567

4

S2

Q27

FDS6900AS

D1

12 8

G1

3

G2

7-,32-,39-

C385

0.1uF_16v

12

R480

2

1

0_5%

4.7_5%

R320

12

+V3AL

5-,6-,14-,31-,39-,40-,45-,47-

1

C415

4.7uF_6.3v

2

10 11 12 13 14 15 16

C411

4.7uF_6.3v

6

8

7

VO2

VFB2

COMP2

TI_TPS51120_QFN_32P

9

EN5 EN3 PGOOD2 EN2 VBST2 DRVH2 LL2 DRVL2

VREG3

CS2

PGND2

19

18

17

12

R1076

13K_1%

+V5AL

5-,7-,14-

1

2

4

5

GND

VFB1

VREF2

VIN

VREG5

V5FILT

21

20

C412

0.1uF_16v

3

22

U16

1

2

VO1

COMP1

33 32

SKIPSEL

31

TONSEL

30

PGOOD1

29

EN1

28

VBST1

27

DRVH1

26

LL1

25

DRVL1

CS1

PGND1

23

24

12

R1075

7.32K_1%

R361

12

10_5%

1 2

51120GND

R363

12

7-,32-,39-

0_5%

C413

1uF_10v

RSMRST#

1 2

5-,8-,9-,10-,12-,13-,14-,32-,39-,41-,43-,46-

4.7_5%

R362

2

1

C414

4.7uF_25v

C431

12

2VREF

0.1uF_16v

SLP_S3#_3R

5-,7-,14-

G

4S1

G

4

23

8765

D

SI7326DN

8765

D

S

123

1 2

4.7uF_25v

Q31

Q30

FDS6690AS

+VBATR

7-

C432

1

C430

2

4.7uF_25v

L1005 12

SLF10040_4R7N7R0

220uF_6.3v

C1052

+V5A

8-,9-,10-,11-,12-,13-,30-,34-,38-,45-

1

C1051

1 2

2

1uF_10v

INVENTEC

TITLE

S-SERIES - Discrete

System Power(+V5A/+V3A)

CODE

CS

SHEET

DOC. NUMBERSIZE

754

31-Mar-2008Drawer_Name

A3

REV

A011310A21614

OFCHANGE by

+V1.8

9-,10-,12-,13-,20-,23-,24-,26-,27-

+VBATR

5-,7-,8-,9-,11-,13-,30-,39-

C48

1 2

4.7uF_25v

12

PCMC063T_1R0MN

1

C1248

2

330uF_2v_9mR_Panasonic

L1026

C46

1 2

4.7uF_25v

FDS6676AS

SI7326DN

12

100K_5%

14-

C85

0.1uF_16v

R118

10_5%

R125

12

12.1K_1%

5-,7-,9-,10-,12-,13-,14-,32-,39-,41-,43-,46-

R121

SLP_S3#_3R

VCCP_PG

12

+V5A

C83

1 2

4.7uF_6.3v

+VBATR

5-,7-,8-,9-,11-,13-,30-,39-

8

765

D

G

S

Q7

SI7326DN

123

4

6

54

8D7

C82

1 2

4.7uF_25v

12

CYNTEC_PCMC063_1R5

G

Q10

S

FDS6676AS

123

L1025

1 2

C92

4.7uF_25v

C89

1 2

4.7uF_25v

1

C1243

220uF_2v_15mR_Panasonic

2

+VCCP

10-,15-,16-,17-,18-,19-,20-,21-,23-,24-,31-,34-

R89

1

43.2K_1%

V1.8_PG

SLP_S4#_3R

765

8

D

Q6

G

S

123

0.1uF_16v

4

8765

D

G

41S23

Q5

12-,32-

C47

14-

12

R122

12

30K_1%

1

R88

0_5%

2

R87

12

4.7_5%

51124GND

R124

12

0_5%_OPEN

7

PGOOD2

8

EN2

9

VBST2

10

DRVH2

TI_TPS51124RGER_QFN_24P

LL2

12

DRVL2

8.06K_1%

R126

12

0_5%

VO2

PGND2

R86

51124GND

6

13

5

VFB2

TONSEL

TRIP2

V5FILT

14

12

9.76K_1%

4

15

R119

2

3

GND

VFB1

TRIP1

V5IN

17

16

12

51124GND

U5

1

VO1

25

GND

24

PGOOD1

23

EN1

22

VBST1

21

DRVH1

2011

LL1

19

DRVL1

PGND1

18

7-,9-,10-,11-,12-,13-,30-,34-,38-,45-

R123

122

30K_1%

R120

12

4.7_5%

C84

1 2

1uF_10v

C494

1 2

0.022uF_16v

12

CHANGE by

Drawer_Name

31-Mar-2008

INVENTEC

TITLE

S-SERIES - Discrete

System Power(+V1.8/+VCCP)

SIZE

CODEOFDOC. NUMBER

A3

1310A21614 A01

CS

SHEET

REV

548

POW_SW1 POW_SW0 +VDD_CORE

00 0

1.1V 1 1.0V 01

0.9V

+VPCIE

POW_SW0

49-,50-,51-

+V1.8

8-,10-,12-,13-,20-,23-,24-,26-,27-

R309

C363

12

10uF_6.3v

2 3 4 5 6 7 8 9

21

1 2

U13

NC VLDO VLDOFB GND ODOFF OD COMP VOSW

TML-PAD

R303

12

0_5%

C326

0.1uF_16v

1

20

VBST

DRVH

VLDOIN

DRVL

PGND

V5IN

PGOOD

ENSW

VSWFB

ENLDO

TI_TPS51511_RHL_20P

10

11

R307

12

0_5%

C322

G

4

567894

Q25

321

8

765

9

D

1S2

3

Q1010

1 2

4.7uF_25v

SI7686DP_T1_E3

1

2

R283

R284

C324

0.1uF_16v

2

1

+V5A

7-,8-,10-,11-,12-,13-,30-,34-,38-,45-

C325

1 2

4.7uF_6.3v

R282

12

0_5%

19 18

LL

17 16

12

15

CS

14

10K_1%

13 12

12

10K_1%

SI7336ADP

14-

VGA_PG

C366

0.1uF_16v

12

R299

R302

12

0_5%

VGAP_AGND

5-,7-,8-,10-,12-,13-,14-,32-,39-,41-,43-,46-

9.31K_1%

1

R301

20K_1%

2

1

R310

75K_1%

2

12

10K_1%

C364

1 2

22uF_6.3v

C362

1 2

1uF_10v

49-

SLP_S3#_3R

C321

1

4.7uF_25v

2

D11

SSM34_3A40V

+VBATR

5-,7-,8-,11-,13-,30-,39-

C323

1 2

4.7uF_25v

L1013

12

MPC1040_0R88

R306

9.53K_1%

1 2

C365

1000pF_50v

VGAP_AGND

1

2

1

R305

30K_1%

2

C319

1

R1104

6.8K_1%

2

1

D

2

S

Q26

D

G

S

SSM3K17FU

VGAP_AGND

R296

12

1K_5%

1 2

C361

1000pF_50v

49-

POW_SW1

+VDD_CORE

1

2

1

C1086

330uF_2v_9mR_Panasonic

2

49-,51-

C320

220uF_2.5v

CHANGE by

Drawer_Name

31-Mar-2008

INVENTEC

TITLE

S-SERIES - Discrete

Graphic Power (+VDD_CORE & +VPCIE)

SIZE

A3

DOC. NUMBER

CODE

1310A21614 A01

CS

SHEET

OF

549

REV

SLP_S3#_3R

5-,7-,8-,9-,12-,13-,14-,32-,39-,41-,43-,46-

+VCCP

8-,15-,16-,17-,18-,19-,20-,21-,23-,24-,31-,34-

R133

12

0_5%

1

2

R132

OPEN

+V5A

7-,8-,9-,11-,12-,13-,30-,34-,38-,45-

C99

1 2

1uF_10v

U6

6

VCNTL

7

POK

82

EN

VIN

GND

9

1

+V1.8

8-,9-,12-,13-,20-,23-,24-,26-,27-

C96

1 2

22uF_6.3v

1 2

5

VIN

3

VOUT

4

VOUT

FB

ANPEC_APL5913_KAC_TRL_SOP_8P

14-

V1.5S_PG

C95

22uF_6.3v

1 2

C94

1uF_10v

1 2

C93

39pF_50v

1

R153

27.4K_1%

2

1

R128

30K_1%

2

+V1.5S

13-,18-,24-,34-,45-,46-

Drawer_Name

31-Mar-2008

INVENTEC

TITLE

S-SERIES - Discrete

System Power (+V1.5S)

CODE

SIZE

A3

1310A21614 A01

CS

SHEETCHANGE by

REVDOC. NUMBER

OF

5410

R2009

10K_5%_OPEN

R2010

0_5%

1

+V3S

1

2

PWR_GOOD_3

2

C1115

330pF_50v

12

R226

1.65K_1%

0.012uF_16v

H_DPRSTP#

PM_DPRSLPVR

5-,14-,39-,49-,50-

12

0_5%_OPEN

32-

12

220pF_25v

C268

PSI#

R2008

C266

1 2

17-

17-,20-,31-

20-,32-

R224

12

0_5%

12

R227

12

68K_1%

C269

680pF_50v

1

18pF_50v

2

1 2

1

C267

R1150

OPEN

5-,13-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,43-,45-,46-,47-,48-,50-,51-

20-,32-,39-

PM_PWROK

VR_PWRGD_CK505#

+V5A

VCOREGND

7-,8-,9-,10-,11-,12-,13-,30-,34-,38-,45-

11-

CSREF

18-

VCCSENSE

18-

1 2

VCOREGND

C1116

1000pF_50v

R1148

12

0_5%

VSSSENSE

R223

12

OPEN

2

R221

1

499_1%

VCOREGND

C1117

4700pF_25v

12

C1143

1000pF_50v

H_VID6

18-

H_VID5

18-

H_VID4

18-

H_VID3

18-

H_VID2

18-

H_VID1

18-

H_VID0

18-

2

49

48

47

TML

1

EN

DPRSLP

DPRSTP

2

PWRGD

3

PGDELAY

4

CLKEN

5

FBRTN

6

FB

7

COMP

U10

8

SS

ADI_ADP3208_LFCSP_48P

9

ST

10

VARFREQ

11

VRTT

12

TTSEN

PMON

PMONFS

13

14

2

R199

113K_1%

1

VCOREGND

1 2

VCOREGND

+VBATR

5-,7-,8-,9-,11-,13-,30-,39-

FBM_11_321611_480A80T

1

2

C129

1 2

4.7uF_25v

FBM_11_321611_480A80T

L23

C130

1 2

4.7uF_25v

C116

C114

1 2

4.7uF_25v

1 2

C128

1 2

C115

1 2

4.7uF_25v

X 3

FDMS8660S

CHANGE by

Q13

FDMS8660S

9

C2005

G

4321

Q14

G

21

43

765

G

4

5678

SI7686DP_T1_E3

9

8765

D

G

41S23

56789

Q12

SI7686DP_T1_E3

8

9

D

D2013

1

S

2

123

SSM34_3A40V_OPEN

Q17

D2014

1

2

SSM34_3A40V_OPEN

L1024

12

CYNTEC_PCMC104T_R36MN_2P

1

R164

OPEN

2

1

C117

OPEN

2

CSREF

12

CYNTEC_PCMC104T_R36MN_2P

1

R178

OPEN

2

1

C165

OPEN

2

TITLE

SIZE

31-Mar-2008Drawer_Name

A3

+VCC_CORE

2 R1158

10_1%

1

11-

2 R1159

10_1%

1

L1021

INVENTEC

S-SERIES - Discrete

CPU Power (+VCC_CORE)

CODE

DOC. NUMBER REV

CS

SHEET

OF

11 54

18-

A011310A21614

1

L24

C167

2.2uF_16v

2

C1226

68uF_25v

1 2

4.7uF_25v

C127

+V5A

7-,8-,9-,10-,11-,12-,13-,30-,34-,38-,45-

2 R1152

10_5%

C168

1

1 2

2.2uF_16v

C1144

1 2

2.2uF_16v

VCOREGND

VID1

VID243VID3

CSCOMP

CSFEF19CSSUM

18

1 2

42

41

40

39

VID4

VID5

VID6

VRPM

RAMP20RPM22RT

21

2

R197

130K_1%

1

2

C222

1000pF_50v

37

SP

VCC

BST1

DRVH1

SW1 PVCC1 DRVL1 PGND1 PGND2 DRVL2 PVCC2

SW2 DRVH2

BST2

GND

23 38

24

R195

215K_1%

12

C223

0.01uF_16v

R198

274K_1%

1

VCOREGND

1

210K_1%

1

C224

2

330pF_50v

36 35 34 33 32 31 30 29 28 27 26 25

VCOREGND

1

C170

2

1000pF_50v

R1146

12

169K_1%

R1147

12

169K_1%

R196

2

R228

76.8K_1%

1

45

44

46

PSI

VID0

CLIM

LLINE

15

16

17

D1004

BAT54A

1

R179

12

4.7_5% 1uF_16v

R180

12

4.7_5%

C169

1uF_16v

+VBATR

5-,7-,8-,9-,11-,13-,30-,39-

R181

12

100_5%

1

R1160

220K_5%

2

NTC thermistor, place near L1021

C166

3

2

1 2

SLP_S4#_3R

SLP_S3#_3R

8-,32-

5-,7-,8-,9-,10-,13-,14-,32-,39-,41-,43-,46-

+V1.8

8-,9-,10-,13-,20-,23-,24-,26-,27-

C88

1 2

4.7uF_6.3v

+V5A

7-,8-,9-,10-,11-,13-,30-,34-,38-,45-

+V0.9S

28-

U7

GMT_G2997F6U_MSOP10_10P

11

TML1VDDQSNS

10

VIN VLDOIN

9

S5

8

GND4PGND

7

S3

6

C87

1uF_10v

C52

1

0.1uF_16v

2

VTTREF

11 2

20-,26-,27-

VTTSNS

VTT

2 3

5

M_VREF

1 2

C53

10uF_6.3v

2

C54

10uF_6.3v

NOTE: DDR2 REGULATOR

CHANGE by

INVENTEC

TITLE

S-SERIES - Discrete

DDR Termination Voltage (+V0.9S)

SIZE DOC. NUMBER

A3

31-Mar-2008Drawer_Name

CS

12 54

REVCODE

A011310A21614

OFSHEET

5-,7-,13-,14-,19-,30-,32-,33-,34-,43-,45-,47-

13-

GATE_3S

BAT54D19

1

3

12

R421

120K_1%

SLP_S3#_3R

+V3A

Q36

6

D

5 2

13

G

FDC655BN

C436

12

0.01uF_16v

SSM3K7002F

SLP_S3#_3R

5-,7-,13-,14-,19-,30-,32-,33-,34-,43-,45-,47-

5-,7-,8-,9-,10-,12-,13-,14-,32-,39-,41-,43-,46-

+V3S

5-,11-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,43-,45-,46-,47-,48-,50-,51-

7-,8-,9-,10-,11-,12-,30-,34-,38-,45-

4

S

R448

120K_1%

2

1

13-

GATE_5S

1

1 R422

47_5%

1

Q37

G

C437

10uF_6.3v

2

3

D

S

2

C435

12

OPEN

5-,7-,8-,9-,10-,12-,13-,14-,32-,39-,41-,43-,46-

SSM3K7002F

Q41

G

1

+VBATR

+V3A

D

S

5-,7-,8-,9-,11-,13-,30-,39-

1

R415

47K_5%

2

1

B

Q42

MMBT3904

1

R400

100K_5%

2

SSM3K7002F

3

2

3

C

E

2

1

R443

130K_1%

2

Q33

1

+V5A

6 5 2

1

C460

12

0.01uF_16v

+VBATR

5-,7-,8-,9-,11-,13-,30-,39-

1

R414

2.7K_5%

2

Q35

2

E

1

B

C

3

MMBT3906

3

D

G

S

2

Q44

D

G

FDC655BN

SSM3K7002F

4

S

3

R449

100_5%

Q40

1

G

R409

12

1K_5%

+V5S

5-,14-,19-,29-,32-,34-,37-,40-,41-

GATE_3S

1

C464

2

10uF_6.3v

1

2

3

D

S

2

D12

1

MMGZ2548B2

1

2

1

2

R404

0_5%

R408

0_5%

Added for VGA

+V1.8

8-,9-,10-,12-,20-,23-,24-,26-,27-

Q8

6

4

D

S

5 2

13

G

FDC655BN

Q9

4

6

D

S

5

R134

120K_1%

12

13-

1

C90

0.022uF_16v

2

13-

GATE_5S GATE_3S

2 1

G

FDC655BN

SSM3K7002F

1

R405

0_5%

2

1

R413

0_5%

2

3

R154

100_5%

Q11

1

G

+V1.8S

49-,50-,51-,52-,53-,54-

1

2

3

D

S

2

13-

1

C101

2

10uF_6.3v

R383

100_5%

Q38

1

G

SSM3K7002F

+V1.5S

10-,18-,24-,34-,45-,46-

1

2

3

D

S

2

INVENTEC

TITLE

S-SERIES - Discrete

Power (Sleep: +V5S/+V3S/+V1.8S)

SIZE

CHANGE by OF

Drawer_Name

31-Mar-2008

A3

DOC. NUMBER

CODE REV

CS

SHEET

13 54

A011310A21614

9-

68.1K_1%

12

R92

1K_5%

R95

12

1K_5%

V1.5S_PG

V1.8_PG

VCCP_PG

R130

12

R131

12

102K_1%

1

R158

137K_1%

2

1

R160

10K_1%

2

D2

DAP202K

10-

8-

R161

12

1M_5%

29.4K_1%

10K_1%

12

R94

12

10K_5%

R96

12

10K_5%

R97

12

10K_5%

49.9K_1%

+VADP

5-,14-

1

2

1

2

+VADP

5-,14-

1

R145

2

1

R141

2

3

1

R129

1000pF_50v

2

R148

22.6K_1%

R159

10K_1%

ON_LM393DR2G_SOP_8P

R93

12

20K_5%

C86

5-

R143

12

1M_5%

U1020-B

100K_5%

U1020-A

3

+

2

-

5

+

6

-

OUT

SLP_S3#_3R

5-,7-,8-,9-,10-,12-,13-,14-,32-,39-,41-,43-,46-

VGA_PG

+V3S

5-,11-,13-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,43-,45-,46-,47-,48-,50-,51-

+V5S

5-,13-,14-,19-,29-,32-,34-,37-,40-,41-

LIMIT_SIGNAL VBIAS

5-

5-,11-,13-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,43-,45-,46-,47-,48-,50-,51-

2VREF

5-,7-,14-

2

R90

1

C49

1 2

0.1uF_16v

+VADP

1 2

8

1

ON_LM393DR2G_SOP_8P

4

1

R150

47K_5%

2

8

CHENKO_LL4148_2P

7

4

5-,14-

1

2

C1244

5-

R2005

1_5%

1uF_25v

D1006

R127

12

1M_5%

+V5AL

5-,7-,14-

8

U4-B

5

+

OUT

6

-

ON_LM393DR2G_SOP_8P

4

1

R162

10K_5%

2

39-

ADP_ID

+VADP

21

R139

220K_5%

ADP_EN#

7

5-,14-

1

R146

220K_5%

2

Q1015

1

SSM3K7002F

2

+V3S

1

R91

10K_5%

2

+V3A

5-,7-,13-,19-,30-,32-,33-,34-,43-,45-,47-

1

R1196

47K_5%

2

5-,7-,8-,9-,10-,12-,13-,14-,32-,39-,41-,43-,46-

R1195

12

100K_5%

3

D

G

S

2

5-,11-,39-,49-,50-

1

B

5-

3

C

Q1016

E

D_MMST3904

2

39-

PWR_GOOD_3

SLP_S3#_3R BATCAL#

ADP_EN

R1180

23.7K_1%

R473

51.1K_1%

+V3AL

5-,6-,7-,14-,31-,39-,40-,45-,47-

12

C498

2200pF_50v

0.1uF_16v

OCP_OC

D18 12

DAN202K

3

12

R477

57.6K_1%

R458

12

23.7K_1%

1 2

+V5AL

5-,7-,14-

R151

12

1M_5%

12

R474

100K_5%

SSM3K7002F

1

C497

2

+V3S

5-,11-,13-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,43-,45-,46-,47-,48-,50-,51-

1

R144

71.5K_1%

2

R147

12

10K_5%

1

R142

21K_1%

2

R140

1

21K_1%

1

R138

3.48K_1%

2

R1197

5-

12

47K_5%

C1246

1uF_6.3v

CHANGE by

3 2

Q46

3

D

G

1

S

2

+V5S

5-,13-,14-,19-,29-,32-,34-,37-,40-,41-

2

R1194

12

470K_5%

2

C1245

1

0.1uF_16v

1

Drawer_Name 31-Mar-2008

R475

115K_1%

R467

12

1M_5%

+V5AL

5-,7-,14-

8

U4-A

+

1

OUT

-

ON_LM393DR2G_SOP_8P

4

2VREF

5-,7-,14-

R149

12

1M_5%

3

9

+

14

OUT

8

-

U1022-C

ON_LM339DR2G_SOP_14P

12

R137

12

1M_5%

3

11

+

13

OUT

10

-

U1022-D

ON_LM339DR2G_SOP_14P

12

+V3AL

5-,6-,7-,14-,31-,39-,40-,45-,47-

ADP_PS0

ADP_PS1

1

2

12

R469

6.04K_1%

R468

100K_5%

12

+V3AL

5-,6-,7-,14-,31-,39-,40-,45-,47-

1

R476

10K_5%

2

7-,39-

VCC1_POR#_3

1

R135

10K_5%

2

+V3S

5-,11-,13-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,43-,45-,46-,47-,48-,50-,51-

1

R136

10K_5%

2

39-

INVENTEC

TITLE

S-SERIES - Discrete

Power (Sequence)

SIZE CODE

A3

DOC. NUMBER

1310A21614 A01

CS

SHEET

OF

_NTC

REV

5414

+VCCP

8-,10-,15-,16-,17-,18-,19-,20-,21-,23-,24-,31-,34-

L1011

BLM18AG471SN1D

1

CPU_BSEL1

CPU_BSEL2

FSB

FSA

1 0 0

17-,2017-,20-

FSC

1

0 0

1 0

0

R1115

1

FSB CLOCK FREQUENCY

667 800

1067

10K_5%_OPEN

10K_5%

2

R1114

10K_5%

*CLKREQ# pin controls SRC Table.

Byte5:bit7=0 , disable CR#_A ; enable CR#_A

CR#_A

Byte5:bit6=0 (PWD)

Byte5:bit6=1

SRC0

Byte5:bit4=0 (PWD) , disable CR#4 ; 1, enable CR#4

CR#_4

SRC4

2

C343

1

10uF_6.3v

2

+VCCP

8-,10-,15-,16-,17-,18-,19-,20-,21-,23-,24-,31-,34-

1

R266

2

1

2

HOST CLOCK FREQUENCY

166 200 266

SRC2

Layout note: All decoupling 0.1uF disperse closed to pin

C344

C340

1

1 2

0.1uF_16v

CPU_BSEL0

2

0.1uF_16v

1 2

17-,20-

22pF_50v_OPEN

32-

46-

323945-

39-

3219-,26-,27-,32-,37-,5019-,26-,27-,32-,37-,50-

X1

12

1

14.318MHz

2

30PPM

R1241

10K_5%

C1094

33pF_50v

CLK_R3S_ICH48

CLK_R3S_CR48

CLK_R3S_ICH14

CLK_R3S_KBC14

CLK_R3S_MINICARD

CLK_R3S_KBPCI

CLK_PWRGD

ICH_3S_SMCLK

ICH_3S_SMDATA

1 2

Please place close to CLKGEN within 500mils

Byte5:bit5=0 (PWD) , disable CR#3 ; 1, enable CR#3

CR#_3

SRC3

Byte5:bit3=0 (PWD) , disable CR#6 ; 1, enable CR#6

CR#_6

SRC6

C1092

C342

1

0.1uF_16v

2

8-,10-,15-,16-,17-,18-,19-,20-,21-,23-,24-,31-,34-

C1091

C300

OPEN

5-,11-,13-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,43-,45-,46-,47-,48-,50-,51-

C1095

33pF_50v

0.1uF_16v

12

1 2

1

2

CLKREQ_SATA#

C1077

1

0.1uF_16v

2

10K_5%_OPEN

R1109

2.2K_5%

10K_5%

R1107 33_5%

R466

12

C303

5.6pF_50v

CLKREQ_MCH#

CLKREQ_NC#

1 2

+VCCP

R1110

R1108

12

22_5%_OPEN

R267

R1113

1 2

C341

0.1uF_16v

1

2

1

2

12 12 1 1

R270

33_5%

+V3S

12

10K_5%

15-,2015-,32-

15-,46-

R269

CLK_3S_ICH48

22_5%R268 22_5% 33_5%

2 2

CR#_7

CR#_9

CR#_10

CR#_11

+V3S

5-,11-,13-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,43-,45-,46-,47-,48-,50-,51-

1

L1012

BLM18AG471SN1D

2

C1076

1 2

10uF_6.3v

1 2

C302

0.1uF_16v

1 2

0.1uF_16v

C299

1 2

0.1uF_16v

C1078

1 2

C1093

0.1uF_16v

Layout note: All decoupling 0.1uF disperse closed to pin

+V3S

U1010

62

VDDSRC_IO

52

VDDSRC_IO

38

VDDSRC_IO

23

VDD96_IO

55

VDDSRC

6

VDDREF

31

VDDPLL3_IO

66

VDDCPU_IO

CPUC2_ITP_LPR_SRCC8_LPR

19

VDD48

12 72 27

20

13 14 15

10

18 22 26 30 42 59 69

34

11 65 21 37 41 73 74 75 76

CPUT2_ITP_LPR_SRCT8_LPR VDDPCI VDDCPU VDDPLL3

USB_48MHZ_FSLA

2

FSLB_TEST_MODE

7

FSLC_TEST_SEL_REF0

8

REF1

PCI1 PCI2_TME PCI3

1

CK_PWRGD_PD#

SCLK

9

SDATA

5

X1

4

X2

GNDPCI GND48 GND

SRCT2_LPR_SATAT_LPR

GND

SRCC2_LPR_SATAC_LPR

GNDSRC GNDSRC

27MHz_NonSS_SRCT1_LPR_SE1

GNDCPU

3

27MHz_SS_SRCC1_LPR_SE2

GNDREF GNDSRC

SRCT0_LPR_DOTT_96_LPR

SRCC0_LPR_DOTC_96_LPR

NC CR#7

CR#3 CR#4 TML-PAD TML-PAD TML-PAD TML-PAD

ICS_ICS9LPRS397_MLF_72P

PCI_STOP#

CPU_STOP#

CPUT1_LPR_F CPUC1_LPR_F

CPUT0_LPR_F CPUC0_LPR_F

SRCT11_LPR SRCC11_LPF

SRCT10_LPR

SRCC10_LPR

SRCT9_LPR SRCC9_LPR

SRCT7_LPR SRCC7_LPR

SRCT6_LPR SRCC6_LPR

PCI4_27_Select PCI_F5_ITP_EN

SRCT4_LPR SRCC4_LPR

SRCT3_LPR SRCC3_LPR

CR#9CR#A CR#11 CR#10

CR#6

54 53

68 67

71 70

63 64

48 47

50 51

44 45

61 60

57 56

CLK_3S_DEBUG

16

CLK_3S_ICHPCI

17

39 40

35 36

32 33

28 29

24 25

43 46 49 58

Byte5:bit2=0 (PWD) , disable CR#7 ; 1, enable CR#7

SRC8

Byte5:bit1=0 (PWD) , disable CR#9 ; 1, enable CR#9

SRC9

Byte5:bit0=0 (PWD) , disable CR#10 ; 1, enable CR#10

SRC10

Byte6:bit7=0 (PWD) , disable CR#11 ; 1, enable CR#11

SRC11

C345

C301

1

2

0.1uF_16v

5-,11-,13-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,43-,45-,46-,47-,48-,50-,51-

1

R1099

R1098

10K_5%

2

33_5%

ITP_EN =0 SRC8/SRC8#

ITP_EN =1 ITP/ITP#

CLKREQ_MCH#

CLKREQ_SATA#

CLKREQ_MINI_WLAN#

CLKREQ_ROB#

CHANGE by

R111212

12

R111133_5%

0_5%R463

12

0_5%R1327

12

5-,11-,13-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,43-,45-,46-,47-,48-,50-,51-

+V3S

R1139

CLKREQ_NC#

2

10K_5%

R1138

2

OPEN

15-,2015-,3215-,46-

15-,4515-,45-

1

12

10K_5%

R1116

R1097

R285 10K_5%12

Drawer_Name

+V3S

R1140

1 12 12 12

32-

PCISTOP#_3

32-

CPUSTOP#_3

21-

CLK_MCHBCLK

21-

CLK_MCHBCLK#

16-

CLK_CPUBCLK

16-

CLK_CPUBCLK#

19-

CLK_XDP#

19-

CLK_XDP

45-

CLK_PCIE_MINI_WLAN

45-

CLK_PCIE_MINI_WLAN#

45-

CLK_PCIE_ROB

45-

CLK_PCIE_ROB#

43-

CLK_PCIE_LAN

43-

CLK_PCIE_LAN#

20-

CLK_PEG_MCH

20-

CLK_PEG_MCH#

45-

CLK_UWB

45-

CLK_UWB#

39-

CLK_R3S_DEBUG

33-

CLK_R3S_ICHPCI

46-

CLK_PCIE_NC

46-

CLK_PCIE_NC#

32-

CLK_PCIE_ICH

32-

CLK_PCIE_ICH#

31-

CLK_SATA1

31-

CLK_SATA1#

49-

CLK_27MHZ

49-

CLK_27MHZ_SS

50-

CLK_PEG_REF

50-

CLK_PEG_REF#

43-

CLKREQ_LAN#

15-,45-

CLKREQ_MINI_WLAN#

15-,45-

CLKREQ_ROB#

27_Selet =0

LCD_SST 100MHZ

27_Selet =1

27MHZ non-spread clock

+V3S

5-,11-,13-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,37-,39-,41-,42-,43-,45-,46-,47-,48-,50-,51-

10K_5%

2

10K_5%R271 10K_5%R1095 10K_5%

INVENTEC

TITLE

S-SERIES - Discrete

Clock Generator

SIZE

CODE

A3

CS

2-Apr-2008

SHEET

DOC. NUMBER

OF

15 54

REV

A011310A21614

H_A#(35:3)

21-

H_A#(3) H_A#(4) H_A#(5) H_A#(6) H_A#(7) H_A#(8) H_A#(9) H_A#(10) H_A#(11) H_A#(12) H_A#(13) H_A#(14) H_A#(15) H_A#(16)

H_REQ#(4:0) H_RS#(2:0)

H_A#(17) H_A#(18) H_A#(19) H_A#(20) H_A#(21) H_A#(22) H_A#(23) H_A#(24) H_A#(25) H_A#(26) H_A#(27) H_A#(28) H_A#(29) H_A#(30) H_A#(31) H_A#(32) H_A#(33) H_A#(34) H_A#(35)

21-

H_ADSTB#0

H_REQ#(0) H_REQ#(1) H_REQ#(2) H_REQ#(3) H_REQ#(4)

H_ADSTB#1

H_STPCLK#

21-

31-

H_A20M#

31-

H_FERR#

31-

H_IGNNE#

3131-

H_INTR

31-

H_NMI

H_SMI# CLK_CPUBCLK#

GMCH

CN1011-1

J4

A3#

L5

A4#

L4

A5#

K5

A6#

M3

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L2

A13#

P4

A14#

P1

A15#

R1

A16#

M1

ADSTB0#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L1

REQ4#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U1

A23#

R4

A24#

T5

A25#

T3

A26#

W2

A27#

W5

A28#

Y4

A29#

U2

A30#

V4

A31#

W3

A32#

AA4

A33#

AB2

A34#

AA3

A35#

V1

ADSTB1#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD01

N5

RSVD02

T2

RSVD03

V3

RSVD04

B2

RSVD05

C3

RSVD06

D2

RSVD07

D22

RSVD08

D3

RSVD09

F6

RSVD010

ADS#

BNR#

BPRI#

DEFER#

DRDY#

DBSY#

BR0#

IERR#

ADDR GROUP 0

INIT#

CONTROL

LOCK#

RESET#

RS0# RS1# RS2#

TRDY#

HIT#

HITM#

BPM0# BPM1# BPM2# BPM3# PRDY#

PREQ#

TCK

TDI

ADDR GROUP 1

TDO TMS

XDP/ITP SIGNALS

TRST#

DBR#

THERMAL

PROCHOT#

THERMDA THERMDC

THERMTRIP#

ICH

H CLK

BCLK0 BCLK1

RESERVED

FOX_PZ4782K_274M_41_478P

CPU

ICH8

H1 E2 G5

H5 F21 E1

F1

D20 B3

H4

C1 F3 F4 G3 G2

G6 E4

AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20

1

R171

D21 A24 B25

10mils/10mils

C7

A22 A21

+VCCP

212121-

21-

31-

21-

2121-

1919191919-

16-,1916-,1916-,19-

19-

16-,19-

19-,32-

+VCCP

2

56_5%

1919-

20-,31-

1515-31-

H_ADS# H_BNR# H_BPRI#

H_DEFER# H_DRDY# H_DBSY#

H_BREQ#0

H_INIT#

H_LOCK#

H_TRDY# H_HIT#

H_HITM#

H_BPM0_XDP# H_BPM1_XDP# H_BPM2_XDP#

H_BPM3_XDP# H_BPM4_PRDY#

H_BPM5_PREQ#

H_TCK TDI_FLEX

H_TDO

H_TMS

XDP_DBRESET#

8-,10-,15-,16-,17-,18-,19-,20-,21-,23-,24-,31-,34-

H_THERMDA H_THERMDC

PM_THRMTRIP#

CLK_CPUBCLK

+VCCP

8-,10-,15-,16-,17-,18-,19-,20-,21-,23-,24-,31-,34-

1

2

51 ohm +/-1% pull-up to +VCCP

R239

R170

51_5%

56_5%

2

1

2

(VCCP) if ITP is implemented.

1

Close to CPU.

19-,21-

19-

H_TRST#

R234

54.9_1%

H_CPURST#

H_RS#(0) H_RS#(1) H_RS#(2)

+VCCP

8-,10-,15-,16-,17-,18-,19-,20-,21-,23-,24-,31-,34-

R1119

12

54.9_1%

R235

12

54.9_1%

R236

12

54.9_1%

R1117

12

54.9_1%

16-,19-

21-

H_BPM5_PREQ#

TDI_FLEX

H_TMS

H_TCK

PM_THRMTRIP# should be T at CPU

CHANGE by

Drawer_Name

31-Mar-2008

INVENTEC

TITLE

S-SERIES - Discrete

CPU Penryn-1

CODE

SIZE

A3

CS

SHEET

DOC. NUMBER

16 54

REV

A011310A21614

OF

Layout note: Zo=55 ohm,

0.5" max for GTLREF.

H_D#(63:0)

H_DSTBN#0

H_D#(63:0)

+VCCP

8-,10-,15-,16-,17-,18-,19-,20-,21-,23-,24-,31-,34-

1

R1178

1K_1%

R1179

2K_1%

H_DSTBN#1

2

1

2

CPU_BSEL0 CPU_BSEL1 CPU_BSEL2

H_DSTBP#0

H_DINV#0

H_DSTBP#1

H_DINV#1

GTLREF

17-,21-

212121-

17-,21-

212121-

15-,2015-,2015-,20-

R1174

OPEN

1

2

R1175

OPEN

H_D#(0) H_D#(1) H_D#(2) H_D#(3) H_D#(4) H_D#(5) H_D#(6) H_D#(7) H_D#(8) H_D#(9) H_D#(10) H_D#(11) H_D#(12) H_D#(13) H_D#(14) H_D#(15)

H_D#(16) H_D#(17) H_D#(18) H_D#(19) H_D#(20) H_D#(21) H_D#(22) H_D#(23) H_D#(24) H_D#(25) H_D#(26) H_D#(27) H_D#(28) H_D#(29) H_D#(30) H_D#(31)

1

2

C1224

0.1uF_16v_OPEN

CN1011-2

E22

D0#

F24

D1#

E26

D2#

G22

D3#

F23

D4#

G25

D5#

E25

D6#

E23

D7#

K24

D8#

G24

DATA GRP 0

D9#

J24

D10#

J23

D11#

H22

D12#

F26

D13#

K22

D14#

H23

D15#

J26

DSTBN0#

H26

DSTBP0#

H25

DINV0#

N22

D16#

K25

D17#

P26

D18#

R23

D19#

L23

D20#

M24

D21#

L22

D22#

M23

D23#

P25

D24#

P23

D25#

P22

DATA GRP 1

D26#

T24

D27#

R24

D28#

L25

D29#

T25

D30#

N25

D31#

L26

DSTBN1#

M26

DSTBP1#

N24

DINV1#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

C1114

1 2

0.1uF_16v_OPEN

MISC

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL0

B23

BSEL1

C21

BSEL2

FOX_PZ4782K_274M_41_478P

Place the capacitance close to the TEST3,TEST5 pin. Make sure TEST3,TEST5 routing is reference to GND and away from other noisy signals.

D32# D33# D34# D35# D36# D37# D38# D39# D40#

DATA GRP 2DATA GRP 3

D41# D42# D43# D44# D45# D46#

D47# DSTBN2# DSTBP2#

DINV2#

D48#

D49#

D50#

D51#

D52#

D53#

D54#

D55#

D56#

D57#

D58#

D59#

D60#

D61#

D62#

D63# DSTBN3# DSTBP3#

DINV3#

COMP0 COMP1 COMP2 COMP3

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

1

2

H_D#(32) H_D#(33) H_D#(34) H_D#(35) H_D#(36) H_D#(37) H_D#(38) H_D#(39) H_D#(40) H_D#(41) H_D#(42) H_D#(43) H_D#(44) H_D#(45) H_D#(46) H_D#(47)

H_D#(48) H_D#(49) H_D#(50) H_D#(51) H_D#(52) H_D#(53) H_D#(54) H_D#(55) H_D#(56) H_D#(57) H_D#(58) H_D#(59) H_D#(60) H_D#(61) H_D#(62) H_D#(63)

2121-

27.4_1%R229

11-,20-,31-

21-

3121-

2111-

12

R1176 27.4_1%

12

R1177 54.9_1%

12 12

R230 54.9_1%

R237

OPEN

+VCCP

8-,10-,15-,16-,17-,18-,19-,20-,21-,23-,24-,31-,34-

17-,21-

H_D#(63:0)

21-

H_DSTBN#2

21-

H_DSTBP#2

21-

H_DINV#2

17-,21-

H_D#(63:0)

H_DSTBN#3 H_DSTBP#3 H_DINV#3

Close to CPU. COMP0, 2: 18mils.

H_DPRSTP#

H_DPSLP#

H_DPWR#

H_CPUSLP# PSI#

Place the 1K series resistor on H_PWRGD_XDP without stub.

R238

1

1K_5%

2

31-

H_PWRGD

19-

H_PWRGD_XDP

CHANGE by

INVENTEC

TITLE

S-SERIES - Discrete

CPU Penryn-2

DOC. NUMBER

CODE

SIZE

A3

CS

SHEET

31-Mar-2008Drawer_Name

17 54

REV

A011310A21614

OF