How it Works
HP
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Envy TouchSmart 15-u
Schematics
42 pgs949.11 Kb0

HP Envy TouchSmart 15-u Schematics

5
www.schematic-x.blogspot.com
4
3
2
1
13"/15"
01
D D
C C
Home Capacitve button
ENE SB35884
B B
G-Sensor
HP3DC2TR
Keyboard
15" KB Backlight only
Touch Pad
TCP-15G24
ERD Review
A A
Intel Skylake ULT Platform Block Diagram
DDR3L SODIMM1 Maxima 8GBs
DDR3L SODIMM2 Maxima 8GBs
SATA - 1st HDD Package :7.2 (mm) Power :
System BIOS SPI ROM
SM BUS
SPI Interface
TPM
SLB9665TT2.0 FW 5
Embedded Controller
ITE 8987
Power :
Package : LQPF128
Size : 14 x 14 (mm)
FAN
DDR3L x1600MHz 1.35V
DDR3L x1600MHz 1.35V
SATA0 6GB/s Gen3
Port 0
Crystal 24MHz
Crystal
32.768KHz
Skylake U Processor
Processor : Daul Core Power : 15 (Watt) Package : BGA1356 Size : 42 X 24 (mm)
INT
Audio Codec
ALC3227
Power :
Package : MQFN48
Size : 6 x 6 (mm)
Speaker
Headphone amplifier
HPA0022642RTJR
PAGE 2~16
Azalia
eDP X2
DP Port 1
ISH
USB3.0 Interface
USB2.0 Interface
USB2.0 Port x 1(USB board)
PCIE Gen 1 x 1 LaneLPC Interface
Port5 Port6Port9
Carde Reader
RTS5237
Power : Package : LQPF32 Size : 6 x 6 (mm)
Int
Combo Jack
PAGE 18 PAGE 23
iPHONE type
USB 3.0 Port 1,3(USB 2.0 Port 1,2)
(2A)
Camera
USB2.0 Port 3USB2.0 Port 6 USB2.0 Port 8
LAN Controller
13" 10/100 RTL8176EH-CG 15" Giga RTL8161GSH
Power : Package : OFN32
Int
PS8201A
Package : QFN-48
Touch Screen
M.2 NGFF Card WLAN / BT Combo
USB2.0 Port7
eDP
HDMI Conn
G-Sensor
HP3DC2TR
Accelerometer/Compass/Gryoscope
HP9DS1TR
USB3.0 Port x 2
(total 2.5A)
PCB 8L STACK UP
LAYER 1 : TOP LAYER 2 : GND1 LAYER 3 : IN1 LAYER 4 : IN2 LAYER 5 : VCC LAYER 6 : IN3 LAYER 7 :GND2 LAYER 8 :BOT
5
Digital MIC
4
3
2
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Block Diagram
Block Diagram
Block Diagram
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
1 42Wednesday, July 22, 2015
1 42Wednesday, July 22, 2015
1 42Wednesday, July 22, 2015
1A
1A
1A
5
+3V 4,10,11,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,29,30,31,37,39 +1.0V 4,6,16,30,36 +VCCIO 6,16,36 +VCCSTPLL 4,5,6,9,36,37
D D
C C
HDMI
eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms
SDVO_CLK21
SDVO_DATA21
+VCCIO
IN_D2#21 IN_D221 IN_D1#21 IN_D121 IN_D0#21 IN_D021 IN_CLK#21 IN_CLK21
TP23
TP21
4
IN_D2# IN_D2 IN_D1# IN_D1 IN_D0# IN_D0 IN_CLK# IN_CLK
DDPC_CTRLDATA
DDPD_CTRLDATA
R220 24.9/F_4
EDP_RCOMP
U17A
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22/DDPD_CTRLCLK
N12
GPP_E23/DDPD_CTRLDATA
E52
EDP_RCOMP
SKL_ULT
REV = 1
SKL_ULT
DDI
DISPLAY SIDEBANDS
3
?
Need apply PN
EDP
GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]
EDP_AUXN EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
?1 OF 20
C47 C46 D46 C45 A45 B45 A47 B47
E45 F45
B52 G50
F50 E48 F48 G46 F46
L9 L7 L6 N9 L10
R12 R11 U13
INT_EDP_TXN0 INT_EDP_TXP0 INT_EDP_TXN1 INT_EDP_TXP1
INT_EDP_AUXN INT_EDP_AUXP
EDP_DISP_UTIL
HDMI_HPD_CON
ULT_EDP_HPD PCH_LVDS_BLON
PCH_DPST_PWM PCH_DISP_ON
2
INT_EDP_TXN0 20 INT_EDP_TXP0 20 INT_EDP_TXN1 20 INT_EDP_TXP1 20
INT_EDP_AUXN 20 INT_EDP_AUXP 20
TP107
HDMI_HPD_CON 21
ULT_EDP_HPD 20 PCH_LVDS_BLON 20
PCH_DPST_PWM 20 PCH_DISP_ON 20
1
Reserve EDP_HPD opposites circuit!
+3V
R30 *10K_4
ULT_EDP_HPD
R51 100K_4
02
?
4 OF 20
Need apply PN
JTAG
PROC_TCK
PROC_TDI PROC_TDO PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS
PCH_TRST#
JTAGX
PDC
XDP_TCK0
B61
XDP_TDI_CPU
D60
XDP_TDO_CPU
A61
XDP_TMS_CPU
C60
XDP_TRST#_CPU
B59
JTAG_TCK_PCH
B56
JTAG_TDI_PCH
D59
JTAG_TDO_PCH
A56
JTAG_TMS_PCH
C59
XDP_TRST#_CPU
C61
JTAGX_PCH
A59
XDP_TCK0 16 XDP_TDI_CPU 16 XDP_TDO_CPU 16 XDP_TMS_CPU 16 XDP_TRST#_CPU 2,16
JTAG_TCK_PCH 16 JTAG_TDI_PCH 16 JTAG_TDO_PCH 16 JTAG_TMS_PCH 16 XDP_TRST#_CPU 2,16 JTAGX_PCH 16
2
Close to EC
PM_THRMTRIP#
Processor pull-up (CPU) TO BE REPLACED WITH 1K OHMS FOR SKL . 470 OHM IS FOR I/P
R469 1K_4
PLACE NEAR CPU
XDP_TMS_CPU XDP_TDI_CPU XDP_TDO_CPU
H_PROCHOT# XDP_TCK0 XDP_TRST#_CPU
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet
R336 *51_4 R323 R324 *51_4
R471 1K_4 R325 51_4 R331 51_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
02 -- SKYPAKE 1/20(eDP/DDI)
02 -- SKYPAKE 1/20(eDP/DDI)
02 -- SKYPAKE 1/20(eDP/DDI)
+VCCSTPLL
+1.0V
*51_4
+1.0V
2 42Wednesday, July 22, 2015
2 42Wednesday, July 22, 2015
2 42Wednesday, July 22, 2015
1
of
1A
1A
1A
SKL_ULT
U17D
AT16
AU16
D63 A54 C65 C63 A65
C55 D55 B54 C56
A6
A7 BA5 AY5
H66 H65
CATERR# PECI PROCHOT# THERMTRIP# SKTOCC#
CPU MISC
BPM#[0] BPM#[1] BPM#[2] BPM#[3]
GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3
PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP
SKL_ULT
REV = 1
TP117
H_PROCHOT#30,32,37
+VCCSTPLL
R470 *49.9/F_4
0612 Change R335 from 0 ohm to short pad
+1.0V
B B
R335 *0_4/S
CATERR#
R326 *51_4 R322 51_4 R329 51_4 R327 51_4 R328 51_4
JTAGX_PCH JTAG_TMS_PCH JTAG_TDI_PCH JTAG_TDO_PCH JTAG_TCK_PCH
R463 499/F_4
EC_PECI30 PM_THRMTRIP#30
XDP_BPM016 XDP_BPM116
TP94 TP92 TP55 TP56
R109 49.9/F_4 R108 49.9/F_4 R273 49.9/F_4 R272 49.9/F_4
CATERR# EC_PECI
PROCHOT# PM_THRMTRIP#
CPU_GP0 CPU_GP1 CPU_GP2 CPU_GP3
PROC_POPIRCOMP PCH_OPI_RCOMP EDRAM_OPIO_RCOMP EOPIO_RCOMP
Close to Chipset
A A
5
4
3
5
M_A_DQSN[7:0]17 M_A_DQSP[7:0]17 M_B_DQSN[7:0]18 M_B_DQSP[7:0]18 M_A_DQ[63:0]17 M_B_DQ[63:0]18
D D
C C
B B
+1.35VSUS 6,17,18,34,36
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_A_DQ16 M_A_DQ17
AW65
M_A_DQ18
AW63
M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25
AW61
M_A_DQ26 M_A_DQ27
AW59
M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31
U17B
AL71
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
BB65
DDR0_DQ[16]/DDR0_DQ[32] DDR0_DQ[17]/DDR0_DQ[33] DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42] DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
SKL_ULT
REV = 1
Need apply PN
?
SKL_ULT
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
NIL-DDR CH ­A
2 OF 20
4
DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]
DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]
DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]
DDR0_MA[3] DDR0_MA[4]
DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1]
DDR0_DQSP[1] DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ DDR1_VREF_DQ
DDR_VTT_CNTL
3
SkyLake ULT Processor (DDR3L)
AU53 AT53 AU55 AT55
BA56 BB56 AW56 AY56
AU45 AU43 AT45 AT43
M_A_A5
BA51
M_A_A9
BB54
M_A_A6
BA52
M_A_A8
AY52
M_A_A7
AW52
M_A_BS#2
AY55
M_A_A12
AW54
M_A_A11
BA54
M_A_A15
BA55
M_A_A14
AY54
M_A_A13
AU46 AU48 AT46 AU50 AU52
M_A_A2
AY51 AT48
M_A_A10
AT50
M_A_A1
BB50
M_A_A0
AY50
M_A_A3
BA50
M_A_A4
BB52
M_A_DQSN0
AM70
M_A_DQSP0
AM69
M_A_DQSN1
AT69
M_A_DQSP1
AT70
M_B_DQSN0
AH66
M_B_DQSP0
AH65
M_B_DQSN1
AG69
M_B_DQSP1
AG70
M_A_DQSN2
BA64
M_A_DQSP2
AY64
M_A_DQSN3
AY60
M_A_DQSP3
BA60
M_B_DQSN2
AR66
M_B_DQSP2
AR65
M_B_DQSN3
AR61
M_B_DQSP3
AR60 AW50
DDR0_PAR
AT52
SM_VREF
AY67
SMDDR_VREF_DQ0_M3
AY68
SMDDR_VREF_DQ1_M3
BA67
DDR_VTT_CNTL
AW67
M_A_CLKN0 17 M_A_CLKP0 17 M_A_CLKN1 17 M_A_CLKP1 17
M_A_CKE0 17 M_A_CKE1 17
M_A_CS#0 17 M_A_CS#1 17 M_A_DIM0_ODT0 17 M_A_DIM0_ODT1 17 M_B_DIM0_ODT0 18
M_A_A5 17 M_A_A9 17 M_A_A6 17 M_A_A8 17 M_A_A7 17 M_A_BS#2 17 M_A_A12 17 M_A_A11 17 M_A_A15 17 M_A_A14 17
M_A_A13 17 M_A_CAS# 17 M_A_WE# 17 M_A_RAS# 17 M_A_BS#0 17 M_A_A2 17 M_A_BS#1 17 M_A_A10 17 M_A_A1 17 M_A_A0 17 M_A_A3 17 M_A_A4 17
TP44
SM_VREF 17 SMDDR_VREF_DQ0_M3 17 SMDDR_VREF_DQ1_M3 18
DDR_VTT_CNTL 4,18
20mils width
M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
U17C
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
SKL_ULT
REV = 1
2
?
SKL_ULT
Need apply PN
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSN[7]/DDR1_DQSN[5]
NIL-DDR CH ­B
3 OF 20
DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]
DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]
DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]
DDR1_MA[3] DDR1_MA[4]
DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSP[5]/DDR1_DQSP[1] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSP[5]/DDR1_DQSP[3] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSP[7]/DDR1_DQSP[5]
DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]
DDR1_ALERT#
DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]
PDC
DDR1_PAR
AN45 AN46 AP45 AP46
AN56 AP55 AN55 AP53
BB42 AY42 BA42 AW42
AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52
BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47
BA38 AY38 AY34 BA34 AT38 AR38 AT32 AR32 BA30 AY30 AY26 BA26 AR25 AR27 AR22 AR21
AN43 AP43 AT13 AR18 AT18 AU18
M_B_A5 M_B_A9 M_B_A6 M_B_A8 M_B_A7
M_B_A12 M_B_A11 M_B_A15 M_B_A14
M_B_A13
M_B_A2 M_B_A10
M_B_A1 M_B_A0 M_B_A3 M_B_A4
M_A_DQSN4 M_A_DQSP4 M_A_DQSN5 M_A_DQSP5 M_B_DQSN4 M_B_DQSP4 M_B_DQSN5 M_B_DQSP5 M_A_DQSN6 M_A_DQSP6 M_A_DQSN7 M_A_DQSP7 M_B_DQSN6 M_B_DQSP6 M_B_DQSN7 M_B_DQSP7
DDR1_PAR SM_DRAMRST# SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2
TP42
R164 121/F_4 R158 80.6/F_4 R154 100/F_4
1
M_B_CLKN0 18 M_B_CLKN1 18 M_B_CLKP0 18 M_B_CLKP1 18
M_B_CKE0 18 M_B_CKE1 18
M_B_CS#0 18 M_B_CS#1 18
M_B_DIM0_ODT1 18 M_B_A5 18
M_B_A9 18 M_B_A6 18 M_B_A8 18 M_B_A7 18 M_B_BS#2 18 M_B_A12 18 M_B_A11 18 M_B_A15 18 M_B_A14 18
M_B_A13 18 M_B_CAS# 18 M_B_WE# 18 M_B_RAS# 18 M_B_BS#0 18 M_B_A2 18 M_B_BS#1 18 M_B_A10 18 M_B_A1 18 M_B_A0 18 M_B_A3 18 M_B_A4 18
+1.35VSUS
R293 470_4
DDR3_DRAMRST# 17,18
03
A A
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
03 -- SKYPAKE 3/20(DDR3-A I/F)
03 -- SKYPAKE 3/20(DDR3-A I/F)
03 -- SKYPAKE 3/20(DDR3-A I/F)
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet
1
1A
1A
1A
3 42Wednesday, July 22, 2015
3 42Wednesday, July 22, 2015
3 42Wednesday, July 22, 2015
of
5
+3V_DEEP_SUS10,11,12,14,15,16,18
+3V2,10,11,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,29,30,31,37,39
+3VS510,15,16,28,29,30,33,35,36,39
+VCCSTPLL2,5,6,9,36,37
+1.0V2,6,16,30,36
+3V_RTC13,15,27,28,32
+3V_RTC_213,15
D D
RSMRST#30
SUSWARN#
SUSACK#_EC30
R97*0_4
R890_4
EC4 *220P/50V_4
SYS_RESET#16
R467 *10K_4
SYS_PWROK16
EC_PWROK16,30
SUSWARN#_EC30
PCIE_WAKE#24,28,30,31
DDR_VTT_CNTL3,18
C427 *0.1U/16V_4
R88 *0_4/S
0612 Change R88 from 0 ohm to short pad
4
?
U17K
PLTRST# SYS_RESET#
RSMRST# PROCPWRGD
H_VCCST_PWRGD SYS_PWROK
PCH_PWROK DSWROK_EC_R
SUSWARN# SUSACK#
PCIE_WAKE# LAN_WAKE# LAN_WAKE#
DDR_VTT_CNTL
AN10
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PW ROK
AR13
GPP_A13/SUSW ARN#/SUSPWRDNACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/RSVD
SKL_ULT
REV = 1
SKL_ULT
SYSTEM POWER MANAGEMENT
Need apply PN
11 OF 20
3
GPP_B12/SLP_S0#
GPD4/SLP_S3# GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS# SLP_LAN#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW #
GPP_A11/PME#
GPP_B11/EXT_PW R_GATE#
INTRUDER#
GPP_B2/VRALERT#
2
PCH_SLP_S0_N
AT11 AP15 BA16 AY16
SLP_SUS#_EC
AN15 AW15 BB17
GPD9
AN16 BA15
DNBSWON# AC_PRESENT_EC
AY15
RF_OFF_PCH
AU13
AU11
INTRUDER#_R
AP16 AM10
GPP_B2
AM11
?
TP100
R140 *1M_4 R134 1M_4
TP33
PCH_SLP_S0_N 16,30 SUSB# 16,30 SUSC# 16,30 SLP_S5# 16
SLP_SUS#_EC 30
SLP_A# 16 DNBSWON# 30
AC_PRESENT_EC 30 RF_OFF_PCH 28
+3V_RTC +3V_RTC_2
PCH Pull-high/low(CLG)
6/12 Change R78 from I to NI
SUSWARN# SUSACK# RF_OFF_PCH
PCIE_WAKE# AC_PRESENT_EC
SYS_RESET# RSMRST#
DSWROK_EC
1
04
+3V_DEEP_SUS
R78 *10K_4 R79 10K_4 R77 10K_4
+3VS5
R75 1K_4 R86 *10K_4 R577 *10K_4
+3V
R400 10K_4 R81 10K_4 R94 100K/F_4
C C
For DS3 Sequence
For DS3 -->Ra Non-DS3 -->Rb
RSMRST#
DSWROK_EC30
PLTRST#(CLG)
Check Q2010 Rise/Fall time less than 100ns
R353
B B
100K/F_4
Rb
R90 *0_4
R91 0_4
Ra
PLTRST# 16,24,26,28,30,31
DSWROK_EC_R
+1.0V
HWPG16,30,33,34,35
D13 MEK500V-40
21
Close to CPU side H_VCCST_PWRGD trace 0.3" - 1.5"
+VCCSTPLL
R472 1K_4
H_VCCST_PWRGD_R
C486 *10P/50V_4
R473 *1K_4
R464 60.4_4
H_VCCST_PWRGD
System PWR_OK(CLG)
R410 0_4
A A
EC_PWROKSYS_PWROK
R411 10K/F_4
+1.0V +3VS5+5VS5
R68 15K_4
+1.0V_PWRGD_G1
C29
0.1U/16V_4
R70 100K_4
2
1 3
R25 100K_4
+1.0V_PWRGD_G2
Q3 METR3904-G
R8 10K_4
R12 100K_4
HWPG
3
2
Q2 2N7002K
1
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
04 -- SKYPAKE 5/20(Power Manger)
04 -- SKYPAKE 5/20(Power Manger)
04 -- SKYPAKE 5/20(Power Manger)
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet
1
1A
1A
1A
4 42Wednesday, July 22, 2015
4 42Wednesday, July 22, 2015
4 42Wednesday, July 22, 2015
of
5
+VCC_CORE37
+VCCSTG6
+VCCSTPLL2,4,6,9,36,37
Under CPU
C253
C167
22U/6.3V_6
D D
C C
10U/6.3V_6
10U/6.3V_4
C164 22U/6.3V_6
C210 10U/6.3V_4
C272 22U/6.3V_6
22U/6.3V_6
C157 10U/6.3V_4
C240 22U/6.3V_6
22U/6.3V_6
C211 10U/6.3V_4
C273 22U/6.3V_6
C271
22U/6.3V_6
C190 10U/6.3V_4
C468 22U/6.3V_6
C177
22U/6.3V_6
C209 10U/6.3V_4
C166 22U/6.3V_6
C189
C249
TP46 TP45
C270
22U/6.3V_6
C461 10U/6.3V_4
VCCEOPIO_SENSE VSSEOPIO_SENSE
Close CPU
+VCC_CORE
C170 47U/6.3VS_8
+VCC_CORE
4
?
SKL_ULT
A30 A34 A39
A44 AK33 AK35 AK37 AK38 AK40
AL33 AL37
AL40 AM32 AM33 AM35 AM37 AM38
G30
K32 AK32 AB62
P62
V62
H63
G61 AC63
AE63 AE62
AG62
AL63 AJ62
C219
47U/6.3VS_8
U17L
VCC_A30 VCC_A34
33A
VCC_A39 VCC_A44 VCC_AK33 VCC_AK35 VCC_AK37 VCC_AK38 VCC_AK40 VCC_AL33 VCC_AL37 VCC_AL40 VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30
RSVD_K32 RSVD_AK32 VCCOPC_AB62
VCCOPC_P62 VCCOPC_V62
VCC_OPC_1P8_H63 VCC_OPC_1P8_G61 VCCOPC_SENSE
VSSOPC_SENSE VCCEOPIO
VCCEOPIO VCCEOPIO_SENSE
VSSEOPIO_SENSE
SKL_ULT
REV = 1
C171
47U/6.3VS_8
+VCC_CORE +VCC_CORE
C165
22U/6.3V_6
C205 47U/6.3VS_8
CPU POWER 1 OF 4
12 OF 20
C169
47U/6.3VS_8
Need apply PN
VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42
VCC_J30 VCC_J33 VCC_J37
VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43
VCC_SENSE VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
PDC
C220
47U/6.3VS_8
47U/6.3VS_8
C222
?
3
G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43
E32 E33
H_CPU_SVIDALRT#
B63
VR_SVID_CLK_R
A63
H_CPU_SVIDDAT
D64 G20
C221
47U/6.3VS_8
C446 1U/6.3V_4
C174 1U/6.3V_4
C198 1U/6.3V_4
C195 1U/6.3V_4
R196 *100/F_4
R190 *100/F_4
+VCCSTG
2
Un
der CPU
C173 1U/6.3V_4
C196 1U/6.3V_4
C200 1U/6.3V_4
C197 1U/6.3V_4C229
+VCC_CORE VCC_SENSE 37
VSS_SENSE 37
C466 1U/6.3V_4
C162 1U/6.3V_4
C191 1U/6.3V_4
C161 1U/6.3V_4
C199 1U/6.3V_4
C187 1U/6.3V_4
C206 1U/6.3V_4
100- ±1% pull-up to VCC near processor.
Layout note: need routing together and ALERT need between CLK and DATA.
+VCCSTPLL
CLOSE TO CPU PLACE THE PU RESISTORS
H_CPU_SVIDALRT#
R260 220/F_4
R259
56.2/F_4
C302 *0.1U/16V_4
SVID ALERT
1
05
VR_SVID_ALERT# 37
C226
B B
A A
5
10U/6.3V_4
C175 10U/6.3V_4
4
C176 10U/6.3V_4
C160 10U/6.3V_4
C463 10U/6.3V_4
C172 10U/6.3V_4
C464 10U/6.3V_4
C467 10U/6.3V_4
3
PLACE THE PU RESISTORS CLOSE TO VR PULL UP IS IN THE VR MODULE
CLOSE TO CPU PLACE THE PU RESISTORS
VR_SVID_CLK_R
H_CPU_SVIDDAT
2
R254 *0_4/S
+VCCSTPLL
+VCCSTPLL
R271 100/F_4
R266 *0_4/S
R253 *54.9/F_4
SVID CLK
VR_SVID_CLK 37
VID DATA
S
VR_SVID_DATA 37
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
05 -- SKYPAKE 6/20 (POWER-1)
05 -- SKYPAKE 6/20 (POWER-1)
05 -- SKYPAKE 6/20 (POWER-1)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
1A
1A
1A
5 42Wednesday, July 22, 2015
5 42Wednesday, July 22, 2015
5 42Wednesday, July 22, 2015
5
+VCCSTPLL 2,4,5,9,36,37 +VCCSA 37,38 +1.35VSUS 3,17,18,34,36 +VCCIO 2,16,36 +1.0V 2,4,16,30,36 +3VPCU 13,18,27,28,30,32,33 +1.35V_VCCPLL_OC 36
Under CPU
D D
C264
10U/6.3V_4
C163
10U/6.3V_4
C280 10U/6.3V_4
C142
10U/6.3V_4
C288 10U/6.3V_4
C265
10U/6.3V_4
Close CPU
+VCCSTPLL
R178 0_4
+1.0V
R179 *0_4
+VCCIO
R574 *0_4
C C
R182 *0_6
+1.35V_VCCPLL_OC
R575 0_6
R175 *0_6/S
+VCCPLL_OC+1.35VSUS
+1.35VSUS
C297 1U/6.3V_4
C179 1U/6.3V_4
C251
1U/6.3V_4
C168 1U/6.3V_4
C276
*10U/6.3V_4
Close CPU Under CPU
+VCCSTG
+VCCPLL+VCCSTPLL
0612 Change R175 from 0 ohm to short pad
C194 1U/6.3V_4
+VCCSTPLL
+VCCSTG
+VCCPLL_OC
+VCCPLL
4
120mA
AU23 AU28 AU35 AU42 BB23 BB32 BB41 BB47 BB51
AM40
AL23
A18 A22
K20 K21
SKL_ULT
U17N
CPU POWER 3 OF 4
VDDQ_AU23 VDDQ_AU28 VDDQ_AU35 VDDQ_AU42 VDDQ_BB23 VDDQ_BB32 VDDQ_BB41 VDDQ_BB47 VDDQ_BB51
VDDQC
0
VCCST VCCSTG_A22 VCCPLL_OC VCCPLL_K20
VCCPLL_K21
SKL_ULT
REV = 1
2A
.12A
0.04A
0.12A
Need apply PN
?
3.
1A
4.5A
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE VCCSA_SENSE
14 OF 20
VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO
VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA
AK28 AK30 AL30 AL42 AM28 AM30 AM42
AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30
AM23 AM22
H21 H20
3
Under CPU Close CPU
C234 1U/6.3V_4
C138 10U/6.3V_4
C136
C132
1U/6.3V_4
10U/6.3V_4
C92
C66
1U/6.3V_4
1U/6.3V_4
C430
C111
10U/6.3V_4
10U/6.3V_4
VSSSA_SENSE 37 VCCSA_SENSE 37
C133 1U/6.3V_4
+VCCSA
C75 1U/6.3V_4
VCCIO_VCCSENSE VCCIO_VSSSENSE
0701 Delete C103 for Layout placement request
C129 10U/6.3V_4
C88 1U/6.3V_4
C113 10U/6.3V_4
C130 10U/6.3V_4
C432 1U/6.3V_4
C431 10U/6.3V_4
VCCIO_VCCSENSE
VCCIO_VSSSENSE
2
C131 1U/6.3V_4
C112 1U/6.3V_4
C436 10U/6.3V_4
C135 1U/6.3V_4
Under CPU
C98 10U/6.3V_4
Close CPU
R180 100/F_4
R107 100/F_4
C237 1U/6.3V_4
C114 10U/6.3V_4
+VCCIO
C428 10U/6.3V_4
C134 1U/6.3V_4
+VCCIO
C78 10U/6.3V_4
C437 10U/6.3V_4
1
C85 10U/6.3V_4
C137 10U/6.3V_4
06
Under CPU Close CPU
+VCCSTG +VCCPLL_OC +VCCPLL
C121 1U/6.3V_4
C115 1U/6.3V_4
+VCCSTPLL
C107 1U/6.3V_4
C104 1U/6.3V_4
+3VPCU
IO Thrm Protect
For 65 degree, 1.8v limit, (SW)
+3VPCU
CPU VR Thrm Protect
For 65 degree, 1.8v limit, (SW)
Close A18 Ball
B B
A A
+VCCSTPLL
C435 *1U/6.3V_4
C434 *22U/6.3V_6
5
R372 20K/F_4
For 75 degree, 1.2v limit, (HW)
C415
0.1U/16V_4
1 2
R373 100K_4 NTC
Close to FAN PIPE BOT Side
4
THRM_MOINTOR1 30 THRM_MOINTOR2 30
+1.35VSUS
R384 20K/F_4
For 75 degree, 1.2v limit, (HW)
C419
0.1U/16V_4
1 2
R456 100K_4 NTC
Close to VCORE Choke BOT Side
C212 10U/6.3V_6
C235 10U/6.3V_6
3
C236 10U/6.3V_6
C139 10U/6.3V_6
C277 10U/6.3V_6
Close to CPU
C140 10U/6.3V_6
C215 1U/6.3V_4
C239 1U/6.3V_4
2
C244 1U/6.3V_4
C218 1U/6.3V_4
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
06 -- SKYPAKE 7/20 (POWER-2)
06 -- SKYPAKE 7/20 (POWER-2)
06 -- SKYPAKE 7/20 (POWER-2)
Date: Sheet of
Date: Sheet of
Date: Sheet
1
6 42Wednesday, July 22, 2015
6 42Wednesday, July 22, 2015
6 42Wednesday, July 22, 2015
of
1A
1A
1A
5
+VCCGT 37
der CPU
C490 10U/6.3V_4
C295 10U/6.3V_4
C261 1U/6.3V_4
C485 1U/6.3V_4
C282 10U/6.3V_4
C287 10U/6.3V_4
C484 1U/6.3V_4
C342 1U/6.3V_4
C296 1U/6.3V_4
C500 1U/6.3V_4
C343 10U/6.3V_4
C498 10U/6.3V_4
C252 1U/6.3V_4
C487 1U/6.3V_4
D D
C C
B B
VCCGT_SENSE37 VSSGT_SENSE37
4
C499 10U/6.3V_4
C341 10U/6.3V_4
C269 1U/6.3V_4
C483 1U/6.3V_4
C294 10U/6.3V_4
C283 10U/6.3V_4
C488 1U/6.3V_4
C262 1U/6.3V_4
+VCCGT
AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71
M62 N63 N64 N66 N67 N69
A48 A53 A58 A62 A66
J43 J45 J46 J48 J50 J52 J53 J55 J56 J58 J60 K48 K50 K52 K53 K55 K56 K58 K60 L62 L63 L64 L65 L66 L67 L68 L69 L70 L71
J70 J69
SKL_ULT
U17M
CPU POWER 2 OF 4
VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT
VCCGT_SENSE VSSGT_SENSE
SKL_ULT
REV = 1
31A
PDC
13 OF 20
?
Need apply PN
VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70
VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56
VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63 VCCGTX_BB57 VCCGTX_BB66
VCCGTX_SENSE VSSGTX_SENSE
VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT
3
+VCCGT
Close CPUUn
N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62
AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66
AK62 AL61
C248 47U/6.3VS_8
C482 22U/6.3V_6
C480 22U/6.3V_6
C247 47U/6.3VS_8
C496 22U/6.3V_6
C481 22U/6.3V_6
C246 47U/6.3VS_8
C284 22U/6.3V_6
C340 22U/6.3V_6
C245 47U/6.3VS_8
C260 22U/6.3V_6
C337 22U/6.3V_6
2
C274 22U/6.3V_6
C281 47U/6.3VS_8
C489 22U/6.3V_6
C263 47U/6.3VS_8
C479 22U/6.3V_6
C335 22U/6.3V_6
1
07
A A
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
07 -- SKYPAKE 8/20 (POWER-3)
07 -- SKYPAKE 8/20 (POWER-3)
07 -- SKYPAKE 8/20 (POWER-3)
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
1A
1A
1A
7 42Wednesday, July 22, 2015
7 42Wednesday, July 22, 2015
7 42Wednesday, July 22, 2015
5
4
3
2
1
08
U17R
?
D D
C C
B B
SKL_ULT
GND 3 OF 3
F8
VSS
G10
VSS
G22
VSS
G43
VSS
G45
VSS
G48
VSS
G5
VSS
G52
VSS
G55
VSS
G58
VSS
G6
VSS
G60
VSS
G63
VSS
G66
VSS
H15
VSS
H18
VSS
H71
VSS
J11
VSS
J13
VSS
J25
VSS
J28
VSS
J32
VSS
J35
VSS
J38
VSS
J42
VSS
J8
VSS
K16
VSS
K18
VSS
K22
VSS
K61
VSS
K63
VSS
K64
VSS
K65
VSS
K66
VSS
K67
VSS
K68
VSS
K70
VSS
K71
VSS
L11
VSS
L16
VSS
L17
VSS
18 OF 20
SKL_ULT
REV = 1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21
?
AA65 AA68 AB15 AB16 AB18 AB21
AD13 AD16 AD19 AD20 AD21 AD62
AE64 AE65 AE66 AE67 AE68 AE69
AF10 AF15 AF17
AF63 AG16 AG17 AG18 AG19 AG20 AG21 AG71 AH13
AH63 AH64 AH67
AJ15
AJ18
AJ20 AK11
AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69
AL28
AL32
AL35
AL38
AL45
AL48
AL52
AL55
AL58
AL64
A67 A70 AA2 AA4
AB8
AD8
AF1
AF2 AF4
AH6
AJ4
AK8 AL2
AL4
U17P
A5
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
SKL_ULT
REV = 1
SKL_ULT
GND 1 OF 3
Need apply PN
?
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
16 OF 20
?
AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58
AT63 AT68 AT71 AU10 AU15 AU20 AU32 AU38
AV68 AV69 AV70
AV71 AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57
AW6 AW60 AW62 AW64 AW66
AW8
AY66
BA10 BA14 BA18
BA23 BA28 BA32 BA36
BA45
U17Q
VSS VSS VSS VSS VSS VSS VSS VSS
AV1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
B10
VSS
B14
VSS
B18
VSS
B22
VSS
B30
VSS
B34
VSS
B39
VSS
B44
VSS
B48
VSS
B53
VSS
B58
VSS
B62
VSS
B66
VSS
B71
VSS
BA1
VSS VSS VSS VSS
BA2
VSS VSS VSS VSS VSS
F68
VSS VSS
SKL_ULT
REV = 1
SKL_ULT
GND 2 OF 3
?
17 OF 20
Need apply PNNeed apply PN
BA49
VSS
BA53
VSS
BA57
VSS
BA6
VSS
BA62
VSS
BA66
VSS
BA71
VSS
BB18
VSS
BB26
VSS
BB30
VSS
BB34
VSS
BB38
VSS
BB43
VSS
BB55
VSS
BB6
VSS
BB60
VSS
BB64
VSS
BB67
VSS
BB70
VSS
C1
VSS
C25
VSS
C5
VSS
D10
VSS
D11
VSS
D14
VSS
D18
VSS
D22
VSS
D25
VSS
D26
VSS
D30
VSS
D34
VSS
D39
VSS
D44
VSS
D45
VSS
D47
VSS
D48
VSS
D53
VSS
D58
VSS
D6
VSS
D62
VSS
D66
VSS
D69
VSS
E11
VSS
E15
VSS
E18
VSS
E21
VSS
E46
VSS
E50
VSS
E53
VSS
E56
VSS
E6
VSS
E65
VSS
E71
VSS
F1
VSS
F13
VSS
F2
VSS
F22
VSS
F23
VSS
F27
VSS
F28
VSS
F32
VSS
F33
VSS
F35
VSS
F37
VSS
F38
VSS
F4
VSS
F40
VSS
F42
VSS
BA41
VSS
PDC
?
A A
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
8 -- SKYPAKE 9/20 (GND-1)
8 -- SKYPAKE 9/20 (GND-1)
8 -- SKYPAKE 9/20 (GND-1)
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
1A
1A
1A
8 42Wednesday, July 22, 2015
8 42Wednesday, July 22, 2015
8 42Wednesday, July 22, 2015
5
+1.0V_DEEP_SUS 13,15,16,35,36
+VCCSTPLL 2,4,5,6,36,37
CFG0-19 need Reserve TP
D D
+1.0V_DEEP_SUS
C C
B B
4
CFG016 CFG116 CFG216 CFG316 CFG416 CFG516 CFG616 CFG716 CFG816 CFG916 CFG1016 CFG1116 CFG1216 CFG1316 CFG1416 CFG1516
CFG1616 CFG1716
CFG1816 CFG1916
R264 49.9/F_4 R121 *1K_4
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15
CFG16 CFG17
CFG18 CFG19
CFG_RCOMP
AL25 AL27
BA70 BA68
E68 B67 D65 D67 E70 C68 D68 C67 F71
G69
F70
G68
H70
G71
H69
G70
E63 F63
E66 F66
E60
E8
AY2 AY1
D1 D3
K46 K45
C71 B70
F60
A52
J71 J68
F65
G65
F61 E61
U17S
CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]
CFG[16] CFG[17]
CFG[18] CFG[19]
CFG_RCOMP ITP_PMODE RSVD_AY2
RSVD_AY1 RSVD_D1
RSVD_D3 RSVD_K46
RSVD_K45 RSVD_AL25
RSVD_AL27 RSVD_C71
RSVD_B70 RSVD_F60 RSVD_A52 RSVD_TP_BA70
RSVD_TP_BA68 RSVD_J71
RSVD_J68 VSS_F65
VSS_G65 RSVD_F61
RSVD_E61
SKL_ULT
REV = 1
SKL_ULT
RESERVED SIGNALS-1
PDC
?
19 OF 20
3
Need apply PN
RSVD_TP_BB68 RSVD_TP_BB69
RSVD_TP_AK13 RSVD_TP_AK12
RSVD_BB2 RSVD_BA3
RSVD_D5 RSVD_D4 RSVD_B2 RSVD_C2
RSVD_B3 RSVD_A3
RSVD_AW1
RSVD_E1 RSVD_E2
RSVD_BA4 RSVD_BB4
RSVD_A4 RSVD_C4
RSVD_A69 RSVD_B69
RSVD_AY3 RSVD_D71
RSVD_C70 RSVD_C54
RSVD_D54
VSS_AY71
RSVD_TP_AW71 RSVD_TP_AW70
PROC_SELECT#
2
BB68 BB69
AK13 AK12
BB2 BA3
AU5
TP5
AT5
TP6
D5 D4 B2 C2
B3 A3
AW1 E1
E2 BA4
BB4 A4
C4 BB5
TP4
0612 Change R379 from 0 ohm to short pad
A69 B69
AY3
R379 *0_4/S
D71 C70
C54 D54
0612 Change R462 from 0 ohm to short pad
AY4
TP1
BB3
TP2
AY71
R462 *0_4/S
AR56
ZVM#
AW71 AW70
AP56
MSM#
C64
R465 *100K_4
?
Cannonlake-U use, SKL-U un-install.
+1.8V_DEEP_SUS
R27 *0_6
Close to CPU
Connect +1.8V_DEEP_SUS and add 1uF Cap in CPU Ball U11 and U12 for Cannonlake-U use, SKL-U un-install.
+VCCSTPLL
C13 *1U/6.3V_4
AW69 AW68
AU56
AW48
C7 U12 U11 H11
U17T
RSVD_AW69 RSVD_AW68 RSVD_AU56 RSVD_AW48 RSVD_C7 RSVD_U12 RSVD_U11 RSVD_H11
SKL_ULT
REV = 1
SKL_ULT
?
SPARE
20 OF 20
Need apply PN
F6
RSVD_F6
E3
RSVD_E3
C11
RSVD_C11
B11
RSVD_B11
A11
RSVD_A11
D12
RSVD_D12
C12
RSVD_C12
F52
RSVD_F52
?
1
09
Processor Strapping
CFG3 (Physcial Debug Enable) DFX Privacy
CFG4
(DP Presence Strap)
A A
5
The CFG signals have a default value of '1' if not terminated on the board.
1 0
Disable: Enable: Set DFX Enable in DFX interface MSR
Disable; No physical DP attached to eDP
4
Enable; An ext DP device is connected to eDP
3
CFG3
CFG4
Circuit
R466 *1K_4
R468 1K_4
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Re
Custom
Custom
Custom
9 -- SKYPAKE 12/20 (RSV-1)
9 -- SKYPAKE 12/20 (RSV-1)
9 -- SKYPAKE 12/20 (RSV-1)
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
1
v
1A
1A
1A
9 42Wednesday, July 22, 2015
9 42Wednesday, July 22, 2015
9 42Wednesday, July 22, 2015
5
+3V_DEEP_SUS 4,11,12,14,15,16,18 +3V 2,4,11,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,29,30,31,37,39 +3VS5 4,15,16,28,29,30,33,35,36,39
D D
C C
4
3
2
1
10
?
U17E
PCH_SPI1_CLK PCH_SPI1_SO PCH_SPI1_SI PCH_SPI_IO2 PCH_SPI_IO3 PCH_SPI_CS0#
SPI1_CLK
TP83
SIO_EXT_SMI#30 PCI_SERR#30
EC_RCIN#30
SIO_EXT_SMI# PCI_SERR# SPI1_IO2 SPI1_IO3
TP87
SPI1_CS#
TP64 TP57
AW13
SERIRQ26,30
AY11
AV2
SPI0_CLK
AW3
SPI0_MISO
AV3
SPI0_MOSI
AW2
SPI0_IO2
AU4
SPI0_IO3
AU3
SPI0_CS0#
AU2
SPI0_CS1#
AU1
SPI0_CS2#
M2
GPP_D1/SPI1_CLK
M3
GPP_D2/SPI1_MISO
J4
GPP_D3/SPI1_MOSI
V1
GPP_D21/SPI1_IO2
V2
GPP_D22/SPI1_IO3
M1
GPP_D0/SPI1_CS#
G3
CL_CLK
G2
CL_DATA
G1
CL_RST#
GPP_A0/RCIN# GPP_A6/SERIRQ
REV = 1
SPI - FLASH
SPI - TOUCH
C LINK
SKL_ULT
SKL_ULT
LPC
PDC
5 OF 20
Need apply PN
SMBUS, SMLINK
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
?
R7 R8 R10
R9 W2 W1
W3 V3 AM7
AY13 BA13 BB13 AY12 BA12 BA11
AW9 AY9 AW11
SMB_PCH_CLK SMB_PCH_DAT SML0ALERT#
SMB_ME0_CLK SMB_ME0_DAT SML1ALERT#
SMB_ME1_CLK SMB_ME1_DAT GPP_B23
CLK_PCI_EC_R CLK_PCI_LPC_R CLKRUN#
SML0ALERT# 11
SML1ALERT# 11
TP14
LAD0 26,28,30 LAD1 26,28,30 LAD2 26,28,30 LAD3 26,28,30 LFRAME# 26,28,30
R111 22/F_4 R120 22/F_4
CLKRUN# 30
R115 *22/F_4
EC6 18P/50V_4
EC8 18P/50V_4
EC7 *18P/50V_4
CLK_24M_KBC 30 CLK_24M_DEBUG 28
EMI(near PCH)
CLK_PCI_TPM 26
EMI(near PCH)
GPIO Pull UP
+3V
SERIRQ CLKRUN# SIO_EXT_SMI# EC_RCIN# PCI_SERR#
B B
R44 10K_4 R43 8.2K/F_4 R401 10K_4 R45 10K_4 R406 10K_4
ACC_LED#12,26
SMB_PCH_CLK SMB_PCH_DAT SMB_ME0_CLK SMB_ME0_DAT SMB_ME1_CLK SMB_ME1_DAT
R14 2.2K_4 R13 2.2K_4 R38 499/F_4 R396 499/F_4 R394 1K_4 R393 1K_4
R405 10K_4
SMBus/Pull-up(CLG)
Q24
MBCLK218,30
MBDATA218,30
A A
R24 4.7K_4
+3V
SMB_RUN_DAT16,17,18,27
R16 4.7K_4
+3V
SMB_RUN_CLK16,17,18,27
5
4 3
1
*2N7002DW
Q1
4 3
1
2N7002KDW
+3V
5
SMB_ME1_CLK
2
SMB_ME1_DAT
6
+3V
5
SMB_PCH_DAT
2
SMB_PCH_CLK
6
CPU heat pipe local thermal sensor DDR thermal sensor EC
Touch Pad XDP DDR3-L
4
+3V_DEEP_SUS
PCH SPI ROM(CLG)
Vender P/N EON Winbond
G
igaDevice Socket
3
Size
8MB 8MB
U14 &U15 footprint
Need place to TOP
TP5 TP4 TP2 TP1 TP3 TP8
C2 1U/10V_4
R1/R2/R3/R4/R5/R7 close to U15 pin
AKE3EZN0Q01 (EN25QH64-104HIP)8MB AKE3EFP0N07 (W25Q64FVSSIQ) AKE3EGN0Q01 (GD25B64BSIGR) DFHS08FS023
PCH_SPI_CS0#_R PCH_SPI1_CLK_R PCH_SPI1_SI_R PCH_SPI1_SO_R BIOS_WP# HOLD#
PCH_SPI_CS0#
R2 15/F_4
PCH_SPI1_CLK
R4 15/F_4 R3 15/F_4 R1 15/F_4
+3VSPI
R6 1K/F_4
PCH_SPI_IO2
R5 15/F_4
PCH_SPI_CS0#_R30 PCH_SPI1_CLK_R30 PCH_SPI1_SI_R30 PCH_SPI1_SO_R30
󴣊󵄖󳓓
PCH SPI ROM(CLG)
PCH_SPI_CS0#_R PCH_SPI1_CLK_R PCH_SPI1_SI_RPCH_SPI1_SI PCH_SPI1_SO_RPCH_SPI1_SO
C1 22P/50V_4
BIOS_WP#
2
U15
1
CE#
6
SCK
5
SI
2
SO
3
WP#
GD25B64BSIGR
AKE3EFP0N07
4M SPI ROM Socket
PCH_SPI_CS0#_R PCH_SPI1_CLK_R PCH_SPI1_SI_R PCH_SPI1_SO_R
BIOS_WP#
0612 Change R10 from 0 ohm to short pad
R15 *0_4
+3VS5
8
7
HOLD#
4
PCH_SPI_IO3
R10 *0_4/S
+3VSPI
R9 1K/F_4 R7 15/F_4
+3V_DEEP_SUS
VDD
HOLD#
VSS
+3VSPI
U14
1
CE#
6
SCK
5
SI
2
SO
3
WP#
*A25LQ32AM-F/Q
DFHS08FS023
91960-0084L-8P-SOCKET
0.1U/16V_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet
8
VDD
7
HOLD#
HOLD#
4
VSS
C4
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
10 -- SKYPAKE 14/20(SPI/LPC/SMBUS)
10 -- SKYPAKE 14/20(SPI/LPC/SMBUS)
10 -- SKYPAKE 14/20(SPI/LPC/SMBUS)
1
10 42Wednesday, July 22, 2015
10 42Wednesday, July 22, 2015
10 42Wednesday, July 22, 2015
of
1A
1A
1A
5
4
3
2
1
+3V_DEEP_SUS 4,10,12,14,15,16,18 +3V 2,4,10,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,29,30,31,37,39
D D
DESIGN NOTE: WEAK PULL UP RESISTOR PRESENT ON THIS NET
ACZ_SPKR14,22
C C
ACZ_SPKR
SML0ALERT#
R381 *20K/F_4
+3V_DEEP_SUS
R53 1K_4
R37 *20K/F_4
Functional Strap Definitions
TOP SWAP OVERRIDE HIGH - TOP SWAP ENABLE LOW-DISABLED HIGH: LPC SELECTED FOR SYSTEM FLASH WEAK INTERNAL PD
No Boot: The signal has a weak internal pull-down. 0 = Disable Intel ME Crypto Transport Layer Security (TLS) cipher suite (no confidentiality). 1 = Enable Intel ME Crypto Transport Layer Security (TLS) cipher suite (with confidentiality). Must be pulled up to support Intel AMT with TLS and Intel SBA (Small Business Advantage) with TLS.
ACZ_SDOUT14
GPIO33_EC30
GPP_B1814SML0ALERT#10
ACZ_SDOUT
R47 1K_4
GPP_B18
+3V_DEEP_SUS
R423 *4.7K_4
ACZ_SDOUT
+3V
R33 *4.7K_4
R26 10K_4
No Boot: The signal has a weak internal pull-down. 0 = Enable security measures defined in the Flash Descriptor. 1 = Disable Flash Descriptor Security (override). This strap should only be asserted high using external pull-up in manufacturing/debug environments ONLY. This function is useful when running ITP/XDP.
No Boot: The signal has a weak internal pull-down. 0 = Disable No Reboot mode. 1 = Enable No Reboot mode (PCH will disable the TCO Timer system reboot feature). This function is useful when running ITP/XDP.
11
+3V_DEEP_SUS
B B
R395
GSPI1_MOSI14
A A
5
GSPI1_MOSI
No Boot: The signal has a weak internal pull-down. This field determines the destination of accesses to the BIOS memory range. Also controllable using Boot BIOS
R54
Destination bit (Chipset Configuration Registers: Offset
*20K/F_4
3410h:Bit 10). This strap is used in conjunction with Boot BIOS Destination Selection 0 strap. Bit 10 Boot BIOS Destination 0 SPI 1 LPC
4
SML1ALERT#10
3
SML1ALERT#
*10K_4
R407 20K/F_4
No Boot: The signal has a weak internal pull-down. 0 = LPC Is selected for EC. 1 = eSPI Is selected for EC.
2
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
11 -- SKYPAKE 15/20(HDA)
11 -- SKYPAKE 15/20(HDA)
11 -- SKYPAKE 15/20(HDA)
Date: Sheet of
Date: Sheet of
Date: Sheet
1
11 42Wednesday, July 22, 2015
11 42Wednesday, July 22, 2015
11 42Wednesday, July 22, 2015
of
1A
1A
1A
5
+3V 2,4,10,11,13,14,15,16,17,18,20,21,22,23,24,25,26,27,29,30,31,37,39 +3V_DEEP_SUS 4,10,11,14,15,16,18
H13 G13 B17
BB11
A17 G11
F11 D16 C16
H16 G16 D17 C17
G15 F15 B19 A19
F16 E16 C19 D19
G18 F18 D20 C20
F20 E20 B21 A21
G21 F21 D21 C21
E22 E23 B23 A23
F25 E25 D23 C23
F5 E5
D56 D61
E28 E27 D24 C24 E30 F30 A25 B25
D D
PCIE_RXN5_CARD31 PCIE_RXP5_CARD31
Cardreader
LAN
W
HDD
C C
LAN
B B
PCIE_TXN5_CARD31 PCIE_TXP5_CARD31
PCIE_RXN6_WLAN28 PCIE_RXP6_WLAN28 PCIE_TXN6_WLAN28 PCIE_TXP6_WLAN28
SATA_RXN026 SATA_RXP026 SATA_TXN026 SATA_TXP026
PCIE_RXN9_LAN24 PCIE_RXP9_LAN24 PCIE_TXN9_LAN24 PCIE_TXP9_LAN24
XDP_PRDY#_CPU16 XDP_PREQ#_CPU16
+3V_DEEP_SUS
C440 0.1U/16V_4 C438 0.1U/16V_4
C443 0.1U/16V_4 C441 0.1U/16V_4
C444 0.1U/16V_4 C442 0.1U/16V_4
R80 10K_4
PCIE_TXN5_CARD_C PCIE_TXP5_CARD_C
PCIE_TXN6_WLAN_C PCIE_TXP6_WLAN_C
PCIE_TXN9_LAN_C PCIE_TXP9_LAN_C
R404 100/F_4 R413 *10K_4
PIRQA#
PCI-E Port Mapping Table
PCI-E Port
A A
5
4
U17H
PCIE/USB3/SATA
PCIE1_RXN/USB3_5_RXN PCIE1_RXP/USB3_5_RXP PCIE1_TXN/USB3_5_TXN PCIE1_TXP/USB3_5_TXP
PCIE2_RXN/USB3_6_RXN PCIE2_RXP/USB3_6_RXP PCIE2_TXN/USB3_6_TXN PCIE2_TXP/USB3_6_TXP
PCIE3_RXN PCIE3_RXP PCIE3_TXN PCIE3_TXP
PCIE4_RXN PCIE4_RXP PCIE4_TXN PCIE4_TXP
PCIE5_RXN PCIE5_RXP PCIE5_TXN PCIE5_TXP
PCIE6_RXN PCIE6_RXP PCIE6_TXN PCIE6_TXP
PCIE7_RXN/SATA0_RXN PCIE7_RXP/SATA0_RXP PCIE7_TXN/SATA0_TXN PCIE7_TXP/SATA0_TXP
PCIE8_RXN/SATA1A_RXN PCIE8_RXP/SATA1A_RXP PCIE8_TXN/SATA1A_TXN PCIE8_TXP/SATA1A_TXP
PCIE9_RXN PCIE9_RXP PCIE9_TXN PCIE9_TXP
PCIE10_RXN PCIE10_RXP PCIE10_TXN PCIE10_TXP
PCIE_RCOMPN PCIE_RCOMPP
PROC_PRDY# PROC_PREQ# GPP_A7/PIRQA#
PCIE11_RXN/SATA1B_RXN PCIE11_RXP/SATA1B_RXP PCIE11_TXN/SATA1B_TXN PCIE11_TXP/SATA1B_TXP PCIE12_RXN/SATA2_RXN PCIE12_RXP/SATA2_RXP PCIE12_TXN/SATA2_TXN PCIE12_TXP/SATA2_TXP
SKL_ULT
REV = 1
Function
Port1
Port2
Port3
Port4
Port5
Port6
Port7
Port8
Port9
Port10
Un-used
Un-used
Un-used
Un-used
CardReader
WLAN
HDD
Un-used
LAN
Un-used
4
?
SKL_ULT
PDC
8 OF 20
CLK RQ Port
Port0
Port1
Port2
Port3
Port4
Port5
Need apply PN
SSIC / USB3
USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
USB2
USB2_VBUSSENSE
GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2
GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2
GPP_E8/SATALED#
Function
Un-used
CardReader
WLAN
LAN
Un-used
Un-used
USB3_1_RXN USB3_1_RXP
USB3_1_TXN USB3_1_TXP
USB3_4_RXN USB3_4_RXP
USB3_4_TXN USB3_4_TXP
USB2N_1 USB2P_1
USB2N_2 USB2P_2
USB2N_3 USB2P_3
USB2N_4 USB2P_4
USB2N_5 USB2P_5
USB2N_6 USB2P_6
USB2N_7 USB2P_7
USB2N_8 USB2P_8
USB2N_9 USB2P_9
USB2N_10 USB2P_10
USB2_COMP
USB2_ID
?
3
H8 G8 C13 D13
J6 H6 B13 A13
J10 H10 B15 A15
E10 F10 C15 D15
AB9 AB10
AD6 AD7
AH3 AJ3
AD9 AD10
AJ1 AJ2
AF6 AF7
AH1 AH2
AF8 AF9
AG1 AG2
AH7 AH8
AB6 AG3 AG4
A9 C9 D9 B9
J1 J2 J3
H2 H3 G4
H1
USB30_RX1­USB30_RX1+ USB30_TX1­USB30_TX1+
USB30_RX3­USB30_RX3+ USB30_TX3­USB30_TX3+
USB2_COMP
R48 113/F_4
DGPU_HOLD_RST# GPU_EVENT# DGPU_PWR_EN DGPU_PWROK
GC6_FB_EN DEVSLP1
OCP_OC#
ODD_PRSNT#_R SATAGP2
USBP1­USBP1+
USBP2­USBP2+
USBP3­USBP3+
USBP4­USBP4+
USBP6­USBP6+
USBP7­USBP7+
USBP8­USBP8+
TP96 TP101 TP26 TP99
TP53 TP78 TP84
TP52 TP68
USB30_RX1- 25 USB30_RX1+ 25 USB30_TX1- 25 USB30_TX1+ 25
USB30_RX3- 25 USB30_RX3+ 25 USB30_TX3- 25 USB30_TX3+ 25
USBP1- 25 USBP1+ 25
USBP2- 25 USBP2+ 25
USBP3- 20 USBP3+ 20
USBP4- 29 USBP4+ 29
USBP6- 23 USBP6+ 23
USBP7- 28 USBP7+ 28
USBP8- 29 USBP8+ 29
ACC_LED# 10,26
R402 *0_4/S
USB3.0 Port Mapping Table
USB3.0 Function PORT-1 PORT-2 PORT-3
USB3.0 MB-1
NC
USB3.0 MB-2
PORT-4 NC
3
2
USB3.0 (M/B-1)
USB3.0 (M/B-2)
Combo USB3.0 MB-1 Combo USB3.0 MB-2 Camera Sensor HUB
USB2.0 Small Board WLAN Touch Screen
PLACE 'R10387' WITHIN 500 MILS FROM USB2_COMP PIN WITH TRACE IMPEDANCE LESS THAN 0.5 OHMS
SATA_LED#SATA_LED#_R
SATA_LED# 26
2
SATA_LED# GC6_FB_EN ODD_PRSNT#_R
DGPU_HOLD_RST# GPU_EVENT# DGPU_PWR_EN DGPU_PWROK
R392 10K_4 R386 *10K_4 R388 *10K_4
R412 *10K_4 R114 *10K_4
R414 *10K_4
USB2.0 Port Mapping Table
USB2.0 Function PORT-1 PORT-2 PORT-3 PORT-4 PORT-5 PORT-6 PORT-7 PORT-8 PORT-9 PORT-10
Cobime USB3.0 MB-1 Cobime USB3.0 MB-2 Camera Sensor HUB
NC
USB2.0 Small Board WLAN Touch Screen
NC NC
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
12 -- SKYPAKE 16/20 (PCIE/USB)
12 -- SKYPAKE 16/20 (PCIE/USB)
12 -- SKYPAKE 16/20 (PCIE/USB)
Date: Sheet of
Date: Sheet of
Date: Sheet
1
12
+3V
+3V
1A
1A
1A
12 42Wednesday, July 22, 2015
12 42Wednesday, July 22, 2015
12 42Wednesday, July 22, 2015
1
of
5
4
3
2
1
+3V_RTC_2 4,15 +3V_RTC 4,15,27,28,32 +3V 2,4,10,11,12,14,15,16,17,18,20,21,22,23,24,25,26,27,29,30,31,37,39 +1.0V_DEEP_SUS 9,15,16,35,36
?
10 OF 20
?
PDC
9 OF 20
Need apply PN
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XCLK_BIASREF
TBT
Need apply PN
CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
?
XTAL24_IN
XTAL24_OUT
RTCX1 RTCX2
SRTCRST#
RTCRST#
C37 D37 C32 D32 C29 D29 B26 A26
E13 B7
AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1
AM2 AM3 AP4
AT1
?
CK_XDP_N_R
F43
CK_XDP_P_R
E43
PCH_SUSCLK
BA17
XTAL24_IN
E37
XTAL24_OUT
E35
XCLK_BIASREF
E42
RTC_X1
AM18
RTC_X2
AM20
SRTC_RST#PCIE_CLKREQ_VGA#
AN18
RTC_RST#
AM16
GPP_D4
GPP_F13 GPP_F14 GPP_F15 GPP_F16 GPP_F17 GPP_F18 GPP_F19 GPP_F20
EMMC_RCLK EMMC_CLK EMMC_CMD
EMMC_RCOMP
TP41
R444 2.7K/F_4 R445 *60.4/F_4
TP60
R136 100/F_4
TP95
TP77 TP67 TP86 TP75 TP66 TP80 TP85 TP59
TP63 TP73 TP70
R380 200/F_4
RP5002 install for XDP
RP1
2
1
4
3
*0_4P2R_4
+1.0V_DEEP_SUS
RTC_RST# 16
CK_XDP_N 16 CK_XDP_P 16
Co-lay 60ohm 1% to GND for Cannonlake use
CLK_REQ/Strap Pin(CLG)
PCIE_CLKREQ_VGA# PCIE_CLKREQ_WLAN# PCIE_CLKREQ_LAN# PCIE_CLKREQ_CR# PCIE_CLKREQ5# PCIE_CLKREQ0#
R73 10K_4 R93 10K_4 R104 10K_4 R92 10K_4 R82 10K_4 R96 10K_4
U17J
D42
CLKOUT_PCIE_N0
C42
D D
Cardreader
W
LAN
LAN
C C
B B
CLK_PCIE_CRN31 CLK_PCIE_CRP31 PCIE_CLKREQ_CR#31
CLK_PCIE_WLANN28 CLK_PCIE_WLANP28 PCIE_CLKREQ_WLAN#28
CLK_PCIE_LANN24 CLK_PCIE_LANP24 PCIE_CLKREQ_LAN#24
PCIE_CLKREQ0# CLK_PCIE_CRN
CLK_PCIE_CRP PCIE_CLKREQ_CR#
CLK_PCIE_WLANN CLK_PCIE_WLANP PCIE_CLKREQ_WLAN#
CLK_PCIE_LANN CLK_PCIE_LANP PCIE_CLKREQ_LAN#
PCIE_CLKREQ5#
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
SKL_ULT
REV = 1
A36 B36 C38 D38 C36 D36 A38 B38
C31 D31 C33 D33 A31 B31 A33 B33
A29 B29 C28 D28 A27 B27 C27 D27
U17I
CSI-2
CSI2_DN0 CSI2_DP0 CSI2_DN1 CSI2_DP1 CSI2_DN2 CSI2_DP2 CSI2_DN3 CSI2_DP3
CSI2_DN4 CSI2_DP4 CSI2_DN5 CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7
CSI2_DN8 CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11
SKL_ULT
SKL_ULT
CLOCK SIGNALS
SKL_ULT
REV = 1
13
+3V
RTC Clock 32.768KHz
C421 12P/50V_4
Y2
32.768KHZ
C422 12P/50V_4
A A
RTC_X1
23
R403 10M_4
4 1
RTC_X2
5
RTC Circuitry(RTC)
30mils
+3V_RTC+3V_RTC_2
R292
R291
*0_4
0_4
R278
+3V_RTC_0
R251
+3V_RTC_0 SRTC_RST#
1K_4
12
CN20 RTC SOCKET
4
RTC Power trace width 20mils.
2 1
+3VPCU
+3V_RTC_1
D7 MEK500V-40
2 1
D6 MEK500V-40
C311 1U/6.3V_4
20K/F_4
R267 20K/F_4
J1
1 2
C310 1U/6.3V_4
C306 1U/6.3V_4
R277 *0_6
3
*SOLDERJUMPER-2
RTC_RST#
SRTC_RST#RTC_RST#
RTC_RST#
3
EC_RTC_RST
2
Q16
2N7002K
1
R298 10K_4
EC_RTC_RST 30
External Crystal and Green Clock
The 24 MHz (50 Ohm ESR) XTAL used for Skylake-U
eeds to be replaced by 38.4 MHz (30 Ohm ESR)
n XTAL for Cannonlake-U.
C460 33P/50V_4
1
XTAL24_IN XTAL24_OUT
0701 Delete TP102, TP103 for Layout placement request
2
2
R442
24MHZ +-30PPM
1M_4
Y3
4
3
C453 33P/50V_4
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
PROJECT : Y62P/Y63P
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
13 -- SKYPAKE 17/20 (CLK)
13 -- SKYPAKE 17/20 (CLK)
13 -- SKYPAKE 17/20 (CLK)
Date: Sheet of
Date: Sheet of
Date: Sheet
1
1A
1A
1A
13 42Wednesday, July 22, 2015
13 42Wednesday, July 22, 2015
13 42Wednesday, July 22, 2015
of
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