HP DV9260 Schematics
1
2
3
4
5
6
7
8
04-- 0402 footprint
PCB STACK UP
LAYER 1 : TOP
LAYER 2 : SGND1
AA
BB
CC
DD
LAYER 3 : IN1
LAYER 4 : IN2
LAYER 5 : VCC
LAYER 6 : IN3
LAYER 7 : SGND2
LAYER 8 : BOT
TV_OUT
Cable
Docking
VGA
RJ-45
CIR/Pwr btn
SPDIF Out
Stereo MIC
Headphone Jack
USB Port
PAG 38
VOL Cntr
SYSTEM CHARGER(MAX8724)
PAG 41
SYSTEM POWER MAX8778
PAG 42
DDR II SMDDR_VTERM
1.8V/1.8VSUS(TPS51116REGR)
VCCP +1.5V AND GMCH
1.05V(MAX8717)
PAG 46
PAG 43
VGACORE(1.025V)MAX1992
PAG 45
CPU CORE MAX8771
PAG 44
1
06-- 0603 footprint
08-- 0805 footprint
12-- 1206 footprint
F-- 1% tolerance
DDRII-SODIMM1
PAG 13,14
DDRII-SODIMM2
PAG 13,14
Option for 17" only
SATA - HDD
SATA - HDD
PATA-
2
PAG 35
PAG 32
CD-ROM
PAG 32
Keyboard
Touch Pad
CIR
Capacitive Sense
SW
AT5 BLOCK DIAGRAM
DDRII 533,667 MHz
DDRII 533,667 MHz
SATA2
SATA0 150MB
(66/100/133)
PATA
PAG 36
PAG 36
PAG 36
3
FAN
CPU
Merom
478P (uPGA)/35W
NORTH BRIDGE
Crestline
PAG
7,8,9,10,11,12
DMI LINK
SOUTH BRIDGE
ICH-8M
PAG 21,22,23,24
LPC
ENE KBC
KB3920 Bx
KB3926 Bx
PAG 37,48
X-Bus
Flash
PAG 37PAG 38
4
PAG 3,4
Two-element
microphone
PAG 29
Audio Jacks
(Phone/ MIC)
PAG 29
SPI
PAG 37
CPU THERMAL
SENSOR
PAG 5
CLK_CPU_BCLK,CLK_CPU_BCLK#
CLK_MCH_BCLK,CLK_MCH_BCLK#
DREFCLK,DREFCLK#
DREFSSCLK,DREFSSCLK#
PCI-Express 16X
TV_OUT
CRT_OUT
LVDS(2 Channel)
USB2.0
0,1,2
BluetoothUSB2.0 I/O Ports
PAG 35
X3
PCI BUS / 33MHz
PCI-E
Azalia
Realtek
ALC 268
PAG 29
AUDIO
Amplifier
MDC DAA
SI3080
PAG 31PAG 30
Jack to
Speaker
MODEM RJ 11
PAG 33PAG 30
5
NVDIA G3-64 for 15.4"
NVDIA G3-128 for 17"
820p FCBGA
CRT/S-VIDEO
Panel Connector
15" / 17"
PAG 32
Mini PCI-E
Card
PCI Express
Mini Card
(Wireless
LAN/WAN)
PAG 39PAG 33,34PAG 35
SIM CARD
PCI ROUTING
TABLE
6
PAG
15,16,17,18,19,20
PAG 25
PAG 26
Camera
X1
LAN
Realtek
PCIE-LAN
RTL8101E/8111B
(10/100/GagaLAN)
NB5/RD1/HW2
354,6,7
PAG 32
RJ45
PAG 33PAG 32
IDSEL
INTERUPTDEVICE
AD25RICOH832REQ0# / GNT0#
INTE#,INTF#
AD22REQ1# / GNT1#
SizeDocument NumberRev
Custom
Date:Sheet of
7
14.318MHz
CLOCK GEN
ICS9LPRS355AGLFT
64pinsTSSOP
PAG 2
Option for 17" only
HDMI CON
PAG 26
NBSRCCLK, NBSRCCLK#
Mini PCI-E Card x1
Express Card x1
Cable Docking x1
Express
Card
RICOH
RICOH 832
(NEW CARD)
PAG 27,28
IEEE1394
CONN
Memory
CardReader
MINI PCI for debugINTC#,INTD#
PROJECT : AT5
Quanta Computer Inc.
BLOCK DIAGRAM
148Monday, March 19, 2007
8
01
PAG 27PAG 28
1A
1
+3V
L42
1 2
BLM21PG600SN1D/08
120 ohms@100Mhz
AA
L43
1 2
BLM21PG600SN1D/08
12
C400
22U/10V/12
SI-2 change
12
C447
22U/10V/12
12
C464
.1U/10V/04
12
C445
.1U/10V/04
12
VDDCPU
2
C436
.1U/10V/04
12
C441
.1U/10V/04
12
C446
.1U/10V/04
3
+CK_VDD_MAIN
12
C429
.1U/10V/04
4
CG_XIN
12
C431
27P/50V/04
Y1
1 2
14.318MHZ
5
CG_XOUT
12
C430
27P/50V/04
SI-1 modify
( remove
R256 --not
need )
14.318MHz
6
CLK_3GPLLREQ#
NEW-CARD_CLK_REQ#
R32110K/04
R32210K/04
internal have
already build-in
33ohm damping
resisteor
7
+3V
12
12
8
02
L44
1 2
BLM21PG600SN1D/08
120 ohms@100Mhz
+3V
BB
CC
R259
10K/04
1 2
PCLK_MINI_LPC
R269
*4.7K/04
0=overclocking
of CPU and
SRC Allowed
1 = overclocking
of CPU and SRC
not Allowed
+3V
R287
*10K/04
1 2
FCTSEL1
R296
10K/04
1 2
0=UMA
1 = External VGA
+3V
12
Enable ITP
1 2
1 2
*10K/04
R283
ITP_EN
10K/04
R825
1
DD
12
PDAT_SMB23,35
PCLK_SMB23,35
C456
.1U/10V/04
C951*33P/50V/04
C416*33P/50V/04
C421*33P/50V/04
C44233P/50V/04
C438*33P/50V/04
C432*33P/50V/04
C479
22U/10V/12
for EMI
CPU Clock select
+1.05V
+1.05V
+1.05V
12
C473
.1U/10V/04
+3V
Q16
2
2N7002E
3
+3V
Q17
2
2N7002E
3
CPU_BSEL03
CPU_BSEL13 MCH_BSEL17
CPU_BSEL23 MCH_BSEL27
2
12
12
C448
.1U/10V/04
R288
10K/06
1
1
CLKUSB_48
PCLK_LPC_KB3920
PCI_CLK_5C832
PCLK_ICH
PCLK_LPC_DEBUG
14M_ICH
R3090/04
R307*56/04
R3011K/04
R3050/04
R302*0/04
R3031K/04
R2770/04
R264*0/04
R2651K/04
C462
.1U/10V/04
R308
10K/06
CGDAT_SMB
CGCLK_SMB
PV-2 Add
PV-2 Modify
12
C458
.1U/10V/04
+CK_VDD_MAIN2
12
C452
.1U/10V/04
+CK_VDD_MAIN
VDDCPU
+CK_VDD_MAIN2
SI-2 add -- reserve not need
R845*100K/04
CK_PWG23
CLK_BSEL0
CLK_BSEL1
CLK_BSEL2
3
CLK_BSEL1
CGCLK_SMB13,14,39
CGDAT_SMB13,14,39
R3100/04
R2990/04
R2580/04
<FAE>
1K to NB only when
XDP is implement.No
XDP can use 0 ohm
R2984.7K/04
CGCLK_SMB
CGDAT_SMB
CG_XIN
CG_XOUT
4
FSB
U16
16
VDDPLL3
9
VDD48
2
VDDPCI
61
39
55
20
26
45
36
49
48
60
59
56
57
64
63
15
19
11
52
8
58
23
29
42
CK505
VDDREF
VDDSRC
VDDCPU
VDDPLL3I/O
VDDSRCI/O
VDDSRCI/O
VDDSRCI/O
VDDCPU_IO
NC
X1
X2
CK_PWRGD/PD#
FSLB/TEST_MODE
SCLK
SDATA
GND
GND
GND48
GNDCPU
GNDPCI
GNDREF
GNDSRC
GNDSRC
GNDSRC
ICS9LPRS355AGLFT/CY28548ZXCT/RTM875T-606
27MHz_Nonss/SRCCLK1/SE1
FSCFSB
MCH_BSEL07
1330
0
0
0
1
1
00
033
1
1
1
1
1
5
54
CPUCLKT0
53
CPUCLKC0
51
CPUCLKT1
50
CPUCLKC1
SRCCLKT4
SRCCLKC4
PCI_STOP#
CPU_STOP#
SRCCLKT6
SRCCLKC6
SRCCLKT9
SRCCLKC9
SRCCLKT10
SRCCLKC10
PCICLK3
47
4612
13
14
17
18
21
22
24
25
27
28
38
37
41
40
44
43
30
31
34
35
33
32
1
3
4
5
6
7
10
62
CPUT2_ITP/SRCT8
CPUT2_ITP/SRCC8VDD96I/O
DOTT_96/SRCT0
DOTC_96/SRCC0
27Mhz_ss/SRCCLC1/SE2
SRCCLKT2/SATACL
SRCCLKC2/SATACL
SRCCLKT3/CR#_C
SRCCLKC3/CR#_D
SRCCLKT7/CR#_F
SRCCLKC7/CR#_E
SRCCLKT11/CR#_H
SRCCLKC11/CR#_G
PCICLK0/CR#_A
PCICLK1/CR#_B
PCICLK2/TME
PCICLK4/27_SELECT
PCI_F5/ITP_EN
USB_48MHZ/FSLA
FSLC/TST_SL/REF
FSACPUSRCPCI
1100
10
1
0
0
0
0
1
133
166
200
266
333
400
RSVD
100
100
100
100
100
100
100
100
33
33
33
33
33
33
RHCLK_CPU
RHCLK_CPU#
RHCLK_MCH
RHCLK_MCH#
CPU_ITP
CPU_ITP#
R_DOT96
R_DOT96#
R_DREFSSCLK
R_DREFSSCLK#
RSRC_SATA
RSRC_SATA#
R_CLK_PCIE_VGA
R_CLK_PCIE_VGA#
RSRC1_LAN
RSRC1_LAN#
PM_STPPCI#
PM_STPCPU#
RSRC_ICH
RSRC_ICH#
CLK_PCIE_MINI_
CLK_PCIE_MINI_#
RSRC_MCH
RSRC_MCH#
CLK_PCIE_NEW
CLK_PCIE_NEW#
NEW-CARD_CLK_REQ#_R
CLK_3GPLLREQ#_R
R_PCLK_KB3920
R_PCLK_5C832
PCLK_MINI_LPC
PCI_ICH
FCTSEL1
SI-1 modify for
S3 resume issue
6
RP404P2R-S-0
4
3
2
RP414P2R-S-0
RP45*4P2R-S-0
RP644P2R-S-0
RP424P2R-S-0
RP434P2R-S-0
RP464P2R-S-0
RP484P2R-S-0
RP504P2R-S-0
RP494P2R-S-0
RP474P2R-S-0
RP524P2R-S-0
RP514P2R-S-0
ITP_EN
FSA
FSC
1
4
3
2
1
2
1
4
3
4
3
2
1
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
4
3
2
1
4
3
2
1
2
1
4
3
2
1
4
3
R324475/F/03
R323475/F/03
R25033/04
R26033/04
R27933/04
T258
R29333/04
R28533/04
R29233/04
R2954.7K/04
R2574.7K/04
R26633/04
GCLK_SEL = FCTSEL1
FCTSEL1
(PIN13)
0=UMA
1 = External
VGA
PIN20
DOT96T
SRCT0SRCC027Mout-NSS27Mout-SS
NB5/RD1/HW2
CLK_CPU_BCLK3
CLK_CPU_BCLK#3
CLK_MCH_BCLK6
CLK_MCH_BCLK#6
CLK_CPU_ITP3
CLK_CPU_ITP#3
NEW-CARD_CLK_REQ#
CLK_3GPLLREQ#
CLK_BSEL0
CLK_BSEL2
PIN21
CLK_PCIE_MINI_C39
CLK_PCIE_MINI_C#39
DREFCLK7
DREFCLK#7
DREFSSCLK7
DREFSSCLK#7
CLK_PCIE_SATA21
CLK_PCIE_SATA#21
CLK_PCIE_VGA20
CLK_PCIE_VGA#20
CLK_PCIE_LAN33
CLK_PCIE_LAN#33
PM_STPPCI#23
PM_STPCPU#23
CLK_PCIE_ICH22
CLK_PCIE_ICH#22
CLK_PCIE_MINI39
CLK_PCIE_MINI#39
CLK_PCIE_3GPLL7
CLK_PCIE_3GPLL#7
CLK_PCIE_NEW_C35
CLK_PCIE_NEW_C#35
PCLK_LPC_KB392037,48
PCI_CLK_5C83228
PCLK_LPC_DEBUG39
PCLK_MINI40
PCLK_ICH22
PIN24
SRCT1/LCDT_100DOT96C
SI-2 Add
SI-1 modify
( add in
UMA BOM )
NEW-CARD_CLK_REQ#35
CLK_3GPLLREQ#7
form ICS FAE
recommend(defaule is
Hi )
CLKUSB_4823
14M_ICH23
PIN25
SRCT1/LCDT_100
PROJECT : AT5
Quanta Computer Inc.
SizeDocument NumberRev
Custom
CLOCK GENERATOR
Date:Sheet of
7
248Monday, March 19, 2007
8
1A
1
2
3
4
5
6
7
8
C936
+1.05V
12
12
R13
*51/F/04
Layout Note:
Place R8
close ITP.
CLK_CPU_ITP#2
CLK_CPU_ITP2
Layout Note:
Place
R4,R361,R346
& R7 close
to CPU.
1
H_A#[3..16]
H_REQ#[0..4]
H_A#[17..35]
C930
C931
C932
C933
C934
C935
R20
51/04
R190/04
*100P/50V/04
*100P/50V/04
*100P/50V/04
*100P/50V/04
*100P/50V/04
*100P/50V/04
*100P/50V/04
12
12
R18
39/F/04
1 2
R1422.6/F/04
1 2
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
R15
150/04
H_A#[3..16]6
AA
H_ADSTB#06
H_REQ#[0..4]6
H_A#[17..35]6
BB
H_ADSTB#16
H_A20M#21
H_FERR#21
H_IGNNE#21
H_STPCLK#21
H_INTR21
H_NMI21
H_SMI#21
SI-2 modified
resevved for power
noise
CC
ITP_TDI
ITP_TMS
ITP_TCK
ITP_TDO
ITP_TRST#
H_RESET#
ITP_TCK
DD
C925
*100P/50V/04
U31A
J4
A[3]#
L5
A[4]#
L4
A[5]#
K5
A[6]#
M3
A[7]#
N2
A[8]#
J1
A[9]#
N3
A[10]#
P5
A[11]#
P2
A[12]#
L2
A[13]#
P4
A[14]#
P1
A[15]#
R1
A[16]#
M1
ADSTB[0]#
K3
REQ[0]#
H2
REQ[1]#
K2
REQ[2]#
J3
REQ[3]#
L1
REQ[4]#
Y2
A[17]#
U5
A[18]#
R3
A[19]#
W6
A[20]#
U4
A[21]#
Y5
A[22]#
U1
A[23]#
R4
A[24]#
T5
A[25]#
T3
A[26]#
W2
A[27]#
W5
A[28]#
Y4
A[29]#
U2
A[30]#
V4
A[31]#
W3
A[32]#
AA4
A[33]#
AB2
A[34]#
AA3
A[35]#
V1
ADSTB[1]#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
M4
RSVD[01]
N5
RSVD[02]
T2
RSVD[03]
V3
RSVD[04]
B2
RSVD[05]
C3
RSVD[06]
D2
RSVD[07]
D22
RSVD[08]
D3
RSVD[09]
F6
RSVD[10]
Merom Ball-out Rev 1a
ADDR GROUP
0
ADDR GROUP
1
THERMAL
ICH
THERMTRIP#
RESERVED
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROLXDP/ITP SIGNALS
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
DBR#
PROCHOT#
THERMDA
THERMDC
H CLK
BCLK[0]
BCLK[1]
H1
E2
G5
H5
F21
E1
F1
H_IERR#
D20
B3
H4
H_RESET#
C1
F3
F4
G3
G2
G6
E4
ITP_BPM#0
AD4
ITP_BPM#1
AD3
ITP_BPM#2
AD1
ITP_BPM#3
AC4
ITP_BPM#4
AC2
ITP_BPM#5
AC1
ITP_TCK
AC5
ITP_TDI
AA6
TDI
ITP_TDO
AB3
ITP_TMS
AB5
ITP_TRST#
AB6
ITP_DBRESET#
C20
CPU_PROCHOT#CPU_PROCHOT#
D21
H_THERMDA
A24
H_THERMDC
B25
PM_THRMTRIP#
C7
A22
A21
SI-2 modified --remove R72
SI-1 modified add ITP connector
Populate ITP700Flex for bringup
R2227/F/04
R21649/F/04
JITP1
1
2
5
7
3
12
11
8
9
10
14
16
18
20
22
2
TDI
TMS
TCK
TDO
TRST#
RESET#
FBO
BCLKN
BCLKP
GND0
GND1
GND2
GND3
GND4
GND5
12
12
VTT0
VTT1
VTAP
DBR#
DBA#
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
GND_0
GND_1
*ITP700Flex
C926*100P/50V/04
R16756/04
1 2
C927*100P/50V/04
R16675/04
R72*56/04
1 2
ITP_TCK
ITP_TRST#
27
28
26
ITP_DBRESET#
25
24
23
21
19
17
15
13
4
NC0
6
NC1
29
30
3
H_ADS#6
H_BNR#6
H_BPRI#6
H_DEFER#6
H_DRDY#6
H_DBSY#6
H_BR0#6
H_INIT#21
H_LOCK#6
H_RESET#6
H_RS#06
H_RS#16
H_RS#26
H_TRDY#6
H_HIT#6
H_HITM#6
SYS_RST#23
12
+1.05V
H_THERMDA5
H_THERMDC5
PM_THRMTRIP#7,21
+1.05V
CLK_CPU_BCLK2
CLK_CPU_BCLK#2
ITP debug signals
+1.05V
C904*0.1U/10V/04
C905*0.1U/10V/04
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
SI-2 modified
resevved for power
noise
+1.05V
12
12
H_D#[0..63]6
H_DSTBN#06
H_DSTBP#06
H_DINV#06
H_D#[0..63]6
Layout Note:
Place voltage
divider within
0.5" of GTLREF
pin
+1.05V
1 2
1 2
R151
1K/F/04
R152
2K/F/04
H_DSTBN#16
H_DSTBP#16
H_DINV#16
CPU_BSEL02
CPU_BSEL12
CPU_BSEL22
R157*1K/F/04
1 2
R158*1K/F/04
1 2
C132*0.1U/10V/04
12
R140*0/04
1 2
Place C close to the
CPU_TEST4 pin. Make sure
CPU_TEST4 routing is
reference to GND and away
from other noisy signal.
ITP disable guidelines
SignalResistor ValueConnect ToResistor Placement
150 ohm +/- 5%
TDI
39 ohm +/- 1%
TMS
500-680ohm +/- 5%
TRST#
27 ohm +/- 1%
TCK
TDO
150 ohm +/- 5%
Note: Populate R5, R8, C372 & R430 when ITP connector is populated.
4
CPU_TEST1
CPU_TEST2
CPU_TEST4
CPU_TEST6
5
H_D#[0..63]
H_D#[0..63]
FSB
533001133
667
800
VTT
GND
GND
VTT
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
V_CPU_GTLREF
CPU_TEST1
CPU_TEST2
CPU_TEST3
CPU_TEST4
CPU_TEST5
CPU_TEST6
*PAD
For the purpose of testability, route these signals
through a ground referenced Z0 = 55ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.
BCLK
166
200
U31B
E22
D[0]#
F24
D[1]#
E26
D[2]#
G22
D[3]#
F23
D[4]#
G25
D[5]#
E25
D[6]#
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
AD26
C23
D25
C24
AF26
AF1
A26
B22
B23
C21
T49
T154*PAD
DATA GRP 0 DATA GRP 1
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
GTLREF
MISC
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
BSEL[0]
BSEL[1]
BSEL[2]
Merom Ball-out Rev 1a
CPU_TEST3
CPU_TEST5
BSEL2BSEL1BSEL0
0
1
DATA GRP 2DATA GRP 3
DSTBN[2]#
DSTBP[2]#
DINV[2]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
0011
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
SLP#
H_D#33
AB24
H_D#34
V24
H_D#35
V26
H_D#36
V23
H_D#37
T22
H_D#38
U25
H_D#39
U23
H_D#40
Y25
H_D#41
W22
H_D#42
Y23
H_D#43
W24
H_D#44
W25
H_D#45
AA23
H_D#46
AA24
H_D#47
AB25
Y26
AA26
U22
H_D#48
AE24
H_D#49
AD24
H_D#50
AA21
H_D#51
AB22
H_D#52
AB21
H_D#53
AC26
H_D#54
AD20
H_D#55
AE22
H_D#56
AF23
H_D#57
AC25
H_D#58
AE21
H_D#59
AD21
H_D#60
AC22
H_D#61
AD23
H_D#62
AF22
H_D#63
AC23
AE25
AF24
AC20
COMP0
R26
COMP1
U26
COMP2
AA1
COMP3
Y1
E5
B5
D24
H_PWRGD
D6
D7
AE6
PSI#
Comp0,2 connect with Zo=27.4ohm,Comp1,3
connect with Zo=55ohm, make those traces
length shorter than 0.5".Trace should be
at least 25 mils away from any other
toggling signal.
H_D#32
Y22
Within 2.0" of the ITPVTT
Within 2.0" of the ITP
Within 2.0" of the ITP
Within 2.0" of the ITP
Within 2.0" of the ITP
6
NB5/RD1/HW2
H_D#[0..63]
H_D#[0..63]
Note:
H_DPRTSTP need to daisy chain
from ICH8 to IMVP6 to CPU.
COMP0
COMP1
COMP2
COMP3
R16
54.9/F/04
1 2
H_D#[0..63]6
H_DSTBN#26
H_DSTBP#26
H_DINV#26
H_D#[0..63]6
SI-2
modified
for fix
run TAT
hang
H_DSTBN#36
H_DSTBP#36
H_DINV#36
H_DPRSTP#7,21,44
H_DPSLP#21
H_DPWR#6
H_PWRGD21
H_CPUSLP#6
PM_PSI#44
H_PWRGD
SI-2 modified
resevved for power
noise
Reserved for EMI.
+1.05V
VIN
R17
27.4/F/04
1 2
12
C911
*.1U/10V/04
1 2
R585
54.9/F/04
*100P/50V/04
+1.05V
+1.5V
+1.05V
H_DPRSTP#
H_DPSLP#
C928
C929
12
C730
*.1U/10V/04
R584
27.4/F/04
1 2
*56/04
1 2
C908
100P/50V/04
*100P/50V/04
PROJECT : AT5
Quanta Computer Inc.
SizeDocument NumberRev
Custom
CLOCK GENERATOR
Date:Sheet of
7
348Monday, March 19, 2007
8
R822
1A
1
VCC_CORE
C88
22U/10V/08
C96
22U/10V/08
12
C672
10U/4V/08
12
C81
22U/10V/08
12
AA
VCC_CORE
12
8 inside cavity, north side, secondary layer.
VCC_CORE
C52
22U/10V/08
C71
22U/10V/08
12
C42
22U/10V/08
12
C63
22U/10V/08
12
BB
VCC_CORE
12
8 inside cavity, south side, secondary layer.
VCC_CORE
12
C40
22U/10V/08
12
C39
22U/10V/08
6 inside cavity, north side, primary layer.
VCC_CORE
C671
22U/10V/08
12
C675
10U/4V/08
CC
12
6 inside cavity, south side, primary layer.
+1.05V
C65
.1U/10V/04
12
C64
.1U/10V/04
12
2
12
C676
10U/4V/08
12
C693
10U/4V/08
12
C72
22U/10V/08
12
C36
22U/10V/08
12
C35
22U/10V/08
12
C682
22U/10V/08
12
C54
.1U/10V/04
12
C683
10U/4V/08
12
C697
10U/4V/08
12
C66
22U/10V/08
12
C95
22U/10V/08
12
C41
22U/10V/08
12
C687
10U/4V/08
12
C56
.1U/10V/04
12
C50
22U/10V/08
12
C692
10U/4V/08
12
C48
.1U/10V/04
3
12
C688
10U/4V/08
12
C87
22U/10V/08
12
C57
22U/10V/08
12
C80
22U/10V/08
12
C55
22U/10V/08
12
C696
10U/4V/08
12
C51
.1U/10V/04
4
VCC_CORE VCC_CORE
U31C
A7
VCC[001]
A9
VCC[002]
A10
VCC[003]
A12
VCC[004]
A13
VCC[005]
A15
VCC[006]
A17
VCC[007]
A18
VCC[008]
A20
VCC[009]
B7
VCC[010]
B9
VCC[011]
B10
VCC[012]
B12
VCC[013]
B14
VCC[014]
B15
VCC[015]
B17
VCC[016]
B18
VCC[017]
B20
VCC[018]
C9
VCC[019]
C10
VCC[020]
C12
VCC[021]
C13
VCC[022]
C15
VCC[023]
C17
VCC[024]
C18
VCC[025]
D9
VCC[026]
D10
VCC[027]
D12
VCC[028]
D14
VCC[029]
D15
VCC[030]
D17
VCC[031]
D18
VCC[032]
E7
VCC[033]
E9
VCC[034]
E10
VCC[035]
E12
VCC[036]
E13
VCC[037]
E15
VCC[038]
E17
VCC[039]
E18
VCC[040]
E20
VCC[041]
F7
VCC[042]
F9
VCC[043]
F10
VCC[044]
F12
VCC[045]
F14
VCC[046]
F15
VCC[047]
F17
VCC[048]
F18
VCC[049]
F20
VCC[050]
AA7
VCC[051]
AA9
VCC[052]
AA10
VCC[053]
AA12
VCC[054]
AA13
VCC[055]
AA15
VCC[056]
AA17
VCC[057]
AA18
VCC[058]
AA20
VCC[059]
AB9
VCC[060]
AC10
VCC[061]
AB10
VCC[062]
AB12
VCC[063]
AB14
VCC[064]
AB15
VCC[065]
AB17
VCC[066]
AB18
VCC[067]
Merom Ball-out Rev 1a
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
.
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
TP_VCCSENSE
AF7
TP_VSSSENSE
AE7
5
ICCODE:
for Merom processors
recommended design
target is 44A
ICCP:
1before vccore stable
peak current is 4.5A
2.after vccore stable
+1.05V
continue current is
2.5A
12
+
C26
*330U/2.5V
ICCA 130mA
CPU_VID044
CPU_VID144
CPU_VID244
CPU_VID344
CPU_VID444
CPU_VID544
CPU_VID644
TP_VCCSENSE44
TP_VSSSENSE44
12
Layout Note:
Place C105 near PIN
B26.
6
C729
.01U/25V/04
+1.5V
12
C733
10U/4V/08
7
U31D
A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3 A25
VSS[082]
VSS[001]
VSS[002]
VSS[083]
VSS[003]
VSS[084]
VSS[004]
VSS[085]
VSS[005]
VSS[086]
VSS[006]
VSS[087]
VSS[007]
VSS[088]
VSS[008]
VSS[089]
VSS[009]
VSS[090]
VSS[010]
VSS[091]
VSS[011]
VSS[092]
VSS[012]
VSS[093]
VSS[013]
VSS[094]
VSS[014]
VSS[095]
VSS[015]
VSS[096]
VSS[016]
VSS[097]
VSS[017]
VSS[098]
VSS[018]
VSS[099]
VSS[019]
VSS[100]
VSS[020]
VSS[101]
VSS[021]
VSS[102]
VSS[022]
VSS[103]
VSS[023]
VSS[104]
VSS[024]
VSS[105]
VSS[025]
VSS[106]
VSS[026]
VSS[107]
VSS[027]
VSS[108]
VSS[028]
VSS[109]
VSS[029]
VSS[110]
VSS[030]
VSS[111]
VSS[031]
VSS[112]
VSS[032]
VSS[113]
VSS[033]
VSS[114]
VSS[034]
VSS[115]
VSS[035]
VSS[116]
VSS[036]
VSS[117]
VSS[037]
VSS[118]
VSS[038]
VSS[119]
VSS[039]
VSS[120]
VSS[040]
VSS[121]
VSS[041]
VSS[122]
VSS[042]
VSS[123]
VSS[043]
VSS[124]
VSS[044]
VSS[125]
VSS[045]
VSS[126]
VSS[046]
VSS[127]
VSS[047]
VSS[128]
VSS[048]
VSS[129]
VSS[049]
VSS[130]
VSS[050]
VSS[131]
VSS[051]
VSS[132]
VSS[052]
VSS[133]
VSS[053]
VSS[134]
VSS[054]
VSS[135]
VSS[055]
VSS[136]
VSS[056]
VSS[137]
VSS[057]
VSS[138]
VSS[058]
VSS[139]
VSS[059]
VSS[140]
VSS[060]
VSS[141]
VSS[061]
VSS[142]
VSS[062]
VSS[143]
VSS[063]
VSS[144]
VSS[064]
VSS[145]
VSS[065]
VSS[146]
VSS[066]
VSS[147]
VSS[148]
VSS[067]
VSS[068]
VSS[149]
VSS[069]
VSS[150]
VSS[070]
VSS[151]
VSS[071]
VSS[152]
VSS[072]
VSS[153]
VSS[073]
VSS[154]
VSS[074]
VSS[155]
VSS[075]
VSS[156]
VSS[076]
VSS[157]
VSS[077]
VSS[158]
VSS[078]
VSS[159]
VSS[079]
VSS[160]
VSS[080]
VSS[161]
VSS[081]VSS[162]
VSS[163]
Merom Ball-out Rev 1a
8
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF25
.
Layout out:
Place these inside socket cavity on North side secondary.
DD
PROJECT : AT5
Quanta Computer Inc.
SizeDocument NumberRev
Custom
1
2
3
4
5
6
NB5/RD1/HW2
Merom Processor (POWER)
Date:Sheet of
7
448Monday, March 19, 2007
8
1A
5
4
3
2
1
+3V
DD
R165
200/F/06
LM86VCC
R161
R163
R164
10K/04
LM86_SMD
THERM_ALERT#23
CC
MBDATA17,36,37,41,48
BB
MBCLK17,36,37,41,48
THERM_ALERT#
Q4
2N7002E
3
Q5
2N7002E
3
1 2
R368*0/06
close to ICH
+3V
2
1
+3V
2
1
LM86_SMD
LM86__SMC
10K/04
LM86__SMC
10K/04
25mils
U4
8
SCLK
7
SDA
6
ALERT#
4
OVERT#
MAX6657/GMT-781
ADDRESS: 98H
VCC
DXP
DXN
GND
SYS_SHDN#
3
2
Q3
C235
0.1U/16V/06
2N7002E
1
add hardware protect
SYS_SHDN#16,42
SYS_SHDN#
Q53
*2N7002E
3
+3V
2
1
2
Q6
2N7002E
R162*0/06
+3V
R176
1M/F/06
3
1
C169
.1U/10V/04
1
2
3
5
H_THERMDA
C126
2200P/50V/06
H_THERMDC
SYS_SHDN-1#
10/20mils
H_THERMDA3
H_THERMDC3
05
PV-2 Add
NV_SYS_SHDN#3
AA
PROJECT : AT5
Quanta Computer Inc.
SizeDocument NumberRev
B
NB5/RD1/HW2
5
4
3
2
THERMAL LM86
Date:Sheet of
548Monday, March 19, 2007
1
1A
1
2
3
4
5
6
7
8
H_A#[3..35]
H_ADS#3
H_ADSTB#03
H_ADSTB#13
H_BNR#3
H_BPRI#3
H_BR0#3
H_DEFER#3
H_DBSY#3
CLK_MCH_BCLK2
CLK_MCH_BCLK#2
H_DPWR#3
H_DRDY#3
H_HIT#3
H_HITM#3
H_LOCK#3
H_TRDY#3
H_DINV#03
H_DINV#13
H_DINV#23
H_DINV#33
H_DSTBN#03
H_DSTBN#13
H_DSTBN#23
H_DSTBN#33
H_DSTBP#03
H_DSTBP#13
H_DSTBP#23
H_DSTBP#33
H_REQ#03
H_REQ#13
H_REQ#23
H_REQ#33
H_REQ#43
H_RS#03
H_RS#13
H_RS#23
H_A#[3..35]3
AD12
AC14
AD11
AC11
AJ14
AE11
AH12
AH13
M10
N12
W10
AE3
AD9
AC9
AC7
AB2
AD7
AB1
AC6
AE2
AC5
AG3
AH8
AE9
AH5
AE7
AE5
AH2
E2
G2
G7
M6
H7
H3
G4
F3
N8
H2
N9
H5
P13
K9
M2
Y8
V4
M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4
W3
N1
Y3
AJ9
AJ5
AJ6
AJ7
AJ2
AJ3
B3
C2
W1
W2
B6
E5
B9
A9
U34A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
CRESTLINE_1p0
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
HOST
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19
G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7
K5
L2
AD13
AE13
M7
K3
AD2
AH11
L7
K2
AC2
AJ10
M14
E13
A11
H13
B12
E12
D7
D8
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_A#3
J13
12
C46
.1U/10V/04
H_D#[0..63]
H_RESET#3
H_CPUSLP#3
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
H_REF
C47
.1U/10V/04
1 2
H_D#[0..63]3
AA
+1.05V
12
R51
221/F/04
H_SWING
12
R55
100/F/04
BB
+1.05V
impedance 55 ohm
12
12
R553
R542
54.9/F/04
54.9/F/04
H_SCOMP
H_SCOMP#
12
CC
H_RCOMP
R41
24.9/F/04
Layout Note:
H_RCOMP trace should be
10-mil wide with 20-mil
spacing.
+1.05V
1 2
12
R52
1K/F/04
R53
2K/F/04
Layout Note:
DD
Place the 0.1 uF
decoupling capacitor
within 100 mils from
GMCH pins.
PROJECT : AT5
Quanta Computer Inc.
SizeDocument NumberRev
Custom
1
2
3
4
5
6
NB5/RD1/HW2
Crestline (HOST)
Date:Sheet of
7
648Monday, March 19, 2007
8
1A
1
AA
WW22 update --- MA14 needs
to be routed if customers
are planning on using 2Gb
technology and width=8 (by
8) DIMMs
SA_MA1413,14
SB_MA1413,14
CRESTLINE
new pin
define
Layout Note:
BB
DELAY_VR_PWRGOOD23,44
CC
PM_THRMTRIP#3,21
GMCH pwrok is 3.3v
tolerant
DD
Location of all MCH_CFG strap
resistors needs to be close to
minmize stub.
MCH_CFG_512
MCH_CFG_912
MCH_CFG_1212
MCH_CFG_1312
MCH_CFG_1612
MCH_CFG_1912
MCH_CFG_2012
PM_BMBUSY#23
H_DPRSTP#3,21,44
PM_EXTTS#013,14
PM_EXTTS#113
PLT_RST-R#20,22
DPRSLPVR23,44
+3V
R2710K/04
R2810K/04
1
T165*PAD
T9*PAD
MCH_BSEL02
MCH_BSEL12
MCH_BSEL22
*PAD
*PAD
*PAD
*PAD
*PAD
T30
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
R360
R840/04
R790/04
R159100/04
R90*0/04
R680/04
1 2
1 2
T18
T158
T27
T16
T20
T21
T17
T23
T28
T26
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
*PAD
2
PM_BMBUSY#_R
ICH_DPRSTP#_R
PM_EXTTS#1_R
PLTRST_MCH#
PM_THRMTRIP#_GMCH
PM_DPRSLPVR_GMCH
TP_NC1
T202
TP_NC2
T204
TP_NC3
T208
TP_NC4
T209
TP_NC5
T210
TP_NC6
T206
TP_NC7
T207
TP_NC8
T203
TP_NC9
T199
TP_NC10
T164
TP_NC11
T160
TP_NC12
T166
TP_NC13
T163
TP_NC14
T162
TP_NC15
T156
TP_NC16
T205
PM_EXTTS#0
PM_EXTTS#1
2
3
U34B
P36
RSVD1
P37
RSVD2
R35
RSVD3
N35
RSVD4
AR12
RSVD5
AR13
RSVD6
AM12
RSVD7
AN13
RSVD8
J12
RSVD9
AR37
RSVD10
AM36
RSVD11
AL36
RSVD12
AM37
RSVD13
D20
RSVD14
H10
RSVD20
B51
RSVD21
BJ20
RSVD22
BK22
RSVD23
BF19
RSVD24
BH20
RSVD25
BK18
RSVD26
BJ18
RSVD27
BF23
RSVD28
BG23
RSVD29
BC23
RSVD30
BD24
RSVD31
BJ29
SA-MA14
BE24
SB_MA14
BH39
RSVD34
AW20
RSVD35
BK20
RSVD36
C48
LVDSA_DATA#_3
D47
LVDSA_DATA_3
B44
RSVD39
C44
RSVD40
A35
RSVD41
B37
RSVD42
B36
RSVD43
B34
RSVD44
C34
RSVD45
P27
CFG_0
N27
CFG_1
N24
CFG_2
CFG3
C21
CFG_3
CFG4
C23
CFG_4
CFG5
F23
CFG_5
CFG6
N23
CFG_6
CFG7
G23
CFG_7
CFG8
J20
CFG_8
CFG9
C20
CFG_9
CFG10
R24
CFG_10
CFG11
L23
CFG_11
CFG12
J23
CFG_12
CFG13
E23
CFG_13
CFG14
E20
CFG_14
CFG15
K23
CFG_15
CFG16
M20
CFG_16
CFG17
M24
CFG_17
CFG18
L32
CFG_18
CFG19
N33
CFG_19
CFG20
L35
CFG_20
G41
PM_BM_BUSY#
L39
PM_DPRSTP#
L36
PM_EXT_TS#_0
J36
PM_EXT_TS#_1
AW49
PWROK
AV20
RSTIN#
N20
THERMTRIP#
G36
DPRSLPVR
BJ51
NC_1
BK51
NC_2
BK50
NC_3
BL50
NC_4
BL49
NC_5
BL3
NC_6
BL2
NC_7
BK1
NC_8
BJ1
NC_9
E1
NC_10
A5
NC_11
C51
NC_12
B50
NC_13
A50
NC_14
A49
NC_15
BK2 R32
NC_16TEST_2
CRESTLINE_1p0
SM_RCOMP_VOH
12
C215
.01U/25V/04
SM_RCOMP_VOL
12
C230
.01U/25V/04
CFGRSVD
PM
NC
12
C209
2.2U/10V/08
12
C245
2.2U/10V/08
DDR MUXINGCLKDMI
GRAPHICS VIDME
MISC
+1.8VSUS_GMCH
3
SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4
SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4
SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF_0
SM_VREF_1
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
PEG_CLK
PEG_CLK#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VR_EN
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
SDVO_CTRL_CLK
SDVO_CTRL_DATA
CLK_REQ#
ICH_SYNC#
TEST_1
12
R178
1K/F/04
12
R179
3.01K/F/04
12
R175
1K/F/04
AV29
BB23
BA25
AV23
AW30
BA23
AW25
AW23
BE29
AY32
BD39
BG37
BG20
BK16
BG16
BE13
BH18
BJ15
BJ14
BE16
BL15
BK14
BK31
BL31
AR49
AW4
B42
C42
H48
H47
K44
K45
AN47
AJ38
AN42
AN46
AM47
AJ39
AN41
AN45
AJ46
AJ41
AM40
AM44
AJ47
AJ42
AM39
AM43
E35
A39
C38
B39
E36
AM49
AK50
AT43
AN49
AM50
H35
K36
G39
G40
A37
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
M_A_CLK014
M_A_CLK114
M_B_CLK014
M_B_CLK114
M_A_CLK0#14
M_A_CLK1#14
M_B_CLK0#14
M_B_CLK1#14
M_A_CKE013,14
M_A_CKE113,14
M_B_CKE013,14
M_B_CKE113,14
M_A_CS#013,14
M_A_CS#113,14
M_B_CS#013,14
M_B_CS#113,14
M_A_ODT013,14
M_A_ODT113,14
M_B_ODT013,14
M_B_ODT113,14
SMRCOMPP
SMRCOMPN
SM_RCOMP_VOH
SM_RCOMP_VOL
SMDDR_VREF_MCH
R170*10K/F/06
R169*10K/F/06
R42EV@0
<check lisr & CRB>
For Calero : 255
For Cresstline:1.3K/F
For external VGA:0
ohm
DFGT_VID_0
DFGT_VID_1
DFGT_VID_2
DFGT_VID_3
DFGT_VR_EN
CL_CLK023
CL_DATA023
ECPWROK16,23,37,48
CL_RST#023,39
MCH_CLVREF
T22
T24
CLK_3GPLLREQ#2
MCH_ICH_SYNC#23
R101
20K/04
1 2
1 2
+1.25V
MCH_CLVREF
C128
.1U/10V/04
1 2
4
<check list & CRB>
For Calero : 1.5K
For
Cresstline:2.4K
SI-1 modified add 470P
1 2
C882470P/50V/X7R/04
C178.1U/10V/04
C196.1U/10V/04
R1680/04
+1.8VSUS_GMCH
DREFCLK2
DREFCLK#2
DREFSSCLK2
DREFSSCLK#2
CLK_PCIE_3GPLL2
CLK_PCIE_3GPLL#2
DMI_TXN[3:0]22
DMI_TXP[3:0]22
DMI_RXN[3:0]22
DMI_RXP[3:0]22
HSYNC_COM15,25
VSYNC_COM15,25
IV&EV Dis/Enable setting
T19
R507
0/04
12
12
4
T159
T157
T155
T161
R586
1K/F/04
R589
392/F/04
In Crestline EDS
Rev.1.0, Render
Standby Voltage is
not finalized
yet(TBD), 1.05V for
Graphic Voltage
range(VCC_AXG) is
between 0.9975V(min.)
and 1.1025V(max.).
Vgfx max at 1.1025V @
8A (estimated)
only resever AT3/5 not
support IAMT,but design
line suggest to connection
these pin ,do not NC
CLKREQ# ( MCH drives CLK_REQ#
to control the PCI-E diff clk
input itself )
SMRCOMPP
SMRCOMPN
+3V
SMDDR_VREF14,46
CRT_B15,25
CRT_G15,25
CRT_R15,25
DDCCLK15,25
DDCDATA15,25
<FAE>
Flexible and safe
+1.8VSUS_GMCH
12
R171
20/F/04
12
R172
20/F/04
5
DPST_PWM16,26
LVDS_BLON16,26
EDIDCLK15,16,26
EDIDDATA15,16,26
DISP_ON16,26
R83*IV@2.4K/04
IV&EV Dis/Enable
setting
LA_CLK#15
LA_CLK15
LB_CLK#15
LB_CLK15
LA_DATAN015
LA_DATAN115
LA_DATAN215
LA_DATAP015
LA_DATAP115
LA_DATAP215
LB_DATAN015
LB_DATAN115
LB_DATAN215
LB_DATAP015
LB_DATAP115
LB_DATAP215
S-CVBS115,25
S-YD115,25
S-CD115,25
R91*2.2K/04
+3V
R100*2.2K/04
<FAE>
If no use can be NC
R88*0/04
R87*0/04
R86*0/04
R48*0/04
R49*0/04
R75*0/04
R34*30/04
R67*0/04
R35*30/04
5
R31*0/06
R26*10K/04
R25*10K/04
R32*0/06
R33*0/06
R46*0/06
R93*0/04
R92*0/04
R96*0/04
CRT_BLUE1
CRT_GREEN1
CRT_RED1
<check list>
HSYNC/VSYNC serial R
place close to NB
DREFSSCLK
DREFSSCLK#
<FAE>
If no use DREFCLK PU and
DREFCLK# PD
IV&EV Dis/Enable setting
DREFCLK
DREFCLK#
<design guide>
If no use
DREFCLK PU and
DREFCLK# PD
<check list>
For EV@
Connect to GND
CRT R/G/B
TV A/B/C
HSYNC/VSYNC
SI-2 change
R64EV@39/F/04
R60EV@39/F/04
R62*IV@150/F/04
R66*IV@150/F/04
R78*IV@150/F/04
R74*IV@150/F/04
R77*IV@150/F/04
R65*IV@150/F/04
J40
H39
E39
E40
C37
D35
K40
LVDS_IBG
L41
L43
T25*PAD
N41
N40
D46
C45
D44
E42
G51
E51
F49
G50
E50
F48
G44
B47
B45
E44
A47
A45
TV_COMP1
E27
TV_Y/G1
G27
TV_C/R1
K27
F27
J27
L27
TV_DCONSEL_0
M35
TV_DCONSEL_1
P33
H32
G32
K29
J29
F29
E29
DDCCLK_R
K33
DDCDATA_R
G35
HSYNC11
F33
CRTIREF
C32
VSYNC11
E33
R69EV@4.7K/04
R76EV@4.7K/04
R59EV@4.7K/04
R57EV@4.7K/04
<check list>
For IV@
Connect to 150ohm
CRT R/G/B
TV A/B/C
Connect to 39ohm
HSYNC/VSYNC
6
U34C
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
TVA_DAC
TVB_DAC
TVC_DAC
TVA_RTN
TVB_RTN
TVC_RTN
TV_DCONSEL_0
TV_DCONSEL_1
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC
CRESTLINE_1p0
HSYNC11
VSYNC11
TV_COMP1
TV_Y/G1
TV_C/R1
CRT_BLUE1
CRT_GREEN1
CRT_RED1
6
+1.25V
+1.25V
LVDS
TV VGA
PCI-EXPRESS GRAPHICS
SI-1 modified
add 150ohm in
the UMA BOM
NB5/RD1/HW2
7
+VCC_PEG
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
R8524.9/F/04
1 2
C62.1U/10V/04
C685.1U/10V/04
C70.1U/10V/04
C690.1U/10V/04
C77.1U/10V/04
C695.1U/10V/04
C92.1U/10V/04
C701.1U/10V/04
C103.1U/10V/04
C709.1U/10V/04
C109.1U/10V/04
C716.1U/10V/04
C111.1U/10V/04
C719.1U/10V/04
C117.1U/10V/04
C722.1U/10V/04
C59.1U/10V/04
C684.1U/10V/04
C67.1U/10V/04
C689.1U/10V/04
C74.1U/10V/04
C694.1U/10V/04
C84.1U/10V/04
C700.1U/10V/04
C97.1U/10V/04
C703.1U/10V/04
C107.1U/10V/04
C713.1U/10V/04
C112.1U/10V/04
C717.1U/10V/04
C122.1U/10V/04
C721.1U/10V/04
PEG_COMPI
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
VCC3G_PCIE_R
N43
M43
J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41
J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42
C_PEG_TXN0
N45
C_PEG_TXN1
U39
C_PEG_TXN2
U47
C_PEG_TXN3
N51
C_PEG_TXN4
R50
C_PEG_TXN5
T42
C_PEG_TXN6
Y43
C_PEG_TXN7
W46
C_PEG_TXN8
W38
C_PEG_TXN9
AD39
C_PEG_TXN10
AC46
C_PEG_TXN11
AC49
C_PEG_TXN12
AC42
C_PEG_TXN13
AH39
C_PEG_TXN14
AE49
C_PEG_TXN15
AH44
C_PEG_TXP0
M45
C_PEG_TXP1
T38
C_PEG_TXP2
T46
C_PEG_TXP3
N50
C_PEG_TXP4
R51
C_PEG_TXP5
U43
C_PEG_TXP6
W42
C_PEG_TXP7
Y47
C_PEG_TXP8
Y39
C_PEG_TXP9
AC38
C_PEG_TXP10
AD47
C_PEG_TXP11
AC50
C_PEG_TXP12
AD43
C_PEG_TXP13
AG39
C_PEG_TXP14
AE50
C_PEG_TXP15
AH43
IV&EV Dis/Enable setting
<check list>
SDVO/PCIE/LVDS not
implement
16 lanes NC
PROJECT : AT5
Quanta Computer Inc.
SizeDocument NumberRev
Custom
Crestline (VGA,DMI)
Date:Sheet of
7
8
PEG_RXN020
PEG_RXN120
PEG_RXN220
PEG_RXN320
PEG_RXN420
PEG_RXN520
PEG_RXN620
PEG_RXN720
PEG_RXN820
PEG_RXN920
PEG_RXN1020
PEG_RXN1120
PEG_RXN1220
PEG_RXN1320
PEG_RXN1420
PEG_RXN1520
PEG_RXP020
PEG_RXP120
PEG_RXP220
PEG_RXP320
PEG_RXP420
PEG_RXP520
PEG_RXP620
PEG_RXP720
PEG_RXP820
PEG_RXP920
PEG_RXP1020
PEG_RXP1120
PEG_RXP1220
PEG_RXP1320
PEG_RXP1420
PEG_RXP1520
PEG_TXN_C020
PEG_TXN_C120
PEG_TXN_C220
PEG_TXN_C320
PEG_TXN_C420
PEG_TXN_C520
PEG_TXN_C620
PEG_TXN_C720
PEG_TXN_C820
PEG_TXN_C920
PEG_TXN_C1020
PEG_TXN_C1120
PEG_TXN_C1220
PEG_TXN_C1320
PEG_TXN_C1420
PEG_TXN_C1520
PEG_TXP_C020
PEG_TXP_C120
PEG_TXP_C220
PEG_TXP_C320
PEG_TXP_C420
PEG_TXP_C520
PEG_TXP_C620
PEG_TXP_C720
PEG_TXP_C820
PEG_TXP_C920
PEG_TXP_C1020
PEG_TXP_C1120
PEG_TXP_C1220
PEG_TXP_C1320
PEG_TXP_C1420
PEG_TXP_C1520
748Monday, March 19, 2007
8
1A
1
AA
M_A_DQ[63:0]14 M_B_DQ[63:0]14
BB
CC
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BF48
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BG10
AW9
AN10
AN11
BD8
AY9
BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8
AT9
AN9
AM9
2
U34D
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
CRESTLINE_1p0
3
BB19
SA_BS_0
BK19
SA_BS_1
BF29
SA_BS_2
BL17
SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_RAS#
SA_RCVEN#
DDR SYSTEM MEMORY A
SA_WE#
AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6
AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2
BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16
BE18
AY20
BA19
M_A_DQM0
M_A_DQM1
M_A_DQM2
M_A_DQM3
M_A_DQM4
M_A_DQM5
M_A_DQM6
M_A_DQM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
TP_SA_RCVEN#
4
M_A_BS#013,14
M_A_BS#113,14
M_A_BS#213,14
M_A_CAS#13,14
M_A_DQM[0..7]14
M_A_DQS[7:0]14
M_A_DQS#[7:0]14
M_A_A[13:0]13,14
M_A_RAS#13,14
T68
M_A_WE#13,14
5
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BK10
BK5
BK9
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2
BL9
BL5
BJ8
BJ6
BJ2
6
U34E
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
CRESTLINE_1p0
7
AY17
SB_BS_0
BG18
SB_BS_1
BG36
SB_BS_2
BE17
SB_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_RAS#
SB_RCVEN#
SB_WE#
DDR SYSTEM MEMORY B
AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2
AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3
BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
AV16
AY18
BC17
M_B_DQM0
M_B_DQM1
M_B_DQM2
M_B_DQM3
M_B_DQM4
M_B_DQM5
M_B_DQM6
M_B_DQM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
TP_SB_RCVEN#
8
M_B_BS#013,14
M_B_BS#113,14
M_B_BS#213,14
M_B_CAS#13,14
M_B_DQM[0..7]14
M_B_DQS[7:0]14
M_B_DQS#[7:0]14
M_B_A[13:0]13,14
M_B_RAS#13,14
T74*PAD
M_B_WE#13,14
DD
PROJECT : AT5
Quanta Computer Inc.
SizeDocument NumberRev
Custom
1
2
3
4
5
6
NB5/RD1/HW2
Crestline (DDR)
Date:Sheet of
7
848Monday, March 19, 2007
8
1A
AT35
AT34
AH28
AC32
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32
AU32
AU33
AU35
AV33
AW33
AW35
AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
BL33
AU30
W13
W14
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AJ20
AN14
5
R30
R20
T14
Y12
U34G
VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC CORE
POWER
VCC SMVCC GFX
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC GFX NCTF
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC SM LF
+1.05V
DD
IVCCSM supply
current 1
channel
1.615A 2
channel
3.318A
CC
BB
AA
+1.8VSUS_GMCH
+VGFX_CORE_INT
T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31
AW45
BC39
BE39
BD17
BD4
AW8
AT6
4
Ivcc_AXG Graphics core supply
current 7.7A
12
+
C91
*330U/6.3V
SI-2 modified --remove
C91&C108
Layout Note:
Inside GMCH cavity for VCC_AXG.
12
C118
.1U/10V/04
GMCH 1.05V
VCC Core
VCC_AXG
VCC_AXD
VTT
VCC_PEG
VCC_AXM
VCCR_RX_DMI
12
+
12
C110
.1U/10V/04
current(A)
1.573
7.7
0.2
0.85
1.2
0.54
0.25
12.313SUM
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
12
C129
.1U/10V/04
12
3
Ivcc (External GFX 1.310 A,
integrate 1.572 A)
+1.05V
12
+
C670
Layout Note:
370 mils from edge.
C108
*330U/6.3V
12
C116
0.47U/10V/06
220U/2.5V
+VGFX_CORE_INT
Layout Note:
370 mils from edge.
12
12
C79
C68
1U/10V/06
10U/6.3V/08
Remark
( 1.3A for external GFX
)
for integrated
Gfx
Ivcc_AXM
Controller
supply
current
540mA
FSB VCCP
for PCIEG
for IAMT
function
DMI
C172
.1U/10V/04
12
C222
0.22U/10V/06
12
C174
0.22U/10V/06
12
C212
0.47U/10V/06
+3V
R50010/04
1 2
12
C663
22U/4V/08
Layout Note:
Inside GMCH cavity.
+1.05V
12
C73
22U/4V/08
+1.05V
Layout Note:
Place close to GMCH edge.
12
C155
1U/10V/06
+VCC_GMCH_L
12
12
C115
0.22U/10V/06
12
12
12
C90
0.22U/10V/06
SI-1 modify (
remove R73,R11
--not need )
for IAMT power if not
support need to
connection to S0 power
Layout Note:
Inside GMCH
cavity.
12
C105
.1U/10V/04
C124
22U/4V/08
C145
1U/10V/06
C94
.1U/10V/04
12
C123
0.22U/10V/06
2
D32
21
CH751H-40PT
12
C106
.1U/10V/04
12
C113
.1U/10V/04
12
C99
0.22U/10V/06
1.8VSUS
12
C267
.1U/10V/04
Layout Note:
Place C901 where LVDS
and DDR2 taps.
1
U34F
AB33
VCC_NCTF_1
AB36
VCC_NCTF_2
AB37
VCC_NCTF_3
AC33
VCC_NCTF_4
AC35
VCC_NCTF_5
AC36
VCC_NCTF_6
AD35
VCC_NCTF_7
AD36
VCC_NCTF_8
AF33
VCC_NCTF_9
AF36
VCC_NCTF_10
AH33
VCC_NCTF_11
AH35
VCC_NCTF_12
AH36
VCC_NCTF_13
AH37
VCC_NCTF_14
AJ33
VCC_NCTF_15
AJ35
VCC_NCTF_16
AK33
VCC_NCTF_17
AK35
VCC_NCTF_18
AK36
VCC_NCTF_19
AK37
VCC_NCTF_20
AD33
VCC_NCTF_21
AJ36
VCC_NCTF_22
AM35
VCC_NCTF_23
AL33
VCC_NCTF_24
AL35
VCC_NCTF_25
AA33
VCC_NCTF_26
AA35
VCC_NCTF_27
AA36
VCC_NCTF_28
AP35
VCC_NCTF_29
AP36
VCC_NCTF_30
AR35
VCC_NCTF_31
AR36
VCC_NCTF_32
Y32
VCC_NCTF_33
Y33
VCC_NCTF_34
Y35
VCC_NCTF_35
Y36
VCC_NCTF_36
Y37 A3
VCC_NCTF_37VSS_SCB1
T30
VCC_NCTF_38
T34
VCC_NCTF_39
T35
VCC_NCTF_40
U29
VCC_NCTF_41
U31
VCC_NCTF_42
U32
VCC_NCTF_43
U33
VCC_NCTF_44
U35
VCC_NCTF_45
U36
VCC_NCTF_46
V32
VCC_NCTF_47
V33
VCC_NCTF_48
V36
VCC_NCTF_49
V37
VCC_NCTF_50
AL24
VCC_AXM_NCTF_1
AL26
VCC_AXM_NCTF_2
AL28
VCC_AXM_NCTF_3
AM26
VCC_AXM_NCTF_4
AM28
VCC_AXM_NCTF_5
AM29
VCC_AXM_NCTF_6
AM31
VCC_AXM_NCTF_7
AM32
VCC_AXM_NCTF_8
AM33
VCC_AXM_NCTF_9
AP29
VCC_AXM_NCTF_10
AP31
VCC_AXM_NCTF_11
AP32
VCC_AXM_NCTF_12
AP33
VCC_AXM_NCTF_13
AL29
VCC_AXM_NCTF_14
AL31
VCC_AXM_NCTF_15
AL32
VCC_AXM_NCTF_16
AR31
VCC_AXM_NCTF_17
AR32
VCC_AXM_NCTF_18
AR33
VCC_AXM_NCTF_19
CRESTLINE_1p0
12
+
C744
330U/6.3V
POWER
12
Layout Note:
Place on the edge.
VCC NCTF
C265
22U/4V/08
VCC AXM NCTF
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS NCTF
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6
VSS SCBVCC AXM
VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7
+1.8VSUS_GMCH
12
C266
22U/4V/08
T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28
B2
C1
BL1
BL51
A51
+1.05V
AT33
AT31
AK29
AK24
AK23
AJ26
AJ23
CRESTLINE_1p0
5
PROJECT : AT5
Quanta Computer Inc.
SizeDocument NumberRev
Custom
4
3
2
NB5/RD1/HW2
Crestline (VCC, NCTF)
Date:Sheet of
948Monday, March 19, 2007
1
1A
5
IV&EV Dis/Enable setting
L62
1 2
*IV@BLM18PG181SN1/06
+VCC_TVBG
12
50mA
+1.25V_VCCA_HPLL
12
12
C714
.1U/10V/04
C715
22U/10V/12
150mA
+1.25V_VCCA_MPLL
+VCCA_MPLL_L
12
C45
*IV@0.1U/10V/04
C909
*IV@1U/06
12
C665
*IV@10U/4V/08
+3V_VCCSYNC
C69
*IV@.1U/04
12
C653
*IV@.1U/04
12
C718
.1U/10V/04
+1.5V_VCCD_TVDAC
R50*IV@0/04
1 2
123
C33
*IV@22nF/3P
R47*IV@0/04
1 2
3
C34
*IV@22N12
+3V_TV_DAC
R24*IV@0/06
+3V
<FAE>
INT VGA disable
VCCSYNC connect
to GND
DD
+3V
FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC
+3V_TV_DAC
R23*IV@0.03/F
FB_120ohm+-25%_100mHz
_200mA_0.2ohm DC
+1.25V
L70
12
BLM11A121S/06
CC
SI-2
BB
modified
for WW44
request
SI-2 add for UMA to
fix TV-out noise
FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC
+3V
AA
L71
BLM11A121S/06
R580
0.5/F/06
1 2
+VCCA_MPLL_L
12
C724
22U/10V/12
+1.5V
C947
*IV@4.7U/10V/06
L63
1 2
*IV@BLM18PG181SN1/06
12
22nF & 0.1uF for
VCC_TVDACA:C_R should
be placed with in 250
mils from Crestline.
R58
EV@0/04
+VCCA_CRTDAC
12
C652
*IV@.1U/04
R5010/04
12
123
C660
*IV@22N
+1.25V
L6
10uH/100MA/08
10uH+-20%_100mA
L66
10uH/100MA/08
0.1Caps should be
placed 200 mils
with in its pins.
+1.25V
R1770/06
+1.5V_VCCD_TVDAC
12
C43
*IV@.1U/04
R5040/04
1 2
123
12
C655
*IV@.1U/04
R5030/04
1 2
12
C656
*IV@.1U/04
R5020/04
1 2
12
C654
*IV@.1U/04
4
R4990/04
1 2
3
R512
EV@0/04
12
12
+1.25V
R43
EV@0/04
C662
*IV@22N
3
C661
*IV@22N12
3
C659
*IV@22N12
C657
*IV@22N12
+1.25V_VCCA_DPLLA
12
C28
+
470U/4V
+1.25V_VCCA_DPLLB
12
C669
+
470U/4V
R1810/08
12
C242
+
100U/6.3V
12
C173
22U/4V/08
+VCCA_MPLL_L
R37*IV@0/06
+1.8VSUS_GMCH
+VCC_TVDACA_R
R514
EV@0/04
+VCC_TVDACB_R
R513
EV@0/04
+VCC_TVDACC_R
R511
EV@0/04
+3V_VCCA_CRT_DAC
R515
EV@0/04
80mA
12
C38
.1U/10V/04
80mA
12
C680
.1U/10V/04
C125
4.7U/6.3V/06
1 2
12
C146
1U/10V/06
R826100/08
250mA
SI-1 modify
( NET name
wrong )
+1.8VSUS_VCC_TX_LVDS
IV&EV Dis/Enable setting
+3V
12
C58
.1U/10V/04
Ivcca_PEG_BG
supply current
100mA
12
C119
22U/4V/08
12
C156
1U/10V/06
R89EV@0/04
R44*IV@0/06
12
C726
.1U/10V/04
C37
C32
*IV@1U/06
*IV@10U/08
+1.25V
BLM21PG221SN1D/08
FB_220ohm+-25%_100MHz
_2A_0.1ohm DC
+1.8VSUS_VCC_TX_LVDS
10mA
R509
EV@0/04
+1.25V_VCCD_PEG_PLL
+1.25V_VCCA_SM
12
C120
22U/4V/08
+1.25V_VCCA_SM_CK
12
C189
.1U/10V/04
+1.5V_VCCD_CRT
+1.5V_VCCD_TVDAC
+1.5V_VCCD_QDAC+VCCQ_TVDAC
+VCCA_MPLL_L
+1.25V_VCCD_PEG_PLL
12
C93
.1U/10V/04
L65
1 2
3
CRT/TV Disable/Enable guideline
External VGA with EV@part,Internal VGA with IV@ part
Ball
Enable
3.3V
3.3V
1.5V
1.5V
3.3V
+VTTLF1
+VTTLF2
+VTTLF3
Disable
GNDVCCA_TVC_DAC
GND
GNDVCCA_DAC_BG
GND
GND
CRTPLLA PEGA SMTV
POWER
A CK A LVDS
D TV/CRTLVDS
12
C710
0.47U/10V/06
+1.25V_VCCA_DPLLA
+1.25V_VCCA_DPLLB
+1.25V_VCCA_HPLL
+1.25V_VCCA_MPLL
C668
*IV@1000P/04
100mA
12
C150
1U/10V/06
+VCC_TVDACA_R
+VCC_TVDACB_R
+VCC_TVDACC_R
+1.8V_VCCD_LVDS
150mA
R70
EV@0/04
100mA
12
R524
1/F/06
12
C679
10U/6.3V/06
VCCA_CRT_DAC
VCCD_CRT
U34H
J32
A33
B33
A30
B32
B49
H49
AL2
AM2
A41
B41
K50
K49
U51
AW18
AV19
AU19
AU18
AU17
AT22
AT21
AT19
AT18
AT17
AR17
AR16
BC29
BB29
C25
B25
C27
B27
B28
A28
M32
L29
N28
AN2
U48
J41
H42
+1.25V_VCCD_PEG_PLL
12
C85
.1U/10V/04
VCCSYNC
VCCA_CRT_DAC_1
VCCA_CRT_DAC_2
VCCA_DAC_BG
VSSA_DAC_BG
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCCA_LVDS
VSSA_LVDS
VCCA_PEG_BG
VSSA_PEG_BG
VCCA_PEG_PLL
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2
VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2
VCCD_CRT
VCCD_TVDAC
VCCD_QDAC
VCCD_HPLL
VCCD_PEG_PLL
VCCD_LVDS_1
VCCD_LVDS_2
Ball
VCCD_TVDAC
VSS_DAC_BG
VCCSYNC
AXD
VCC_AXD_NCTF
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
SM CK
HV
VCC_RXR_DMI_1
VCC_RXR_DMI_2
DMI
CRESTLINE_1p0
12
C49
0.47U/10V/06
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
AXF
VCC_DMI
VCC_TX_LVDS
VCC_HV_1
VCC_HV_2
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
PEG
VTTLF1
VTTLF2
VTTLF3
VTTLF
Enable
3.3V
1.5V
3.3VVCCD_QDAC
GNDVCCA_TVA_DAC
3.3VVCCA_TVB_DAC
12
U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1
AT23
AU28
AU24
AT29
AT25
AT30
AR29
B23
B21
A21
AJ50
BK24
BK23
BJ24
BJ23
A43
C40
B40
AD51
W50
W51
V49
V50
AH50
AH51
A7
F2
AH1
C666
0.47U/10V/06
Disable
GND
1.5V
GND
GND
GND
12
C76
2.2U/6.3V/06
Place on the edge.
12
C78
0.47U/6.3V/04
Place on the edge.
+1.25V_AXD
12
C137
1U/10V/06
+1.25V_VCC_AXF
+1.25V_VCC_DMI
+1.25V_VCC_DMI
+1.8VSUS_VCC_SM_CK
200mA
+1.8VSUS_VCC_TX_LVDS
+3V_VCC_HV
12
C667
.1U/10V/04
+VCC_RXR_DMI
+VTTLF1
+VTTLF2
+VTTLF3
2
LVDS Disable/Enable guideline
External VGA with EV@part,Internal VGA with IV@ part
Signal
VCCD_LVDS
VCCA_LVDS
VCC_TX_LVDS
If SDVO Disable
LVDS Disable
GND
GND
GND
If LVDS
enable
1.8V
1.8V
1.8V
+3V_VCC_HV
D1
CH751H-40HPT_NC
Ivcc_VTT FSB
12
supply
C686
4.7U/10V/08
12
+
12
+
12
12
C53
220U/4V
C743
*220U/4V
C691
4.7U/10V/08
1 2
C258
22U/10V/12
R508
EV@0/04
+VCC_PEG
current
0.85A
+1.05V
12
+
C24
220U/4V
+VCC_AXD_R
L260/04
Reserved L81 pad for
inductor.
Place caps close
to VCC_AXD.
Ivcc_DMI supply
current 100mA
R5830/08
12
C725
.1U/10V/04
+1.8VSUS_VCC_TX_LVDS
100mA
12
C664
*IV@1000P/04
L8
BLM21PG220SN1D/08
12
C89
10U/6.3V
L21
BLM21PG220SN1D/08
12
C114
10U/6.3V/06
+1.8VSUS_VCC_SM_CK
12
12
C257
22U/10V/12
R1840/08
L64*IV@1UH/08
12
1uH+-20%_300mA
+
C29
*IV@220U
SI-1 modified change
+1.05V
12
C187
+VCC_SM_CK_L
.1U/10V/04
12
+1.05V
1uH+-20%_300mA
R173
1/F/06
C213
10U/6.3V/06
IV&EV Dis/Enable setting
Ivcc_RX_DMI
supply current
250mA
+1.25V
+1.25V
+1.8VSUS_GMCH
12
Ivcc_PEG
supply current
1.2A
L25
1uH/300mA/08
+3V_VCC_HV
R5050/04
+1.25V_VCC_AXF
12
C30
1U/10V/06
Place caps close
to VCC_AXF
12
+1.05V
21
12
R40
10/04
+3V
+1.25V
12
C31
10U/6.3V/06
+1.8VSUS_GMCH
40 mil
wide
+3V_VCC_HV_L
R29
0/08
1
IV&EV Dis/Enable setting
5
4
3
2
NB5/RD1/HW2
PROJECT : AT5
Quanta Computer Inc.
SizeDocument NumberRev
Custom
Crestline (POWER)
Date:Sheet of
1
1048Monday, March 19, 2007
1A
5
4
3
2
1
U34I
A13
VSS_1
A15
VSS_2
A17
VSS_3
A24
VSS_4
AA21
VSS_5
AA24
VSS_6
AA29
VSS_7
DD
CC
BB
AA
AB20
AB23
AB26
AB28
AB31
AC10
AC13
AC3
AC39
AC43
AC47
AD1
AD21
AD26
AD29
AD3
AD41
AD45
AD49
AD5
AD50
AD8
AE10
AE14
AF20
AF23
AF24
AF31
AG2
AG38
AG43
AG47
AG50
AH3
AH40
AH41
AH7
AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28
AK31
AK51
AM11
AM13
AM3
AM4
AM41
AM45
AN1
AN38
AN39
AN43
AN5
AN7
AP48
AP50
AR11
AR2
AR39
AR44
AR47
AR7
AT10
AT14
AT41
AT49
AU1
AU23
AU29
AU3
AU36
AU49
AU51
AV39
AV48
AW1
AW12
AW16
AE6
AL1
AP4
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
CRESTLINE_1p0
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41
U34J
C46
C50
C7
D13
D24
D3
D32
D39
D45
D49
E10
E16
E24
E28
E32
E47
F19
F36
F4
F40
F50
G1
G13
G16
G19
G24
G28
G29
G33
G42
G45
G48
G8
H24
H28
H4
H45
J11
J16
J2
J24
J28
J33
J35
J39
K12
K47
K8
L1
L17
L20
L24
L28
L3
L33
L49
M28
M42
M46
M49
M5
M50
M9
N11
N14
N17
N29
N32
N36
N39
N44
N49
N7
P19
P2
P23
P3
P50
R49
T39
T43
T47
U41
U45
U50
V2
V3
CRESTLINE_1p0
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28
AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50
PROJECT : AT5
Quanta Computer Inc.
SizeDocument NumberRev
Custom
5
4
3
2
NB5/RD1/HW2
Crestline (VSS)
Date:Sheet of
1148Monday, March 19, 2007
1
1A
Strap table
5
All strap are sampled with respect to the leading edge of the GMCH Power OK(PWROK) Signal
CFG[17:3] Have internal Pull-up
CFG[18:19] Have internal Pull-down
Any CFG signal strapping option not list below should be left NC Pin
Pin NameStrap description
DD
CFG[2:0]
CFG[4:3]
CFG5
CFG6
CFG7
CFG8
CFG9
CFG[11:10]
CC
CFG[13:12]
CFG[15:14]
CFG16
CFG[18:17]
SDVO_CTRLDATA
CFG19
CFG20
BB
DMI X2 Select
MCH_CFG_5Low = DMIX2
MCH_CFG_57
High = IDMIX4(Default)
R71
*4.02K/F/04
FSB Dynamic ODT
MCH_CFG_16Low = ODT Disable
AA
MCH_CFG_167
High = ODT Enable(Default)
R81
*4.02K/F/04
5
FSB Frequency Select
Reserved
DMI X2 Select
Reserved
CPU Strap
Low power PCI Express
PCI Express Graphics Lane Reversal
Reserved
XOR/ALLZ
Reserved
FSB Dynamic ODT
Reserved
SDVO Present
DMI Lane Reversal
SDVO/PCIe concurrent
DMI Lane Reversal
MCH_CFG_19Low = Normal operation(Default)
MCH_CFG_197
SDVO/PCIE Concurrent operation
MCH_CFG_20
MCH_CFG_207
4
High = Reverse Lane
+3V
R95
*4.02K/F/04
Low = Only SDVO or PCIE X1 is
operational(Default)
High = SDVO andPCIE X1 are operating
simultaneously via the PEG port
+3V
R82
*4.02K/F/04
4
3
2
Configuration
010 = FSB 800MHz
011 = FSB 667MHz
0 = DMI X2
1 = DMI X4(Default)
0 = Reserved
1 = Mobile CPU(Default)
0 = Normal mode
1 = Low Power mode
0 = Reverse Lanes
1 = Normal operation(Default)
00 = Reserved
01 = XOR Mode Enable
10 = All-Z Mode Enabled
11 = Normal operation(Default)
0 = Dynamic ODT disable
1 = Dynamic ODT Enable(Default)
0 = No SDVO Card present(Default)
1 = SDVO Card Present
0 = Normal operation(Default)
1 = Reverse Lanes
0 = Only SDVO or PCIE x1 is operation(Default)
1 = SDVO and PCIE x1 are operating simultaneously via the PEG port
XOR /ALLz /Clock Un-gating
MCH_CFG_12MCH_CFG_13Configuration
0
0
1
1
MCH_CFG_127
MCH_CFG_137
0
1
0
1
Clock gating disable
XOR Mode Enable
ALL-z Mode Enable
Normal operation(Default)
3
R63
*4.02K/F/04
R80
*4.02K/F/04
PCI Express Graphics
MCH_CFG_9Low = Reverse Lane
High = Normal operation(Default)
MCH_CFG_97
2
SDVO Present
Strap define at External
DVI control page
R61
*4.02K/F/04
PROJECT : AT5
Quanta Computer Inc.
SizeDocument NumberRev
Custom
NB5/RD1/HW2
10 -- GMCH STRAP-3(6 of 6)
Date:Sheet of
1
12
1248Monday, March 19, 2007
1
1A
1
2,5,7,9,10,12,14,15,16,17,20,21,22,23,24,25,26,27,28,29,30,32,33,35,36,37,38,39,40,42,47
2
3
4
5
6
7
8
DDRII DUAL CHANNEL A,B.
AA
13
DDRII A CHANNELDDRII B CHANNEL
M_A_A[13..0]M_B_A[13..0]
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
C325
.1U/10V/04
BB
M_A_ODT07,14
M_A_CKE17,14
M_A_BS#08,14
M_A_RAS#8,14
M_A_BS#18,14
CC
DD
PM_EXTTS#17
1
M_A_WE#8,14
M_A_CAS#8,14
SA_MA147,14
SB_MA147,14
C380
.1U/10V/04
CGCLK_SMB2,14,39
CGDAT_SMB2,14,39
PM_EXTTS#07,14
C384
.1U/10V/04
M_A_ODT0
M_A_A13
M_A_A8
M_A_A5
M_A_A3
M_A_A1
M_A_CKE1
M_A_A11
M_A_A10
M_A_BS#0
M_A_A7
M_A_A6
M_A_A2
M_A_A4
M_A_BS#1
M_A_A9
M_A_A12
PM_EXTTS#1PM_EXTTS#1
C419
.1U/10V/04
R238*0/04
2
C378
.1U/10V/04
.1U/10V/04
RP2156X2
1
3
RP1356X2
1
3
RP1456X2
1
3
RP2356X2
1
3
RP1556X2
1
3
RP2456X2
1
3
RP1856X2
1
3
RP2056X2
1
3
RP2256X2
1
3
RP1656X2
1
3
R74256/04
R74356/04
CGCLK_SMB
CGDAT_SMB
PM_EXTTS#0
8
7
6
4
M_A_A[13..0]8,14 M_B_A[13..0]8,14
C434
.1U/10V/04
SMDDR_VTERM46
C415
C379
.1U/10V/04
.1U/10V/04
C401
.1U/10V/04
C418
.1U/10V/04
C362
.1U/10V/04
.1U/10V/04
SMDDR_VTERM
C363
.1U/10V/04
C361
.1U/10V/04
C360
.1U/10V/04
C383
.1U/10V/04
C332
.1U/10V/04
1.8VSUS
+3V
C320
.1U/10V/04
C321
.1U/10V/04
Layout note: Place one cap close to every 2 pullup resistors terminated to SMDDR_VTERM
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
U12
SCLK
SDA
ALERT#
OVERT#
*LM86CIMM
VCC
DXP
DXN
GND
1
2
3
5
3
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
SI-1 modify
(add
terminater
resistor)
R270
*200/04
LM86_3V
+3V
C437
*.1U/10V/04
DDR_THERMDA
DDR_THERMDC
Uninstall
13
Q13
2
*PMST3904
4
RP3756X2
M_B_BS#18,14
M_B_BS#28,14
M_B_CKE07,14
M_B_RAS#8,14
M_B_CS#07,14
M_B_BS#08,14
M_B_CAS#8,14
M_B_WE#8,14
5
M_B_A0
M_B_A5
M_B_A1
M_B_A8
M_B_A3
M_B_A4
M_B_A2
M_B_A12
M_B_A9
M_B_A7
M_B_A6
M_B_A10
M_A_CS#07,14
M_B_ODT07,14
M_B_ODT17,14
M_B_CS#17,14
M_A_CS#17,14
M_A_ODT17,14
M_B_CKE17,14
M_A_CKE07,14
M_A_BS#28,14
1
3
RP2756X2
1
3
RP2656X2
1
3
RP3656X2
1
3
RP2556X2
1
3
RP3356X2
1
3
RP3156X2
1
3
RP3456X2
1
3
RP2956X2
1
3
RP2856X2
1
3
M_A_A0
M_B_A13
M_ODT3
M_ODT1
M_B_A11
6
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
RP1956X2
1
3
RP3556X2
1
3
RP3056X2
1
3
RP1756X2
1
3
RP3256X2
1
3
RP1256X2
1
3
NB5/RD1/HW2
1.8VSUS7,9,10,14,46
+3V
C353
C318
.1U/10V/04C326
2
4
2
4
2
4
2
4
2
4
2
4
C359
.1U/10V/04
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
C381
C420
.1U/10V/04
.1U/10V/04
SMDDR_VTERM
.1U/10V/04
C382
.1U/10V/04C435
PROJECT : AT5
Quanta Computer Inc.
SizeDocument NumberRev
B
DDRII RES.ARRAY
Date:Sheet of
7
1348Monday, March 19, 2007
8
1A
1
CGCLK_SMB+3V
CGDAT_SMB
M_A_CKE[0..1]
M_A_CS#[0..1]
M_A_RAS#
M_A_CAS#
M_A_WE#
CGCLK_SMB2,13,39
CGDAT_SMB2,13,39
M_A_CKE[0..1]7,13 M_A_CLK07
M_A_CS#[0..1]7,13
M_A_RAS#8,13
M_A_CAS#8,13
M_A_WE#8,13
M_A_CLK0
M_A_CLK0#
M_A_CLK1
M_A_CLK1#
M_A_BS#[0..2]
M_A_ODT[0..1]
2
M_A_CLK0#7
M_A_CLK17
M_A_CLK1#7
M_A_BS#[0..2]8,13 M_A_DQS#[0..7]8
M_A_ODT[0..1]7,13
3
M_A_DQM[0..7]
M_A_DQ[0..63]
M_A_DQS[0..7]
M_A_DQS#[0..7]
M_A_A[13..0]
M_A_DQM[0..7]8
M_A_DQ[0..63]8
M_A_DQS[0..7]8
M_A_A[13..0]8,13
4
M_B_CKE[0..1]
M_B_CS#[0..1]
M_B_RAS#
M_B_CAS#
M_B_WE#
5
M_B_CKE[0..1]7,13
M_B_CS#[0..1]7,13
M_B_RAS#8,13
M_B_CAS#8,13
M_B_WE#8,13
1.8VSUS
M_B_CLK0
M_B_CLK0#
M_B_CLK1
M_B_CLK1#
M_B_BS#[0..2]
M_B_ODT[0..1]
6
+3V2,5,7,9,10,12,13,15,16,17,20,21,22,23,24,25,26,27,28,29,30,32,33,35,36,37,38,39,40,42,47
1.8VSUS7,9,10,46
M_B_CLK07
M_B_CLK0#7
M_B_CLK17
M_B_CLK1#7
M_B_BS#[0..2]8,13
M_B_ODT[0..1]7,13
M_B_DQM[0..7]
M_B_DQ[0..63]
M_B_DQS[0..7]
M_B_DQS#[0..7]
M_B_A[13..0]
7
M_B_DQM[0..7]8
M_B_DQ[0..63]8
M_B_DQS[0..7]8
M_B_DQS#[0..7]8
M_B_A[13..0]8,13
8
14
AA
M_B_DQ1
M_B_DQ4
M_B_DQ2
M_B_DQ3
M_B_DQ5
M_B_DQ0
M_B_DQ7
M_B_DQ6
M_B_DQ13
M_B_DQ12
M_B_DQ10
M_B_DQ11
M_B_DQ8
M_B_DQ9
M_B_DQ15
M_B_DQ14
M_B_DQ21
M_B_DQ17
M_B_DQ19
M_B_DQ23
M_B_DQ20
M_B_DQ16
M_B_DQ18
M_B_DQ22
M_B_DQ28
M_B_DQ29
M_B_DQ27
M_B_DQ26
M_B_DQ24
M_B_DQ25
M_B_DQ31
M_B_DQ30
BB
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_BS#0
M_B_BS#1
M_B_BS#2
M_B_CLK0
M_B_CLK0#
M_B_CLK1
M_B_CLK1#
CGCLK_SMB
CGDAT_SMB
DIM2_SA0
DIM2_SA1
CC
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
107
BA0
106
BA1
85
NC/BA2
30
CLK0
32
CLK0
164
CLK1
166
CKL1
197
SCL
195
SDA
198
SA0
200
SA1
199
VDDSPD
FOX=AS0A426-M2S-TR
CN26A
DIM2_SA0
DIM2_SA1
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0
DQS0
DQS1
PC2100 DDR2 SDRAM SO-DIMM
(200P)
DQS1
DQS2
DQS2
DQS3
DQS3
DQS4
DQS4
DQS5
DQS5
DQS6
DQS6
DQS7
DQS7
CS0
CS1
RAS
CAS
WE
CKE0
CKE1
R26710K/04
R26810K/04
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
10
26
52
67
130
147
170
185
13
11
31
29
51
49
70
68
131
129
148
146
169
167
188
186
110
115
108
113
109
79
80
CKEA 0,1
M_B_DQ36
M_B_DQ33
M_B_DQ35
M_B_DQ39
M_B_DQ37
M_B_DQ32
M_B_DQ34
M_B_DQ38
M_B_DQ40
M_B_DQ41
M_B_DQ46
M_B_DQ43
M_B_DQ45
M_B_DQ44
M_B_DQ47
M_B_DQ42
M_B_DQ55
M_B_DQ49
M_B_DQ51
M_B_DQ53
M_B_DQ48
M_B_DQ52
M_B_DQ50
M_B_DQ54
M_B_DQ61
M_B_DQ60
M_B_DQ59
M_B_DQ63
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ62
M_B_DQM0
M_B_DQM1
M_B_DQM2
M_B_DQM3
M_B_DQM4
M_B_DQM5
M_B_DQM6
M_B_DQM7
M_B_DQS0
M_B_DQS#0
M_B_DQS1
M_B_DQS#1
M_B_DQS2
M_B_DQS#2
M_B_DQS3
M_B_DQS#3
M_B_DQS4
M_B_DQS#4
M_B_DQS5
M_B_DQS#5
M_B_DQS6
M_B_DQS#6
M_B_DQS7
M_B_DQS#7
M_B_CS#0
M_B_CS#1
M_B_RAS#
M_B_CAS#
M_B_WE#
M_B_CKE0
M_B_CKE1
+3V
M_A_DQ1
M_A_DQ5
M_A_DQ3
M_A_DQ2
M_A_DQ4
M_A_DQ0
M_A_DQ7
M_A_DQ6
M_A_DQ13
M_A_DQ8
M_A_DQ15
M_A_DQ10
M_A_DQ9
M_A_DQ12
M_A_DQ14
M_A_DQ11
M_A_DQ16
M_A_DQ21
M_A_DQ23
M_A_DQ19
M_A_DQ20
M_A_DQ17
M_A_DQ18
M_A_DQ22
M_A_DQ24
M_A_DQ28
M_A_DQ31
M_A_DQ30
M_A_DQ25
M_A_DQ29
M_A_DQ27
M_A_DQ26
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_BS#0
M_A_BS#1
M_A_BS#2
M_A_CLK0
M_A_CLK0#
M_A_CLK1
M_A_CLK1#
CGCLK_SMB
CGDAT_SMB
DIM1_SA0
DIM1_SA1
+3V+3V
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
89
107
106
85
30
32
164
166
197
195
198
200
199
R21610K/04
R21710K/04
PC2100 DDR2 SDRAM SO-DIMM
A11
A12
BA0
BA1
NC/BA2
CLK0
CLK0
CLK1
CKL1
SCL
SDA
SA0
SA1
VDDSPD
FOX=AS0A426-MAS-TR
CN24A
SMbus address A0SMbus address A4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS0
DQS0
DQS1
(200P)
DQS1
DQS2
DQS2
DQS3
DQS3
DQS4
DQS4
DQS5
DQS5
DQS6
DQS6
DQS7
DQS7
CKE0
CKE1
DIM1_SA0
DIM1_SA1
M_A_DQ32
123
M_A_DQ35
125
M_A_DQ37
135
M_A_DQ38
137
M_A_DQ33
124
M_A_DQ36
126
M_A_DQ39
134
M_A_DQ34
136
M_A_DQ40
141
M_A_DQ41
143
M_A_DQ46
151
M_A_DQ42
153
M_A_DQ45
140
M_A_DQ44
142
M_A_DQ43
152
M_A_DQ47
154
M_A_DQ52
157
M_A_DQ48
159
M_A_DQ55
173
M_A_DQ54
175
M_A_DQ53
158
M_A_DQ49
160
M_A_DQ50
174
M_A_DQ51
176
M_A_DQ60
179
M_A_DQ56
181
M_A_DQ62
189
M_A_DQ58
191
M_A_DQ57
180
M_A_DQ61
182
M_A_DQ59
192
M_A_DQ63
194
M_A_DQM0
10
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
M_A_DQM1
26
M_A_DQM2
52
M_A_DQM3
67
M_A_DQM4
130
M_A_DQM5
147
M_A_DQM6
170
M_A_DQM7
185
M_A_DQS0
13
M_A_DQS#0
11
M_A_DQS1
31
M_A_DQS#1
29
M_A_DQS2
51
M_A_DQS#2
49
M_A_DQS3
70
M_A_DQS#3
68
M_A_DQS4
131
M_A_DQS#4
129
M_A_DQS5
148
M_A_DQS#5
146
M_A_DQS6
169
M_A_DQS#6
167
M_A_DQS7
188
M_A_DQS#7
186
M_A_CS#0
110
CS0
M_A_CS#1
115
CS1
M_A_RAS#
108
RAS
M_A_CAS#
113
CAS
M_A_WE#
109
WE
M_A_CKE0
79
M_A_CKE1
80
CKEB 0,1
H 5.2H 9.2
SMDDR_VREF_DIMM SMDDR_VREF_DIMM
M_B_ODT0
M_B_ODT1
PM_EXTTS#07,13 PM_EXTTS#07,13
M_B_A13
1
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
VREF
81
VDD_1
82
VDD_2
87
VDD_3
88
VDD_4
95
VDD_5
96
VDD_6
103
VDD_7
104
VDD_8
111
VDD_9
112
VDD_10
117
VDD_11
118
VDD_12
114
ODT0
119
ODT1
50
NC_1
69
NC_2
83
NC_3
84
NC_4/A15
86
NC_5/A14
116
NC_6/A13
120
NC_7
163
NC_8
162
VSS_45
165
VSS_46
168
VSS_47
171
VSS_48
172
VSS_49
177
VSS_50
178
VSS_51
183
VSS_52
184
VSS_53
187
VSS_54
190
VSS_55
193
VSS_56
196
VSS_57
201 202
VSS_58VSS_59
FOX=AS0A426-M2S-TR
CN26B
C771470P/50V/04
SMDDR_VREF_DIMM
1 2
R603*10K/F/06
2
VSS_1
3
VSS_2
8
VSS_3
9
VSS_4
12
VSS_5
15
VSS_6
18
VSS_7
21
VSS_8
24
VSS_9
27
VSS_10
28
VSS_11
33
VSS_12
34
VSS_13
39
VSS_14
40
VSS_15
41
VSS_16
42
VSS_17
47
VSS_18
48
VSS_19
53
VSS_20
54
VSS_21
59
VSS_22
60
VSS_23
65
VSS_24
66
VSS_25
71
VSS_26
72
VSS_27
77
VSS_28
78
VSS_29
121
VSS_30
122
VSS_31
127
VSS_32
PC2100 DDR2 SDRAM
SO-DIMM (200P)
128
VSS_33
132
VSS_34
133
VSS_35
138
VSS_36
139
VSS_37
144
VSS_38
145
VSS_39
149
VSS_40
150
VSS_41
155
VSS_42
156
VSS_43
161
VSS_44
R2260/06
R227
*10K/F/06
1.8VSUS
SI-1 CHANGESI-1 CHANGE
SA_MA147,13SB_MA147,13
SMDDR_VREF7,46
M_A_ODT0
M_A_ODT1
1
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
1.8VSUS
M_A_A13
VREF
81
VDD_1
82
VDD_2
87
VDD_3
88
VDD_4
95
VDD_5
96
VDD_6
103
VDD_7
104
VDD_8
111
VDD_9
112
VDD_10
117
VDD_11
118
VDD_12
114
ODT0
119
ODT1
50
NC_1
69
NC_2
83
NC_3
84
NC_4/A15
86
NC_5/A14
116
NC_6/A13
120
NC_7
163
NC_8
162
VSS_45
165
VSS_46
168
VSS_47
171
VSS_48
172
VSS_49
177
VSS_50
178
VSS_51
183
VSS_52
184
VSS_53
187
VSS_54
190
VSS_55
193
VSS_56
196
VSS_57
201 202
VSS_58VSS_59
FOX=AS0A426-MAS-TR
CN24B
2
VSS_1
3
VSS_2
8
VSS_3
9
VSS_4
12
VSS_5
15
VSS_6
18
VSS_7
21
VSS_8
24
VSS_9
27
VSS_10
28
VSS_11
33
VSS_12
34
VSS_13
39
VSS_14
40
VSS_15
41
VSS_16
42
VSS_17
47
VSS_18
48
VSS_19
53
VSS_20
54
VSS_21
59
VSS_22
60
VSS_23
65
VSS_24
66
VSS_25
71
VSS_26
72
VSS_27
77
VSS_28
78
VSS_29
121
VSS_30
122
VSS_31
127
VSS_32
PC2100 DDR2 SDRAM
SO-DIMM (200P)
128
VSS_33
132
VSS_34
133
VSS_35
138
VSS_36
139
VSS_37
144
VSS_38
145
VSS_39
149
VSS_40
150
VSS_41
155
VSS_42
156
VSS_43
161
VSS_44
1.8VSUS
SMDDR_VREF_DIMM
DD
Place these Caps near So-Dimm1.Place these Caps near So-Dimm2.
C773
2.2U/6.3V/06
C772
.1U/10V/04
C775
2.2U/6.3V/06
C768
2.2U/6.3V/06
C785
2.2U/6.3V/06
C444
2.2U/6.3V/06
+3V
C317
2.2U/6.3V/06
C764
2.2U/6.3V/06
C770
.1U/10V/04
C316
.1U/10V/04
C788
.1U/10V/04
C439
.1U/10V/04
C433
.1U/10V/04
C769
.1U/10V/04
C767
.1U/10V/04
SO-DIMM BYPASS PLACEMENT :
1.8VSUS
C774
2.2U/6.3V/06
SMDDR_VREF_DIMM
C371
.1U/10V/04
C786
2.2U/6.3V/06
C373
2.2U/6.3V/06
C784
2.2U/6.3V/06
C759
2.2U/6.3V/06
+3V
C372
2.2U/6.3V/06
C760
2.2U/6.3V/06
C385
.1U/10V/04
C789
C787
C776
.1U/10V/04
.1U/10V/04
.1U/10V/04
C443
.1U/10V/04
SO-DIMM BYPASS PLACEMENT :
C765
.1U/10V/04
C766
.1U/10V/04
Place these Caps near So-Dimm1.Place these Caps near So-Dimm2
No Vias Between the Trace of PIN to CAP.
1
2
3
4
No Vias Between the Trace of PIN to CAP.
5
PROJECT : AT5
Quanta Computer Inc.
SizeDocument NumberRev
Custom
6
NB5/RD1/HW2
DDRII SO-DIMM(200P)
Date:Sheet of
7
1448Monday, March 19, 2007
8
1A
5
15mil
IFPA_IOVDD
YELLOW BLOCK is
for G8X chip
only
AC9
AD9
AF9
AF8
15mil
AM4
AL5
+1.8V
80mA
+2.5V
DD
45mA
SI-2 change to bead
L12BLM18PG330SN1D /06
L17*BLM18PG330SN1D /06
C164470P/50V
C1514700P/25V
C10210U/6.3V/06
C86220U/6.3V
+
C152470P/50V
C1604700P/25V
+1.8V
C10110U/6.3V/06
L11BLM18PG330SN1D /06
T195
T196
IFPAB_PLLVDD
IFPABVPROBE
IFPABRSET
15mil
BLM18PG330SN1D /06
DACA_VDD
+3V
L10
C180470P/50V
C1814700P/25V
C10010U/6.3V/06
AD10
15mil
15mil
120mA
DACA_VREF
DACA_RSET
DACB_VDD
DACB_VREF
DACB_RSET
IFPCDVPROBE
IFPCDRSET
IFPCD_PLLVDD
IFPC_IOVDD
IFPD_IOVDD
15mil
DACC_VD
NV_PLLVDD
DISP_PLLVDD
15mil
AH10
AH9
AG9 AH12
V8
R5
R7
V7
AK3
AH3
AA10
AB10
AD6
AE7
AD7
AH4
AF5
T9
T10
U10
C167.01U/16V
R572124/F/04
+3V
CC
+1.8V
40mA
+2.5V
300mA
L14
L19
IFPC_DVI_3V
15mil
BLM18PG330SN1D /06
*BLM18PG330SN1D /06
C163470P/50V
C1714700P/25V
C17710U/6.3V/06
L69BLM18PG330SN1D /06
C130470P/50V
C1354700P/25V
C71110U/6.3V/06
R15310K
L15BLM18PG330SN1D /06
C149470P/50V
C1574700P/25V
C17610U/6.3V/06
C153.01U/16V/04
R155124/F/04
C136.01U/16V
R150*1K
15mil
need add to 3v
R15610K
VGA1.2V
L16BLM18PG330SN1D /06
+2.5V
40mA
BB
40mA
VGA1.2V
L13*BLM18PG330SN1D /06
L20*BLM18PG330SN1D /06
+2.5V
L24BLM18PG330SN1D /06
YELLOW BLOCK is
for G8X chip
only
C154.1U/10V/04
C1654700P/25V/04
C14310U/6.3V/06
C183.1U/10V/04
C1844700P/25V/04
C17910U/6.3V/06
4
U37D
IFPAB_PLLVDD
IFPAB_PLLGND
IFPA_IOVDD
IFPB_IOVDD
IFPAB_VPROBE
IFPAB_RSET
DACA_VDD
DACA_VREF
DACA_RSET
DACA_IDUMPDACA_BLUE
DACB_VDD
DACB_VREF
DACB_RSET
DACB_IDUMP
IFPCD_VPROBE
IFPCD_RSET
IFPCD_PLLVDD
IFPCD_PLLGND
IFPC_IOVDD
IFPD_IOVDD
DACC_VDD
DACC_VREF
DACC_RSET
PLLVDD
VID_PLLVDD
PLLGND
U_GPU_G3
LVDS
DACA_HSYNC
CRT
DACA_VSYNC
DACA_GREEN
DACB_GREEN
TV
TMDS
DACC_HSYNC
DAC
DACC_VSYNC
DACC_GREEN
XTALOUTBUFF
XTAL
IFPA_TXC#
IFPA_TXC
IFPA_TXD0#
IFPA_TXD0
IFPA_TXD1#
IFPA_TXD1
IFPA_TXD2#
IFPA_TXD2
IFPA_TXD3#
IFPA_TXD3
IFPB_TXC#
IFPB_TXC
IFPB_TXD4#
IFPB_TXD4
IFPB_TXD5#
IFPB_TXD5
IFPB_TXD6#
IFPB_TXD6
IFPB_TXD7#
IFPB_TXD7
I2CA_SCL
I2CA_SDA
DACA_RED
DACB_RED
DACB_BLUE
IFPC_TXC#
IFPC_TXC
IFPC_TXD0#
IFPC_TXD0
IFPC_TXD1#
IFPC_TXD1
IFPC_TXD2#
IFPC_TXD2
IFPD_TXC#
IFPD_TXC
IFPD_TXD4#
IFPD_TXD4
IFPD_TXD5#
IFPD_TXD5
IFPD_TXD6#
IFPD_TXD6
I2CB_SCL
I2CB_SDA
DACC_RED
DACC_BLUEDACC_IDUMP
XTALSSIN
XTALIN
XTALOUT
AJ9
AK9
AJ6
AH6
AH7
AH8
AK8
AJ8
AH5
AJ5
AL4
AK4
AM5
AM6
AL7
AM7
AK5
AK6
AL8
AK7
K2
J3
AF10
AK10
AH11
AJ12
R6
T5
T6
AM3
AM2
AE1
AE2
AF2
AF1
AH1
AG1
AH2
AG3
AJ1
AK1
AL1
AL2
AJ3
AJ2
H4
J4
AG7
AG5
AF6
AG6
AE5AG4
T2
T1
U1
U2
5ppm
C_TXLCLKOUTC_TXLCLKOUT+
C_TXLOUT0C_TXLOUT0+
C_TXLOUT1C_TXLOUT1+
C_TXLOUT2C_TXLOUT2+
C_TXUCLKOUTC_TXUCLKOUT+
C_TXUOUT0C_TXUOUT0+
C_TXUOUT1C_TXUOUT1+
C_TXUOUT2C_TXUOUT2+
C_TXUOUT3C_TXUOUT3+
L_DDCCLK
L_DDCDAT
CRT_HSYNC
CRT_VSYNC
L_CRT_R
L_CRT_G
L_CRT_B
L_S-CD1
L_S-YD1
L_S-CVBS1
TXC_HDMITXC_HDMI+
TX0_HDMITX0_HDMI+
TX1_HDMITX1_HDMI+
TX2_HDMITX2_HDMI+
IFPD_TCX-
IFPD_TC4IFPD_TC4+
IFPD_TC5IFPD_TC5+
IFPD_TC6+
HDMI_SCL
HDMI_SDA
DAC_HSYNC
DAC_VSYNC
DAC_RED
DAC_GRN
DAC_BLU
XTALO_GPU
GFX_27MSS
EVGA-XTALI
EVGA-XTALO
C708
27P/04
3
L_CRT_R
L_CRT_G
L_CRT_B
L_S-CD1
L_S-YD1
L_S-CVBS1
Close to GPU
T70
T72
R1040/04
R1050/04
R1300/04
R1180/04
R970/04
R980/04
R990/04
R1090/04
R1100/04
R1110/04
DDCCLK
DDCDATA
HSYNC_COM
VSYNC_COM
CRT_R
CRT_G
CRT_B
S-CD1
S-YD1
S-CVBS1
FOR G72M/G73M only
TXC_HDMI-26
TXC_HDMI+26
TX0_HDMI-26
TX0_HDMI+26
TX1_HDMI-26
TX1_HDMI+26
TX2_HDMI-26
TX2_HDMI+26
T193
T179
T169
T183
T171
T181
HDMI_SCL26
HDMI_SDA26
T71
T55
T59
T45
T46
R55922/04
R560*10K/04
2 1
27MHZ
27M_BUFO
Y5
C706
27P/04
R120150/F/04
R121150/F/04
R122150/F/04
R129150/F/04
R127150/F/04
R128150/F/04
DDCCLK7,25
DDCDATA7,25
HSYNC_COM7,25
VSYNC_COM7,25
CRT_R7,25
CRT_G7,25
CRT_B7,25
S-CD17,25
S-YD17,25
S-CVBS17,25
2
OPTION SIGNAL FROM NB FOR UMA VGA
TXLCLKOUT+
TXLCLKOUT-
TXLOUT0+
TXLOUT0TXLOUT1+
TXLOUT1-
TXLOUT2+
TXLOUT2-
TXUCLKOUTTXUCLKOUT+
TXUOUT0+
TXUOUT0TXUOUT1+
TXUOUT1-
TXUOUT2TXUOUT2+
RP60*4P2R-S-0
3
1
RP54*4P2R-S-0
1
3
RP55*4P2R-S-0
3
1
RP58*4P2R-S-0
1
3
RP4*4P2R-S-0
3
1
RP6*4P2R-S-0
1
3
RP10*4P2R-S-0
3
1
RP8*4P2R-S-0
1
3
OPTION SIGNAL FROM Nvidia to VGA
+5V
C_TXLCLKOUT+
C_TXLCLKOUTC_TXLOUT0C_TXLOUT0+
C_TXLOUT1C_TXLOUT1+
C_TXLOUT2C_TXLOUT2+
C_TXUCLKOUTC_TXUCLKOUT+
C_TXUOUT0C_TXUOUT0+
C_TXUOUT1C_TXUOUT1+
C_TXUOUT2+
C_TXUOUT2-
C341
*1U/04
RP594P2R-S-0
3
1
RP114P2R-S-0
1
3
RP564P2R-S-0
1
3
RP574P2R-S-0
3
1
RP34P2R-S-0
3
1
RP54P2R-S-0
3
1
RP94P2R-S-0
1
3
RP74P2R-S-0
3
1
C34: PUN issue reserve
U54,C950,c949,R726,R727
U9
3 4
VINVOUT
1
SHDN
2
GND
SET
*G923
1
4
2
2
4
4
2
2
4
4
2
2
4
4
2
2
4
4
2
2
4
2
4
4
2
4
2
4
2
2
4
4
2
5
LA_CLK
LA_CLK#
LA_DATAP0
LA_DATAN0
LA_DATAP1
LA_DATAN1
LA_DATAP2
LA_DATAN2
LB_CLK#
LB_CLK
LB_DATAP0
LB_DATAN0
LB_DATAP1
LB_DATAN1
LB_DATAN2
LB_DATAP2
Ra
R191
*86.6K/F/04
R195
*49.9K/04
TXLCLKOUT+26
TXLCLKOUT-26
TXLOUT0-26
TXLOUT0+26
TXLOUT1-26
TXLOUT1+26
TXLOUT2-26
TXLOUT2+26
TXUCLKOUT-26
TXUCLKOUT+26
TXUOUT0-26
TXUOUT0+26
TXUOUT1-26
TXUOUT1+26
TXUOUT2+26
TXUOUT2-26
3V_IFPC
C339
*1U/04
LA_CLK7
LA_CLK#7
15
LA_DATAP07
LA_DATAN07
LA_DATAP17
LA_DATAN17
LA_DATAP27
LA_DATAN27
LB_CLK#7
LB_CLK7
LB_DATAP07
LB_DATAN07
LB_DATAP17
LB_DATAN17
LB_DATAN27
LB_DATAP27
Rb
Vout=1.25(1+Ra/Rb)
C342
.1U/16V/04
2 1
L350/06
L37*0/06
Q10
3
AO3409
VGA_GD#
R19610K/04
3
Q9
2N7002E
1
2
R605
0/06
15mil
1
IFPC_DVI_3V
FOR IFPC VDD LEAKAGE CIRCIUT
5
+3V
R192
10K/04
AA
2
IPFC_C
+3V
3V_IFPC
R549
10K/04
EDIDCLK7,16,26
EDIDDATA7,16,26
4
SPREAD SPECTRUM
+3V
ICSS_PD
27M_BUFO
EDIDCLK
EDIDDATA
U32
8
PD#
1
CLKIN
7
SCL
6
SDA
ICS91730AMLF-T
VDD
CLKOUT
REFOUT
GND
I2C ADDRESS: 0xD4H
2
4
ICSS_RFO
5
3
R532
10K/04
+3V
R529
10K/04
R53022/04
GFX27M_L
3V_SSC
C698
470P/50V/04
C699
.1U/10V/04
GFX_27MSS
C707
10P/50V/04
C705
4.7U/10V/08
PV-2 Modify
R5334.7/06
C704
4.7U/10V/08
+3V
PROJECT : AT5
Quanta Computer Inc.
SizeDocument NumberRev
Custom
3
2
NB5/RD1/HW2
NVG73M (LVDS/DVI/CRT/TV)
Date:Sheet of
1548Monday, March 19, 2007
1
1A
Loading...