HP DV52112BR Schematic

THIS DRAWING AND SPECIFICATIONS, HEREIN, ARE THE PROPERTY OF INVENTEC

CORPORATION AND SHALL NOT BE REPODUCED, COPIED, OR USED IN WHOLE OR

IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT

DATE

AMD DANUBE PLATFORM

CHANGE NO.

REV

SI - R Build

U811 Hynix DDR3 6019B0647101 R1206 Install , R1186 Open U811 Samsung DDR3 6019B0648501 R1206 Open , R1186 Install

U805 Change to 6019B0653601 CN804 Change to 6026B0184301 CN807 Change to 6026B0184301 CN808 Change to 6026B0121002

DRAWER DESIGN CHECK RESPONSIBLE

SIZE = FILE NAME :

P/N

XXXXXXXXXXXX

EE POWER

3

XXXX-XXXXXX-XX

2009/12/21

DATE

VER :

DATE

TITLE

SIZE

A3

INVENTEC

ST145a-UMA

Project Name

DOC. NUMBER REV

CODE

Model_No X01

CS

SHEET

511

OF

Index Of Content

PAGE

01- Project Name 02- Index

03- Block Diagram 04- Power Procedure 05- NOTE

06- DC & BATTERY CHARGER 07- BATTERY CONN 08- +V5A & +V3A & +V2.5S 09- +V1.2A & +VCC_NB 10- +VCC_CORE & +VCC_CORE_NB 11- +V1.1S & +V1.1A & +V1.05S 12- NOTE 13- +V1.5 & +V1.8S 14- POWER (SLEEP) 15- CLK GEN-RTM880N 16- CPU-1

17- CPU-2 18- CPU-3 19- CPU-4 20- FAN & THERMAL IC 21- RS880M-1 22- RS880M-2 23- RS880M-3

PAGE

24- RS880M-4 25- DDR3 DIMM0

26- DDR3 DIMM1 27- DDR3 SIDE-PORT 28- SB820M-1

29- SB820M-2 30- SB820M-3 31- SB820M-4 32- SB820M-5 33- CRT 34- NOTE 35- LCM 36- HDMI 37- KBC 38- Keyboard CONN & Indicate LED 39- Card reader

40- SATA HDD & SATA ODD CONN 41- Touch screen & FingerPrint CONN 42- ESATA CONN & USB Board CONN 43- LAN 44- RJ45 CONN 45- AUDIO CODEC & SPEAKER CONN 46- HP JACK & MIC JACK 47- NOTE 48- WLAN & BLUETOOTH 49- WWAN

PAGE

50- NOTE 51- USB BOARD & BUTTON BOARD

52- HDD Board & ODD Board

CHANGE by

ALAN W 27-Jul-2009

INVENTEC

TITLE

ST145a-UMA

Index

DOC. NUMBERSIZE

CODE

A3

Model_No X01

CS

SHEET

OF

REV

512

Inventec Confidential

PCB STACK UP

LAYER 1 : TOP LAYER 2 : GND LAYER 3 : IN1 LAYER 4 : IN2

LAYER 5 : VCC

LAYER 6 : BOT

FINGER PRINT

TOUCH SCREEN

MAIN BATT

P.07

System Charger &

DC/DC System power

USB_6

CLK GEN

REA-RTM880N-796

WEB CAM

P.42

USB_7

P.42

P.06

P.16

USB_4

P.36

USB_8

MINI CARD

CONN

(WWAN)

SIMCARD

CONN

P.50

CARD READER

P.50

Speaker

DMIC

P.47

P.36

Thermal Sensor

HDMI

LCM

VGA

USB_3

USB2 CONN

(DB)

P.50

USB_1

AU6433

5 in 1

Conn

P.40

AUDIO CODEC

IDT 92HD80B1

HP JACK

P.47

P.20

P.37

P.36

P.35

USB_2

USB1 CONN

(DB)

P.50

BLUE TOOTH

MIC JACK

USB_2

P.47

TMDS

LVDS

CRT

USB2.0

P.49

638 P(PGA) 45W/35W

Side-port

Memory

128MB

HDA

AMD

Champlain

S1G4 Processor

35mm X 35mm

Transport 3

P.16~19

Hyper

P.21~24

AMD

RS880M

A12

21mm X 21mm, 528pin BGA

DDR3

P.26

A-link X 4

P.29~33

AMD

SB820M

21mm X 21mm, 528pin BGA

A12

4.5W (Ext)

4.3W (Int)

Keyboard

P.39

DDR3

PCI_EXPRESS

REALTEK

GIGA RTL8111DL-VB-GR

SATA SMBus

Accelerometer

LPC

KBC

ITE 8502E-KX

TouchPad

SYSTEM

P.39

CHANGE by OF

X1

LAN

RJ45

P.38

SPI

BIOS

channel A

channel B

PCIE_0

P.44

P.40

P.38

DDR III _SODIMM0

DDR III _SODIMM1

P.43

HDD

ALAN W 29-Nov-2009

Half MINI CARD

SATA_0

P.40

P.27

P.28

X1

PCIE_1 USB_8

CONN

(WLAN)

SATA_1

ODD

P.40

TITLE

SIZE

A3

P.48

SATA_2

USB_0

ESATA

P.42

INVENTEC

ST145a-UMA

Block Diagram

DOC. NUMBER

CODE

Model_No X01

CS

SHEET

513

REV

Adapter

(65W)

ADP_PRES

CHGCTRL_3

Selector

(Discrete)

Charger

(BQ24721C)

+VBDC

+VBADC

+VBATR

CHGCTRL_3

I_ADP

BATT_CLK

BATT_DATA

ADP_IP

ACOK

Main Battery

ALWAYS_EN

+V5A

+V1.2A_PG

VRM_PWRGD

VCC_NB_PG

RESUME_PWEN

5V/3.3V

(TPS51125)

+V1.1A

(TPS51117)

NB POWER

I/O POWER

(TPS51117)

DDR POWER

(Max17000ETG)

I = 0.02A

I = 0.05A

I = 8.6A

I = 9.593A

I = 7.42A

+V1.1A

+V0.75S

I = 1A

APL5610C

VRM_PWRGD

+VCC_NB

I = 9A

+V1.5

+V5AL

+V3AL

+V5A

+V3A

I = 7.6A

AM3402N

+V1.1S

CORE_PWEN#

AM3402N

CORE_PWEN#

AM3402N

CPU_VDDR

RT8015AP

+V1.8S

RT8015AP

I = 6.8A

+V1.5S

+V5S

I = 2.53A

+V3S

CPU_VDDR

I = 1.5A

+V1.8S

I = 1.3A

I = 1.23A

I = 2.6A

+V2.5S

(APL5315)

+V2.5S

I = 0.25A

+VDD_CORE

VGA POWER

(TPS51511)

VGAVCC_EN

VPCIE_SW

POW_SW1

SVC

SVD

CPU_PWEN

VRM_PWRGD

AMD Griff

MAX17480

+VDD_CORE

+VDDNB_CORE

I = 38A

I = 4A

CHANGE by

INVENTEC

TITLE

ST145a-UMA

Power Procedure

CODE

CS

SHEET

DOC. NUMBER

REV

451

X01Model_No

OF

SIZE

10-Aug-2009ALAN W

A3

SB800

3

SB_PWRBTN#

SLP_S3#

SLP_S5#

4

KBC

ITE8502E

1

ALWAYS_PW_EN

5

CORE_PWEN

5

RESUME_PWEN

TPS51125

MAX 17000E

2

+V3A

+V5A

+V1.5

+V0.75S

+V1.1A

2

TPS51117

3

V1.1A_PG

6

5

CORE_PWEN#

5

CORE_PWEN#

7

CORE_PWEN_D#

7

CPU_PWEN

RT8015A

MOSFET

SWITCH

RT8015A

MAX 17480G

+V1.8S

+V5S

+V3.3S

+V1.5S

CPU_VDDR

VDD_CORE

VDDNB_CORE

6

10

9

VRM_PWRGD

8

VRM_PWRGD

TPS51117

9

MOSFET

VCC_NB

10

+V1.1S

SWITCH

INVENTEC

TITLE

ST145a-UMA

Power Sequence

CHANGE by

ALAN W 13-Aug-2009

SIZE

A3

CODE

CS

SHEET

DOC. NUMBER

Model_No X01

REV

515

OF

POWER ON SEQUENCW REQUIRED. SB820M

1. +V3.3A RAMP BEFORE +V1.1A

2. +V3.3S RAMP BEFORE +V1.8S

3. +V1.8S RAMP BEFORE +V1.1S

4. +V3.3S RAMP BEFORE +V1.1S

5. VDDIO_33_S RAMPING DOWN TIME <= 300uS

6. 50uS <= ALL POWER RAILS EXPECT VDDIO_33_S <= 40mS

7. 100uS <= VDDIO_33_S <= 40mS

RS880M

1. 0 <(+V3.3S) - (+V1.8S) < 2.1

2. +V1.8S RAMP BEFORE +V1.1S

3. +V1.1S RAMP BEFORE VCC_NB

SB_PWRGD

ALL_PWGD_IN

VCC_NB_PG

VCC_NB

10mS

GROUP B

GROUP A

CPU MEM CTL &

DDR3_SODIMM PWRS

CPU_THM/SB/SB_SCL1/2 SB_KB/SPI/LPC ROM PWRS

KBC IS READY

KBC IS POWERED BY +V3AL

+V1.1S/+VLDT

VRM_PWRGD

CPU_VDDR

VDD_CORE

VDDNB_CORE

+V2.5S

(CPU_VDDA_2.5_RUN)

+V1.8S

+V3S/+V5S/+V1.5S

CORE_PWEN

SLP_S3#

M_VREF/+0.75S

+V1.5

(CPU_VDDIO_SUS)

RESUME_PWEN

SLP_S5#

SB_PWRBTN#

RSMRST#

DUAL RAILS

ALWAYS_PW_EN

EC_PWRBTN#

AC_OK

(AC_IN DETECT)

+V3AL/+V5AL

5ms

POWER BUTTON PRESSED

+VIN/+19V

CHANGE by

ALAN W 17-Aug-2009

INVENTEC

TITLE

ST145a-UMA

CPU_VDDR & +V1.1A & +V1.1S

CODE

SIZE

A3

DOC. NUMBER

Model_No X01

CS

SHEET

OF

REV

516

R849

1

100K_1%

2

R847

1

26.7K_1%

2

+VADP

7-

PWR-E

R848

1

200K_1%

2

R845

1

24.3K_1%

2

DGND

R846

1

26.7K_1%

2

DGND

SINGA_2WA1554_107111_7P

DGND PWR-A PWR-A PWR-A

1

R841 1K_1%

2

R842

1

13.7K_1%

2

DGND

Q815

FDMC8884

CN802

G1

AC IN_90W_5A

G

1

2

3

4

5

6

7

G2

G

37-

ADP_ID

N E P

1

V

5

O

5

8

_

2

1

C

V

_

0

F

5

u

_

2

1

2

F

. 0

p 0 0 2

2

RF

765

8

D

Q809

G

FDMC8884

S

4

123

L803

PWR-B

12

PCMB103T_8R2MS

8765

N

1

E

9

D

9

OP

8

_

G

2

R 0 4

2

0

N E

1

PWR-B

OP

5

RF

_

41S23

CHANGE by

2

0

2

9

0

C817

C

4 0

DGND

1

2

4.7uF_25v

R850

1

10K_5%

2

C847

56pF_50v

C846

1

0.0015uF_50V

2

CELLSEL#=0,Vcharger=12.6V CELLSEL#=1,Vcharger=16.8V

ALAN W 27-Jul-2009

AMBER

AC_LED

CN539 Pin6

WHITE

9 cell_2.8AHr_93W_8.78A

+VBATR

9-,10-,11-,12-,13-,35-,47-

PWR-A

1 2

7

5

2

5

v

8

5

C

2

C

2

1

_

F

u

7

.

2

.

4

DGND

PWR-E

1

2

Icharger=3A

v 5 2

1

_ F u 7

2

. 4

1

2

C860

4.7uF_25v

3 5 8 C

CHARGE_GND

2

1

N

1

E

4

P

1

O

C

1

_

V

0

5

2

_

F

p

3

RF

R852

12

34

0.01_1%

C900

0.1uF_16v

1

C901

1

2

0.1uF_25V

3

1

2

C814

0.1uF_16V

1

2

DGND

2

C899

1

2

PWR-A

0.1uF_25V

CHARGE_GND

Note:

high power trace

INVENTEC

TITLE

ST145a-UMA

DC & BATTERY CHARGER

CODE

SIZE

A3

CS

SHEET

CHG_LED# CN539 Pin5

Q801

S

G

AM7331P

C816 C859

4.7uF_25v

0.1uF_25V

DOC. NUMBER

Model_No

D

1

2

C898

+VBDC

8 7 6 54

1

2

PWR-A

CHARGE_GND

OF

8-

PWR-E

517

REV

X01

AC IN

+V3AL

7-,8-,9-,29-,37-

PWR-B

1SS355W

D800

21

PWR-A

AMBER#

WHITE#

1

2

3838-

C843

0.0015uF_50V

DGND

PWR-E

C842

0603_OPEN

PWR-A

12

ANALOG_AM7333P_POWER33_8P

Q808

D8

1S 2

7 3 4

PWR-E 6 5

G

DGND

C838

10pF_50v

1 2

DGND

+VADP

7-

1

2

0.1uF_25V

C836

DGND

L802

NFM60R30T222

12

3

4

DGND

1

R837 15K_5%

2

+VADPTR

1 2

C837 10pF_50v

+VADPTR

1

2

DGNDDGND

PWR-E

C839

0.1uF_25V

C811

1uF_25v

1

2

1

2

DGND

C834

C835

0.1uF_25V

1

2

prevent KBC latchup

1

2

D804

13

R896

1

33K_5%

2

Q800

D

S

8

1 2

7

3

6 5

4

G

ANALOG_AM7333P_POWER33_8P

PWR-B

C904

0.1uF_16v

1

2

12

C903

1uF_25v

1

R843 18K_5%

2

R844

1

200K_5%

2

1

C845

2

100pF_50v

SYS

PH

SRP SRN BAT

EAO

EAI

FBO

TML

DGND

PWR-A

2

23

24

32

30

29

PWR-A

12

31

PWR-A

28

27 26

DGND 22 21 20 19 18

7

8 9

16 33

PWR-E

C90212

0.1uF_25V

R904

PWR-A

12

1K_5%

R898

0_5%

PWR-A

PWR-A PWR-A

PWR-A

DGND

C812

0.1uF_16V

R901

12

1K_5%

PWR-A

BAT54_30V_0.2A

PWR-A

R840

2

1 34

0.01_1%

1

C844

C841

C840

1

2

DGND

AC_OK

0.1uF_25V

2

0.1uF_25V

37-

PWR-A

R892

1

47K_5%

PWR-A

2

R890

1

100K_5%

2

R889

1

20_5%

2

C896

1

2

0.47uF_25V

C848

0.1uF_25V

DGND

C895

1

1uF_10v

2

33uF_25v

ADP_PRES

37-

PWR-APWR-A

1

2

R897

12

1K_5%

PWR-A

12 C849

0.1uF_16v

1

R891 100K_1%

2

PWR-A

1

R895 100K_1%

2

1

C850

2

0.1uF_25V

DGND

PWR-A

12

11

10

15

14 13 25

17

U802

VCC

3

ACN

4

ACP

6

BYPASS#

5

ACDET

VREF5

AGND

TS

1

CHGEN#

SCL SDA ALARM#

IOUT

TI_BQ24721C_QFN_32P

PWR-E

A

R W

P

ACDRV#

BATDRV#

PVCC

HIDRV

BTST

REGN

LODRV

PGND SYNP SYNN

ISYNSET

PAD5001

POWERPAD1x1m

CHARGE_GND

I_ADP

CHARGE_GND

BATT_CLK

BATT_DAT

CHG_EN#

PWR-A

37-

8-,37-

PWR-B

+V3AL

7-,8-,9-,29-,37-

SMBUS

R851

12

200K_5%

R894

12

10_5%

R893

12

10_5%

PWR-A

CHARGE_GND

1

2

PWR-A

C897

0.1uF_10V

37-

9cell_2.8AHr_93W_8.78A

BATT_DAT BATT_CLK

BATT_ID

BATT_A_IN#

7-,377-,373737-

7-,8-,9-,29-,37-

+V3AL

9 9 V A

PWR-B

B _

O K M N E H C

DGND

+VBDC

7-

CN800

1

2

3

4

5

G1

6

G

6

G2

7

G

7

8

P

2 _ 3 2 5 D O

S

1

_

4

3

B

0

B

9

1

D

S 0 V

1

5 D S E

2

P

2

_

C815

P

0.1uF_25V

H P

DGND

8

FOX_BP02083_B69B5_7H_8P

DGND

INVENTEC

TITLE

ST145a-UMA

BATTERY CONN

CODE

CS

SHEET OFCHANGE by

DOC. NUMBER REV

851

X01Model_No

SIZE

27-Jul-2009ALAN W

A3

PWR-B

DGND

+V3AL

3

1

8 C

2

7-,8-,9-,29-,37-

1

R1400 100K_5%

2

N E P O

_ 2 0 4 0

12

R807

1

R805 R803

1

R801

1

4

6

V

5

0

8

5

C

1

_ F p

2 0 0 1

DGND

8

V

5

0

8

5

C

1

_

F

p

2

0

1

DGND

+V3AL

7-,8-,9-,29-,37- 7-,8-,9-,29-,37-

PWR-B

2009/10/14

1

R806

R802

2.2K_5%

2

7-,8-,9-,29-,37-

+V3AL

1

2

1

9 9 V

3

A

PWR-B

B _

0 0

O

9

K

D

2

M N E H C

DGND

+V3AL

9

9 V

3

A B _

1 0

O

8

K

2

D

M N E H

DGND

C

7-,8-,9-,29-,37-7-,8-,9-,29-,37-

+V3AL

1

3

1

PWR-B

9 9 V

3

A B

DGND

3

_

0 8

O

D

K

2

M N E H C

2 0 8 D

+V3AL

PWR-B

1

R804 100K_5%

2

100_5% 100_5%

2

100_5%

2

PWR-A

2

100_5%

P 2 _ 3 2 5 D O S _ B B 1 S 0 V 5 D S E P _ P H P

PWR-A

P

2

_

3

2

5

D

O

S

1

_

1

B

0

B

9

1

D

S 0 V 5 D S E P

2

_ P H P

DGND

1

_

2

B

0

B

9

1

D

S 0 V 5 D S E P

2

2 _ P H P

2009/11/26

Typ@9.6A

+V3A OCP = 6.2A

Vout=(R1266/R1267+1)*2

+V3A

11-,13-,14-,18-,29-,30-,31-, 32-,33-,35-,40-,41-,43-,47-,48-

PAD804

POWERPAD_2_0610

C1333

10uF_6.3V

1

2

ALWAYS_PW_EN

1

C1359

DGND

330uF_6.3V

2

37-

RF

PCMC063T_3R3MN

1

R1266

6.8K_1%

2

1

R1267 10K_1%

2

PWR-A

51125GND

R1262

12

0_5%

R1261

10K_5%

DGND

7-,9-,10-,11-,12-,13-,35-,47-

N E

4

5

P

7

O

3

_

1

V

C

1

0 5 _

2

F p 0 0

2 2

L851

12

N E

2009/12/21

OP _ V 5 2 _ F u

C2000

1 .

4.7uF_25v

0

1

2

PWR-C

1

2

N E

OP _ 2 0 4

0 N E

OP _ 2 0 4 0

RF

R1305 100K_5%

Q840

SSM3K7002FU

1

C1327

1 2

0.1uF_16V

DGND

2009/11/07

+VBATR

8/14

1

AON7410

2

C1380

4.7uF_25v

1

1 2 3 1

SI7716ADN_T1_GE3

R

2

1

0 0

2

4 1 C

+V5AL

PWR-A

9-

1

2

3

D

G

S

2

DGND

Typ@0.05A

D

Q850

S

D

Q851

S

PWR-A

8

123

765

8

12

765

G

DGND

3

4

U825

1

S1

2

G1

6

D1

3

D2

5

G2

4

S2

2N7002DW

+V3AL

7-,8-,9-,29-,37-

C1358

1

10uF_6.3V

DGND

2

C1357

0.1uF_16V

R1311

12

PWR-C

0_5%

12

RICH_RT8205EGQW_WQFN_24P

9-

7-,9-,10-,11-,12-,13-,35-,47-

DGND

2VREF

R1268

95.3K_1%

51125GND

R1308

12

0402_OPEN

DGND

7 8

PWR-C

10 11

PWR-C

R1309

12

330K_5%

R1310 1M_5%

C1356

4.7uF_25v

PWR-A

1

2

VREG3 BOOT2

PHASE2 LGATE2

PWR-A

1

R1263

90.9K_1%

2

PWR-APWR-A

51125GND

R1306

0_5%

1

2

1 P

I R

T N E

VOUT1VOUT2

BOOT1

C N

8

7

1

R1301

1

0402_OPEN

2

+V5AL+VBATR

1

2

2VREF

9-

C1328

1

PWR-A

2

51125GND

24 23

R1304

12

229

PWR-C

21

0_5%

20 1912

PWR-C

2009/11/07

+V3AL

Typ@0.02A

9-

C1355

10uF_6.3V

DGND

CHENMKO_BAV99

0.22uF_6.3v

POWERPAD1x1m

PAD5002

C1354

PWR-C

12

7-,8-,9-,29-,37-

1

%

0

5

1

_

5

K

1

0

R

0

2

1

2

0.1uF_16V

R1303

1

0_5%

2

C1352

0.1uF_16V

3

CHENMKO_BAV99

1

8/14

PWR-C

2

5 2

3

4

6

5

1

2

D

F

L

P

E

B

N

I

F

S

R

G

R

N

T

O

N

T

E

PGOOD

U826

UGATE1UGATE2 PHASE1 LGATE1

L E

5

S

G

P

D

E

I

N

R

I

N

K

G

V

E

S

5

6

3

4

1

D N G D

1

2

1

DGND

2

D826

C1350

1

2

0.1uF_25V

DGND DGND DGND DGND

8765

D

Q848

G

AON7410

41S23

765

8

D

Q849

G

SI7716ADN_T1_GE3

41S23

DGND

R1302

12

0_5%

2

C1349

1

2

0.1uF_25V

+VBATR

7-,9-,10-,11-,12-,13-,35-,47-

C1379

1

2

4.7uF_25v

DGND

PWR-C

N E

OP _ 2 0 4

0 N E

1

OP _

2 2 0 4

0

DGNDDGND

C1353

1

2

0.1uF_16V

3

1

D825

C1378

1

2

4.7uF_25v

DGND

L850

12

PCMC063T_3R3MN

1

8 3 3 1 R

2

9 9 3 1 C

RF

10-

2009/11/07

C1351

1

2

1uF_25V

N

E 7 7 3

OP 1

_

V

C

1

5

2

_

2

F

u

1

RF

+V1.1A_EN

+V15A

. 0

14-,40-

R1299

1

5.1M_5%

2

1 2

DGND

N E

6

P

7

O

3

_

1

V

C

0 5 _ F p 0 0

2 2

1

R1265

15.4K_1%

2

1

R1264

10K_1%

2

PWR-A

51125GND

10-,11-,12-,13-,14-,35-,36-,37-,38-,42-,47-

1

C1373

2

330uF_6.3V

DGND

Typ@8.6A

+V5A OCP = 6.8A

Vout=(R1265/R1264+1)*2

+V5A

PAD806

PWR-E

C1398

1

10uF_6.3V

2

POWERPAD_2_0610

INVENTEC

TITLE

ST145a-UMA

+V3.3A & +V5A & +V2.5S

DOC. NUMBERSIZE

CODE

A3

CS

CHANGE by OF

27-Jul-2009ALAN W

SHEET

951

REV

X01Model_No

2009/11/07

+V1.1A_EN

RSMRST#

9-

31-,37-

R1298

0_5%

12

R1293

0_5%

12

C1326

1

C1348

1

2

0402_OPEN

2

1uF_6.3v

DGND

+V1.2S_GND

12-,14-,20-,23-,24-,26-,27-,29-,30-,31-,32-,33-,35-,36-,37-,38-,39-,40-,41-,43-,45-,48-

+V3S

1

C1066

2

10uF_6.3v

V1.1A_PG

PWR-A

0.1uF_16V

U824

1

EN_PSV

2

TON

3

VOUT

4

V5FILT

5

VFB

6

PGOOD

7

GND

TI_TPS51117_QFN_14P

PWR-B

R1066

12

10K_5%

2009/09/28

C1501

R1296

2

1

10_5%

R1297

12

180K_5%

PAD5003

POWERPAD1x1m

1

2

+V5A

9-,11-,12-,13-,14-,35-,36-,37-,38-,42-,47-

PWR-E

R1260

0_5%

12

14

VBST

13

DRVH

12

LL

11

TRIP

10

V5DRV

9

DRVL

8

PGND

15

TML

DGND

1

DGND

2

C1324

1uF_6.3v

ANPEC_APL5315_BI_TRL_SOT23_5P

5

8/14

Q838

SI7716ADN_T1_GE3

R1259

10.7K_1%

5

SETSHDN

G

4

G

4

C1325

0.1uF_16V

12

1

PWR-A

2

+V1.2S_GND

U815

1

2

GND

34

VIN

VOUT

76

8

D

Q839

AON7410

S

123

8

765

D

S

123

DGND

R1002

1

22K_1%

2

R1062

1

10K_1%

2

DGND

+VBATR

7-,9-,11-,12-,13-,35-,47-

1

C1323

C1320

2

DGND

4.7uF_25v

L845

12

PCMC063T_2R2MN

N

1

E

3 0

OP

2

_

1

2

R

0 4

2

0

C1301

N E

1

330uF_2.5V

0

OP

0

_

2

3

2

1

0

C

4 0

DGND

RF

Typ@0.25A

Vout=(R1002/R1062)*0.8

+V2.5S

18-

C1061

10uF_6.3v

1

2

N

E

1

2

P

2

O

3

OP

1

_ V

C

1

5 2 _

2

F u 1

. 0

RF

1

DGND

R1295

5.11K_1%

+V1.2S_GND

2

R1294

1

10K_1%

2

1

2

_

1

V

C

1

0

2

DGND

C1347

1

2

0402_OPEN

5 _ F p 0 0 2 2

POWERPAD_2_0610

Typ@ 7.42A

+V1.1A OCP = 9A

Vout=(R1295/R1294)*0.75

+V1.1A

14-,32-

PAD803

CHANGE by

INVENTEC

TITLE

ST145a-UMA

+V1.2A & VCC_NB

SIZE

CODE

27-Jul-2009ALAN W

A3

DOC. NUMBER

CS

SHEET OF

10 51

REV

X01Model_No

CORE_PWEN

RESUME_PWEN

DEFAULT_NET_TYPE

11-,37-

37-,38-

R853

12

0_5%

R900

12

0_5%

C906

0.1uF_10V_OPEN

DEFAULT_NET_TYPE

C1502

1

2

DGND

0.1uF_10V_OPEN

DGND

+V5A

9-,10-,11-,12-,13-,14-,35-,36-,37-,38-,42-,47-

PWR-A

R854

12

C907

1uF_6.3v

1

2

PWR-A

DEFAULT_NET_TYPE

3300pF_50v

1

C864

2

MAX_MAX17000ETG+_TQFN_24P

PAD5004

POWERPAD1x1m

17000GND

10_5%

DGND

C908

1

DGND

2

U801

1

OVP

TON

BST

DH

2

PGOOD1

3

LX

PGOOD2

19

VDD

DL

PGND1

CSH

23

VCC

CSL

21

FB

AGND

4

STDBY

24

SHDN

VTTI

22

SKIP

PGND2

10

VTT

REFIN

VTTS

25

GND

VTTR

NOTE: DDR3 REGULATOR

2.2uF_6.3v

14 17 15

16

18 20

13 12

11

9

7 8 5 6

10uF_6.3v

PWR-A

R857

0_5%

12

PWR-A

1

2

C865

DGND

R858

1

150K_5%

1

DGND

2

10uF_6.3v

2

DGND

C863

C867

0.1uF_16V 2

+V0.75S

PWR-A

26-,27-

1

2

C861

10uF_6.3v

+VBATR

7-,9-,10-,12-,13-,35-,47-

1

RF

N E

OP _ 2 0 4

2

0 N E

1

OP _

2 2 0 4 0

DGND

1

DGND

2

PCMC063T_1R0MN

1

R925

2

3K_1%

0 9 R

2

C866

9 0 9 C

0.22uF_16v

12

5

76

8

8/14

D

G

S

123

4

6

5

87

D

G

DGND

41S23

Q817

AON7410

1

PWR-D

Q816

FDS6680S

M_VREF

26-,27PWR-A

C868 C869

4.7uF_25v

L805

2009/09/09

R926

12

1K_1%

12

1 2

N E

1 7

OP _

8

V

C

5 2 _ F u 1

. 0

RF

PWR-D

R855

5.36K_1%

R856 10K_1%

1 2

DGND

PWR-A

17000GND

N E P

0

O

7

_

8

V

C

0 5 _ F p 0 0

2 2

1

2

1

PWR-A

2

C8621

0.33uF_10V

2

PWR-A

17000GND

+V1.5 OCP = 10.2A

Vout=(R855/R856+1)*1

12-,14-,18-,19-,26-,27-,32-,33-

+V1.5

PAD801

POWERPAD_2_0610

1

C929

330uF_2V_15mR_Pana_-35%

2

DGND

PWR-D

Typ@9A

CORE_PWEN

9-,10-,11-,12-,13-,14-,35-,36-,37-,38-,42-,47-

R1501

12

11-,37-

10K_5%

C1500

0.1uF_10V

SSM3K7002FU

1

2

DGND

+V5A

% 5 _

M 1

Q856

3

D

1

G

S

2

2009/09/09

9-,13-,14-,18-,29-,30-,31-,32-,33-,35-,40-,41-,43-,47-,48-

1

0 0 5 1 R

2

R1083

750K_1%

1

DGND

DEFAULT_NET_TYPE

RICH_RT8015APQW_WDFN_10P

1

SHDN-RT

2

GND

3

LX

U816

4

LX

5

PGND

COMP

PVDD PVDD

FB

VDD

GND

DGND

+V3A

PWR-D

10 9

12

8 7

R1080

6 11

10_5%

L828

C1150

1

2

2.2uF_6.3v

DGND

12

LTF5022T_2R2N3R2_LC

2009/09/18

R1081

1000pF_50V

10K_5%

12

C1151

1

2

1

R1082 309K_1%

2

C1153

22uF_6.3V

DGND

12

240K_1%

C1152

1

0402_OPEN

2

1

2

R1079

18-,21-,23-,24-,31-

+V1.8S

PWR-D

Vout=(R1082/R1079+1)*0.8

1

C1154

DGND

22uF_6.3V

2

Typ@1.3A

TITLE

CHANGE by SHEET

ALAN W

27-Jul-2009

INVENTEC

ST145a-UMA

DDR3 POWER

CODE

SIZE REV

A3

DOC. NUMBER

Model_No X01

CS

OF

5111

+V1.5

1

2

10-,14-,20-,23-,24-,26-,27-,29-,30-,31-,32-,33-,35-,36-,37-,38-,39-,40-,41-,43-,45-,48-

MAX17480

VRM_PWRGD

VRD_PROCHOT#

OCP@4A

Typ@4A

VDDNB_CORE

18-,19-

PWR-D

C918

1

C917

2

C919

47uF_6.3V 47uF_6.3V 47uF_6.3V

SVC

SVD1VDD_CORE

0

1 0

1

11-,12-,14-,18-,19-,26-,27-,32-,33-

C824

0.1uF_10V CPU_PWRGD_SVID_REG

+V5A

+V3S

1

R819

4.7K_5%

2 1318-

PCMC063T_1R0MN

1

2

R918

12

0_5%

PWR-A

C888

4700pF_50V

1

2

1

2

1.1V

1.0V0

0.9V

0.8V

C831

2.2uF_6.3V

MAX17480

CPU_SVC_R CPU_SVD_R

CPU_PWEN

DEFAULT_NET_TYPE

9-,10-,11-,12-,13-,14-,35-,36-,37-,38-,42-,47-

R825

1

100K_5%

2

MAX17480

L804

12

R882 511_1%

PWR-A

12

C889

0.22uF_16V

R919

C890

10_5%

1000pF_50V

R920

12

5.1K_5%

1

R874

2

143K_1%

1

R872

100K_1%

12

100K_5%

2

1818-

18-

12

13-,37-

R869

100_1%

PWR-E

R826

1

2

PWR-A

2

C884

1

2

2200pF_50V

1

2

1

R827

13K_1%

2

R870 2_5%

POWERPAD1x1m

MAX_MAX17480GTL+_TQFN_40P

2

1

R871

45.3K_1%

DEFAULT_NET_TYPE

R873

12

0_5%

CPU-I

+V5A

C887

10uF_6.3V

9-,10-,11-,12-,13-,14-,35-,36-,37-,38-,42-,47-

2

1

2

C886

0.1uF_10V

C885

12

PWR-A

0.1uF_16V

PWR-A

PAD800

(Should routed in 5/5/5 pair and need to have 10mil clearance to other traces.)

RF

VDD_CORE

12-,19-

PWR-E

1

18-

N

E

P

8

9

O

0

O

_

8

_

V

C

1

0

5

2

_

2

F

p

u

0

1 .

0

2 2

41S23

G

41S23

8765

D

G

S

123

4

8D765

G

S

3

4

12

(Should routed in 5/5/5 pair and need to have 10mil clearance to other traces.)

C810

0.1uF_16V

2

C830

2200pF_50V

R821

3.01K_1%

2

C826

2200pF_50V

8/13

2

R820

1

PWR-A

MAX17480

+V5A

1

2

12

R800

1

12

VDD_CORE

12-,19-

1

R816

0402_OPEN

0.0047uF_50v

2

C823

C828

4.7uF_6.3V

R830

1

3.01K_1%

E

1

R

R817

W P

51_5%

2

C827

2

1

2

R828

1

100_1%

2

0.0047uF_50v

18-

VDD1_FB

0.1uF_16V

1

R829

3.01K_1%

2

PWR-A

1

C832

2

MAX17480

R832

1

100_1%

1

C833

0.0047uF_50v

2

MAX17480

R831

2

R833

1

51_5%

2

51_5%

VDD0_FB

VDD0_FB#

DH1

LX1

DL1

DH2

LX2

DL2

27

29

28

26

33

34

18

17

23

21

22

24

36

35

37

15

16

14

1

18-

VDD1_FB#

9-,10-,11-,12-,13-,14-,35-,36-,37-,38-,42-,47-

R824 0_5%

0_5%

1

2

1

3.01K_1%

R823

12

10_5%

2

5

3

2

U800

39

C

D

BST1

OSC

C

TIME

ILIM12

VDDIO

SVC SVD

PGD_IN SHDN

OPTION

PWRGD VRHOT

THRM

ILIM3

IN3 IN3

LX3 LX3

BST3

OUT3

AGDN

V

+V1.5

D V

CSP1

CSN1

CSP2

CSN2

BST2

FBAC1

FBDC1

GNDS1

FBAC2

FBDC2

D N G

GNDS2

P

1 4

11-,12-,14-,18-,19-,26-,27-,32-,33-

R822

12

10_5%

40

1

13

12 11

19

8

38

20 30

31

2

3 4

5 6

7

9

10

G

1

2

Q802

FDMS8692

Q803

FDS6680S

8765

D

Q805

FDMS8692

8765

D

Q804

FDS6680S

C803

4.7uF_25v

7-,9-,10-,11-,12-,13-,35-,47-

C806

1

2

4.7uF_25v

+VBATR

7-,9-,10-,11-,12-,13-,35-,47-

C802

1

2

4.7uF_25v

+VBATR

PWR-A

C821

1

PWR-A

2

330pF_50V

1

C807

C805

1

2

1

3 1 8 R

2

2 2 8 C

RF

1

2

100uF_25V

C804

4.7uF_25v

C818

2

1

R818

1.5K_5%

2

N

E

P

0

1

O

0

O

_

8

_

V

C

1

0

5

2

_

2

F

p

u

0

1 .

0

2 2

2

N E P O _ 2 0 4

0 N E

1 P O _

2 2 0 4 0

RF

R811

1

1.5K_5%

2

C820

330pF_50V

1

R810

2.4K_1%

2

4.02K_1%

1

N

1 E P

2 1

O

8

_ 2

R 0 4

2

0

N E

1 P O

1

9

_

2

1

2

8

0

C

4

2

0

RF

C829

12

R815

12

10K_1%_THER_NTC

4.02K_1%

1

R814

2.4K_1%

2

L801

1

ETQP4LR45XFC

330uF_2V_6mR_OPEN

Typ@38A

L800

ETQP4LR45XFC

12

R808

R809

12

2

10K_1%_THER_NTC

C825

12

0.22uF_10v

R868

12

2

C880

OCP@45A

VDD_CORE

C883

330uF_2V_6mR

VDD_CORE

12-,19-

1

2

C881

2

330uF_2V_6mR

12-,19-

1

2

1

C882

2

330uF_2V_6mR

MAX17480

CHANGE by

ALAN W 27-Jul-2009

INVENTEC

TITLE

ST145a-UMA

+VCC_CORE & +VCC_CORE_NB

SIZE

A3

DOC. NUMBERCODE

Model_No X01

CS

SHEET

OF

REV

5112

VRM_PWRGD

DEFAULT_NET_TYPE

VCC_NB_PG

12-

14-

2009/09/28

R1068

47K_5%

2

R1106

0_5%

12

8/17

C1128

0.1uF_10V

1

DEFAULT_NET_TYPE

1

2

1

2

+VCC_NB_GND

CPU_PWEN

C1171

1uF_6.3v

1 2 3 4 5 6 7

TI_TPS51117_QFN_14P

R1504

12

12-,37-

10K_5%

R1105

12

10_5%

R1067

12

180K_5%

EN_PSV TON VOUT

U819

V5FILT VFB PGOOD GND

PAD5005

POWERPAD1x1m

2009/09/28

C1601

1000pF_50V

2

+V5A

14

VBST

13

DRVH

12

LL

11

TRIP

10

V5DRV

9

DRVL

8

PGND

15

TML

+V5A

9-,10-,11-,12-,13-,14-,35-,36-,37-,38-,42-,47-

% 5

_ M

1

Q857

3

D

1

G

S

2

SSM3K7002FU

1

9-,10-,11-,12-,13-,14-,35-,36-,37-,38-,42-,47-

8/14

R1108

C1172

0_5%

0.1uF_16V

12

FDMS0310S

Q830

1

C1173

1

2

1

3 0 5 1 R

2

1uF_6.3v

PWR-A

+VCC_NB_GND

750K_1%

R1107

2

3.92K_1%

R1060

12

DEFAULT_NET_TYPE

+VBATR

7-,9-,10-,11-,12-,35-,47-

1

C1197

8D765

4.7uF_25v

Q832

AON7410

N E

OP _ 2 0 4 0

N E

OP _ 2 0 4 0

COMP

PVDD PVDD

1

2

VDD

GND

2

PCMC063T_1R0MN

1

9 0 1 1 R

2

6 7 1 1 C

RF

10 9

FB

8

PWR-D

7 6 11

G

S

4

123

6

8

7

5

D

G

S

4

3

2

1

12/22

U814

RICH_RT8015APQW_WDFN_10P

1

SHDN-RT

2

GND

3

LX

4

LX

5

PGND

PWR-C

L824

12

LTF5022T_2R2N3R2_LC

1

C1198

4.7uF_25v

2

L830

12

C1199

330uF_2.5V

R1104 CHANGE TO 13.3K

VCC_NBSTRP_DATA

0

1.25

10.95

+V3A

9-,11-,14-,18-,29-,30-,31-,32-,33-,35-,40-,41-,43-,47-,48-

PWR-D

R1064

10K_5%

12

PWR-A

12

R1063

10_5%

C1127

2.2uF_6.3V

1

2

SSM3K7002FU

8/17

VDDR_0.9_EN

29-

C1051

22uF_6.3V

2009/09/28

R1104

10K_1%

1

2

23.2K_1%

PWR-A

Q827

1

G

N

E 4 7 1

OP 1

_

V

C

1

5 2 _

2

F u 1

. 0

RF

1

2

1

R1102

PWR-A

2

+VCC_NB_GND

C1126

1000pF_50V

12

3

D

S

2

1

R998

20.5K_1%

2

1

2

5 7 1 1 C

1 2

PWR-A

R1061

1

31.6K_1%

2

C1052

22uF_6.3V

VCC_NB OCP = 10A

N E P O _ V 0 5 _ F p 0 0 2 2

MAX 10A

Typ@7.6A

VCC_NB

24-,47-

PAD802

POWERPAD_2_0610

Vout={R1104/[(R1100+R1099+R1101)//R1102]}*0.75

PWR-A

R1101

1

226K_1%

PWR-A

2

PWR-A 2

12

5.1K_1%

C1169

11

2

4700pF_25V

R1100

R1099

1

16.2K_1%

C1170

2

0.0015uF_50V

R1065

12

100K_1%

Typ@1.5A

C1124

1

Vout=(R1061/R1065)*0.8

2

0402_OPEN

+V1.05S

CPU_VDDR

18-,19-

0.9_EN

0

1

CHANGE by

Power State

UVD Moe - High

UVD Mode - Low

Performance Mode

Battery Mode

Power State

UVD Moe - High

UVD Mode - Low

Performance Mode

Battery Mode

R1098

1

10K_5%

2

CPU_VDDR

1.05

0.9

RS880M

Enging Clock

500 MHz

380 MHz

500 MHz - 200MHz

200MHz

High Performance Variant

RS880M

Enging Clock

380 MHz

200MHz

23-

STRP_DATA

ALAN W 27-Jul-2009

Northbridge

Core Voltage

1.1 V

0.95 V

1.1 V

0.95 V

Northbridge Core Voltage

1.25 V590 MHz 550 MHz / 400 MHz

0.95 V

1.25 V590 MHz - 200MHz

0.95 V

STRP_DATA

0

UVD Clocks

550 MHz / 400 MHz

400 MHz / 300 MHz

n / a

UVD Clocks

400 MHz / 300 MHz

n / a

VCC_NB

1.1

0.951

INVENTEC

TITLE

ST145a-UMA

CODE

SIZE

A3

DOC. NUMBER

Model_No X01

CS

SHEET

OF

REV

5113

CORE_PWEN#

9-,11-,13-,18-,29-,30-,31-,32-,33-,35-,40-, 41-,43-,47-,48-

1

C1381 2200pF_50V

2

+V3A

PWR-D

Q843

6

D

S

5 2 1

G

AO6402AL

2009/11/29

R1323

V3_EN

12

34-

0_5%

DEFAULT_NET_TYPE

+V5A

9-,10-,11-,12-,13-,35-,36-,37-,38-,42-,47-

Q847

6

S

D

5 2 13

G

AO6402AL

R1320

12

V5_EN

0_5%

10-,12-,14-,20-,23-,24-,26-,27-,29-,30-,31-,32-,33-,35-,36-,37-,38-,39-,40-,41-,43-,45-,48-

100_5%

12

R1147

R1146

R1179

100_5%

12

100_5%_OPEN

2

1

+V15A

9-,14-,40PWR-A

1

R1322

750K_5%

2

+V15A_RC

Q852

14-,37-

V35_EN

SSM3K7002FU

L

H

L

V1.1A_PG

VCC_NB_PG

SYS_RST#

D

1

G

S

+V3S & +V5S

3V & 5V

0V

10-

13-

31-

3

2

10-,12-,14-,20-,23-,24-,26-,27-,29-,30-,31-,32-,33-,35-,36-,37-,38-,39-,40-,41-,43-,45-,48-

+V3S

470 OHM

1

R1325

470_5%

2

NA

3

D

Q853

SSM3K7002FU

S

2

+V5S

20-,34-,35-,36-,38-,40-,41-,45-,47-

Typ@2.72A

1

2

PWR-D

4

3

1

G

Typ@2.6A

4

1

2

PWR-E

470 OHM

1

R1300

470_5%

2

NA

3

D

1

G

Q842

SSM3K7002FU

S

2

+V3S

PWR-D

2

R1149 10K_5%

1

C1258 1000pF_50V

2

C1382

10uF_6.3V

C1372

10uF_10V

37-

ALL_PWGD_IN

CORE_PWEN#

CORE_PWEN_D#

14-,37-

37-

DEFAULT_NET_TYPE

Q818

SSM3K7002FU

1

G

SSM3K7002FU

+V15A

D

S

9-,14-,40-

PWR-A

1

R903

1M_5%

2

3

2

9-,14-,40-

Q837

1

G

+V15A

D

S

+V1.5

1

C910 3300pF_50V

2

PWR-A

1

R1204

1M_5%

2

3

2

11-,12-,18-,19-,26-,27-,32-,33-

PWR-D

Q820

6

4

S

D

5 2 13

G

AO6402AL

V1.5_EN

2009/11/12

+V1.1A

10-,32-

PWR-D

Q835

8

D

7 6 5

G

SI7716ADN_T1_GE3

1

C1302 2200pF_50V

2

S

+V1.5S

1

G

1 2 3 4

18-,24-,25-,45-,47-,48-

PWR-C

1

2

470 OHM

1

R905

470_5%

2

3

D

Q819

SSM3K7002FU

S

2

Typ@6.8A

+V1.1S

1

2

3

D

1

G

S

2

Typ@1.23A

C911 10uF_6.3V

NA

18-,19-,21-,22-,23-,24-,32-,47-

1

C1260

10uF_6.3V

2

470 OHM

R1181

470_5%

NA

Q836

SSM3K7002FU

CHANGE by

ALAN W 27-Jul-2009

INVENTEC

TITLE

ST145a-UMA

+V5S & +V3.3S & +V1.5S & +V1.2S

DOC. NUMBER

CODE

SIZE

A3

Model_No X01

CS

SHEET

OF

REV

5114

ALAN W 21-Dec-2009

INVENTEC

TITLE

ST145a-UMA

CLK GEN

SIZE CODE REV

A3

DOC. NUMBER

Model_No X01

CS

SHEET

5115

OFCHANGE by

L0_CLKIN1H

L0_CLKIN1L

L0_CLKIN0H

L0_CLKIN0L

L0_CTLIN1H

L0_CTLIN1L

L0_CTLIN0H

L0_CTLIN0L

L0_CADIN15H

L0_CADIN15L

L0_CADIN14H

L0_CADIN14L

L0_CADIN13H

L0_CADIN13L

L0_CADIN12H

L0_CADIN12L

L0_CADIN11H

L0_CADIN11L

L0_CADIN10H

L0_CADIN10L

L0_CADIN9H L0_CADIN9L L0_CADIN8H L0_CADIN8L

L0_CADIN7H L0_CADIN7L L0_CADIN6H L0_CADIN6L L0_CADIN5H L0_CADIN5L L0_CADIN4H L0_CADIN4L L0_CADIN3H L0_CADIN3L L0_CADIN2H L0_CADIN2L L0_CADIN1H L0_CADIN1L L0_CADIN0H L0_CADIN0L

CN810-1

21212121-

21212121212121212121212121212121-

21212121212121-

2121212121212121-

J5

L0_CLKIN_H1

K5

L0_CLKIN_L1

J3

L0_CLKIN_H0

J2

L0_CLKIN_L0

P3

L0_CTLIN_H1

P4

L0_CTLIN_L1

N1

L0_CTLIN_H0

P1

L0_CTLIN_L0

N5

L0_CADIN_H15

P5

L0_CADIN_L15

M3

L0_CADIN_H14

M4

L0_CADIN_L14

L5

L0_CADIN_H13

M5

L0_CADIN_L13

K3

L0_CADIN_H12

K4

L0_CADIN_L12

H3

L0_CADIN_H11

H4

L0_CADIN_L11

G5

L0_CADIN_H10

H5

L0_CADIN_L10

F3

L0_CADIN_H9

F4

L0_CADIN_L9

E5

L0_CADIN_H8

F5

L0_CADIN_L8

N3

L0_CADIN_H7

N2

L0_CADIN_L7

L1

L0_CADIN_H6

M1

L0_CADIN_L6

L3

L0_CADIN_H5

L2

L0_CADIN_L5

J1

L0_CADIN_H4

K1

L0_CADIN_L4

G1

L0_CADIN_H3

H1

L0_CADIN_L3

G3

L0_CADIN_H2

G2

L0_CADIN_L2

E1

L0_CADIN_H1

F1

L0_CADIN_L1

E3

L0_CADIN_H0

E2

L0_CADIN_L0

FOX_PZ63823_284S_41F_TEMP_638P

T R O P S N A R T R E P

Y H

L0_CLKOUT_H1 L0_CLKOUT_L1 L0_CLKOUT_H0 L0_CLKOUT_L0

L0_CTLOUT_H1 L0_CTLOUT_L1 L0_CTLOUT_H0 L0_CTLOUT_L0

L0_CADOUT_H15 L0_CADOUT_L15 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H10 L0_CADOUT_L10

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H0

L0_CADOUT_L0

Y4 Y3 Y1 W1

T5 R5 R2 R3

T4 T3 V5 U5 V4 V3 Y5 W5 AB5 AA5 AB4 AB3 AD5 AC5 AD4 AD3

T1 R1 U2 U3 V1 U1 W2 W3 AA2 AA3 AB1 AA1 AC2 AC3 AD1 AC1

21-

L0_CLKOUT1H

21-

L0_CLKOUT1L

21-

L0_CLKOUT0H

21-

L0_CLKOUT0L

21-

L0_CTLOUT1H

21-

L0_CTLOUT1L

21-

L0_CTLOUT0H

21-

L0_CTLOUT0L

21-

L0_CADOUT15H

21-

L0_CADOUT15L

21-

L0_CADOUT14H

21-

L0_CADOUT14L

21-

L0_CADOUT13H

21-

L0_CADOUT13L

21-

L0_CADOUT12H

21-

L0_CADOUT12L

21-

L0_CADOUT11H

21-

L0_CADOUT11L

21-

L0_CADOUT10H

21-

L0_CADOUT10L

21-

L0_CADOUT9H

21-

L0_CADOUT9L

21-

L0_CADOUT8H

21-

L0_CADOUT8L

21-

L0_CADOUT7H

21-

L0_CADOUT7L

21-

L0_CADOUT6H

21-

L0_CADOUT6L

21-

L0_CADOUT5H

21-

L0_CADOUT5L

21-

L0_CADOUT4H

21-21-

L0_CADOUT4L

21-

L0_CADOUT3H

21-

L0_CADOUT3L

21-

L0_CADOUT2H

21-

L0_CADOUT2L

21-

L0_CADOUT1H

21-

L0_CADOUT1L

21-

L0_CADOUT0H

21-

L0_CADOUT0L

A1

AF1

S1

Top View

A26

Layout: Add stitching caps if crossing plane split.

CHANGE by

ALAN W 27-Jul-2009

INVENTEC

TITLE

ST145a-UMA

CPU-1

CODE

SIZE

A3

DOC. NUMBER

Model_No X01

CS

SHEET

OF

REV

5116