Microsoft, Windows, Windows NT, Windows NT Server and Workstation, Microsoft SQL Server
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for Windows NT are trademarks and/or registered trademarks of Microsoft Corporation.
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PCI Bus Balancing and Optimization on Compaq
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ProLiant Servers
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First Edition (March 1998)
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Document Number: ECG073/0398
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, PERFORMANCE, OR USE OF THIS MATERIAL.
, NOR FOR
ECG073/0398
2
NOTE:Table 1 lists the
Compaq Pr oLiant fami ly of
servers that embody the
dual-peer P C I bus architecture.
NOTE:Table 1 lists the
Compaq Pr oLiant fami ly of
servers that embody the bridged
PCI bus ar chitecture.
WHITE PAPER (cont.)
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EXECUTIVE SUMMARY
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With the in t roduction of the Compaq ProLiant 5000 Server and its dual-peer PCI (Peripher a l
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Component Interconnect) bus architecture, Compaq recommended certain configurations to
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balance the load between the two PCI buses and achieve optimal performance on the server.
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Customers now question what load balancing means, how it affects server performance and what
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to consider for future planning and implementation of PCI bus loading.
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This white paper identifies the overall importance of PCI bus balancing and provides technical
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configurations for achieving high performance and availability on bridged and dual-peer PCI bus
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architectures. The supporting facts presented along with recommendations will assist system
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administrators and network operators in attaining and maintain in g th is goal.
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PCI ARCHITECTURE
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Two basic architectures are used to connect the primary and secondary PCI bus to the host bus:
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the dual-peer PCI bus or the bridged PCI bus. The dual-peer bus architecture, as shown in
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Figure 1, provides two PCI buses independently linked to the host processor bus by means of two
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Host-to-PCI Bridges. Since each PCI bus runs independently, it is possible to have two PCI bus
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masters transferring data simultaneously thus producing more overall throughput. This is an
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advantage with systems that have two or more high-bandwidth peripherals. Splitting these
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peripherals between the two buses provides an uniformed load.
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Processors
Slots
Figure 1: Dual-peer PCI architecture.
The bridged PCI architecture, as shown in Figure 2, requires all processed transactions on the
bridged PCI bus (the secondary bus) to go through the PCI-to-PCI Bridge to reach the primary
bus, then through the Host-to-PCI Bridge. In effect there is only one path to the host bus;
therefore, no load balancing is required on a system with this type of architecture.
133 MB/s133 MB/s
Secon dary PCI Bus
Bridge
Host Bus
Host Bus
540 MB/s
Host-
Host-
to-PCI
to-PCI
PCI-to-EISA
Bridge
Primary PCI Bus
Bridge
33 MB/s
EISA Bus
Memory
Slots
Slots
ECG073/0398
3
WHITE PAPER (cont.)
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ProcessorsMemory
Figure 2: Bridged PCI architecture.
Knowing what PCI bus specific slots are assigned can be difficult to determine; therefore, Table 1
lists the slots for Compaq PCI bridged and dual-peer PCI servers and which bus they populate.
Use this matrix to identify which slot is assigned to the primary or secondary bus.
For any servers not listed, refer to the server user guide for the slot information or the Compaq
and Microsoft Windows NT Frontline Partnership web site located at: