HP C7S14A User Manual

Board Specification

TESLA K20 GPU ACCELERATOR

BD-06455-001_v05 | November 2012

Updated Table 4

• Changed Gen3 to Gen2

• Removed “Preliminary Information” from

DOCUMENT CHANGE HISTORY

BD-06455-001_v05

Version Date Authors Description of Change

01 August 1, 2012 GG, SM Preliminary Information (Information contained

within this document is subject to change)

02 September 6, 2012 GG, SM

03 September 7, 2012 GG, SM

04 October 9, 2012 GG, SM

05 November 9, 2012 GG, SM

• Updated “Key Features” section

• Updated Figure 1

• Updated Table 1

• Updated “Standard I/O Connector Placement”

section

•

• General edits throughout this specification

• Updated block diagram (Figure 1)

• Added memory bandwidth

• Changed idle power to 25 W

document as this board specification is now final

• Removed “NVIDIA Confidential” from document

• Updated package size

• Updated block diagram (Figure 1)

Tesla K20 GPU Accelerator BD-06455-001_v05 | ii

TABLE OF CONTENTS

Overview ........................................................................................... 1

Key Features ..................................................................................... 1

Tesla K20 Block Diagram ....................................................................... 2

Configuration .................................................................................... 3

Mechanical Specifications ....................................................................... 4

PCI Express System ............................................................................. 4

Tesla K20 Bracket ............................................................................... 5

Power Connectors ............................................................................... 6

Power Specifications ............................................................................. 9

Support Information ............................................................................. 10

Certificates and Agencies ..................................................................... 10

Agencies ...................................................................................... 10

Languages ....................................................................................... 11

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LIST OF FIGURES

Figure 1. Tesla K20 Block Diagram ............................................................ 2

Figure 2. Tesla K20 GPU Accelerator .......................................................... 4

Figure 3. Tesla K20 Bracket .................................................................... 5

Figure 4. 6-Pin PCI Express Power Connector ................................................ 6

Figure 5. 8-Pin PCI Express Power Connector ................................................ 7

LIST OF TABLES

Table 1. Board Configuration .................................................................. 3

Table 2. 6-Pin PCI Express Power Connector Pinout ....................................... 8

Table 3. 8-Pin PCI Express Power Connector Pinout ....................................... 8

Table 4. Auxiliary Power Connectors ......................................................... 9

Table 5. Languages Supported ............................................................... 11

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OVERVIEW

The NVIDIA® Tesla® K20 graphics processing unit (GPU) accelerator is a PCI Express,
dual-slot full height (4.376 inches by 10.5 inches by 1.52 inches) form factor computing
module comprising of a single GK110 GPU. The Tesla K20 is designed for servers and
offers a total of 5 GB of GDDR5 on-board memory and supports PCI Express Gen2.

The Tesla K20 can be configured by the OEM or by the end user to enable or disable
ECC or error correcting codes that can fix single-bit errors and detect double-bit errors.
Enabling ECC will cause some of the memory to be used for the ECC bits, so the user
available memory will decrease by 10%. On the Tesla K20, the register files, cache, and
DRAM are ECC protected.

KEY FEATURES

GPU

 Number of processor cores: 2496
 Processor core clock: 706 MHz
 Package size: 45 mm × 45 mm 2397-pin ball grid array (S-FCBGA)

Board

 PCI Express Gen2 ×16 system interface
 Physical dimensions: 4.376 inches × 10.5 inches, dual-slot

Display Connectors

 None

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