HP AT-32011, AT-32033 User Manual

查询AT-32011供应商
Low Current, High Performance NPN Silicon Bipolar Transistor
Technical Data
AT-32011 AT-32033
Features
• High Performance Bipolar Transistor Optimized for Low Current, Low Voltage Operation
• 900 MHz Performance:
AT-32011: 1 dB NF, 14 dB G AT-32033: 1 dB NF, 12.5 dB G
• Characterized for End-Of­Life Battery Use (2.7 V)
• SOT-23 and SOT-143 SMT Plastic Packages
• Tape-And-Reel Packaging Option Available
[1]
Outline Drawing
EMITTER COLLECTOR
320
BASE EMITTER
SOT-143 (AT-32011)
COLLECTOR
320
Description
Hewlett Packard’s AT-32011 and AT-32033 are high performance NPN bipolar transistors that have been optimized for maximum ft at low voltage operation, making
A
them ideal for use in battery powered applications in wireless
A
markets. The AT-32033 uses the 3␣ lead SOT-23, while the AT-320 11 places the same die in the higher performance 4 lead SOT-143. Both packages are industry standard, and compatible with high volume surface mount assembly techniques.
The 3.2 micron emitter-to-emitter pitch and reduced parasitic design of these transistors yields extremely high performance products that can perform a multiplicity of tasks. The 20␣ emitter finger interdigitated geometry yields an easy to match to and extremely fast transistor with moderate power, low noise resistance, and low operating currents.
Optimized performance at 2.7 V makes these devices ideal for use in 900 MHz, 1.8 GHz, and 2.4 GHz battery operated systems as an LNA, gain stage, buffer, oscillator, or active mixer. Typical amplifier designs at 900 MHz yield 1.2 dB noise figures with 12 dB or more associated gain at a 2.7 V, 2 mA bias, with noise performance being relatively insensitive to input match. High gain capability at 1 V, 1 mA makes these devices a good fit for 900 MHz pager applications. Voltage breakdowns are high enough for use at 5 volts.
The AT-3 series bipolar transistors are fabricated using an optimized version of Hewlett Packard’s 10␣ GHz ft, 30 GHz f Aligned-Transistor (SAT) process. The die are nitride passivated for surface protection. Excellent device uniformity, performance and reliability are produced by the use of ion-implantation, self­alignment techniques, and gold metalization in the fabrication of these devices.
MAX
Self-
BASE EMITTER
SOT-23 (AT-32033)
Note:
1. Refer to “Tape-and-Reel Packaging for Semiconductor Devices.”
4-53
5965-8920E
AT-32011, AT-32033 Absolute Maximum Ratings
Absolute
Symbol Parameter Units Maximum
V V V
T
EBO
CBO
CEO
I
C
P
T
STG
T
j
Emitter-Base Voltage V 1.5 Collector-Base Voltage V 11 Collector-Emitter Voltage V 5.5 Collector Current mA 32 Power Dissipation
[2, 3]
mW 200
Junction Temperature °C 150 Storage Temperature °C -65 to 150
[1]
Thermal Resistance
[2]
:
θjc = 550 °C/W
Notes:
1. Operation of this device above any one of these parameters may cause permanent damage.
2. T
Mounting Surface
3. Derate at 1.82 mW/°C for TC > 40°C.
= 25°C.
Electrical Specifications, T
= 25°C
A
AT-32011 AT-32033
Symbol Parameters and Test Conditions Units Min. Typ. Max. Min. Typ. Max.
NF Noise Figure
14
[1]
[1]
VCE = 2.7 V, IC = 2 mA f = 0.9 GHz dB 1.0
G
h
FE
Associated Gain
A
VCE = 2.7 V, IC = 2 mA f = 0.9 GHz dB 12.5
Forward Current Transfer Ratio
[1]
1.3
[1]
11
[2]
1.0
12.5
[2]
1.3
[2]
VCE = 2.7 V, IC = 2 mA 70 300 70 300
I
CBO
Collector Cutoff Current
VCB = 3 V µA 0.2 0.2
I
EBO
Emitter Cutoff Current
VEB = 1 V µA 1.5 1.5
Notes:
1. Test circuit A, Figure 1. Numbers reflect device performance de-embedded from circuit losses. Input loss = 0.3 dB; output loss = 0.3 dB.
2. Test circuit B, Figure 1. Numbers reflect device performance de-embedded from circuit losses. Input loss = 0.3 dB; output loss = 0.3 dB.
1000 pF
RF IN
TEST CIRCUIT BOARD MATL = 0.062" FR-4 (ε = 4.8)
V
BB
W = 10 L = 1870
W = 10 CKT A: L = 380 CKT B: L = 380
W = 30 L = 60
W = 30
L = 60
CKT A: W = 30 L = 50 x 2 CKT B: W = 30 L = 60
W = 10 L = 1870
NOT TO SCALE
V
CC
CKT A: 25 CKT B: 5
W = 10 CKT A: L = 105 CKT B: L = 850
1000 pF
RF OUT
[2]
DIMENSIONS IN MILS
Figure 1. Test Circuit for Noise Figure and Associated Gain. This circuit is a compromise match between best noise figure, best gain, stability, and a practical
synthesizable match.
4-54
Characterization Information, T
= 25°C
A
AT-32011 AT-32033
Symbol Parameters and Test Conditions Units Typ. Typ.
P
1dB
Power at 1 dB Gain Compression (opt tuning)
VCE = 2.7 V, IC = 20 mA f = 0.9 GHz dBm 13 13
G
1dB
Gain at 1 dB Gain Compression (opt tuning)
VCE = 2.7 V, IC = 20 mA f = 0.9 GHz dB 16.5 15
IP
3
Output Third Order Intercept Point (opt tuning)
VCE = 2.7 V, IC = 20 mA f = 0.9 GHz dBm 24 24
2
|S21|
Gain in 50 System
E
VCE = 2.7 V, IC = 2 mA f = 0.9 GHz dB 13 11.5
2
1.5
1
0.5
NOISE FIGURE (dB)
0
0
0.5 2.5 FREQUENCY (GHz)
1 1.5
1 mA 2 mA 5 mA 10 mA 20 mA
2
Figure 2. AT-32011 and AT-32033 Minimum Noise Figure vs. Frequency and Current at VCE␣ = 2.7 V.
20
15
10
5
P 1dB (dBm)
2 mA
0
5 mA 10 mA 20 mA
-5
0.5 2.5
0
1.0 1.5
FREQUENCY (GHz)
2.0
25
20
15
Ga (dB)
10
1 mA 2 mA 5 mA
5
10 mA 20 mA
0
0.5 2.5
0
1.0 1.5
FREQUENCY (GHz)
2.0
Figure 3. AT-32011 Associated Gain at Optimum Noise Match vs. Frequency and Current at VCE␣ = 2.7 V.
20
15
10
G 1dB (dB)
2 mA
5
5 mA 10 mA 20 mA
0
0
1.0 1.5
0.5 2.5 FREQUENCY (GHz)
2.0
20
15
10
Ga (dB)
1 mA 2 mA
5
5 mA 10 mA 20 mA
0
0
1.0 1.5
0.5 2.5 FREQUENCY (GHz)
2.0
Figure 4. AT-32033 Associated Gain at Optimum Noise Match vs. Frequency and Current at VCE␣ = 2.7 V.
20
15
10
G 1dB (dB)
2 mA
5
5 mA 10 mA 20 mA
0
0
1.0 1.5
0.5 2.5 FREQUENCY (GHz)
2.0
Figure 5. AT-32011 and AT-32033 Power at 1 dB Gain Compression vs. Frequency and Current at VCE␣ = 2.7 V.
Figure 6. AT-32011 1 dB Compressed Gain vs. Frequency and Current at VCE␣ = 2.7 V.
4-55
Figure 7. AT-32033 1 dB Compressed Gain vs. Frequency and Current at VCE␣ = 2.7 V.
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