HP AT1, AT9, AT3U Schematics

04-- 0402 footprint

PCB STACK UP

LAYER 1 : TOP LAYER 2 : SGND1

A A

LAYER 3 : IN1 LAYER 4 : IN2 LAYER 5 : VCC LAYER 6 : IN3 LAYER 7 : SGND2 LAYER 8 : BOT

06-- 0603 footprint 08-- 0805 footprint 12-- 1206 footprint F-- 1% tolerance

AT3U BLOCK DIAGRAM

CPU Merom

478P (uPGA)/35W

PAG 3,4

CPU THERMAL SENSOR

PAG 11

CLK_CPU_BCLK,CLK_CPU_BCLK# CLK_MCH_BCLK,CLK_MCH_BCLK#

DREFCLK,DREFCLK# DREFSSCLK,DREFSSCLK#

14.318MHz

CLOCK GEN

ICS9LPRS355AGLFT 64pinsTSSOP

PAG 2

DDRII-SODIMM1

Cable

B B

Docking

VGA RJ-45 CIR/Pwr btn Stereo MIC

TV_OUT

PAG 12,13

DDRII-SODIMM2

PAG 12,13

Headphone Jack

DDRII 533,667 MHz

NORTH BRIDGE

Crestline

PAG 5,6,7,8,9,10,11

USB Port VOL Cntr

DMI LINK

PAG 31

SYSTEM CHARGER(MAX8724)

PAG 33

SATA - HDD1

PAG 24

SYSTEM POWER MAX8778

PAG 34

VCCP +1.5V AND GMCH

C C

1.05V(MAX8717)

PAG 35

SATA - HDD2

PATA-

PAG 27

CD-ROM

PAG 24

CPU CORE MAX8771

PAG 36

DDR II SMDDR_VTERM

1.8V/1.8VSUS(TPS51116REGR)

PAG 37

DISCHARGE/3VS/5VS/LANVCC

PAG 38

Keyboard Touch Pad

CIR

Capacitive Sense SW

D D

SATA2

SATA0

PATA

PAG 28

PAG 22

PAG 28

(66/100/133)

SOUTH BRIDGE

ICH-8M

PAG 14,15,16,17

LPC

ENE KBC

KB3926QF A2

PAG 32

Two-element microphone

PAG 28

Audio Jacks

(Phone/ MIC)

PAG 22

TV_OUT CRT_OUT

LVDS(2 Channel)

CRT/S-VIDEO

PAG 18

Panel Connector

PAG 19

USB2.0

5 4,6,7

Bluetooth USB2.0 I/O Ports

PAG 27

PAG 24

Camera

PAG 24

PCI BUS / 33MHz

PCI-E

Azalia

LAN

Realtek PCIE-LAN

RTL8101 (10/100)

Realtek

ALC 268

PAG 22

Mini PCI-E Card

PCI Express Mini Card (Wireless LAN)

PAG 30 PAG 25,26 PAG 27

RJ45

PAG 25

AUDIO Amplifier

PAG 23

PCI ROUTING TABLE

IDSEL

AD25 RICOH832REQ0# / GNT0# AD22REQ1# / GNT1#

NBSRCCLK, NBSRCCLK#

Mini PCI-E Card x1 Express Card x1 Cable Docking x1

Express Card 34

RICOH

RICOH 832

(NEW CARD)

PAG 20,21

IEEE1394

CONN

INTERUPT DEVICE

INTE#,INTF#

MINI PCI for debugINTC#,INTD#

PAG 31

Memory CardReader

PAG 20PAG 21

FAN

PAG 31

SPI

PAG 32

Jack to Speaker

PAG 28

PROJECT : AT3U

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

BLOCK DIAGRAM

NB5/RD1/HW2

BLOCK DIAGRAM

Date: Sheet

137Monday, April 30, 2007

+3V

L42

1 2

BLM21PG600SN1D/08

120 ohms@100Mhz

A A

L43

1 2

BLM21PG600SN1D/08

C400

C400 22U/10V/12

22U/10V/12

SI-2 change

C447

C447 22U/10V/12

22U/10V/12

C464

C464 .1U/10V/04

.1U/10V/04

C445

C445 .1U/10V/04

.1U/10V/04

C436

C436 .1U/10V/04

.1U/10V/04

VDDCPU

+CK_VDD_MAIN

C446

C446 .1U/10V/04

.1U/10V/04

C441

C441 .1U/10V/04

.1U/10V/04

C429

C429 .1U/10V/04

.1U/10V/04

CG_XIN

C431

C431 27P/50V/04

27P/50V/04

1 2

14.318MHZ

CG_XOUT

C430

C430 27P/50V/04

27P/50V/04

SI-1 modify ( remove R256 --not need )

14.318MHz

CLK_3GPLLREQ# NEW-CARD_CLK_REQ#

internal have already build-in 33ohm damping resisteor

R321 10K/04R321 10K/04 R322 10K/04R322 10K/04

12 12

+3V

L44

1 2

BLM21PG600SN1D/08

120 ohms@100Mhz

+3V

B B

C C

R259

R259 10K/04

10K/04

1 2

PCLK_MINI_LPC

R269

R269 *4.7K/04

*4.7K/04

0=overclocking of CPU and SRC Allowed

1 = overclocking of CPU and SRC not Allowed

+3V

R287

R287 *10K/04

*10K/04

1 2

FCTSEL1

R296

R296 10K/04

10K/04

1 2

C479

C479 22U/10V/12

22U/10V/12

PDAT_SMB[16,27]

PCLK_SMB[16,27]

C456

C456 .1U/10V/04

.1U/10V/04

2N7002E

C951 *33P/50V/04C951 *33P/50V/04

C416 *33P/50V/04C416 *33P/50V/04 C421 *33P/50V/04C421 *33P/50V/04 C442 33P/50V/04C442 33P/50V/04 C438 *33P/50V/04C438 *33P/50V/04 C432 *33P/50V/04C432 *33P/50V/04

for EMI

C473

C473 .1U/10V/04

.1U/10V/04

Q16

Q17

C448

C448 .1U/10V/04

.1U/10V/04

+3V

R288

10K/06

+3V

CLKUSB_48

PCLK_LPC_KB3920 PCI_CLK_5C832 PCLK_ICH PCLK_LPC_DEBUG 14M_ICH

C462

C462 .1U/10V/04

.1U/10V/04

R308

R308 10K/06

10K/06

CGDAT_SMB

CGCLK_SMB

C458

C458 .1U/10V/04

.1U/10V/04

+CK_VDD_MAIN2

C452

C452 .1U/10V/04

.1U/10V/04

+CK_VDD_MAIN

VDDCPU

+CK_VDD_MAIN2

SI-2 add -- reserve not need

R845 *100K/04R845 *100K/04

CK_PWG[16]

CGCLK_SMB[12,13,29] CGDAT_SMB[12,13,29]

CLK_BSEL1

R298 4.7K/04R298 4.7K/04

CGCLK_SMB CGDAT_SMB

CG_XIN CG_XOUT

CPU Clock select

0=UMA 1 = External VGA

+3V

Enable ITP

*10K/04

D D

1 2

*10K/04 R283

R283

ITP_EN

10K/04

10K/04 R825

R825

CPU_BSEL0[3]

+1.05V

CPU_BSEL1[3] MCH_BSEL1 [6]

+1.05V

CPU_BSEL2[3] MCH_BSEL2 [6]

+1.05V

R309 0/04R309 0/04 R307 *56/04R307 *56/04 R301 1K/04R301 1K/04 R305 0/04R305 0/04 R302 *0/04R302 *0/04 R303 1K/04R303 1K/04 R277 0/04R277 0/04 R264 *0/04R264 *0/04 R265 1K/04R265 1K/04

CLK_BSEL0

CLK_BSEL1

CLK_BSEL2

R310 0/04R310 0/04

R299 0/04R299 0/04

R258 0/04R258 0/04

<FAE> 1K to NB only when XDP is implement.No XDP can use 0 ohm

FSB

U16

VDDPLL3

VDD48

VDDPCI

VDDREF

VDDSRC

VDDCPU

VDD96I/O

VDDPLL3I/O

VDDSRCI/O

VDDCPU_IO

CK_PWRGD/PD#

FSLB/TEST_MODE

SCLK

SDATA

GND

GND48

GNDCPU

GNDPCI

GNDREF

GNDSRC

CK505

ICS9LPRS355AGLFT/CY28548ZXCT/RTM875T-606

FSC FSB

MCH_BSEL0 [6]

1330 0 0 0 00 1 1 1

CPUCLKT0

CPUCLKC0

CPUCLKT1

CPUCLKC1

SRCCLKT4 SRCCLKC4

PCI_STOP#

SRCCLKT6 SRCCLKC6

SRCCLKT9 SRCCLKC9

PCICLK3

47 46

13 14

17 18

21 22

24 25

27 28

38 37

41 40

44 43

30 31

34 35

33 32

1 3 4 5 6

7 10 62

CPUT2_ITP/SRCT8 CPUT2_ITP/SRCC8

DOTT_96/SRCT0

DOTC_96/SRCC0

27MHz_Nonss/SRCCLK1/SE1

27Mhz_ss/SRCCLC1/SE2

SRCCLKT2/SATACL SRCCLKC2/SATACL

SRCCLKT3/CR#_C

SRCCLKC3/CR#_D

CPU_STOP#

SRCCLKT7/CR#_F SRCCLKC7/CR#_E

SRCCLKT10

SRCCLKC10

SRCCLKT11/CR#_H SRCCLKC11/CR#_G

PCICLK0/CR#_A PCICLK1/CR#_B

PCICLK2/TME

PCICLK4/27_SELECT

PCI_F5/ITP_EN USB_48MHZ/FSLA FSLC/TST_SL/REF

FSA CPU SRC PCI 1 100 10 1

0 0

0 33

RSVD

133

166

200

266

333

400

100 100 100 100 100 100 100 100

RHCLK_CPU RHCLK_CPU#

RHCLK_MCH RHCLK_MCH#

CPU_ITP CPU_ITP#

R_DOT96 R_DOT96#

R_DREFSSCLK R_DREFSSCLK#

RSRC_SATA RSRC_SATA#

R_CLK_PCIE_VGAR_CLK_PCIE_VGAR_CLK_PCIE_VGAR_CLK_PCIE_VGAR_CLK_PCIE_VGAR_CLK_PCIE_VGAR_CLK_PCIE_VGAR_CLK_PCIE_VGAR_CLK_PCIE_VGAR_CLK_PCIE_VGAR_CLK_PCIE_VGAR_CLK_PCIE_VGA R_CLK_PCIE_VGA#R_CLK_PCIE_VGA#R_CLK_PCIE_VGA#R_CLK_PCIE_VGA#R_CLK_PCIE_VGA#R_CLK_PCIE_VGA#R_CLK_PCIE_VGA#R_CLK_PCIE_VGA#R_CLK_PCIE_VGA#R_CLK_PCIE_VGA#R_CLK_PCIE_VGA#R_CLK_PCIE_VGA#

RSRC1_LAN RSRC1_LAN#

PM_STPPCI# PM_STPCPU#

RSRC_ICH RSRC_ICH#

CLK_PCIE_MINI_ CLK_PCIE_MINI_#

RSRC_MCH RSRC_MCH#

CLK_PCIE_NEW CLK_PCIE_NEW#

NEW-CARD_CLK_REQ#_R CLK_3GPLLREQ#_R

R_PCLK_KB3920 R_PCLK_5C832 PCLK_MINI_LPC PCI_ICH FCTSEL1

for S3 resume issue

33 33 33 33

33 33

RP40 4P2R-S-0RP40 4P2R-S-0

RP41 4P2R-S-0RP41 4P2R-S-0

RP45 *4P2R-S-0RP45 *4P2R-S-0

RP64 4P2R-S-0RP64 4P2R-S-0

RP42 4P2R-S-0RP42 4P2R-S-0

RP43 4P2R-S-0RP43 4P2R-S-0

RP46 4P2R-S-0RP46 4P2R-S-0

RP50 4P2R-S-0RP50 4P2R-S-0

RP49 4P2R-S-0RP49 4P2R-S-0

RP47 4P2R-S-0RP47 4P2R-S-0

RP52 4P2R-S-0RP52 4P2R-S-0

RP51 4P2R-S-0RP51 4P2R-S-0

ITP_EN

FSA FSC

R324 475/F/03R324 475/F/03 R323 475/F/03R323 475/F/03

R250 33_04R250 33_04 R260 33_04R260 33_04 R279 33_04R279 33_04

T258T258

R285 33_04R285 33_04 R292 33_04R292 33_04 R295 4.7K/04R295 4.7K/04 R257 4.7K/04R257 4.7K/04 R266 33_04R266 33_04

GCLK_SEL = FCTSEL1

FCTSEL1 (PIN13)

0=UMA 1 = External

VGA

PIN20

DOT96T

SRCT0 SRCC0 27Mout-NSS 27Mout-SS

T289T289 T290T290

NEW-CARD_CLK_REQ# CLK_3GPLLREQ#

CLK_BSEL0 CLK_BSEL2

PIN21

CLK_CPU_BCLK [3] CLK_CPU_BCLK# [3]

CLK_MCH_BCLK [5] CLK_MCH_BCLK# [5]

CLK_CPU_ITP [3] CLK_CPU_ITP# [3]

CLK_PCIE_MINI_C [29] CLK_PCIE_MINI_C# [29]

DREFCLK [6] DREFCLK# [6]

DREFSSCLK [6] DREFSSCLK# [6]

CLK_PCIE_SATA [14] CLK_PCIE_SATA# [14]

DEL VGA CLK NET

CLK_PCIE_LAN [25] CLK_PCIE_LAN# [25]

PM_STPPCI# [16] PM_STPCPU# [16]

CLK_PCIE_ICH [15] CLK_PCIE_ICH# [15]

CLK_PCIE_MINI [29] CLK_PCIE_MINI# [29]

CLK_PCIE_3GPLL [6] CLK_PCIE_3GPLL# [6]

CLK_PCIE_NEW_C [27] CLK_PCIE_NEW_C# [27]

PCLK_LPC_KB3920 [31] PCI_CLK_5C832 [21] PCLK_LPC_DEBUG [29]

PCLK_ICH [15]

CLKUSB_48 [16]

14M_ICH [16]

PIN24

SRCT1/LCDT_100DOT96C

Size Document Number Rev

Size Document Number Rev Custom

Custom

NB5/RD1/HW2

Custom Date: Sheet

Date: Sheet

NEW-CARD_CLK_REQ# [27] CLK_3GPLLREQ# [6]

form ICS FAE recommend(defaule is Hi )

PIN25

SRCT1/LCDT_100

PROJECT : AT3U

Quanta Computer Inc.

CLOCK GENERATOR

237Wednesday, May 02, 2007

H_REQ#[0..4]

C935

C936

+1.05V

R20

R13

51_04

*51/F/04

R19 0/04R19 0/04

Layout Note: Place R8 close ITP.

CLK_CPU_ITP#[2] CLK_CPU_ITP[2]

Layout Note: Place R4,R361,R346 & R7 close to CPU.

H_A#[3..16]

H_A#[17..35]

C930

C931

C932

C933

C934

*100P/50V/04

R18

R18 39/F/04

39/F/04

1 2

R14 22.6/F/04R14 22.6/F/04

1 2

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

*100P/50V/04

R15

R15 150/04

150/04

H_A#[3..16][5]

A A

H_ADSTB#0[5] H_REQ#[0..4][5]

H_A#[17..35][5]

B B

H_ADSTB#1[5]

H_A20M#[14]

H_FERR#[14]

H_IGNNE#[14] H_STPCLK#[14]

H_INTR[14] H_NMI[14] H_SMI#[14]

modified resevved for power noise

C C

ITP_TDI ITP_TMS ITP_TCK ITP_TDO ITP_TRST#

H_RESET#

ITP_TCK

D D

C925

*100P/50V/04

U31A

A[3]#

A[4]#

A[5]#

A[6]#

A[7]#

A[8]#

A[9]#

A[10]#

A[11]#

A[12]#

A[13]#

A[14]#

A[15]#

A[16]#

ADSTB[0]#

REQ[0]#

REQ[1]#

REQ[2]#

REQ[3]#

REQ[4]#

A[17]#

A[18]#

A[19]#

A[20]#

A[21]#

A[22]#

A[23]#

A[24]#

A[25]#

A[26]#

A[27]#

A[28]#

A[29]#

A[30]#

A[31]#

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

ADSTB[1]#

A20M#

FERR#

IGNNE#

STPCLK#

LINT0

LINT1

SMI#

RSVD[01]

RSVD[02]

RSVD[03]

RSVD[04]

RSVD[05]

RSVD[06]

RSVD[07]

D22

RSVD[08]

RSVD[09]

RSVD[10]

Merom Ball-out Rev 1a

ADDR GROUP 0

ADDR GROUP 1

THERMAL

ICH

THERMTRIP#

RESERVED

ADS#

BNR#

BPRI#

DEFER#

F21

DRDY#

DBSY#

BR0#

D20

IERR#

INIT#

LOCK#

CONTROLXDP/ITP SIGNALS

RESET#

RS[0]#

RS[1]#

RS[2]#

TRDY#

HIT#

HITM#

AD4

BPM[0]#

AD3

BPM[1]#

AD1

BPM[2]#

AC4

BPM[3]#

AC2

PRDY#

AC1

PREQ#

AC5

TCK

AA6

TDI

AB3

TDO

AB5

TMS

AB6

TRST#

C20

DBR#

D21

PROCHOT#

A24

THERMDA

B25

THERMDC

H CLK

A22

BCLK[0]

A21

BCLK[1]

modified --remove R72

Populate ITP700Flex for bringup

R22 27/F/04R22 27/F/04

R21 649/F/04R21 649/F/04

JITP1

1 2 5 7 3

8 9

10 14 16 18 20 22

TDI TMS TCK TDO TRST#

RESET#

FBO BCLKN

BCLKP

GND0 GND1 GND2 GND3 GND4 GND5

12 12

BPM0# BPM1# BPM2# BPM3# BPM4# BPM5#

GND_0 GND_1

*ITP700Flex

C926*100P/50V/04C926*100P/50V/04

R167 56_04R167 56_04

H_IERR#

1 2

C927*100P/50V/04C927*100P/50V/04

H_RESET#

ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4 ITP_BPM#5 ITP_TCK ITP_TDI ITP_TDO ITP_TMS ITP_TRST# ITP_DBRESET#

R166 75_04R166 75_04

CPU_PROCHOT#CPU_PROCHOT# H_THERMDA H_THERMDC

PM_THRMTRIP#

R72 *56/04R72 *56/04

1 2

ITP_TCK ITP_TRST#

VTT0

VTT1

VTAP

DBR#

DBA#

23 21 19 17 15 13 4

NC0

NC1

29 30

H_ADS# [5] H_BNR# [5] H_BPRI# [5]

H_DEFER# [5] H_DRDY# [5] H_DBSY# [5]

H_BR0# [5]

H_INIT# [14] H_LOCK# [5] H_RESET# [5]

H_RS#0 [5] H_RS#1 [5] H_RS#2 [5] H_TRDY# [5]

H_HIT# [5] H_HITM# [5]

SYS_RST# [16]

+1.05V

H_THERMDA [11]

H_THERMDC [11] PM_THRMTRIP# [6,14]

+1.05V

CLK_CPU_BCLK [2] CLK_CPU_BCLK# [2]

ITP debug signals

+1.05V

ITP_DBRESET#

ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4 ITP_BPM#5

for power noise

+1.05V

Layout Note: Place voltage divider within

0.5" of GTLREF pin

C904 *0.1U/10V/04C904 *0.1U/10V/04

C905 *0.1U/10V/04C905 *0.1U/10V/04

H_D#[0..15][5]

H_DSTBN#0[5] H_DSTBP#0[5] H_DINV#0[5]

H_D#[16..31][5]

+1.05V

R151

1 2

R151 1K/F/04

1K/F/04

R152

R152 2K/F/04

2K/F/04

H_DSTBN#1[5] H_DSTBP#1[5] H_DINV#1[5]

CPU_BSEL0[2] CPU_BSEL1[2] CPU_BSEL2[2]

R157 *1K/F/04R157 *1K/F/04

1 2

R158 *1K/F/04R158 *1K/F/04

1 2

C132 *0.1U/10V/04C132 *0.1U/10V/04

R140 *0/04R140 *0/04

1 2

Place C close to the CPU_TEST4 pin. Make sure CPU_TEST4 routing is reference to GND and away from other noisy signal.

ITP disable guidelines

Signal Resistor Value Connect To Resistor Placement

150 ohm +/- 5%

TDI

39 ohm +/- 1%

TMS

500-680ohm +/- 5%

TRST#

27 ohm +/- 1%

TCK

150 ohm +/- 5%

TDO

Note: Populate R5, R8, C372 & R430 when ITP connector is populated.

CPU_TEST1 CPU_TEST2

CPU_TEST4

CPU_TEST6

H_D#[0..15]

H_D#[16..31]

FSB 533 0 0 1133 667 800

VTT GND GND VTT

U31B

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

V_CPU_GTLREF CPU_TEST1 CPU_TEST2 CPU_TEST3 CPU_TEST4 CPU_TEST5 CPU_TEST6

For the purpose of testability, route these signals through a ground referenced Z0 = 55ohm trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection.

BCLK

166 200

U31B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

T154T154

T49T49

G24

H26 H25

M24 M23

R24

N25 M26

N24

AD26

C23 D25 C24

AF26

AF1

C21

E23 K24

J24

J23 H22 F26 K22 H23

J26

N22 K25 P26 R23 L23

L22 P25

P23 P22 T24

L25 T25

L26

A26 B22

B23

Merom Ball-out Rev 1a

D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#

D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#

GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6

BSEL[0] BSEL[1] BSEL[2]

CPU_TEST3 CPU_TEST5

DATA GRP 0 DATA GRP 1

MISC

BSEL2 BSEL1 BSEL0

1 1

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]#

DATA GRP 2DATA GRP 3

D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]# COMP[0]

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

1 00

H_D#32

Y22

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

V23

H_D#37

T22

H_D#38

U25

H_D#39

U23

H_D#40

Y25

H_D#41

W22

H_D#42

Y23

H_D#43

W24

H_D#44

W25

H_D#45

AA23

H_D#46

AA24

H_D#47

AB25 Y26 AA26 U22

H_D#48

AE24

H_D#49

AD24

H_D#50

AA21

H_D#51

AB22

H_D#52

AB21

H_D#53

AC26

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AC25

H_D#58

AE21

H_D#59

AD21

H_D#60

AC22

H_D#61

AD23

H_D#62

AF22

H_D#63

AC23 AE25 AF24 AC20

COMP0

R26

COMP1

U26

COMP2

AA1

COMP3

Y1 E5

B5 D24

H_PWRGD

D6 D7 AE6

COMP0 COMP1 COMP2 COMP3

Comp0,2 connect with Zo=27.4ohm,Comp1,3 connect with Zo=55ohm, make those traces length shorter than 0.5".Trace should be at least 25 mils away from any other toggling signal.

Within 2.0" of the ITPVTT Within 2.0" of the ITP Within 2.0" of the ITP Within 2.0" of the ITP Within 2.0" of the ITP

H_D#[32..47]

H_D#[48..63]

Note: H_DPRTSTP need to daisy chain from ICH8 to IMVP6 to CPU.

R16

54.9/F/04

1 2

H_D#[32..47] [5]

H_DSTBN#2 [5] H_DSTBP#2 [5] H_DINV#2 [5]

H_D#[48..63] [5]

SI-2 modified for fix run TAT hang

H_DSTBN#3 [5] H_DSTBP#3 [5] H_DINV#3 [5]

H_DPRSTP# [6,14,35] H_DPSLP# [14] H_DPWR# [5] H_PWRGD [14] H_CPUSLP# [5] PM_PSI# [35]

NB5/RD1/HW2

H_PWRGD

C928

SI-2 modified resevved for power noise

Reserved for EMI.

+1.05V

VIN

R17

27.4/F/04

1 2

*100P/50V/04

+1.05V

C911

C911 *.1U/10V/04

*.1U/10V/04

+1.5V

R585

54.9/F/04

1 2

PROJECT : AT3U

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

CLOCK GENERATOR

Date: Sheet

+1.05V

C730

C730 *.1U/10V/04

*.1U/10V/04

1 2

R822

*56/04

1 2

C908

C908 100P/50V/04

100P/50V/04

H_DPRSTP# H_DPSLP#

C929

*100P/50V/04

R584

27.4/F/04

337Wednesday, May 02, 2007

VCC_CORE

A A

VCC_CORE

C88

C88 22U/10V/08

22U/10V/08

C96

C96 22U/10V/08

22U/10V/08

C672

C672 10U/4V/08

10U/4V/08

C81

C81 22U/10V/08

22U/10V/08

8 inside cavity, north side, secondary layer.

VCC_CORE

B B

VCC_CORE

C52

C52 22U/10V/08

22U/10V/08

C71

C71 22U/10V/08

22U/10V/08

C42

C42 22U/10V/08

22U/10V/08

C63

C63 22U/10V/08

22U/10V/08

8 inside cavity, south side, secondary layer.

VCC_CORE

C40

C40 22U/10V/08

22U/10V/08

C39

C39 22U/10V/08

22U/10V/08

6 inside cavity, north side, primary layer.

VCC_CORE

C671

C671 22U/10V/08

22U/10V/08

C675

C675 10U/4V/08

10U/4V/08

C C

6 inside cavity, south side, primary layer.

+1.05V

C65

C65 .1U/10V/04

.1U/10V/04

C64

C64 .1U/10V/04

.1U/10V/04

C676

C676 10U/4V/08

10U/4V/08

C693

C693 10U/4V/08

10U/4V/08

C72

C72 22U/10V/08

22U/10V/08

C36

C36 22U/10V/08

22U/10V/08

C35

C35 22U/10V/08

22U/10V/08

C682

C682 22U/10V/08

22U/10V/08

C54

C54 .1U/10V/04

.1U/10V/04

C683

C683 10U/4V/08

10U/4V/08

C697

C697 10U/4V/08

10U/4V/08

C66

C66 22U/10V/08

22U/10V/08

C95

C95 22U/10V/08

22U/10V/08

C41

C41 22U/10V/08

22U/10V/08

C687

C687 10U/4V/08

10U/4V/08

C56

C56 .1U/10V/04

.1U/10V/04

C50

C50 22U/10V/08

22U/10V/08

C692

C692 10U/4V/08

10U/4V/08

C48

C48 .1U/10V/04

.1U/10V/04

C688

C688 10U/4V/08

10U/4V/08

C87

C87 22U/10V/08

22U/10V/08

C57

C57 22U/10V/08

22U/10V/08

C80

C80 22U/10V/08

22U/10V/08

C55

C55 22U/10V/08

22U/10V/08

C696

C696 10U/4V/08

10U/4V/08

C51

C51 .1U/10V/04

.1U/10V/04

VCC_CORE VCC_CORE

A9 A10 A12 A13 A15 A17 A18 A20

B9 B10 B12 B14 B15 B17 B18 B20

C9 C10 C12 C13 C15 C17 C18

D9 D10 D12 D14 D15 D17 D18

E9 E10 E12 E13 E15 E17 E18 E20

F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9

AA10 AA12 AA13 AA15 AA17 AA18 AA20

AB9

AC10 AB10 AB12 AB14 AB15 AB17 AB18

U31C

VCC[001]

VCC[068]

VCC[002]

VCC[069]

VCC[003]

VCC[070]

VCC[004]

VCC[071]

VCC[005]

VCC[072]

VCC[006]

VCC[073]

VCC[007]

VCC[074]

VCC[008]

VCC[075]

VCC[009]

VCC[076]

VCC[010]

VCC[077]

VCC[011]

VCC[078]

VCC[012]

VCC[079]

VCC[013]

VCC[080]

VCC[014]

VCC[081]

VCC[015]

VCC[082]

VCC[016]

VCC[083]

VCC[017]

VCC[084]

VCC[018]

VCC[085]

VCC[019]

VCC[086]

VCC[020]

VCC[087]

VCC[021]

VCC[088]

VCC[022]

VCC[089]

VCC[023]

VCC[090]

VCC[024]

VCC[091]

VCC[025]

VCC[092]

VCC[026]

VCC[093]

VCC[027]

VCC[094]

VCC[028]

VCC[095]

VCC[029]

VCC[096]

VCC[030]

VCC[097]

VCC[031]

VCC[098]

VCC[032]

VCC[099]

VCC[033]

VCC[100] VCC[034] VCC[035]

VCCP[01] VCC[036]

VCCP[02] VCC[037]

VCCP[03] VCC[038]

VCCP[04] VCC[039]

VCCP[05] VCC[040]

VCCP[06] VCC[041]

VCCP[07] VCC[042]

VCCP[08] VCC[043]

VCCP[09] VCC[044]

VCCP[10] VCC[045]

VCCP[11] VCC[046]

VCCP[12] VCC[047]

VCCP[13] VCC[048]

VCCP[14] VCC[049]

VCCP[15] VCC[050]

VCCP[16] VCC[051] VCC[052]

VCCA[01] VCC[053]

VCCA[02] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064]

VCCSENSE VCC[065] VCC[066] VCC[067]

VSSSENSE

Merom Ball-out Rev 1a

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

TP_VCCSENSE

TP_VSSSENSE

ICCODE: for Merom processors recommended design target is 44A

ICCP: 1before vccore stable peak current is 4.5A

2.after vccore stable

+1.05V

continue current is

2.5A

C26

C26 *330U/2.5V

*330U/2.5V

ICCA 130mA

CPU_VID0 [35] CPU_VID1 [35] CPU_VID2 [35] CPU_VID3 [35] CPU_VID4 [35] CPU_VID5 [35] CPU_VID6 [35]

TP_VCCSENSE [35]

TP_VSSSENSE [35]

Layout Note: Place C105 near PIN B26.

C729

C729 .01U/25V/04

.01U/25V/04

+1.5V

C733

C733 10U/4V/08

10U/4V/08

U31D

VSS[001]

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

VSS[009]

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

VSS[017]

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

VSS[023]

C22

VSS[024]

C25

VSS[025]

VSS[026]

VSS[027]

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

VSS[035]

VSS[036]

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

VSS[044]

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

VSS[050]

F22

VSS[051]

F25

VSS[052]

VSS[053]

VSS[054]

G23

VSS[055]

G26

VSS[056]

VSS[057]

VSS[058]

H21

VSS[059]

H24

VSS[060]

VSS[061]

VSS[062]

J22

VSS[063]

J25

VSS[064]

VSS[065]

VSS[066]

K23

VSS[067]

K26

VSS[068]

VSS[069]

VSS[070]

L21

VSS[071]

L24

VSS[072]

VSS[073]

VSS[074]

M22

VSS[075]

M25

VSS[076]

VSS[077]

VSS[078]

N23

VSS[079]

N26

VSS[080] VSS[081]P3VSS[162]

Merom Ball-out Rev 1a

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]

VSS[163]

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

Layout out: Place these inside socket cavity on North side secondary.

D D

PROJECT : AT3U

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

Merom Processor (POWER)

NB5/RD1/HW2

Merom Processor (POWER)

Date: Sheet

437Wednesday, May 02, 2007

U34A

M10 N12

W10

AD12

AE3 AD9 AC9

AC7 AC14 AD11 AC11

AB2

AD7

AB1

AC6

AE2

AC5

AG3

AH8

AJ14

AE9 AE11 AH12

AH5

AE7

AE5

AH2 AH13

E2 G2 G7 M6 H7 H3 G4

F3 N8 H2

N9 H5

P13

K9 M2

V4 M3

J1 N5 N3 W6 W9 N2

Y7 Y9

P4 W3 N1

AJ9

AJ5 AJ6 AJ7

AJ2 AJ3

B3 C2

W1 W2

U34A

H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63

H_SWING H_RCOMP

H_SCOMP H_SCOMP#

H_CPURST# H_CPUSLP#

H_AVREF H_DVREF

CRESTLINE_1p0

H_ADSTB#_0 H_ADSTB#_1

HOST

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0 H_RS#_1 H_RS#_2

J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19

G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7

K5 L2 AD13 AE13

M7 K3 AD2 AH11

L7 K2 AC2 AJ10

M14 E13 A11 H13 B12

E12 D7 D8

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

C46

C46 .1U/10V/04

.1U/10V/04

H_D#[0..63]

H_RESET#[3]

H_CPUSLP#[3]

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWING H_RCOMP

H_SCOMP H_SCOMP#

H_REF

H_D#[0..63][3]

A A

+1.05V

R51

R51 221/F/04

221/F/04

H_SWING

R55

R55 100/F/04

100/F/04

B B

+1.05V

C47

C47 .1U/10V/04

.1U/10V/04

1 2

impedance 55 ohm

R553

R542

54.9/F/04

H_SCOMP H_SCOMP#

C C

H_RCOMP

R41

24.9/F/04

Layout Note: H_RCOMP trace should be 10-mil wide with 20-mil spacing.

+1.05V

1 2

R52

R52 1K/F/04

1K/F/04

R53

R53 2K/F/04

2K/F/04

H_A#[3..35]

H_ADS# [3] H_ADSTB#0 [3] H_ADSTB#1 [3] H_BNR# [3] H_BPRI# [3] H_BR0# [3] H_DEFER# [3] H_DBSY# [3] CLK_MCH_BCLK [2] CLK_MCH_BCLK# [2] H_DPWR# [3] H_DRDY# [3] H_HIT# [3] H_HITM# [3] H_LOCK# [3] H_TRDY# [3]

H_DINV#0 [3] H_DINV#1 [3] H_DINV#2 [3] H_DINV#3 [3]

H_DSTBN#0 [3] H_DSTBN#1 [3] H_DSTBN#2 [3] H_DSTBN#3 [3]

H_DSTBP#0 [3] H_DSTBP#1 [3] H_DSTBP#2 [3] H_DSTBP#3 [3]

H_REQ#0 [3] H_REQ#1 [3] H_REQ#2 [3] H_REQ#3 [3] H_REQ#4 [3]

H_RS#0 [3] H_RS#1 [3] H_RS#2 [3]

H_A#[3..35] [3]

Layout Note: Place the 0.1 uF decoupling capacitor

D D

within 100 mils from GMCH pins.

PROJECT : AT3U

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

Crestline (HOST)

NB5/RD1/HW2

Crestline (HOST)

Date: Sheet

537Wednesday, May 02, 2007

A A

WW22 update --- MA14 needs to be routed if customers are planning on using 2Gb technology and width=8 (by

8) DIMMs

SA_MA14[12,13] SB_MA14[12,13]

CRESTLINE new pin define

B B

C C

D D

PM_BMBUSY#[16] H_DPRSTP#[3,14,35] PM_EXTTS#0[12,13] PM_EXTTS#1[12]

DELAY_VR_PWRGOOD[16,35]

PM_THRMTRIP#[3,14]

DPRSLPVR[16,35]

GMCH pwrok is 3.3v tolerant

+3V

R27 10K/04R27 10K/04 R28 10K/04R28 10K/04

SM_RCOMP_VOH

C215

C215 .01U/25V/04

.01U/25V/04

SM_RCOMP_VOL

C230

C230 .01U/25V/04

.01U/25V/04

Layout Note: Location of all MCH_CFG strap resistors needs to be close to minmize stub.

MCH_BSEL0[2] MCH_BSEL1[2] MCH_BSEL2[2]

MCH_CFG_5[11]

MCH_CFG_9[11]

MCH_CFG_12[11] MCH_CFG_13[11]

MCH_CFG_16[11]

MCH_CFG_19[11] MCH_CFG_20[11]

R36 0/04R36 0/04 R84 0/04R84 0/04

R79 0/04R79 0/04

PLT_RST-R#[15]

1 2 1 2

C209

2.2U/10V/08

C245

2.2U/10V/08

R159 100/04R159 100/04 R90 *0/04R90 *0/04 R68 0/04R68 0/04 R69 *4.7K/04R69 *4.7K/04

PM_EXTTS#0 PM_EXTTS#1

+1.8VSUS_GMCH

R178

R178 1K/F/04

1K/F/04

R179

3.01K/F/04

R175

R175 1K/F/04

1K/F/04

T165T165

T9T9

T18T18 T158T158

T27T27 T16T16 T20T20

T30T30

T21T21

T17T17 T23T23

T28T28 T26T26

PM_BMBUSY#_R ICH_DPRSTP#_R

PM_EXTTS#1_R PLTRST_MCH#

PM_THRMTRIP#_GMCH PM_DPRSLPVR_GMCH

T202T202 T204T204 T208T208 T209T209 T210T210 T206T206 T207T207 T203T203 T199T199 T164T164 T160T160 T166T166 T163T163 T162T162 T156T156 T205T205

+1.25V

MCH_CLVREFMCH_CLVREF

C128

C128 .1U/10V/04

.1U/10V/04

1 2

CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20

TP_NC1 TP_NC2 TP_NC3 TP_NC4 TP_NC5 TP_NC6 TP_NC7 TP_NC8 TP_NC9 TP_NC10 TP_NC11 TP_NC12 TP_NC13 TP_NC14 TP_NC15 TP_NC16

R586

R586 1K/F/04

1K/F/04

R589

R589 392/F/04

392/F/04

P36 P37 R35

N35 AR12 AR13 AM12 AN13

J12

AR37

AM36

AL36

AM37

D20

H10

B51

BJ20 BK22 BF19

BH20

BK18 BJ18 BF23

BG23 BC23 BD24

BJ29

BE24

BH39

AW20

BK20

C48 D47 B44 C44 A35 B37 B36 B34 C34

P27 N27 N24 C21 C23 F23 N23

G23

J20 C20 R24

L23

J23 E23 E20 K23 M20 M24

L32

N33

L35

G41

L39

L36

J36

AW49

AV20

N20 G36

BJ51 BK51 BK50 BL50 BL49

BL3 BL2 BK1

BJ1

A5 C51 B50 A50 A49 BK2

CRESTLINE_1p0

U34B

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14

RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 SA-MA14 SB_MA14 RSVD34 RSVD35 RSVD36 LVDSA_DATA#_3 LVDSA_DATA_3 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20

PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR

NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16

DDR MUXINGCLKDMI

CFGRSVD

GRAPHICS VIDME

MISC

SM_CK_0 SM_CK_1 SM_CK_3 SM_CK_4

SM_CK#_0 SM_CK#_1 SM_CK#_3 SM_CK#_4

SM_CKE_0 SM_CKE_1 SM_CKE_3 SM_CKE_4

SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3

SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH SM_RCOMP_VOL

SM_VREF_0 SM_VREF_1

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

SDVO_CTRL_CLK

SDVO_CTRL_DATA

CLK_REQ#

ICH_SYNC#

TEST_1 TEST_2

+1.8VSUS_GMCH

R171

20/F/04

SMRCOMPP

AV29 BB23 BA25 AV23

AW30 BA23 AW25 AW23

BE29 AY32 BD39 BG37

BG20 BK16 BG16 BE13

BH18 BJ15 BJ14 BE16

BL15 BK14

BK31 BL31

AR49 AW4

B42 C42 H48 H47

K44 K45

AN47 AJ38 AN42 AN46

AM47 AJ39 AN41 AN45

AJ46 AJ41 AM40 AM44

AJ47 AJ42 AM39 AM43

E35 A39 C38 B39 E36

AM49 AK50 AT43 AN49 AM50

H35 K36 G39 G40

A37 R32

SMRCOMPP SMRCOMPN

SM_RCOMP_VOH SM_RCOMP_VOL

SMDDR_VREF_MCH

R170 *10K/F/06R170 *10K/F/06 R169 *10K/F/06R169 *10K/F/06

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0

DMI_TXP1

DMI_TXP2

DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

<check lisr & CRB> For Calero : 255 For Cresstline:1.3K/F For external VGA:0 ohm

DFGT_VID_0 DFGT_VID_1 DFGT_VID_2 DFGT_VID_3 DFGT_VR_EN

MCH_CLVREF

T22T22 T24T24

R101

R101 20K/04

20K/04

1 2

SMRCOMPN

20/F/04

M_A_CLK0 [13] M_A_CLK1 [13] M_B_CLK0 [13] M_B_CLK1 [13]

M_A_CLK0# [13] M_A_CLK1# [13] M_B_CLK0# [13] M_B_CLK1# [13]

M_A_CKE0 [12,13] M_A_CKE1 [12,13] M_B_CKE0 [12,13] M_B_CKE1 [12,13]

M_A_CS#0 [12,13] M_A_CS#1 [12,13] M_B_CS#0 [12,13] M_B_CS#1 [12,13]

M_A_ODT0 [12,13] M_A_ODT1 [12,13] M_B_ODT0 [12,13] M_B_ODT1 [12,13]

DREFCLK [2] DREFCLK# [2] DREFSSCLK [2] DREFSSCLK# [2]

CLK_PCIE_3GPLL [2] CLK_PCIE_3GPLL# [2]

R42 1.3K/04R42 1.3K/04

<check list & CRB> For Calero : 1.5K For Cresstline:2.4K

modified add 470P

1 2

C882 470P/50V/04C882 470P/50V/04 C178 .1U/10V/04C178 .1U/10V/04 C196 .1U/10V/04C196 .1U/10V/04 R168 0/04R168 0/04

+1.8VSUS_GMCH

DMI_TXN[3:0] [15]

DMI_TXP[3:0] [15]

DMI_RXN[3:0] [15]

DMI_RXP[3:0] [15]

IV&EV Dis/Enable setting

T29T29 T31T31 T32T32 T33T33 T34T34

CL_CLK0 [16]

CL_DATA0 [16] ECPWROK [11,16,31] CL_RST#0 [16,29]

CLK_3GPLLREQ# [2] MCH_ICH_SYNC# [16]

CLKREQ# ( MCH drives CLK_REQ# to control the PCI-E diff clk

R507

R507 0/04

0/04

1 2

R172

input itself )

+3V

SMDDR_VREF [13,36]

+3V

<FAE> If no use can be NC

DDCCLK[18] DDCDATA[18]

HSYNC_COM[18] VSYNC_COM[18]

<FAE> Flexible and safe

In Crestline EDS Rev.1.0, Render Standby Voltage is not finalized yet(TBD), 1.05V for Graphic Voltage range(VCC_AXG) is between 0.9975V(min.) and 1.1025V(max.). Vgfx max at 1.1025V @ 8A (estimated)

only resever AT3/5 not support IAMT,but design line suggest to connection these pin ,do not NC

DPST_PWM[19] LVDS_BLON[19]

EDIDCLK[19] EDIDDATA[19]

DISP_ON[19]

R83 2.4K/04R83 2.4K/04

Dis/Enable setting

TXLCLKOUT-[19] TXLCLKOUT+[19] TXUCLKOUT-[19]

TXUCLKOUT+[19]

S-CVBS1[18] S-YD1[18] S-CD1[18]

R91 *2.2K/04R91 *2.2K/04 R100 *2.2K/04R100 *2.2K/04

CRT_B[18]

CRT_G[18]

CRT_R[18]

R26 10K/04R26 10K/04 R25 10K/04R25 10K/04

TXLOUT0-[19] TXLOUT1-[19] TXLOUT2-[19]

TXLOUT0+[19] TXLOUT1+[19] TXLOUT2+[19]

TXUOUT0-[19] TXUOUT1-[19] TXUOUT2-[19]

TXUOUT0+[19] TXUOUT1+[19] TXUOUT2+[19]

CRT_B CRT_G CRT_R

R34 30_04R34 30_04 R35 30_04R35 30_04

<check list> HSYNC/VSYNC serial R place close to NB

DREFSSCLK DREFSSCLK#

<FAE> If no use DREFCLK PU and DREFCLK# PD

IV&EV Dis/Enable setting

DREFCLK DREFCLK#

<design guide> If no use DREFCLK PU and DREFCLK# PD

DPST_PWM

J40

LVDS_BLONLVDS_BLONLVDS_BLONLVDS_BLON

H39 E39 E40

EDIDCLK

C37

EDIDDATA

D35

DISP_ON

K40

LVDS_IBG

L41

S-CVBS1S-CVBS1S-CVBS1S-CVBS1S-CVBS1S-CVBS1S-CVBS1S-CVBS1 S-YD1S-YD1S-YD1S-YD1 S-CD1S-CD1S-CD1S-CD1

DDCCLKDDCCLKDDCCLKDDCCLK DDCDATADDCDATADDCDATADDCDATADDCDATADDCDATADDCDATADDCDATA HSYNC11 CRTIREF VSYNC11

L43 N41 N40 D46 C45 D44 E42

G51

E51 F49

G50

E50 F48

G44

B47 B45

E44 A47 A45

E27

G27

K27 F27

J27 L27

M35

P33

H32

G32

K29 J29 F29 E29

K33

G35

F33 C32 E33

T25T25

TXLCLKOUTTXLCLKOUT+ TXUCLKOUTTXUCLKOUT+

TXLOUT0TXLOUT1TXLOUT2-

TXLOUT0+ TXLOUT1+ TXLOUT2+

TXUOUT0TXUOUT1TXUOUT2-

TXUOUT0+ TXUOUT1+ TXUOUT2+

TV_DCONSEL_0 TV_DCONSEL_1

R76 *4.7K/04R76 *4.7K/04

R59 *4.7K/04R59 *4.7K/04 R57 *4.7K/04R57 *4.7K/04

U34C

L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN

LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK

LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2

LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2

LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2

LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2

TVA_DAC TVB_DAC TVC_DAC

TVA_RTN TVB_RTN TVC_RTN

TV_DCONSEL_0 TV_DCONSEL_1

CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED#

CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC

CRESTLINE_1p0

+1.25V

PEG_COMPI

PEG_COMPO

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8

LVDS

TV VGA

<check list> For EV@ Connect to GND CRT R/G/B TV A/B/C HSYNC/VSYNC

PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8

PEG_TX#_9 PEG_TX#_10 PEG_TX#_11

PCI-EXPRESS GRAPHICS

PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

SI-2 change

R64 *39/F/04R64 *39/F/04 R60 *39/F/04R60 *39/F/04

R62 150/F/04R62 150/F/04 R66 150/F/04R66 150/F/04 R78 150/F/04R78 150/F/04

R74 150/F/04R74 150/F/04 R77 150/F/04R77 150/F/04 R65 150/F/04R65 150/F/04

close to chip

PROJECT : AT3U

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

Crestline (VGA,DMI)

NB5/RD1/HW2

Crestline (VGA,DMI)

Date: Sheet

VCC3G_PCIE_R

N43 M43

J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41

J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42

N45 U39 U47 N51 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44

M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43

<check list> For IV@ Connect to 150ohm CRT R/G/B TV A/B/C Connect to 39ohm HSYNC/VSYNC

HSYNC11 VSYNC11

S-CVBS1 S-YD1 S-CD1

CRT_B CRT_G CRT_R

R85 24.9/F/04R85 24.9/F/04

1 2

637Wednesday, May 02, 2007

+VCC_PEG

M_A_DQ[63:0][13] M_B_DQ[63:0][13]

A A

B B

C C

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

AR43

AW44

BA45 AY46 AR41 AR45 AT42

AW47

BB45 BF48 BG47

BJ45 BB47 BG50 BH49 BE45

AW43

BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40

AW40

AT39

AW36 AW41

AY41 AV38 AT38 AV13 AT13

AW11

AV11 AU15 AT11 BA13 BA11 BE10 BD10

BG10

AW9

AM8

AN10

AN9 AM9

AN11

BD8 AY9

BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3

AT9

U34D

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

CRESTLINE_1p0

BB19

SA_BS_0

BK19

SA_BS_1

BF29

SA_BS_2

BL17

SA_CAS#

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13

SA_RAS#

SA_RCVEN#

DDR SYSTEM MEMORY A

SA_WE#

AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6

AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2

BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16

BE18 AY20

BA19

M_A_DQM0 M_A_DQM1 M_A_DQM2 M_A_DQM3 M_A_DQM4 M_A_DQM5 M_A_DQM6 M_A_DQM7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13

TP_SA_RCVEN#

M_A_BS#0 [12,13] M_A_BS#1 [12,13] M_A_BS#2 [12,13]

M_A_CAS# [12,13]

M_A_DQM[0..7] [13]

M_A_DQS[7:0] [13]

M_A_DQS#[7:0] [13]

M_A_A[13:0] [12,13]

M_A_RAS# [12,13]

T68T68

M_A_WE# [12,13]

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

AP49

AR51 AW50 AW51

AN51

AN50

AV50

AV49

BA50

BB50

BA49

BE50

BA51

AY49

BF50

BF49

BJ50 BJ44 BJ43

BL43 BK47 BK49 BK43 BK42

BJ41

BL41

BJ37

BJ36 BK41

BJ40

BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12

BJ10

BK10

BK5 BK9

BF4 BH5 BG1 BC2 BK3 BE4 BD3

BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2

BL9 BL5

BJ8 BJ6

BJ2

U34E

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

CRESTLINE_1p0

AY17

SB_BS_0

BG18

SB_BS_1

BG36

SB_BS_2

BE17

SB_CAS# SB_DM_0

SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

DDR SYSTEM MEMORY B

AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2

AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3

BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13

AV16 AY18

BC17

M_B_DQM0 M_B_DQM1 M_B_DQM2 M_B_DQM3 M_B_DQM4 M_B_DQM5 M_B_DQM6 M_B_DQM7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13

TP_SB_RCVEN#

M_B_BS#0 [12,13] M_B_BS#1 [12,13] M_B_BS#2 [12,13]

M_B_CAS# [12,13] M_B_DQM[0..7] [13]

M_B_DQS[7:0] [13]

M_B_DQS#[7:0] [13]

M_B_A[13:0] [12,13]

M_B_RAS# [12,13]

T74T74

M_B_WE# [12,13]

D D

PROJECT : AT3U

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

Crestline (DDR)

NB5/RD1/HW2

Crestline (DDR)

Date: Sheet

737Wednesday, May 02, 2007

AT35 AT34 AH28 AC32 AC31 AK32

AJ31

AJ28 AH32 AH31 AH29 AF32

AU32 AU33 AU35 AV33

AW33 AW35

AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35

BJ32

BJ33

BJ34 BK32 BK33 BK34 BK35

BL33 AU30

W13 W14

AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31

AJ20 AN14

R30

R20 T14

Y12

U34G

VCC_1 VCC_2 VCC_3 VCC_5 VCC_4 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12

VCC_13

VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36

VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34

VCC CORE

POWER

VCC SMVCC GFX

VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8

VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55

VCC GFX NCTF

VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 VCC_AXG_NCTF_61 VCC_AXG_NCTF_62 VCC_AXG_NCTF_63 VCC_AXG_NCTF_64 VCC_AXG_NCTF_65 VCC_AXG_NCTF_66 VCC_AXG_NCTF_67 VCC_AXG_NCTF_68 VCC_AXG_NCTF_69 VCC_AXG_NCTF_70 VCC_AXG_NCTF_71 VCC_AXG_NCTF_72 VCC_AXG_NCTF_73 VCC_AXG_NCTF_74 VCC_AXG_NCTF_75 VCC_AXG_NCTF_76 VCC_AXG_NCTF_77 VCC_AXG_NCTF_78 VCC_AXG_NCTF_79 VCC_AXG_NCTF_80 VCC_AXG_NCTF_81 VCC_AXG_NCTF_82 VCC_AXG_NCTF_83

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31

AW45 BC39 BE39 BD17 BD4 AW8 AT6

+1.05V

D D

IVCCSM supply current 1 channel

1.615A 2 channel

3.318A

C C

B B

A A

+1.8VSUS_GMCH

+VCC_AXG

+1.05V

Ivcc (External GFX 1.310 A, integrate 1.572 A)

Layout Note: 370 mils from edge.

Ivcc_AXG Graphics core supply current 7.7A

C91

C91 *330U/6.3V

*330U/6.3V

SI-2 modified --remove C91&C108

Layout Note: Inside GMCH cavity for VCC_AXG.

C118

C118 .1U/10V/04

.1U/10V/04

GMCH 1.05V

VCC Core

VCC_AXG

VCC_AXD

VTT

VCC_PEG

VCC_AXM

VCCR_RX_DMI

C108

C108 *330U/6.3V

*330U/6.3V

C110

C110 .1U/10V/04

.1U/10V/04

current(A)

1.573

7.7

0.2

0.85

1.2

0.54

0.25

12.313SUM

VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7

C129

C129 .1U/10V/04

.1U/10V/04

C172

C172 .1U/10V/04

.1U/10V/04

+1.05V

+VCC_AXG

Layout Note: 370 mils from edge.

C116

C79

0.47U/10V/06

1U/10V/06

Remark

( 1.3A for external GFX )

for integrated Gfx

FSB VCCP

for PCIEG

for IAMT function

DMI

C222

C174

0.22U/10V/06

C670

C670 220U/2.5V

220U/2.5V

C68

C68 10U/6.3V/08

10U/6.3V/08

Ivcc_AXM Controller supply current 540mA

C212

0.47U/10V/06

+3V

+1.05V

R500 10_04R500 10_04

1 2

C663

C663 22U/4V/08

22U/4V/08

Layout Note: Inside GMCH cavity.

+1.05V

C73

C73 22U/4V/08

22U/4V/08

C155

C155 1U/10V/06

1U/10V/06

+VCC_GMCH_L

C115

0.22U/10V/06

for IAMT power if not support need to connection to S0 power

C105

C105 .1U/10V/04

.1U/10V/04

C124

C124 22U/4V/08

22U/4V/08

Layout Note: Place close to GMCH edge.

C145

C145 1U/10V/06

1U/10V/06

CH751H-40PT

C90

0.22U/10V/06

Layout Note: Inside GMCH cavity.

C94

C94 .1U/10V/04

.1U/10V/04

C123

0.22U/10V/06

D32

C106

C106 .1U/10V/04

.1U/10V/04

C113

C113 .1U/10V/04

.1U/10V/04

C99

0.22U/10V/06

1.8VSUS

C267

C267 .1U/10V/04

.1U/10V/04

Layout Note: Place C901 where LVDS and DDR2 taps.

AB33 AB36

AB37 AC33 AC35 AC36 AD35 AD36

AF33

AF36 AH33 AH35 AH36 AH37

AJ33

AJ35

AK33

AK35

AK36

AK37 AD33

AJ36 AM35

AL33

AL35

AA33

AA35

AA36

AP35

AP36 AR35 AR36

AL24

AL26

AL28 AM26 AM28 AM29 AM31 AM32 AM33

AP29

AP31

AP32

AP33

AL29

AL31

AL32 AR31 AR32 AR33

Y32 Y33 Y35 Y36 Y37 T30 T34 T35 U29 U31 U32 U33 U35 U36 V32 V33 V36 V37

U34F

CRESTLINE_1p0

VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44 VCC_NCTF_45 VCC_NCTF_46 VCC_NCTF_47 VCC_NCTF_48 VCC_NCTF_49 VCC_NCTF_50

VCC_AXM_NCTF_1 VCC_AXM_NCTF_2 VCC_AXM_NCTF_3 VCC_AXM_NCTF_4 VCC_AXM_NCTF_5 VCC_AXM_NCTF_6 VCC_AXM_NCTF_7 VCC_AXM_NCTF_8 VCC_AXM_NCTF_9 VCC_AXM_NCTF_10 VCC_AXM_NCTF_11 VCC_AXM_NCTF_12 VCC_AXM_NCTF_13 VCC_AXM_NCTF_14 VCC_AXM_NCTF_15 VCC_AXM_NCTF_16 VCC_AXM_NCTF_17 VCC_AXM_NCTF_18 VCC_AXM_NCTF_19

C744

C744 330U/6.3V

330U/6.3V

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16

VSS NCTF

VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21

VCC NCTF

POWER

VSS_SCB1 VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6

VSS SCBVCC AXM

VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_5 VCC_AXM_6 VCC_AXM_7

VCC AXM NCTF

+1.8VSUS_GMCH

Layout Note: Place on the edge.

C265

C265 22U/4V/08

22U/4V/08

C266

C266 22U/4V/08

22U/4V/08

T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28

A3 B2 C1 BL1 BL51 A51

+1.05V

AT33 AT31 AK29 AK24 AK23 AJ26 AJ23

CRESTLINE_1p0

PROJECT : AT3U

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

Crestline (VCC, NCTF)

NB5/RD1/HW2

Crestline (VCC, NCTF)

Date: Sheet

837Monday, April 30, 2007

LVDS Disable/Enable guideline

External VGA with EV@part,Internal VGA with IV@ part

Signal VCCD_LVDS VCCA_LVDS VCC_TX_LVDS

If SDVO Disable LVDS Disable

GND GND GND

If LVDS enable

1.8V

+3V_VCC_HV

D1 CH751H-40PT

CH751H-40PT

+3V_VCC_HV

C686

4.7U/10V/08

C691

4.7U/10V/08

C258

C258 22U/10V/12

22U/10V/12

+1.25V_VCC_DMI

R508

R508 *0/04

*0/04

C53

C53 220U/4V

220U/4V

C743

C743 *220U/4V

*220U/4V

Ivcc_VTT FSB supply current

0.85A

+1.05V

+VCC_AXD_R

1 2

L26 0/04L26 0/04

Reserved L81 pad for inductor.

Place caps close to VCC_AXD.

Ivcc_DMI supply

current 100mA

R583 0/08R583 0/08

C725

.1U/10V/04

+1.8VSUS_VCC_TX_LVDS

100mA

C664

C664 1000P/04

1000P/04

+VCC_PEG

BLM21PG220SN1D/08

C89

C89 10U/6.3V

10U/6.3V

L21

BLM21PG220SN1D/08

C114

C114 10U/6.3V/06

10U/6.3V/06

NB5/RD1/HW2

C24

C24 220U/4V

220U/4V

+VTTLF1 +VTTLF2 +VTTLF3

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet

Date: Sheet

Date: Sheet of

R505 0/04R505 0/04

+1.25V

R184 0/08R184 0/08

+1.25V

L64 1UH/08L64 1UH/08

1uH+-20%_300mA

C29

C29 220U/4V

220U/4V

IV&EV Dis/Enable setting

+1.05V

Ivcc_PEG supply current

1.2A

SI-1 modified change

+1.05V

Ivcc_RX_DMI supply current 250mA

C49

C710

0.47U/10V/06

PROJECT : AT3U

Quanta Computer Inc.

Crestline (POWER)

+1.05V

40 mil wide

+3V_VCC_HV_L

R40

R40 10_04

10_04

+3V

+1.25V

+1.25V_VCC_AXF+1.25V_VCC_AXF

C30

C30 1U/10V/06

1U/10V/06

Place caps close to VCC_AXF

+1.8VSUS_GMCH

C666

0.47U/10V/06

937Monday, April 30, 2007

R29

0/08

C31

C31 10U/6.3V/06

10U/6.3V/06

+1.25V_VCCA_HPLL+1.25V_VCCA_HPLL+1.25V_VCCA_HPLL+1.25V_VCCA_HPLL

C715

C715 22U/10V/12

22U/10V/12

+1.25V_VCCA_MPLL+1.25V_VCCA_MPLL+1.25V_VCCA_MPLL+1.25V_VCCA_MPLL

+1.25V_VCCA_MPLL+1.25V_VCCA_MPLL

+VCCA_MPLL_L

C45

0.1U/10V/04

C909

C909 1U/06

1U/06

+3V_TV_DAC

C665

10U/4V/08

+3V_VCCSYNC

C69

C69 .1U/10V/04

.1U/10V/04

50mA

C714

C714 .1U/10V/04

.1U/10V/04

150mA

R50 0/04R50 0/04

1 2

123

1 2 123

+3V_VCC_SYNC+3V_VCC_SYNC+3V_VCC_SYNC

R499 0/04R499 0/04

1 2

C652

C652 .1U/04

.1U/04

R501 0/04R501 0/04

123

C653

C653 .1U/04

.1U/04

C718

C718 .1U/10V/04

.1U/10V/04

+1.5V_VCCD_TVDAC

C33

C33 *IV@22nF/3P

*IV@22nF/3P

R47 0/04R47 0/04

C34

C34 *IV@22N

*IV@22N

R504 0/04R504 0/04

1 2 123

C655

C655 .1U/04

.1U/04

R503 0/04R503 0/04

1 2 123

C656

C656 .1U/04

.1U/04

R502 0/04R502 0/04

1 2 123

C654

C654 .1U/04

.1U/04

R58

R58 *0/04

*0/04

123

C657

C657 *IV@22N

*IV@22N

C660

*IV@22N

+1.25V

+1.5V_VCCD_TVDAC+1.5V_VCCD_TVDAC+1.5V_VCCD_TVDAC+1.5V_VCCD_TVDAC

+VCCQ_TVDAC

C43

.1U/04

C662

C662 *IV@22N

*IV@22N

C661

C661 *IV@22N

*IV@22N

C659

C659 *IV@22N

*IV@22N

+3V_VCCA_CRT_DAC+3V_VCCA_CRT_DAC+3V_VCCA_CRT_DAC+3V_VCCA_CRT_DAC+VCCA_CRTDAC

R515

*0/04

+3V_VCCA_DAC_BG+VCC_TVBG+VCC_TVBG

R512

R512 *0/04

*0/04

10uH/100MA/08

10uH+-20%_100mA

L66

10uH/100MA/08

0.1Caps should be placed 200 mils with in its pins.

+VCC_TVDACA_R+VCC_TVDACA_R+VCC_TVDACA_R

R514

R514 *0/04

*0/04

+VCC_TVDACB_R+VCC_TVDACB_R

R513

R513 *0/04

*0/04

+VCC_TVDACC_R+VCC_TVDACC_R

R511

R511 *0/04

*0/04

+1.25V_VCCA_DPLLA

C28

330U/4V

+1.25V_VCCA_DPLLB

C669

330U/4V

R37 0/06R37 0/06

+1.8VSUS_GMCH

80mA

C38

.1U/10V/04

80mA

C680

.1U/10V/04

+1.25V

R177 0/06R177 0/06

C37

C37 1U/06

1U/06

R181 0/08R181 0/08

C242

100U/6.3V

C173

C173 22U/4V/08

22U/4V/08

+1.5V_VCCD_TVDAC

R43

R43 *0/04

*0/04

C32

C32 10U/08

10U/08

C125

4.7U/6.3V/06

1 2

C146

C146 1U/10V/06

1U/10V/06

R826 100/08R826 100/08

+VCCA_MPLL_L

250mA

+1.8V_VCCD_LVDS+1.8V_VCCD_LVDS

R70

R70 *0/04

*0/04

SI-1 modify ( NET name wrong )

+1.8VSUS_VCC_TX_LVDS

IV&EV Dis/Enable setting

+3V

C58

C58 .1U/10V/04

.1U/10V/04

Ivcca_PEG_BG supply current 100mA

C119

C119 22U/4V/08

22U/4V/08

C156

C156 1U/10V/06

1U/10V/06

R89 *0/04R89 *0/04 R44 0/06R44 0/06

C726

C726 .1U/10V/04

.1U/10V/04

+1.25V

FB_220ohm+-25%_100MHz _2A_0.1ohm DC

+3V_VCC_SYNC +3V_VCCA_CRT_DAC

+3V_VCCA_DAC_BG+3V_VCCA_DAC_BG+3V_VCCA_DAC_BG+3V_VCCA_DAC_BG

+1.8VSUS_VCC_TX_LVDS

10mA

R509

R509 *0/04

*0/04

+1.25V_VCCD_PEG_PLL

+1.25V_VCCA_SM

C120

C120 22U/4V/08

22U/4V/08

+1.25V_VCCA_SM_CK

C189

C189 .1U/10V/04

.1U/10V/04

+1.5V_VCCD_CRT

+1.5V_VCCD_QDAC+VCCQ_TVDAC +VCCA_MPLL_L +1.25V_VCCD_PEG_PLL

C93

C93 .1U/10V/04

.1U/10V/04

L65

1 2

BLM21PG221SN1D/08

+1.25V_VCCA_DPLLA +1.25V_VCCA_DPLLB +1.25V_VCCA_HPLL +1.25V_VCCA_MPLL

C668

C668 1000P/04

1000P/04

100mA

C150

C150 1U/10V/06

1U/10V/06

+VCC_TVDACA_R +VCC_TVDACB_R +VCC_TVDACC_R

+1.8V_VCCD_LVDS

150mA

100mA

+1.25V_VCCD_PEG_PLL

R524

R524 1/F/06

1/F/06

C679

C679 10U/6.3V/06

10U/6.3V/06

CRT/TV Disable/Enable guideline

External VGA with EV@part,Internal VGA with IV@ part

Ball

VCCA_CRT_DAC

VCCD_CRT

U34H

J32

VCCSYNC

A33

VCCA_CRT_DAC_1

B33

VCCA_CRT_DAC_2

A30

VCCA_DAC_BG

B32

VSSA_DAC_BG

B49

VCCA_DPLLA

H49

VCCA_DPLLB

AL2

VCCA_HPLL

AM2

VCCA_MPLL

A41

VCCA_LVDS

B41

VSSA_LVDS

K50

VCCA_PEG_BG

K49

VSSA_PEG_BG

U51

VCCA_PEG_PLL

AW18

VCCA_SM_1

AV19

VCCA_SM_2

AU19

VCCA_SM_3

AU18

VCCA_SM_4

AU17

VCCA_SM_5

AT22

VCCA_SM_7

AT21

VCCA_SM_8

AT19

VCCA_SM_9

AT18

VCCA_SM_10

AT17

VCCA_SM_11

AR17

VCCA_SM_NCTF_1

AR16

VCCA_SM_NCTF_2

BC29

VCCA_SM_CK_1

BB29

VCCA_SM_CK_2

C25

VCCA_TVA_DAC_1

B25

VCCA_TVA_DAC_2

C27

VCCA_TVB_DAC_1

B27

VCCA_TVB_DAC_2

B28

VCCA_TVC_DAC_1

A28

VCCA_TVC_DAC_2

M32

VCCD_CRT

L29

VCCD_TVDAC

N28

VCCD_QDAC

AN2

VCCD_HPLL

U48

VCCD_PEG_PLL

J41

VCCD_LVDS_1

H42

VCCD_LVDS_2

C85

C85 .1U/10V/04

.1U/10V/04

Enable

3.3V

1.5V

3.3V

Disable

GND VCCA_TVC_DAC

GND

GND VCCA_DAC_BG

GND

POWER

D TV/CRTLVDS

+1.8VSUS_VCC_SM_CK

C257

C257 22U/10V/12

22U/10V/12

VCCD_TVDAC

VSS_DAC_BG

VCCSYNC

CRTPLLA PEGA SMTV

A CK A LVDS

Ball

AXD

VCC_AXD_NCTF

AXF

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

SM CK

VCC_TX_LVDS

PEG

VCC_RXR_DMI_1 VCC_RXR_DMI_2

DMI

CRESTLINE_1p0

C187

C187 .1U/10V/04

.1U/10V/04

Enable

3.3V

1.5V

3.3VVCCD_QDAC

GNDVCCA_TVA_DAC

3.3VVCCA_TVB_DAC

U13

VTT_1

U12

VTT_2

U11

VTT_3

VTT_4

VTT_5

VTT_6

VTT_7

VTT_8

VTT_9

VTT_10

T13

VTT_11

T11

VTT_12

T10

VTT_13

VTT_14

VTT

VTT_15

VTT_16

VTT_17

VTT_18

VTT_19

VTT_20

VTT_21

VTT_22

AT23

VCC_AXD_1

AU28

VCC_AXD_2

AU24

VCC_AXD_3

AT29

VCC_AXD_4

AT25

VCC_AXD_5

AT30

VCC_AXD_6

AR29

B23

VCC_AXF_1

B21

VCC_AXF_2

A21

VCC_AXF_3

AJ50

VCC_DMI

BK24 BK23 BJ24 BJ23

A43

C40

VCC_HV_1

B40

VCC_HV_2

AD51

VCC_PEG_1

W50

VCC_PEG_2

W51

VCC_PEG_3

V49

VCC_PEG_4

V50

VCC_PEG_5

AH50 AH51

VTTLF1

VTTLF2

AH1

VTTLF3

VTTLF

1uH+-20%_300mA

R173

R173 1/F/06

1/F/06

+VCC_SM_CK_L

C213

C213 10U/6.3V/06

10U/6.3V/06

Disable

+3V_VCC_HV

+VCC_RXR_DMI

+VTTLF1 +VTTLF2 +VTTLF3

+1.8VSUS_GMCH

L25

L25 1uH/300mA/08

1uH/300mA/08

GND

1.5V

GND

C76

2.2U/6.3V/06

Place on the edge.

C78

0.47U/6.3V/04

Place on the edge.

+1.25V_AXD

C137

C137 1U/10V/06

1U/10V/06

+1.25V_VCC_AXF

+1.25V_VCC_DMI

+1.8VSUS_VCC_SM_CK

200mA

+1.8VSUS_VCC_TX_LVDS

C667

C667 .1U/10V/04

.1U/10V/04

IV&EV Dis/Enable setting

D D

+3V_TV_DAC

C C

+1.5V

B B

+3V

BLM18PG181SN1/06

FB_180ohm+-25% _100mHz_1500mA _0.09ohm DC

R24 0/06R24 0/06

+3V

<FAE> INT VGA disable VCCSYNC connect to GND

L62

+3V

+1.25V

1 2

L62

1 2

BLM18PG181SN1/06

FB_180ohm+-25% _100mHz_1500mA _0.09ohm DC

R23 0.03/FR23 0.03/F

FB_120ohm+-25%_100mHz _200mA_0.2ohm DC

L70

BLM11A121S/06

L71

L71 BLM11A121S/06

BLM11A121S/06

R580

0.5/F/06

1 2

+VCCA_MPLL_L

C724

C724 22U/10V/12

22U/10V/12

C947

4.7U/10V/06

L63

IV&EV Dis/Enable setting

A A

22nF & 0.1uF for VCC_TVDACA:C_R should be placed with in 250 mils from Crestline.

U34I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

AB20

D D

C C

B B

A A

AB23 AB26 AB28 AB31 AC10 AC13

AC39 AC43 AC47

AD21 AD26 AD29

AD41 AD45 AD49

AD50 AE10

AE14 AF20

AF23 AF24 AF31

AG2 AG38 AG43 AG47 AG50

AH40 AH41

AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45

AJ49 AK20 AK21 AK26 AK28 AK31 AK51

AM11 AM13

AM3

AM4 AM41 AM45

AN38 AN39 AN43

AP48 AP50 AR11

AR39 AR44 AR47

AT10 AT14 AT41 AT49

AU23 AU29

AU36 AU49 AU51 AV39 AV48

AW1 AW12 AW16

AC3

AD1

AD3

AD5 AD8

AE6

AH3

AH7 AH9

AL1

AN1

AN5 AN7 AP4

AR2

AR7

AU1

AU3

VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

CRESTLINE_1p0

VSS

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198

AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41

U34J

C46

VSS_199

C50

VSS_200

VSS_201

D13

VSS_202

D24

VSS_203

VSS_204

D32

VSS_205

D39

VSS_206

D45

VSS_207

D49

VSS_208

E10

VSS_209

E16

VSS_210

E24

VSS_211

E28

VSS_212

E32

VSS_213

E47

VSS_214

F19

VSS_215

F36

VSS_216

VSS_217

F40

VSS_218

F50

VSS_219

VSS_220

G13

VSS_221

G16

VSS_222

G19

VSS_223

G24

VSS_224

G28

VSS_225

G29

VSS_226

G33

VSS_227

G42

VSS_228

G45

VSS_229

G48

VSS_230

VSS_231

H24

VSS_232

H28

VSS_233

VSS_234

H45

VSS_235

J11

VSS_236

J16

VSS_237

VSS_238

J24

VSS_239

J28

VSS_240

J33

VSS_241

J35

VSS_242

J39

VSS_243

K12

VSS_245

K47

VSS_246

VSS_247

VSS_248

L17

VSS_249

L20

VSS_250

L24

VSS_251

L28

VSS_252

VSS_253

L33

VSS_254

L49

VSS_255

M28

VSS_256

M42

VSS_257

M46

VSS_258

M49

VSS_259

VSS_260

M50

VSS_261

VSS_262

N11

VSS_263

N14

VSS_264

N17

VSS_265

N29

VSS_266

N32

VSS_267

N36

VSS_268

N39

VSS_269

N44

VSS_270

N49

VSS_271

VSS_272

P19

VSS_273

VSS_274

P23

VSS_275

VSS_276

P50

VSS_277

R49

VSS_278

T39

VSS_279

T43

VSS_280

T47

VSS_281

U41

VSS_282

U45

VSS_283

U50

VSS_284

VSS_285

VSS_286

CRESTLINE_1p0

VSS

VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305

VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313

W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28

AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50

PROJECT : AT3U

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

Crestline (VSS)

NB5/RD1/HW2

Crestline (VSS)

Date: Sheet

10 37Monday, April 30, 2007

Strap table

+3V

All strap are sampled with respect to the leading edge of the GMCH Power OK(PWROK) Signal

10/20mils

D48

*CH500H

2 1

3920_RST#

ECPWROK

H_THERMDA [3]

H_THERMDC [3]

SYS_SHDN# [32]

3920_RST# [31]

ECPWROK [6,16,31]

+3V

CFG[17:3] Have internal Pull-up CFG[18:19] Have internal Pull-down Any CFG signal strapping option not list below should be left NC Pin

Pin Name Strap description

D D

CFG[2:0] CFG[4:3] CFG5

CFG6 CFG7

CFG8

CFG9

CFG[11:10]

CFG[13:12]

C C

CFG[15:14]

CFG16

CFG[18:17] SDVO_CTRLDATA

CFG19

CFG20

FSB Frequency Select Reserved DMI X2 Select

Reserved CPU Strap

Low power PCI Express

PCI Express Graphics Lane Reversal

Reserved

XOR/ALLZ

Reserved

FSB Dynamic ODT

Reserved SDVO Present

DMI Lane Reversal

SDVO/PCIe concurrent

Configuration 010 = FSB 800MHz

011 = FSB 667MHz

0 = DMI X2 1 = DMI X4(Default)

0 = Reserved 1 = Mobile CPU(Default)

0 = Normal mode 1 = Low Power mode

0 = Reverse Lanes 1 = Normal operation(Default)

00 = Reserved 01 = XOR Mode Enable 10 = All-Z Mode Enabled 11 = Normal operation(Default)

0 = Dynamic ODT disable 1 = Dynamic ODT Enable(Default)

0 = No SDVO Card present(Default) 1 = SDVO Card Present 0 = Normal operation(Default) 1 = Reverse Lanes

0 = Only SDVO or PCIE x1 is operation(Default) 1 = SDVO and PCIE x1 are operating simultaneously via the PEG port

R164

R164 10K/04

10K/04

LM86_SMD

THERM_ALERT#[16]

1 2

R368 *0/06R368 *0/06

close to ICH

SI 4/20

R163

R163 10K/04

10K/04

LM86__SMC

SYS_SHDN-1#SYS_SHDN-1#SYS_SHDN-1#SYS_SHDN-1#SYS_SHDN-1#SYS_SHDN-1#SYS_SHDN-1#SYS_SHDN-1#SYS_SHDN-1#SYS_SHDN-1#SYS_SHDN-1#SYS_SHDN-1#

R165

R165 200/F/06

200/F/06

LM86VCC

R161

R161 10K/04

10K/04

25mils

SCLK

SDA

ALERT#

OVERT#

MAX6657/GMT-781

ADDRESS: 98H

D46

CH500H

VCC

DXP

DXN

GND

reserve for power shutdown ( if can )

Q56

MMBT3904

1 3

C169

C169 .1U/10V/04

.1U/10V/04

R860 *0/04R860 *0/04

R861 0/04R861 0/04

H_THERMDAH_THERMDAH_THERMDAH_THERMDA

C126

C126 2200P/50V/06

2200P/50V/06

H_THERMDCH_THERMDCH_THERMDCH_THERMDC

SYS_SHDN#SYS_SHDN#

D47

2 1

CH500H

R859 10KR859 10K

B B

+3V

DMI X2 Select

MCH_CFG_5 Low = DMIX2

MCH_CFG_5[6]

High = IDMIX4(Default)

R71

R71 *4.02K/F/04

*4.02K/F/04

FSB Dynamic ODT

MCH_CFG_16 Low = ODT Disable

A A

MCH_CFG_16[6]

High = ODT Enable(Default)

R81

R81 *4.02K/F/04

*4.02K/F/04

DMI Lane Reversal

MCH_CFG_19 Low = Normal operation(Default)

MCH_CFG_19[6]

High = Reverse Lane

+3V

R95

R95 *4.02K/F/04

*4.02K/F/04

SDVO/PCIE Concurrent operation

MCH_CFG_20

MCH_CFG_20[6]

Low = Only SDVO or PCIE X1 is operational(Default) High = SDVO andPCIE X1 are operating simultaneously via the PEG port

+3V

R82

R82 *4.02K/F/04

*4.02K/F/04

XOR /ALLz /Clock Un-gating

MCH_CFG_12MCH_CFG_13 Configuration

MCH_CFG_12[6] MCH_CFG_13[6]

Clock gating disable

XOR Mode Enable

ALL-z Mode Enable

Normal operation(Default)

R63

R63 *4.02K/F/04

*4.02K/F/04

PCI Express Graphics

MCH_CFG_9 Low = Reverse Lane

MCH_CFG_9[6]

R80

R80 *4.02K/F/04

*4.02K/F/04

High = Normal operation(Default)

R61

R61 *4.02K/F/04

*4.02K/F/04

MBDATA[28,31,33]

MBCLK[28,31,33]

SDVO Present

Strap define at External DVI control page

Size Document Number Rev

Size Document Number Rev Custom

Custom

NB5/RD1/HW2

Custom Date: Sheet

Date: Sheet

2N7002EQ42N7002E

+3V

2N7002EQ52N7002E

PROJECT : AT3U

Quanta Computer Inc.

10 -- GMCH STRAP-3(6 of 6)

LM86_SMD

LM86__SMC

11 37Wednesday, May 02, 2007

C382

C382 .1U/10V/04

.1U/10V/04

DDRII DUAL CHANNEL A,B.

A A

SMDDR_VTERM

DDRII A CHANNEL DDRII B CHANNEL

C325

C325 .1U/10V/04

.1U/10V/04

C380

C380 .1U/10V/04

.1U/10V/04

SMDDR_VTERM

C384

C419

.1U/10V/04

M_A_A[13..0] M_B_A[13..0]

SMDDR_VTERM

C378

C435

.1U/10V/04

M_A_A[13..0] [7,13] M_B_A[13..0] [7,13]

C434

C434 .1U/10V/04

.1U/10V/04

SMDDR_VTERM [36]

C415

C379

.1U/10V/04

C401

C401 .1U/10V/04

.1U/10V/04

C418

C418 .1U/10V/04

.1U/10V/04

C362

C362 .1U/10V/04

.1U/10V/04

C326 .1U/10V/04

.1U/10V/04

SMDDR_VTERM

C363

C363 .1U/10V/04

.1U/10V/04

C361

C361 .1U/10V/04

.1U/10V/04C379

C360

C360 .1U/10V/04

.1U/10V/04

C383

C383 .1U/10V/04

.1U/10V/04

C332

C332 .1U/10V/04

.1U/10V/04

1.8VSUS +3V

C320

C320 .1U/10V/04

.1U/10V/04

C321

C321 .1U/10V/04

.1U/10V/04

1.8VSUS [6,8,9,13,36] +3V [2,6,8,9,11,13,14,15,16,17,18,19,20,21,22,23,24,25,27,28,29,30,31,32,37]

C420

C359

C318

C318 .1U/10V/04

.1U/10V/04

.1U/10V/04C326

C381

C381 .1U/10V/04

.1U/10V/04

C353

C353 .1U/10V/04

.1U/10V/04

Layout note: Place one cap close to every 2 pullup resistors terminated to SMDDR_VTERM

M_A_ODT0[6,13]

B B

M_A_CKE1[6,13]

M_A_BS#0[7,13]

M_A_RAS#[7,13]

M_A_BS#1[7,13]

M_A_WE#[7,13]

M_A_CAS#[7,13]

SA_MA14[6,13] SB_MA14[6,13]

M_A_ODT0 M_A_A13 M_A_A8 M_A_A5 M_A_A3 M_A_A1

M_A_CKE1 M_A_A11 M_A_A10 M_A_BS#0 M_A_A7 M_A_A6 M_A_A2 M_A_A4

M_A_BS#1 M_A_A9 M_A_A12

RP21 56X2RP21 56X2 RP13 56X2RP13 56X2 RP14 56X2RP14 56X2

RP23 56X2RP23 56X2 RP15 56X2RP15 56X2 RP24 56X2RP24 56X2 RP18 56X2RP18 56X2

RP20 56X2RP20 56X2 RP22 56X2RP22 56X2 RP16 56X2RP16 56X2

R742 56_04R742 56_04 R743 56_04R743 56_04

SMDDR_VTERM

add terminater resistor

M_B_BS#1[7,13]

M_B_BS#2[7,13]

M_B_CKE0[6,13] M_B_RAS#[7,13]

M_B_CS#0[6,13] M_B_BS#0[7,13]

M_B_CAS#[7,13]

M_B_WE#[7,13]

M_B_A0 M_B_A5 M_B_A1 M_B_A8 M_B_A3

M_B_A4 M_B_A2 M_B_A12 M_B_A9 M_B_A7 M_B_A6

M_B_A10

RP37 56X2RP37 56X2 RP27 56X2RP27 56X2 RP26 56X2RP26 56X2

RP36 56X2RP36 56X2 RP25 56X2RP25 56X2 RP33 56X2RP33 56X2 RP31 56X2RP31 56X2

RP34 56X2RP34 56X2 RP29 56X2RP29 56X2 RP28 56X2RP28 56X2

SMDDR_VTERM

+3V

R270

C C

CGCLK_SMB[2,13,29] CGDAT_SMB[2,13,29]

PM_EXTTS#0[6,13]

PM_EXTTS#1[6]

D D

PM_EXTTS#1PM_EXTTS#1

CGCLK_SMB CGDAT_SMB PM_EXTTS#0

R238 *0/04R238 *0/04

U12

SCLK

SDA

ALERT#

OVERT#

*LM86CIMM

VCC DXP DXN

GND

R270 *200/04

*200/04

LM86_3V

1 2 3 5

C437

C437 *.1U/10V/04

*.1U/10V/04

DDR_THERMDA

DDR_THERMDC

Uninstall

Q13

*PMST3904

M_A_CS#0[6,13]

M_B_ODT0[6,13] M_B_ODT1[6,13] M_B_CS#1[6,13] M_A_CS#1[6,13]

M_A_ODT1[6,13]

M_B_CKE1[6,13]

M_A_CKE0[6,13]

M_A_BS#2[7,13]

M_A_A0 M_B_A13

M_ODT3

M_ODT1 M_B_A11

RP19 56X2RP19 56X2 RP35 56X2RP35 56X2 RP30 56X2RP30 56X2 RP17 56X2RP17 56X2 RP32 56X2RP32 56X2 RP12 56X2RP12 56X2

SMDDR_VTERM

NB5/RD1/HW2

PROJECT : AT3U

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

DDRII RES.ARRAY

Date: Sheet

12 37Wednesday, May 02, 2007

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