HP 6910P Schematics

A
1 1
2 2
B
C
D
E
Compal confidential
Schematics Document
Mobile Merom uFCPGA with Intel Crestline_PM+ICH8-M core logic
3 3
IBT00 LA-3261P UMA
2007-03-28
4 4
Secur ity Classification
Issued Date
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2006/02/13 2006/03/10
REV:1A (MV2)
Compal Secret Data
Deciphered Date
D
Title
Size Doc ument Number Re v
Cus tom
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
LA -3 26 1P U MA
E
1 55Wednesday, March 28, 2007
0.4
A
Compal confidential
File Name : LA-3261P
B
C
Chimay UMA
D
E
1 1
CRT & TV OUT
P16
LVDS Panel Interface
P17
Thermal Sensor AD M1032ARMZ
P4
Fan c onn
P4
Intel Crestline MCH
SDV O
2 2
DVI (Docking)
P33
CH 7307 C
P16
DM I X4
PCI-E BUS
10/100/1000 LAN
Mini-Card
Intel 82566MM
P23
RJ 45/11 CONN
3 3
P24
LED
P30
CardBus Controller & PCMCIA conn
Ri coh R5C853 & R5C851
P25
Slot 0/Smart Card
1394 port
P28
6in1 Slot
PCI
daug hte r board
RTC CKT.
P19
Mo bile Merom
uFCPGA-478 CPU
H_ A#( 3.. 35)
H_ D#( 0..6 3)
FSB
667/800MH z 1.05V
FC BGA 1299
P7, 8, 9, 10, 11, 12
Intel ICH8-M
mB GA-676
P18, 19, 20, 21
SPI ROM & Debug port
16Mb*2 or 32Mb*1
P4, 5, 6
C- Link
SPI
LPC BUS
DDR2 667MHz 1. 8V
Dual Channel
USB2.0
Azalia
SATA Master
PATA Slave
P30
DDR2- SO-DIMM X2
BANK 0, 1, 2, 3
P13, 14
USB conn x2 (Docking)
FingerPrint er 2501B USBx1
USB conn x3
BT Co nn
Mini-Card WWAN
P25P25
Audio CKT
AD1981HD
P26
SATA HDD Connector
P22
Multi-bay II Connector
P22
P33
P30
P28
P28
CK505
TSSOP- 64
Clock Generator IC S 9LPR S355
P15
daug hte r board
MDC
P32
AMP & Audio Jack
MAX9710
P33
Docking CONN.
*RJ-45(LED*2) *RJ-11(Pass Through) *CRT *COMPOSITE Video Out *TVOUT *DVI *LINE IN
P27
*LINE OUT
Power OK CKT.
P35
4 4
Power On/Off CKT.
P32
TPM1.2 SLB9635TT
P30
Touch P ad CON N.
SMSC KBC 1070
SMSC KBC 1021-NU
P31
Int.KBD
P32 P32
SMSC Super I/O
LPC47N217
COM1 LPT ( Docking ) ( Docking )
P33 P33
P29
*PCI-E x2 *Serial Port *Parallel Port *PS/2 x2 *USB x2 *DC JACK
DC/DC Interface CKT.
P34
A
TrackPoint CONN.
B
P32
Secur ity Classification
Issued Date
C
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
D
Title
Size Doc ument Number Re v
Cus tom
Date: Sheet of
Compal Electronics, Inc.
Block Diagram
LA -3 26 1P U MA
E
2 55Tuesday, March 27, 2 007
0.4
A
Voltage Rails
power plane
State
S0
S3/M1
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery don't exist
1 1
PCI Devices
EXTERNAL
CA RD B US & 139 4
DMA Channel DM A0 DM A1 DM A2 DM A3 DM A4 DM A5 DM A6 DM A7
USB PORT#
O MEANS ON X MEANS OFF
+B
LDO3
LDO5
O
O
O
O
O
X
De st in at ion
0
1
2
3
4
5
6
7
8
9
Walk -up0 (R ight side)
Finge rprint
Reserv e
WWAN
Walk -up1 (Le ft Side)
Walk -up2 (Le ft Side)
Bluet ooth
Reserv e
Dockin g
Dockin g
+5VS
+3VS
+2.5VS
+1.8VS
+5VALW
+3VALW
O
O
O
O
X
+1.8V
+5V
+0.9V
+1.5VS
+1.25VS
+VGA_CORE
+CPU_CORE
+VCCP
O
O
X X
X
OO
X
X
X
X X X
ID SE L# RE Q/G NT# PI RQ
AD 22 2 C, D, E, G
Device MODEM / LAN ECP FL OPP Y DISK AUDIO (Cascade) Unused Unused Unused
+3VM
+1.05VM
+1.25VM
O
O
O
O
X
X
CLOCK
O
O
O
O
X
X
IRQ
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Secur ity Classification
Issued Date
A
De vic e
Syste m Timer
Keyboa rd
N/A
Seri al po rt (COM2),L AN/Modem
Seri al port (COM1)
Audio /VGA
Floppy
Para llel port
Syst em CM OS/Real-tim e clock
Micr osoft ACPI
N/A, Momem,LAN
Mass str orag e contr ol/ PCI sim ple communi cation cont rol
syna ctic PS2 port Gl idePAD
Nume ric Data Process
Prim ary I DE interfac e,HDD
Seco ndar y IDE innt erface,CD-R OM
Mobi le I ntel Crestline E xpress Chip set Family
Micr osof t UA A Bus Dri ver for Hig h Definitio n Audio
Inte l 82 801H (ICH8 Fa mily) PCI E xpress Root Port -27D0
Broa dcom NetXtrem e Gigabit E thernet
Inte l 82 801H (ICH8 Fa mily)PCI Ex press Root Port - 27D2
Broa dcom 80 2.11b/g WLA N
Inte l 82 801H (ICH8 Fa mily)USB Un iversal Hos t Controll
Inte l 82 801H (ICH8 Fa mily)USB Un iversal Hos t Controll
Rico h R5C 853 Cardbus Control
Rico h R5 C853 Integrates FlashMedia Control
Rico h R5 C853 Gemcore bas ed SmartCar d Control
Inte l 82 801H (ICH8 Fa mily)PCI Ex press Root Port - 27D6
Inte l 82 801H (ICH8 Fa mily)USB Un iversal Hos t Controll
Inte l 82 801H (ICH8 Fa mily)USB Un iversal Hos t Controll
Inte l 82 801H (ICH8 Fa mily)USB2 E nhanced Hos t Controll
Inte l 82 801H (ICH8 Fa mily)USB Un iversal Hos t Controll
SDA Stan dard Co mpliant SD Host Contro ller
HP M obil e Data Pro tection Sen sor
2005/03/10 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
Cus tom
Date: Sheet of
Compal Electronics, Inc.
Notes List
LA -3 26 1P U MA
3 55Tuesday, March 27, 2 007
0.4
5
D D
H_A#[ 3..16]7
H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16
H_NMI19 H_SMI#19
12
R1255
56_0402_5%@
B
2
C
Q85 MMBT3904_SOT23
H_ADSTB#0
H_REQ#0 H_REQ#1 H_REQ#2
H_REQ#4
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1
H_A20M# H_FER R# H_IGNN E#
H_STPCLK# H_INT R H_NMI H_SMI#
OCP# 20,44
H_ADSTB#07
H_REQ#07 H_REQ#17 H_REQ#27 H_REQ#37 H_REQ#47
C C
B B
A A
H_A#[ 17..35]7
H_ADSTB#17
H_A20M#19
H_FER R#19
H_IGNN E#19
H_STPCLK#19 H_INT R19
+VCCP
H_PROCH OT# OCP#
E
3 1
@
JP12A
J4
A[3]#
L5
A[4]#
L4
A[5]#
K5
A[6]#
M3
A[7]#
N2
A[8]#
J1
A[9]#
N3
A[10]#
P5
A[11]#
P2
A[12]#
L2
A[13]#
P4
A[14]#
P1
A[15]#
R1
A[16]#
M1
ADSTB[0]#
K3
REQ[0]#
H2
REQ[1]#
K2
REQ[2]#
J3
REQ[3]#
L1
REQ[4]#
Y2
A[17]#
U5
A[18]#
R3
A[19]#
W6
A[20]#
U4
A[21]#
Y5
A[22]#
U1
A[23]#
R4
A[24]#
T5
A[25]#
T3
A[26]#
W2
A[27]#
W5
A[28]#
Y4
A[29]#
U2
A[30]#
V4
A[31]#
W3
A[32]#
AA4
A[33]#
AB2
A[34]#
AA3
A[35]#
V1
ADSTB[1]#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
M4
RSVD[01]
N5
RSVD[02]
T2
RSVD[03]
V3
RSVD[04]
B2
RSVD[05]
C3
RSVD[06]
D2
RSVD[07]
D22
RSVD[08]
D3
RSVD[09]
F6
RSVD[10]
Mero m Ball-out Rev 1a
ADDR GROUP 0 ADDR GROUP 1
ICH
ADS# BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
RESET#
RS[0]# RS[1]# RS[2]#
TRDY#
HIT#
HITM#
BPM[0]# BPM[1]# BPM[2]# BPM[3]#
PRDY# PREQ#
TCK
TDO TMS
TRST#
XDP/ITP SIGNALS
DBR#
TH ERMAL
PROCHOT#
THERMDA THERMDC
THERMTRIP#
H CLK
BCLK[0] BCLK[1]
RESERVED
conn@
TDI
4
3
XDP Connector
H_ADS#H_A#3
H1
H_BNR #
E2
H_BPR I#
G5
H_DEF ER#
H5
H_D RDY#
F21
H_ DBSY#
E1
H_BR0#
F1
H_IER R#
D20
H_INIT#
B3
H_LOCK#
H4
H_RESET#
C1
H_RS#0
F3
H_RS#1
F4
H_RS#2
G3
H_ TRDY#H_REQ#3
G2
H_HIT#
G6
H_HITM#
E4
XDP_BPM#0
AD4
XDP_BPM#1
AD3
XDP_BPM#2
AD1
XDP_BPM#3
AC4
XDP_BPM#4
AC2
XDP_BPM#5
AC1
XDP_TCK
AC5
XDP_TDI
AA6
XDP_TDO
AB3
XDP_TMS
AB5
XDP_TRST#
AB6
XDP_DBRESET#
C20
H_PROCH OT#
D21
H_THERMDA_R
A24
H_THE RMDC_R
B25
H_THERMTRIP#
C7
CLK_CP U_BCLK
A22
CLK_CP U_BCLK#
A21
1113 Add res isto rs in ser ies with th e diode sig nals going to ADM1032.
For Mero m, R1798 and R1799 a re 0ohm For Penr yn, R17 98 and R179 9 are 100oh m.
H_ADS# 7 H_BNR # 7
H_BPR I# 7
H_DEF ER# 7 H_D RDY# 7 H_D BSY# 7
H_BR0# 7
H_INIT# 19
H_LOCK# 7
H_RESET# 7
H_RS#0 7
H_RS#1 7
H_RS#2 7
H_T RDY# 7
H_HIT# 7 H_HITM# 7
XDP_DBRESET# 20
R1798 0_0402_5%
1 2
R1799 0_0402_5%
1 2
R172
56_0402_5%
12
+VCCP
12
H_THERMDA H_THERMDC
H_PROCH OT# 43
+VCCP
R410
68_0402_5%
H_THERMTRIP# 7,19
CLK_CP U_BCLK 15 CLK_CP U_BCLK# 15
H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil
H_PW RGOOD_R5
+VCCP +VCCP
0.1U_0402_16V4Z
1
C1099
2
2
layo ut n ote: Cha nge R237 to 649 ohm if using XTP to ITP adap ter
JP51
1
XDP_BPM#5 XDP_BPM#4
XDP_BPM#3 XDP_BPM#2
XDP_BPM#1 XDP_BPM#0
H_PW RGOOD_R XDP_HOOK1
XDP_TCK
Thermal Sensor ADM1032ARMZ
3
5
7
9
11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
conn@
1 2
2200P_0402_50V7K
+3VS
GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16
SAMTE_BSH-030-01-L-D-A
C273
0.1U_0402_16V4Z
H_THERMDA
C264
H_THERMDC
R228
1 2
10K_0402_5%
ITPCLK/HOOK4
ITPCLK#/HOOK5
RESET#/HOOK6
+3VS
2
1
THERM#
OBSDATA_C0 OBSDATA_C1
OBSDATA_C2 OBSDATA_C3
OBSDATA_D0 OBSDATA_D1
OBSDATA_D2 OBSDATA_D3
VCC_OBS_CD
DBR#/HOOK7
2
GND1
4
OBSFN_C0
6
OBSFN_C1
8
GND3
10 12 14
GND5
16 18 20
GND7
22
OBSFN_D0
24
OBSFN_D1
26
GND9
28 30 32
GND11
34 36 38
GND13
40 42 44 46 48 50
GND15
52
TD0
54
TRST#
56
TDI
58
TMS
60
GND17
U16
1
VDD
2
D+
3
D-
THERM#4GND
ADM1032ARMZ-2REEL_MSOP8
Addres s:100_1100
PWM Fan Control circuit
+3VS
FAN_PWM31
THERM#
1
INB
2
INA
XDP_DBRESET#_R
R243
1 2
04/ 10 no stuff
XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5
XDP_HOOK1
XDP_TRST#
XDP_TCK
CLK_CPU_XDP CLK_CPU_XDP#
XDP_TDO XDP_TRST# XDP_TDI XDP_TMS XDP_PRE
R143 54.9_0402_1%
1 2
R236 54.9_0402_1%
1 2
R1670 54.9_0402_1%
1 2
R241 54.9_0402_1%
1 2
R1430 54.9_0402_1%@
1 2
R237 51_0402_1%
1 2
R239 54.9_0402_1%
1 2
1K_0402_1%
H_RESET#H_RESET#_R
R1431
1 2
XDP_DBRESET#XDP_DBRESET#_R
12
200_0402_1%
R1432
R1433 0_0402_5%
1 2
Plac e R1 431 withi n 200ps (~1 ") to CPU
R227
8
SCLK
7
SDATA
6
ALERT#
5
ICH_SM _CLK20,25
ICH_SM_DA20,25
0308 change desig n
5
U24
P
4
O
G
TC7SH00FU_ SSOP5
3
ICH_SM_CLK
ICH_SM_DA
THERM_SCI#
+5VS
1 2
ICH_SM_CLK ICH_SM_DA
ACES_85204-03001
10K_0402_5%
1 2 3
1
THERM_SCI# 20
conn@
JP8
1 2
G1
3
G2
+3VS
1K_0402_5%@
+VCCP
CLK_CPU_XDP 15 CLK_CPU_XDP# 15
4 5
Secur ity Classification
Issued Date
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
Cus tom
2
Date: Sheet of
Compal Electronics, Inc.
Merom(1/3)-AGTL+/XDP
LA -3 26 1P U MA
1
4 55Tuesday, March 27, 2007
0.4
5
4
3
2
1
H_D #[0..15]7
D D
H_DSTBN#07 H_DSTBP#07
H_DIN V#07
H_D# [16..31]7
C C
H_DSTBN#17 H_DSTBP#17
H_DIN V#17
R1264 1K_0402_5%@
1 2
R1265 1K_0402_5%@
1 2
C1101 0.1U_0402_16V4Z@
1 2
CPU_BSEL015 CPU_BSEL115 CPU_BSEL215
T1
T2 T3
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DIN V#0
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DIN V#1 H_DIN V#3
V_CPU_GTLREF
TEST1 TEST2 TEST3 TEST4 TEST5 TEST6
CPU_BSEL0 H_PW RGOOD CPU_BSEL1 CPU_BSEL2
JP12B
E22
D[0]#
F24
D[1]#
E26
D[2]#
G22
D[3]#
F23
D[4]#
G25
D[5]#
E25
D[6]#
E23
D[7]#
K24
D[8]#
G24
D[9]#
J24
D[10]#
J23
D[11]#
H22
D[12]#
F26
D[13]#
K22
D[14]#
H23
D[15]#
J26
DSTBN[0]#
H26
DSTBP[0]#
H25
DINV[0]#
N22
D[16]#
K25
D[17]#
P26
D[18]#
R23
D[19]#
L23
D[20]#
M24
D[21]#
L22
D[22]#
M23
D[23]#
P25
D[24]#
P23
D[25]#
P22
D[26]#
T24
D[27]#
R24
D[28]#
L25
D[29]#
T25
D[30]#
N25
D[31]#
L26
DSTBN[1]#
M26
DSTBP[1]#
N24
DINV[1]#
AD26
GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
B22
BSEL[0]
B23
BSEL[1]
C21
BSEL[2]
Mero m Ball-out Rev 1 a
conn@
DATA GRP 1
MISC
DATA GRP 0
D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]#
DATA GRP 2DATA GRP 3
D[46]#
D[47]# DSTBN[2]# DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]# DSTBN[3]# DSTBP[3]#
DINV[3]#
COMP[0] COMP[1] COMP[2] COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20
R26 U26 AA1 Y1
E5 B5 D24 D6 D7 AE6
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DIN V#2
H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3
COMP0 COMP1 COMP2 COMP3
H_DPRSTP# H_DPSLP# H_DPW R#
H_CPUSLP # H_PSI#
R1436
1K_0402_5%
H_PW RGOOD_R
12
layo ut n ote: Rou te TES T3 & TEST5 traces on g round refer enced layer to the TPs
CPU_BSEL CPU_BSEL2 CPU_BSEL1
166
B B
200
0 1
0
1
CPU_BSEL0
1
0
H_D# [32..47] 7
H_DSTBN#2 7 H_DSTBP#2 7 H_DIN V#2 7 H_D# [48..63] 7
H_DSTBN#3 7 H_DSTBP#3 7 H_DIN V#3 7
H_DPRSTP# 7,19,43
H_DPSLP# 19 H_DPW R# 7 H_PW RGOOD 19
H_CPUSLP # 7 H_PSI# 43
H_PW RGOOD_R 4
12
R355
R1220
27.4_0402_1%
54.9_0402_1%
Resistor placed within
0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils.
12
R245
R244
54.9_0402_1%
27.4_0402_1%
12
12
+VCC_C ORE +VCC_C ORE
JP12C
A7
VCC[001]
A9
VCC[002]
A10
VCC[003]
A12
VCC[004]
A13
VCC[005]
A15
VCC[006]
A17
VCC[007]
A18
VCC[008]
A20
VCC[009]
B7
VCC[010]
B9
VCC[011]
B10
VCC[012]
B12
VCC[013]
B14
VCC[014]
B15
VCC[015]
B17
VCC[016]
B18
VCC[017]
B20
VCC[018]
C9
VCC[019]
C10
VCC[020]
C12
VCC[021]
C13
VCC[022]
C15
VCC[023]
C17
VCC[024]
C18
VCC[025]
D9
VCC[026]
D10
VCC[027]
D12
VCC[028]
D14
VCC[029]
D15
VCC[030]
D17
VCC[031]
D18
VCC[032]
E7
VCC[033]
E9
VCC[034]
E10
VCC[035]
E12
VCC[036]
E13
VCC[037]
E15
VCC[038]
E17
VCC[039]
E18
VCC[040]
E20
VCC[041]
F7
VCC[042]
F9
VCC[043]
F10
VCC[044]
F12
VCC[045]
F14
VCC[046]
F15
VCC[047]
F17
VCC[048]
F18
VCC[049]
F20
VCC[050]
AA7
VCC[051]
AA9
VCC[052]
AA10
VCC[053]
AA12
VCC[054]
AA13
VCC[055]
AA15
VCC[056]
AA17
VCC[057]
AA18
VCC[058]
AA20
VCC[059]
AB9
VCC[060]
AC10
VCC[061]
AB10
VCC[062]
AB12
VCC[063]
AB14
VCC[064]
AB15
VCC[065]
AB17
VCC[066]
AB18
VCC[067]
Mero m Ball-out Rev 1a
conn@
VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]
VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]
VCCA[01] VCCA[02]
VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]
VCCSENSE
VSSSENSE
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20
R1434 0_0402_5%
G21 V6
R1435 0_0402_5%
J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21
B26 C26
AD6 AF5 AE5 AF4 AE3 AF3 AE2
VCCSENS E
AF7
VSSSENSE
AE7
.
Length match within 25 mils.
+VCCP
12 12
C1100
CPU_V ID0 43 CPU_V ID1 43 CPU_V ID2 43 CPU_V ID3 43 CPU_V ID4 43 CPU_V ID5 43 CPU_V ID6 43
VCCSENSE 43
VSSSENSE 4 3
1
+
330U_D2E_2.5VM _R7
2
0228 change value
1
1
C531
C520
2
2
10U_0805_6.3V6M
Near pin B26
+1.5VS
0.01U_0402_16V7K
The trace width/space/other is 20/7/25.
+VCC_ CORE
1 2
1 2
R1269 100_0402_1%
R1270 100_0402_1%
VCCSENS E
VSSSENSE
V_CPU_GTLREF
+VCCP
12
R1268 1K_0402_1%
12
R1271 2K_0402_1%
Close to CPU pin AD26 within 500mils.
A A
Secur ity Classification
Issued Date
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
2
Close to CPU pin within 500mils.
Title
Size Doc ument Number Re v
Cus tom
Date: Sheet of
Compal Electronics, Inc.
Merom(2/3)-AGTL+/PWR
LA -3 26 1P U MA
1
5 55Tuesday, March 27, 2007
0.4
5
Place these capac itors on L8
D D
JP12D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
A23
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
C C
B B
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080] VSS[081]P3VSS[162]
Mero m Ball-out Rev 1a
conn@
VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]
VSS[163]
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
.
(Nort h side ,Secon dary L ayer)
Place these capac itors on L8 (Nort h side ,Secon dary L ayer)
Place these capac itors on L8 (Sort h side ,Secon dary L ayer)
Place these capac itors on L8 (Sort h side ,Secon dary L ayer)
0314 change to mo unt
330U_D2E_2.5VM _R7
+VCCP
1
C940
0.1U_0402_10V6K
2
4
+VCC_ CORE
1
+
C931
2
+VCC_ CORE
1
C899
10U_0805_6.3V6M
2
+VCC_ CORE
1
C907
10U_0805_6.3V6M
2
+VCC_ CORE
1
C915
10U_0805_6.3V6M
2
+VCC_ CORE
1
C923
10U_0805_6.3V6M
2
Near CPU CORE regulator
330U_D2E_2.5VM_R7
1
+
C932
C933
2
330U_D2E_2.5VM _R7
1
C941
0.1U_0402_10V6K
2
1
C900
10U_0805_6.3V6M
2
1
C908
10U_0805_6.3V6M
2
1
C916
10U_0805_6.3V6M
2
1
C924
10U_0805_6.3V6M
2
1
+
C935
2
330U_D2E_2.5VM_R7
1
C942
0.1U_0402_10V6K
2
1
+
2
1
C901
10U_0805_6.3V6M
2
1
C909
10U_0805_6.3V6M
2
1
C917
10U_0805_6.3V6M
2
1
C925
10U_0805_6.3V6M
2
330U_D2E_2.5VM _R7
1
+
C937
C936
2
330U_D2E_2.5VM _R7
1
C943
0.1U_0402_10V6K
2
3
1
C902
10U_0805_6.3V6M
2
1
C910
10U_0805_6.3V6M
2
1
C918
10U_0805_6.3V6M
2
1
C926
10U_0805_6.3V6M
2
ESR <= 1.5m ohm Capacitor > 1980uF
1
1
+
+
C934
@
2
820U_E9_2_5V_M_R7
2
1
C944
0.1U_0402_10V6K
2
1
C903
10U_0805_6.3V6M
2
1
C911
10U_0805_6.3V6M
2
1
C919
10U_0805_6.3V6M
2
1
C927
10U_0805_6.3V6M
2
Plac e these inside sock et cavity o n L8 (North side Seco ndary)
1
C945
0.1U_0402_10V6K
2
1
C904
10U_0805_6.3V6M
2
1
C912
10U_0805_6.3V6M
2
1
C920
10U_0805_6.3V6M
2
1
C928
10U_0805_6.3V6M
2
2
1
C905
10U_0805_6.3V6M
2
1
C913
10U_0805_6.3V6M
2
1
C921
10U_0805_6.3V6M
2
1
C929
10U_0805_6.3V6M
2
1
C906
10U_0805_6.3V6M
2
1
C914
10U_0805_6.3V6M
2
1
C922
10U_0805_6.3V6M
2
1
C930
10U_0805_6.3V6M
2
1
Mid Frequence Decoupling
A A
Secur ity Classification
Issued Date
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
Cus tom
2
Date: Sheet of
Compal Electronics, Inc.
Merom(3/3)-GND&Bypass
LA -3 26 1P U MA
1
6 55Tuesday, March 27, 2007
0.4
5
W10
AD12
AC14 AD11 AC11
AG3
AJ14
AE11 AH12
AH13
M10 N12
AE3 AD9 AC9 AC7
AB2 AD7 AB1
AC6 AE2 AC5
AH8
AE9
AH5
AE7
AE5
AH2
E2
G2 G7 M6 H7 H3 G4
F3 N8 H2
N9 H5
P13
K9 M2
Y8
V4 M3
J1 N5 N3 W6 W9 N2
Y7 Y9
P4 W3 N1
Y3
AJ9
AJ5
AJ6
AJ7 AJ2
AJ3
B3 C2
W1 W2
B6
E5
B9
A9
U15A
H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63
H_SWING H_RCOMP
H_SCOMP H_SCOMP#
H_CPURST# H_CPUSLP#
H_AVREF H_DVREF
CRES TLINE_1p0
H_ADSTB#_0 H_ADSTB#_1
H_DEFER#
HOST
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3
H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3
H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3
H_REQ#_0 H_REQ#_1
H_REQ#_2 H_REQ#_3
H_REQ#_4
H_D #[0..63]5
D D
C C
+VCCP
12
12
R1197
R1196
54.9_0402_1%
54.9_0402_1%
H_RESET#4
H_CPUSLP #5
B B
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
H_SW NG H_RCOMP
H_SCOMP H_SCOMP#
H_RESET# H_CPUSLP #
H_VRE F
layo ut note:
Rout e H_ SCOM P an d H_ SCOMP # with trac e width, sp acing and i mpedance (5 5 ohm) same as FSB dat a traces
Layout Note: H_RCOM P / H_VREF / H_SWNG
trace width and spacing is 10/20
+VCCP
12
1K_0402_1%
R1208
0.1U_0402_16V4Z
H_VRE F
12
A A
1
C60
2
R1212
2K_0402_1%
H_RCOMP
12
R1199
24.9_0402_1%
12
R1206
221_0603_1%
H_SW NG
12
1
R1210
C896
2
100_0402_1%
0.1U_0402_16V4Z
Near B3 pinwith in 100 mils from N B
5
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8
H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35
H_ADS#
H_BNR#
H_BPRI#
H_BREQ#
H_DBSY#
H_DRDY#
H_HIT# H_HITM#
H_LOCK# H_TRDY#
H_RS#_0 H_RS#_1 H_RS#_2
J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19
G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7
K5 L2 AD13 AE13
M7 K3 AD2 AH11
L7 K2 AC2 AJ10
M14 E13 A11 H13 B12
E12 D7 D8
4
PM_PWROK20,31,45
V_DDR _MCH_REF13,14,42
4
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR # H_BPR I# H_BR0# H_DEF ER# H_ DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPW R# H_D RDY# H_HIT# H_HITM# H_LOCK# H_ TRDY#
H_DIN V#0 H_DIN V#1 H_DIN V#2 H_DIN V#3
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
H_RS#0 H_RS#1 H_RS#2
VGATE20,31
Layout Note: V_DDR_MCH_REF trace width and spacin g is 20/20.
H_A#[ 3..35] 4
H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4 H_BNR# 4 H_BPR I# 4 H_BR0# 4 H_DEF ER# 4 H_DB SY# 4 CLK_MCH_BCLK 15 CLK_MCH_BCLK# 15 H_DPW R# 5 H_D RDY# 4 H_HIT# 4 H_HITM# 4 H_LOCK# 4 H_TR DY# 4
H_DIN V#0 5 H_DIN V#1 5 H_DIN V#2 5 H_DIN V#3 5
H_DSTBN#0 5 H_DSTBN#1 5 H_DSTBN#2 5 H_DSTBN#3 5
H_DSTBP#0 5 H_DSTBP#1 5 H_DSTBP#2 5 H_DSTBP#3 5
H_REQ#0 4 H_REQ#1 4 H_REQ#2 4 H_REQ#3 4 H_REQ#4 4
H_RS#0 4 H_RS#1 4 H_RS#2 4
R1483 0_0402_5%@
12
12
R1484 0_0402_5%
V_DDR _MCH_REF
1
C895
2
0.1U_0402_16V4Z
3
2.2U_0 603_6.3V4Z
2.2U_0 603_6.3V4Z
PM_EXTTS#0
PM_EXTTS#1
CLKREQ#_B DMI_TXN0
MCH_CLKSEL015 MCH_CLKSEL115 MCH_CLKSEL215
PM_BMBUSY#20
0612 a dd
1128 Install R1739
1226 Add C
0309 add
+1.8V
12
12
SMRCOMP_VOH
SMRCOMP_VOL
H_THERMTRIP#4,19
PM_POK_R
R1201
1K_0402_1%@
R1204
1K_0402_1%
@
Secur ity Classification
Issued Date
3
+1.8V
2
2
12
C1103
C1105
CFG59 CFG6 CFG79 CFG89 CFG99
R1437
1
1K_0402_1%
0.01U_0402_25V7K
12
R31
3.01K_0402_1%
NA le ad free
12
R1438
1
1K_0402_1%
2
0612 a dd
0.01U_0402_25V7K
DDR_A_MA1413 DDR_B_MA1414
+3VS
12
12
12
MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2
CFG5 CFG6 CFG7
CFG9 CFG10 CFG11 CFG12 CFG13
CFG16
CFG18 CFG19 CFG20
PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PM_POK_R PLT_RST#_R THERMTRIP#
12
DPRSLPVR
C1370
R1446
100_0402_5%
1
C1102
1
2
C1104
R1439
10K_0402_5%
R1440
10K_0402_5%
R1441
<>
10K_0402_5%
CFG10 CFG11 CFG129 CFG139
CFG169
CFG18 CFG199 CFG209
H_DPRSTP#5,19,43 PM_EXTTS#013 PM_EXTTS#114
R1739 0_0402_5%
DPRSLPVR20,43
2006/02/13 2006/03/10
U15B
P36
RSVD1
P37
RSVD2
R35
RSVD3
N35
RSVD4
AR12
RSVD5
AR13
RSVD6
AM12
RSVD7
AN13
RSVD8
J12
RSVD9
AR37
RSVD10
AM36
RSVD11
AL36
RSVD12
AM37
RSVD13
D20
RSVD14
H10
RSVD20
B51
RSVD21
BJ20
RSVD22
BK22
RSVD23
BF19
RSVD24
BH20
RSVD25
BK18
RSVD26
BJ18
RSVD27
BF23
RSVD28
BG23
RSVD29
BC23
RSVD30
BD24
RSVD31
BJ29
RSVD32
BE24
RSVD33
BH39
RSVD34
AW20
RSVD35
BK20
RSVD36
C48
RSVD37
D47
RSVD38
B44
RSVD39
C44
RSVD40
A35
RSVD41
B37
RSVD42
B36
RSVD43
B34
RSVD44
C34
RSVD45
P27
CFG_0
N27
CFG_1
N24
CFG_2
C21
CFG_3
C23
CFG_4
F23
CFG_5
N23
CFG_6
G23
CFG_7
J20
CFG_8
C20
CFG_9
R24
CFG_10
L23
CFG_11
J23
CFG_12
E23
CFG_13
E20
CFG_14
K23
CFG_15
M20
CFG_16
M24
CFG_17
L32
CFG_18
N33
CFG_19
L35
CFG_20
G41
PM_BM_BUSY#
L39
PM_DPRSTP#
L36
PM_EXT_TS#_0
J36
PM_EXT_TS#_1
AW49
PWROK
AV20
RSTIN#
N20
THERMTRIP#
G36
DPRSLPVR
BJ51
NC_1
BK51
NC_2
BK50
1
NC_3
BL50
NC_4
BL49
NC_5
BL3
NC_6
2
BL2
NC_7
0.1U_0402_16V4Z
BK1
NC_8
BJ1
NC_9
E1
NC_10
A5
NC_11
C51
NC_12
B50
NC_13
A50
NC_14
A49
NC_15
BK2
NC_16
CRES TLINE_1p0
PLT_RST#PLT_RST#_R
12
Compal Secret Data
Deciphered Date
2
SM_CK_0 SM_CK_1 SM_CK_3 SM_CK_4
SM_CK#_0 SM_CK#_1 SM_CK#_3 SM_CK#_4
SM_CKE_0 SM_CKE_1 SM_CKE_3 SM_CKE_4
SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3
SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF_0
DDR M UXIN GCLK
SM_VREF_1
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
PEG_CLK
PEG_CLK#
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2
CFGRS VD
PM
DMI_TXN_3
DMI_TXP_0 DMI_TXP_1
DMI
DMI_TXP_2 DMI_TXP_3
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3
GFX_VR_EN
GRA PHI CS V ID
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
ME
NC
SDVO_CTRL_CLK
SDVO_CTRL_DATA
CLK_REQ#
ICH_SYNC#
MI SC
PLT_RST# 16,18 ,22,30
083 0 A dd pu ll- up an d pul l-dow n re sisto r.
2
M_CLK_DD R0
AV29
M_CLK_DD R1
BB23
M_CLK_DD R2
BA25
M_CLK_DD R3
AV23
M_CLK_DDR#0
AW30
M_CLK_DDR#1
BA23
M_CLK_DDR#2
AW25
M_CLK_DDR#3
AW23
DDR_CKE 0_DIMMA
BE29
DDR_CKE 1_DIMMA
AY32
DDR_CKE 2_DIMMB
BD39
DDR_CKE 3_DIMMB
BG37
DDR_C S0_DIMMA#
BG20
DDR_C S1_DIMMA#
BK16
DDR_C S2_DIMMB#
BG16
DDR_C S3_DIMMB#
BE13
M_ODT0
BH18
M_ODT1
BJ15
M_ODT2
BJ14
M_ODT3
BE16
SMRCOMP
BL15
SMRCOMP#
BK14
SMRCOMP_VOH
BK31
SMRCOMP_VOL
BL31
AR49
V_DDR _MCH_REF
AW4
CLK_M CH_DREFCLK
B42
CLK_M CH_DREFCLK#
C42
MCH_ SSCDREFCLK
H48
MCH_ SSCDREFCLK#
H47
CLK_MCH_3GPLL
K44
CLK_MCH_3GPLL#
K45
AN47
DMI_TXN1
AJ38
DMI_TXN2
AN42
DMI_TXN3
AN46
DMI_TXP0
AM47
DMI_TXP1
AJ39
DMI_TXP2
AN41
DMI_TXP3
AN45
DMI_RXN0
AJ46
DMI_RXN1
AJ41
DMI_RXN2
AM40
DMI_RXN3
AM44
DMI_RXP0
AJ47
DMI_RXP1
AJ42
DMI_RXP2
AM39
DMI_RXP3
AM43
DFGT_ VID_0
E35
DFGT_ VID_1
A39
DFGT_ VID_2
C38
DFGT_ VID_3
B39
DFGT_VR_E N
E36
CL_CLK0
AM49
CL_CLK
CL_DATA0
AK50
M_PWROK
AT43
CL_RST#
AN49
CL_VRE F CL_VRE F
AM50
062 1 a dd CL K a nd DA T fo r DVI
SDVO_SCLK
H35
SDVO_SDAT
K36
CLKREQ#_B
G39
MCH _ICH_SYNC #
G40
A37
TEST_1
R32
TEST_2
12
R1444
20K_0402_5%
12
R1445
0_0402_5%
Title
CRESTLINE(1/6)-AGTL+/DMI/DDR2
Size Doc ument Number Re v
Cus tom
LA -3 26 1P U MA
Date: Sheet of
1
For Crestli ne: 20ohm For Calero: 80.6ohm
M_CLK_DD R0 13 M_CLK_DD R1 13 M_CLK_DD R2 14 M_CLK_DD R3 14
M_CLK_DD R#0 13 M_CLK_DD R#1 13 M_CLK_DD R#2 14 M_CLK_DD R#3 14
DDR_CKE 0_DIMMA 13 DDR_CKE 1_DIMMA 13 DDR_CKE 2_DIMMB 14 DDR_CKE 3_DIMMB 14
DDR_CS0_D IMMA# 13 DDR_CS1_D IMMA# 13 DDR_CS2_D IMMB# 14 DDR_CS3_D IMMB# 14
M_ODT0 13 M_ODT1 13 M_ODT2 14
DFGT_ VID_0 DFGT_ VID_1 DFGT_ VID_3
R1786
M_ODT3 14
CLK_M CH_DREFCLK 15
CLK_M CH_DREFCLK# 1 5
MCH_ SSCDREFCLK 1 5
MCH_ SSCDREFCLK# 15
CLK_MCH_3GPLL 15 CLK_MCH_3GPLL# 15
DMI_TXN0 20 DMI_TXN1 20 DMI_TXN2 20 DMI_TXN3 20
DMI_TXP0 20 DMI_TXP1 20 DMI_TXP2 20 DMI_TXP3 20
DMI_RXN0 20 DMI_RXN1 20 DMI_RXN2 20 DMI_RXN3 20
DMI_RXP0 20 DMI_RXP1 20 DMI_RXP2 20 DMI_RXP3 20
DFGT_ VID_0 45 DFGT_ VID_1 45 DFGT_ VID_2 45 DFGT_ VID_3 45 DFGT_VR_E N 45
CL_CLK0 20 CL_DATA0 20 M_PWROK 20,35 CL_RST# 20
0.1U_0402_16V4Z
SDVO_SCLK 16 SDVO_SDAT 16+VCCP
CLKREQ#_B 15 MCH _ICH_SYNC # 20
12
22K_0402_5%
20_0402_1%
R1194
R1195 20_0402_1%
C1106
+1.25VM_AXD
1
2
12 12
12
R1442
1K_0402_1%
12
R1443 392_0402_1%
04/ 10 ch ange size
+3VS
12
12
22K_0402_5%
R1787
22K_0402_5%
R1789
R1788
Compal Electronics, Inc.
7 55Tuesday, March 27, 2 007
1
+1.8V
12
22K_0402_5%
DFGT_ VID_2
0.4
5
D D
DDR_ A_D[0..63 ]13
C C
B B
DDR_A _D0 DDR_A _D1 DDR_A _D2 DDR_A _D3 DDR_A _D4 DDR_A _D5 DDR_A _D6 DDR_A _D7 DDR_A _D8
DDR_A _D9 DDR_A _D10 DDR_A _D11 DDR_A _D12 DDR_A _D13 DDR_A _D14 DDR_A _D15 DDR_A _D16 DDR_A _D17 DDR_A _D18 DDR_A _D19 DDR_A _D20 DDR_A _D21 DDR_A _D22 DDR_A _D23 DDR_A _D24 DDR_A _D25 DDR_A _D26 DDR_A _D27 DDR_A _D28 DDR_A _D29 DDR_A _D30 DDR_A _D31 DDR_A _D32 DDR_A _D33 DDR_A _D34 DDR_A _D35 DDR_A _D36 DDR_A _D37 DDR_A _D38 DDR_A _D39 DDR_A _D40 DDR_A _D41 DDR_A _D42 DDR_A _D43 DDR_A _D44 DDR_A _D45 DDR_A _D46 DDR_A _D47 DDR_A _D48 DDR_A _D49 DDR_A _D50 DDR_A _D51 DDR_A _D52 DDR_A _D53 DDR_A _D54 DDR_A _D55 DDR_A _D56 DDR_A _D57 DDR_A _D58 DDR_A _D59 DDR_A _D60 DDR_A _D61 DDR_A _D62 DDR_A _D63
AR43
AW44
BA45
AY46 AR41 AR45
AT42
AW47
BB45
BF48 BG47
BJ45 BB47 BG50 BH49 BE45
AW43
BE44 BG42 BE40
BF44 BH45 BG40
BF40 AR40
AW40
AT39
AW36 AW41
AY41 AV38
AT38 AV13
AT13
AW11
AV11 AU15
AT11 BA13 BA11 BE10 BD10
BD8 AY9
BG10
AW9
BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8
AN10
AT9 AN9 AM9
AN11
U15D
SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63
CRES TLINE_1p0
DDR SYSTEM MEMORY A
SA_BS_0 SA_BS_1 SA_BS_2
SA_CAS#
SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6
SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8
SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13
SA_RAS#
SA_RCVEN#
SA_WE#
4
DDR_A_BS 0
BB19 BK19 BF29
BL17
AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6
AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2
BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16
BE18 AY20
BA19
DDR_A_BS 1 DDR_A_BS 2
DDR_A _CAS#
DDR_A_DM 0 DDR_A_DM 1 DDR_A_DM 2 DDR_A_DM 3 DDR_A_DM 4 DDR_A_DM 5 DDR_A_DM 6 DDR_A_DM 7
DDR_A _DQS0 DDR_A _DQS1 DDR_A _DQS2
DDR_A _DQS4 DDR_A _DQS5 DDR_A _DQS6 DDR_A _DQS7 DDR_A _DQS#0 DDR_A _DQS#1 DDR_A _DQS#2 DDR_A _DQS#3 DDR_A _DQS#4 DDR_A _DQS#5 DDR_A _DQS#6 DDR_A _DQS#7
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13
DDR_A _RAS# SA_RCVEN #
DDR_A_W E#
DDR_A_BS 0 13 DDR_A_BS 1 13 DDR_A_BS 2 13
DDR_A _CAS# 13 DDR_B _CAS# 14 DDR_A _DM[0..7] 13
DDR_ A_DQS[0.. 7] 13
DDR_A _DQS#[0.. 7] 13
DDR_A _MA[0..13] 13
DDR_A _RAS# 13
T5
DDR_A_W E# 13
3
DDR_ B_D[0..63 ]14
DDR_B _D0 DDR_B _D1 DDR_B _D2 DDR_B _D3 DDR_B _D4 DDR_B _D5 DDR_B _D6 DDR_B _D7 DDR_B _D8
DDR_B _D9 DDR_B _D10 DDR_B _D11 DDR_B _D12 DDR_B _D13 DDR_B _D14 DDR_B _D15 DDR_B _D16 DDR_B _D17 DDR_B _D18DDR_A _DQS3 DDR_B _D19 DDR_B _D20 DDR_B _D21 DDR_B _D22 DDR_B _D23 DDR_B _D24 DDR_B _D25 DDR_B _D26 DDR_B _D27 DDR_B _D28 DDR_B _D29 DDR_B _D30 DDR_B _D31 DDR_B _D32 DDR_B _D33 DDR_B _D34 DDR_B _D35 DDR_B _D36 DDR_B _D37 DDR_B _D38 DDR_B _D39 DDR_B _D40 DDR_B _D41
DDR_B _D43 DDR_B _D44 DDR_B _D45 DDR_B _D46 DDR_B _D47 DDR_B _D48 DDR_B _D49 DDR_B _D50 DDR_B _D51 DDR_B _D52 DDR_B _D53 DDR_B _D54 DDR_B _D55 DDR_B _D56 DDR_B _D57 DDR_B _D58 DDR_B _D59 DDR_B _D60 DDR_B _D61 DDR_B _D62 DDR_B _D63
AP49
AR51 AW50 AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49 BF50 BF49 BJ50 BJ44 BJ43
BL43 BK47 BK49 BK43 BK42
BJ41
BL41
BJ37
BJ36 BK41
BJ40
BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12
BJ10
BK5
BK9
BK10
BH5 BG1 BC2 BK3 BE4 BD3
BA3 BB3 AR1
AU2
BL9
BL5
BJ8 BJ6 BF4
BJ2
AT3 AY2 AY3
AT2
2
U15E
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
CRES TLINE_1p0
1
DDR_B_BS0
AY17
SB_BS_0 SB_BS_1 SB_BS_2
SB_CAS#
SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7
SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6
SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7
SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8
SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13
SB_RAS#
SB_RCVEN#
SB_WE#
DDR SYSTEM MEMORY B
BG18 BG36
BE17
AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2
AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3
BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13
AV16 AY18
BC17
DDR_B_BS 1 DDR_B_BS 2
DDR_B _CAS#
DDR_B_DM 0 DDR_B_DM 1 DDR_B_DM 2 DDR_B_DM 3 DDR_B_DM 4 DDR_B_DM 5 DDR_B_DM 6 DDR_B_DM 7
DDR_B _DQS0 DDR_B _DQS1 DDR_B _DQS2 DDR_B _DQS3 DDR_B _DQS4 DDR_B _DQS5 DDR_B _DQS6
DDR_B _DQS7 DDR_B _DQS#0 DDR_B _DQS#1 DDR_B _DQS#2 DDR_B _DQS#3 DDR_B _DQS#4 DDR_B _DQS#5 DDR_B _DQS#6 DDR_B _DQS#7
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8
DDR_B_MA9 DDR_B_MA10DDR_B _D42 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13
DDR_B _RAS#
SB_RCVEN #
DDR_B_W E#
DDR_B _RAS# 14
T4
DDR_B_W E# 14
DDR_B_BS 0 14 DDR_B_BS 1 14 DDR_B_BS 2 14
DDR_B _DM[0..7] 14
DDR_ B_DQS[0.. 7] 14
DDR_B _DQS#[0.. 7] 14
DDR_B _MA[0..13] 14
A A
Secur ity Classification
Issued Date
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
Cus tom
2
Date: Sheet of
Compal Electronics, Inc.
CRESTLINE((2/6)-DDR2 A/B CH
LA -3 26 1P U MA
8 55Tuesday, March 27, 2 007
1
0.4
5
For Crestli ne:2.4kohm For Calero: 1.5Kohm
+3VS
M_COMP M_LUMA M_CRMA
R175
M_BLUE M_GREEN M_RED
R180
BLON_PWM ENABLT
DDC2_ CLK DDC2_DAT A
ENAVDD
2.4K_0402_1%
R1447
TXCLK_L­TXCLK_L+ TXCLK_U­TXCLK_U+
TXOUT_L0­TXOUT_L1­TXOUT_L2-
TXOUT_L0+ TXOUT_L1+ TXOUT_L2+
TXOUT_U0­TXOUT_U1­TXOUT_U2-
TXOUT_U0+ TXOUT_U1+ TXOUT_U2+
75_0402_1%
12
R94
12
75_0402_1%
BLON_PWM17
ENABLT17
DDC2_ CLK17 DDC2_DAT A17
ENAVDD17
D D
TXCLK_L-17 TXCLK_L+17 TXCLK_U-17 TXCLK_U+17
TXOUT_L0-17 TXOUT_L1-17 TXOUT_L2-17
TXOUT_L0+17 TXOUT_L1+17 TXOUT_L2+17
TXOUT_U0-17 TXOUT_U1-17 TXOUT_U2-17
TXOUT_U0+17 TXOUT_U1+17 TXOUT_U2+17
M_COMP M_LUMA
0622 change value
C C
M_CRMA
M_BLUE
M_GREEN
M_RED
0314 change desig n
+3VS
0821
1013 change value
DDC1_ CLK16
DDC1_DAT A16
M_HS YNC1 6
M_VSYNC16
DDC1_ CLK DDC1_DAT A M_H SYNC
M_VSYNC
R165
R166
0821
B B
+3VS
1013 change value
2.2K_0402_5%
2.2K_0402_5%
DDC2_ CLK DDC2_DAT A
R92 R158
1 2 1 2
TV-Out Termination/EMI Filter
M_COMP
M_LUMA
A A
M_COMP
M_LUMA
M_CRMA
1
2
C238
5.6P_0402_50V8D
C7
5.6P_0402_50V8D
1
1
2
2
0314 add
R95 10K_0402_5%
1 2
R160 10K_0402_5%
1 2
12
75_0402_1%
75_0402_1%
12
12
R177
R176
2.2K_0402_5%
1 2
75_0402_1%
1 2
30.1_0402_1%
1 2
30.1_0402_1%
L38
1 2
CHB1608U301_ 0603
L37
1 2
CHB1608U301_ 0603
L17
1 2
CHB1608U301_ 0603
C251
5.6P_0402_50V8D
0314 add
75_0402_1%
12
12
R182
R181
HS YNC
VSYN C
1.15K_0402_1%
For Crestli ne:1.3kohm For Calero: 255ohm
5.6P_0402_50V8D
U15C
J40
H39
E39
E40 C37 D35
K40
L41
L43 N41 N40 D46 C45 D44
E42
G51
E51
F49
G50
E50
F48
G44
B47
B45
E44
A47
A45
E27 G27
K27
F27
J27
L27
M35
P33
H32 G32
K29
J29 F29 E29
K33
G35
F33
C32
E33
12
R1449
CRES TLINE_1p0
Pl a c e c l o
Pl a c e c l o s e t o U 15
Pl a c e c l oPl ace c lo
1
1
2
2
C243
C8
5.6P_0402_50V8D
Note: C RT / TV-out s hould rout e to JP30 fir st then to the JP1 & JP2 on system side.
5
L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN
LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK
LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2
LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2
LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2
LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2
TVA_DAC TVB_DAC TVC_DAC
TVA_RTN TVB_RTN TVC_RTN
TV_DCONSEL_0 TV_DCONSEL_1
CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED#
CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC
1
C253
2
5.6P_0402_50V8D
4
LVDS
TV VGA
se to U1 5
se to U1 5s e t o U 15
COMP 16,33
LUMA 16,33
CRMA 16,33
0314 change desig n
4
PCI-EXPRESS GRAPHICS
PEG_COMPI
PEG_COMPO
PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8
PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15
PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8
PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15
PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9
PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
3
N43 M43
J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41
J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42
N45 U39 U47 N51 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44
M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43
PEGCOMP
PEG_RXP1
PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3
PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3
R1176
24.9_0402_1%
1 2
PEG_RXN1
C1058 0.1U_0402_16V4Z
1 2
C1059 0.1U_0402_16V4Z
1 2
C1060 0.1U_0402_16V4Z
1 2
C1061 0.1U_0402_16V4Z
1 2
C1062 0.1U_0402_16V4Z C1063 0.1U_0402_16V4Z C1066 0.1U_0402_16V4Z C1067 0.1U_0402_16V4Z
+VCCP
1 2 1 2 1 2 1 2
0809 Ad d M AX9511
PEG_RXN1 16
PEG_RXP1 16
1013 Re mov e MAX9511
CRT Termination/EMI Filter
M_RED
M_GREEN
M_BLUEM_CRMA
1
C194
@
1
2
2
10P_0402_50V8J
10P_0402_50V8J
C240
@
Secur ity Classification
Issued Date
L28
1 2
HLC06 03CSCC39NJT_0603
L35
1 2
HLC06 03CSCC39NJT_0603
L27
1 2
HLC06 03CSCC39NJT_0603
1
C233
@
2
10P_0402_50V8J
3
C_RED _L
C_GRN _L
C_BLU_L
1
C193
22P_0402_50V8J
2
0314 change desig n
2006/02/13 2006/03/10
PE GC OMP tr ace w idth and sp acing is 2 0/25 mils .
SDVOB_R- 16 SDVOB_G- 16 SDVOB_B- 16 SDVOB_CLK- 16
SDVOB_R+ 16 SDVOB_G+ 16 SDVOB_B+ 16 SDVOB_CLK+ 16
Pl a c e C
Pl a c e C lo sed to U1 5
Pl a c e CPl ace C
L31
1 2
HLC06 03CSCCR11JT_0603
L34
1 2
HLC06 03CSCCR11JT_0603
L26
1 2
HLC06 03CSCCR11JT_0603
1
1
C237
2
2
22P_0402_50V8J
C232
22P_0402_50V8J
@
Compal Secret Data
Deciphered Date
2
lo sed to U1 5
lo sed to U1 5lo sed to U1 5
1
C195
1
2
2
10P_0402_50V8J
10P_0402_50V8J
C244
@
2
10P_0402_50V8J
@
CFG[2:0] FSB Freq select
CFG5 (DMI select)
CFG6
CFG7 (CPU Strap)
CFG8 (Low power PCIE)
CFG9
(PCIE Graphics Lane Reversal)
CFG[11:10]
CFG[13:12] (XOR/ALLZ)
CFG16 (FSB Dynamic ODT)
SDVO_CTRLDATA
CFG19 (DMI Lane Reversal)
CFG20 (PCIE/SDVO concurrent)
RED
GREEN
BLUE
1
2
C245
RED 33
GREEN 33
BLUE 33
Title
Size Doc ument Number Re v
Cus tom
Date: Sheet
1
Strap Pin Table
010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved
0 = DMI x 2
1 = DMI x 4
*
Reserved
0 = Reserved
1 = Mobile CPU
*
0 = Normal mode
1 = Low Power mode
*
0 = Reverse Lane
1 = Normal Operation
*
Reserved
00 = Reserved 01 = XOR Mode Enabled 10 = All Z Mode Enabled 11 = Normal Operation
(Default)
ReservedCFG[15:14]
0 = Disabled
1 = Enabled
*
ReservedCFG[18:17]
0 = No SDVO Device Present
1 = SDVO Device Present
0 = Normal Operation
(Lane number in Order)
*
1 = Reverse Lane
0 = Only PCIE or SDVO is operational.
1 = PCIE/SDVO are operating simu.
R1151 4.02K_0402_1%@
CFG57
CFG77
CFG87
CFG97
CFG127
CFG137
CFG167
1 2
R1152 4.02K_0402_1%@
1 2
R1451 4.02K_0402_1%@
1 2
R1153 4.02K_0402_1%@
1 2
R1155 4.02K_0402_1%@
1 2
R1156 4.02K_0402_1%@
1 2
R1157 4.02K_0402_1%@
1 2
CFG[17 :3] ha ve internal pull up
CFG[19 :18] h ave internal pull down
R1159 4.02K_0402_1%@
CFG197
CFG207
CFG5
1 2
R1160 4.02K_0402_1%@
1 2
J37
2 1
PAD-N O SHORT 2 x2m
Compal Electronics, Inc.
CRESTLINE((3/6)-VGA/LVDS/TV
LA -3 26 1P U MA
9 55Tuesday, March 27, 2 007
1
*
*
*
+3VS
0.4
of
5
+3VS_DAC_BG
0.022U_0402_16V7K
D D
+3VS_DAC_CRT
0.022U_0402_16V7K
+1.25VM
C C
1
C1108
2
1
C1113
2
MBK1608102Y ZF 0603
22U_0805_6.3V
0.1U_0402 _16V4Z
C1375
1
1
C1109
2
2
0621 Chan ge R to BLM18PG1 SN1D
BLM18PG181SN1D_0603
R1456
0.1U_0402_16V4Z
1
C1114
2
+3VS
1
+
C1126
150U_D_6.3V M
R1462
0_0603_5%
0316 add
2
+1.25VM_A_SM_CK
12
R1453
12
R1459
0_0603_5%
0.1U_0402_16V 4Z
R1461
1 2
0_0805_5%
C1127
22U_0805_6.3VAM
12
1U_0402_6 .3V4Z
C1226
1
2
0317 c hange value
+3VS
+3VS
+1.8V_TXLVDS
+3VS_PEG_BG
12
C1121
0317 c hange value
1
4.7U_0805_10 V4Z
2
22U_0805_6.3VAM
C1130
1
2
1116 Change to BLM18PG181SN1D_0603
+3VS_TVDACC
B B
0.022U_0402_16V7K
C1144
+3VS_TVDACA
0.022U_0402_16V7K
C1148
A A
+3VS_TVDACB
0.022U_0402_16V7K
C1152
1
C1145
2
1
C1149
2
1
C1153
2
BLM18PG181SN1D_0603
0.1U_0402_16V4Z
1
2
BLM18PG181SN1D_0603
0.1U_0402_16V4Z
1
2
BLM18PG181SN1D_0603
0.1U_0402 _16V4Z
1
2
5
R1468
R1472
R1473
12
12
12
+3VS
1
2
C1131
+3VS
+3VS
+3VS
R1452
0_0603_5%
+1.25VM_A_SM
C1128
1U_0603_10V4Z
1
2
+1.25VS_PEGPLL
VCC SYNC
12
1
C1107
2
+3VS_DA C_CRT
+1.25VS_DPLLA
+1.25VS_DPLLB
+1.25VM_HPLL
+1.25VM_MPLL
1000P_0402_50V7K
C1118
+1.25VS_PEGPLL
1
2
1U_0603_10V4Z
0.1U_0402 _16V4Z
C1132
1
2
+1.5VS_TV DAC
+1.5VS_Q DAC
+1.25VM_HPLL
+1.8V_LVDS
+1.5VS_QDA C
0.022U_0402_16V7K
10U_0805_10V4Z
0.1U_0402 _16V4Z
+3VS_DAC_BG
1
2
20 mils
1
C1129
2
+3VS_TVDACA
+3VS_TVDACB
+3VS_TVDACC
1
1
C1147
C1146
2
2
0119 Add C1374 20070301 Install C1374
+1.8V_LVDS
1U_0603_10V4Z
C1151
C1150
1
2
4
U15 H
J32
VCCSYNC
A33
VCCA_CRT_DAC_1
B33
VCCA_CRT_DAC_2
A30
VCCA_DAC_BG
B32
VSSA_DAC_BG
B49
VCCA_DPLLA
H49
VCCA_DPLLB
AL2
VCCA_HPLL
AM2
VCCA_MPLL
A41
VCCA_LVDS
B41
VSSA_LVDS
K50
VCCA_PEG_BG
K49
VSSA_PEG_BG
U51
VCCA_PEG_PLL
AW18
VCCA_SM_1
AV19
VCCA_SM_2
AU19
VCCA_SM_3
AU18
VCCA_SM_4
AU17
VCCA_SM_5
AT22
VCCA_SM_7
AT21
VCCA_SM_8
AT19
VCCA_SM_9
AT18
VCCA_SM_10
AT17
VCCA_SM_11
AR17
VCCA_SM_NCTF_1
AR16
VCCA_SM_NCTF_2
BC29
VCCA_SM_CK_1
BB29
VCCA_SM_CK_2
C25
VCCA_TVA_DAC_1
B25
VCCA_TVA_DAC_2
C27
VCCA_TVB_DAC_1
B27
VCCA_TVB_DAC_2
B28
VCCA_TVC_DAC_1
A28
VCCA_TVC_DAC_2
M32
VCCD_CRT
L29
VCCD_TVDAC
N28
VCCD_QDAC
AN2
VCCD_HPLL
U48
VCCD_PEG_PLL
J41
VCCD_LVDS_1
H42
VCCD_LVDS_2
CRESTLINE _1p0
1107 Change to 100 ohm
R1471
1
C1374
+
2
R1474
0_0603_5%
220U_D2_4VM
100_0603_1%
12
4
0.1U_0402 _16V4Z
1
2
12
+1.8V
CRTPLLA PEGA SMTV
POWER
A CK A LVDS
D TV/CRTLVDS
+1.5VS
VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8
VTT_9 VTT_10 VTT_11 VTT_12 VTT_13
VTT
VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22
VCC_AXD_1 VCC_AXD_2 VCC_AXD_3 VCC_AXD_4 VCC_AXD_5
AXD
VCC_AXD_6
VCC_AXD_NCTF
VCC_AXF_1 VCC_AXF_2 VCC_AXF_3
AXF
VCC_DMI
VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4
SM CK
VCC_TX_LVDS
VCC_HV_1 VCC_HV_2
HV
VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4
PEG
VCC_PEG_5
VCC_RXR_DMI_1 VCC_RXR_DMI_2
DMI
VTTLF1 VTTLF2 VTTLF3
VTTLF
40 mils
1000P_0402_50V7K
1
C1269
2
3
+VCCP
330U_D2E_2. 5VM_R7
U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1
AT23 AU28 AU24 AT29 AT25 AT30
AR29
B23 B21 A21
AJ50
BK24 BK23 BJ24 BJ23
A43
C40 B40
AD51 W50 W51 V49 V50
AH50 AH51
A7 F2 AH1
+1.8V_TXLVDS
1
220U_D2_4VM_R15
+
2
C1141
C1285
+1.25VM_AXD
0.47U_0603_10V7K
1
2
R1476
0_0603_5%
C830
C849
1U_0603_10V4Z
1
2
+V1.25VS_AXF
+1.25VS_DMI
+1.8V_SM_CK
+1.8V_TXLVDS
+VCC_PEG
20mils
0.47U_0603_10V7K
C1142
1
2
12
1
+
2
1
2
C1143
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
4.7U_0805_10V4Z
1
C838
2
0316 add
0.47U_0603_10V7K
C836
C1119
C1120
1
2
+3VS_HV
C1136
0.47U_0603_10V7K
1
2
+1.8V
2.2U_0805 _16V4Z
4.7U_0805 _10V4Z
1
1
C837
2
2
R1671
1 2
10U_0805_10V4Z
+1.25VM
0_0805_5%
0.1U_0402 _16V4Z
1
2
2006/02/13 2006/03/10
Compal Secret Data
+1.25VS_DPLLB
0.1U_0402_16V4Z
+1.25VS_DMI
+1.25VS_PEGPLL
+1.25VS_DP LLA
220U_D2_4VM
1
C1227
+
2
Deciphered Date
22U_0805_6.3VAM
C1110
1
2
1 2
0.1U_0402 _16V4Z
C1117
1
2
0.1U_0402 _16V4Z
C1122
1
2
C1133
1
2
0.1U_0402_16V 4Z
+VCC_PEG
220U_D2_4VM
1
C1137
+
2
2
R1454
1 2
10U_FLC-453232-1 00K_0.25A_10%
1
C1231
2
+1.25VS
R1457
0_0603_5%
BLM18PG121SN1D_0 603
10U_0805_10V4Z
C1123
1
2
10U_0805_10V4Z
C1276
1
2
C1138
1
2
2
+1.25VS
0619 c hange
+1.25VS
L77
12
R1463
1 2
10U_FLC-453232-1 00K_0.25A_10%
0316 add
10U_0805_10V4Z
04/ 10 stu ff
R1465
0_0805_5%
R1467
@
0_0805_5%
+1.25VS
12
12
04/ 10 no stu ff
2 1
+VCCP
CH751H-40PT_S OD323-2
+3VS
1
+V1.25VS_AXF
0619 c hange value
+VCCP
+1.25VS
D12
Title
Size Documen t Number Re v
Cust om
Date : Sheet of
+1.8V_SM_CK
10U_0603_6.3V6M
1
C1230
2
+1.5VS_TVDAC
+1.25VM_HPLL
C1134
0.1U_0402_16 V4Z
+1.25VM_MPLL
C1139
0.1U_0402_16 V4Z
+VCCP_ D
R1469
10_0402_5%
Compal Electronics, Inc.
CRESTLINE(4/6)-PWR
LA -3 26 1P U MA
1U_0603_10V4Z
10U_0805_10V4Z
C1112
C1111
1
1
2
2
1 2
0.1U_0402 _16V4Z
10U_0603_6.3V6M
1
C1115
2
0.022U_0402_16V7K
1
C1124
2
1
2
1
2
12
0.1U_0402_16V4Z
1
C1125
2
MBK2012121YZF _0805
1
C1135
10U_0805_10V4Z
2
MBK2012121YZF _0805
1
C1140
10U_0805_10V4Z
2
R1470
0_0402_5%
1
C1116
1
2
1 2
R1464
R1466
12
0_0805_5%
0_0805_5%
1 2
0_0603_5%
R1458
R1460
+1.25VM
12
+1.25VM
12
+3VS_HV
10 55Tuesd ay, March 27, 2007
+1.25VS
R1455
+1.8V
+1.5VS
0.4
5
4
3
2
1
+VCCP
D D
22U_0805_6.3VAM
220U_D2_4VM_R15
1
C806
+
2
0317 change value
C C
0.22U_0402_10V4 Z
0.22U_0402_10V4 Z
C803
C796
1
2
1
1
2
2
+1.05VM
10U_0805_10V4Z
04/ 10 mo nit or N B cra ck
B B
0.22U_0402_10V4 Z
C1158
1
2
5
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C1159
1
1
2
2
+3VS
100K_0402_5%
MCHGN D4
Q123
@
RHU002N06_S OT323
0.22U_0402_10V4 Z
C1157
1
2
+3VS
A A
100K_0402_5%
R1701
@
MCHGN D6
Q118
@
RHU002N06_S OT323
CRAC K_GPIO28
13
D
1 2
2
G
S
+VCCP
0.1U_0402_16V4Z
C797
C798
1
2
10U_0805_10V4Z
C1154
C1155
1
1
2
2
0.1U_0402_16V4Z
C1160
C1161
1
2
04/ 10 mo nit or N B cra ck 101 3 n o insta ll 121 3 i nsta ll 012 9 i nsta ll 200 702 27 No inst all 200 702 28 Ch ange to +3VL
CRAC K_GPIO28
R1711
@
13
D
1 2
2
G
S
AB33 AB36 AB37 AC33 AC35 AC36 AD35 AD36 AF33 AF36 AH33 AH35 AH36 AH37
AJ33
AJ35 AK33 AK35 AK36 AK37 AD33
AJ36
AM35
AL33
AL35 AA33 AA35 AA36 AP35 AP36 AR35 AR36
AL24
AL26
AL28
AM26 AM28 AM29 AM31 AM32 AM33
AP29 AP31 AP32 AP33
AL29
AL31
AL32 AR31 AR32 AR33
Y32 Y33 Y35 Y36 Y37 T30 T34
T35 U29 U31 U32 U33 U35 U36
V32
V33
V36
V37
U15F
CRES TLINE_1p0
VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44 VCC_NCTF_45 VCC_NCTF_46 VCC_NCTF_47 VCC_NCTF_48 VCC_NCTF_49 VCC_NCTF_50
VCC_AXM_NCTF_1 VCC_AXM_NCTF_2 VCC_AXM_NCTF_3 VCC_AXM_NCTF_4 VCC_AXM_NCTF_5 VCC_AXM_NCTF_6 VCC_AXM_NCTF_7 VCC_AXM_NCTF_8 VCC_AXM_NCTF_9 VCC_AXM_NCTF_10 VCC_AXM_NCTF_11 VCC_AXM_NCTF_12 VCC_AXM_NCTF_13 VCC_AXM_NCTF_14 VCC_AXM_NCTF_15 VCC_AXM_NCTF_16 VCC_AXM_NCTF_17 VCC_AXM_NCTF_18 VCC_AXM_NCTF_19
+3VS
1 2
100K_0402_5%
MCHGN D2
Q121
@
RHU002N06_S OT323
VCC NCTF
POWER
VCC AXM NCTF
R1709
@
CRAC K_GPIO28
13
D
2
G
S
4
VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8
VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15
VSS NCTF
VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21
VSS_SCB1 VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6
VSS SCBVCC AXM
VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_5 VCC_AXM_6 VCC_AXM_7
100K_0402_5%
R1703
@
MCHGN D5
RHU002N06_S OT323
T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28
A3 B2 C1 BL1 BL51 A51
AT33 AT31 AK29 AK24 AK23 AJ26 AJ23
MCHGN D1 MCHGN D2 MCHGN D3 MCHGN D4 MCHGN D5 MCHGN D6
+3VS
Q119
@
0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%
R112
1 2
R132
1 2
R133
1 2
R122
1 2
R113
1 2
R111
1 2
0314 add
101 3 i ns tal l R 111 ,R113 ,R122 ,R13 2 121 3 N o- ins tal l R 111, R113 ,R122 ,R132 012 9 N o- ins tal l R 111, R113 ,R122 ,R132 200 702 27 In sta ll R111 ,R11 3,R12 2,R13 2
+3VL
R1702
CRAC K_GPIO28
1 2 13
D
1 2
100K_0402_5%
2
G
S
R1475
1 2
0_0603_5%
330U_D2E_2.5VM_R9
+1.8V
+1.05VM
1
C1286
C1175
1U_0603_10V4Z
Secur ity Classification
2
330U_D2E_2.5VM _R9
0316 change value
CRAC K_GPIO28 21,31
Issued Date
3
22U_0805_6.3VAM
1
+
C808
2
0317 change value
10U_0805_10V4Z
1
1
+
C812
2
C811
2
10U_0805_10V4Z
2006/02/13 2006/03/10
C809
1
2
22U_0805_6.3VAM
1
2
0.1U_0402_16V4Z
1
C1156
2
0.01U_0402_16V7K
C794
C810
2
1
VCCGFX
1
2
Compal Secret Data
Deciphered Date
AT35
AT34 AH28 AC32 AC31 AK32
AJ31
AJ28 AH32 AH31 AH29
AF32
AU32 AU33 AU35 AV33
AW33 AW35
AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35
BF33
BF34 BG32 BG33 BG35 BH32 BH34 BH35
BJ32
BJ33
BJ34 BK32 BK33 BK34 BK35
BL33 AU30
W13 W14
AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28
AF21
AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31
AJ20 AN14
R30
R20 T14
Y12
U15G
VCC_1 VCC_2 VCC_3 VCC_5 VCC_4 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12
VCC_13
VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36
VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34
CRES TLINE_1p0
2
VCC CORE
POWER
VCC SMVCC GFX
VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8
VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54
VCC GFX NCTF
VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 VCC_AXG_NCTF_61 VCC_AXG_NCTF_62 VCC_AXG_NCTF_63 VCC_AXG_NCTF_64 VCC_AXG_NCTF_65 VCC_AXG_NCTF_66 VCC_AXG_NCTF_67 VCC_AXG_NCTF_68 VCC_AXG_NCTF_69 VCC_AXG_NCTF_70 VCC_AXG_NCTF_71 VCC_AXG_NCTF_72 VCC_AXG_NCTF_73 VCC_AXG_NCTF_74 VCC_AXG_NCTF_75 VCC_AXG_NCTF_76 VCC_AXG_NCTF_77 VCC_AXG_NCTF_78 VCC_AXG_NCTF_79 VCC_AXG_NCTF_80 VCC_AXG_NCTF_81 VCC_AXG_NCTF_82 VCC_AXG_NCTF_83
VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7
VCC SM LF
Title
Size Doc ument Number Re v
Cus tom
Date: Sheet of
VCCGFX
T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31
AW45 BC39 BE39 BD17 BD4 AW8 AT6
VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7
0.1U_0402_16V4Z
C1287
1
2
C1162 0.1 U_0402_16V4Z
C1163 0.1 U_0402_16V4Z
1
1
2
2
C1288
1
2
0.22U_0402_10V4 Z
C795 0.22U_060 3_10V7K
C1318 0.22U_0603_10V7K
1
1
2
2
Compal Electronics, Inc.
CRESTLINE((5/6)-PWR/GND
LA -3 26 1P U MA
1
4.7U_0603_6.3V6M
1
C1176
2
0316 add
C814 1U_0 603_10V4Z
C1164 0.4 7U_0402_6.3V6K
1
1
1
2
2
2
11 55Tuesday, M arch 27, 2007
C813 1U_0 603_10V4Z
0.4
5
U15I
A13
VSS_1
A15
VSS_2
A17
VSS_3
A24
VSS_4
AA21
VSS_5
AA24
VSS_6
AA29
VSS_7
AB20
D D
C C
B B
A A
AB23 AB26 AB28 AB31 AC10 AC13
AC39 AC43 AC47
AD21 AD26 AD29
AD41 AD45 AD49
AD50
AE10 AE14
AF20 AF23 AF24 AF31
AG38 AG43 AG47 AG50
AH40 AH41
AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45
AJ49 AK20 AK21 AK26 AK28 AK31 AK51
AM11 AM13
AM3
AM4 AM41 AM45
AN38 AN39 AN43
AP48 AP50 AR11
AR39 AR44 AR47
AT10 AT14 AT41 AT49
AU23 AU29
AU36 AU49 AU51 AV39 AV48
AW1
AW12 AW16
AC3
AD1
AD3
AD5
AD8
AE6
AG2
AH3
AH7 AH9
AL1
AN1
AN5 AN7 AP4
AR2
AR7
AU1
AU3
VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99
CRES TLINE_1p0
VSS
VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198
4
AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41
3
U15J
C46
VSS_199
C50
VSS_200
C7
VSS_201
D13
VSS_202
D24
VSS_203
D3
VSS_204
D32
VSS_205
D39
VSS_206
D45
VSS_207
D49
VSS_208
E10
VSS_209
E16
VSS_210
E24
VSS_211
E28
VSS_212
E32
VSS_213
E47
VSS_214
F19
VSS_215
F36
VSS_216
F4
VSS_217
F40
VSS_218
F50
VSS_219
G1
VSS_220
G13
VSS_221
G16
VSS_222
G19
VSS_223
G24
VSS_224
G28
VSS_225
G29
VSS_226
G33
VSS_227
G42
VSS_228
G45
VSS_229
G48
VSS_230
G8
VSS_231
H24
VSS_232
H28
VSS_233
H4
VSS_234
H45
VSS_235
J11
VSS_236
J16
VSS_237
J2
VSS_238
J24
VSS_239
J28
VSS_240
J33
VSS_241
J35
VSS_242
J39
VSS_243
K12
VSS_245
K47
VSS_246
K8
VSS_247
L1
VSS_248
L17
VSS_249
L20
VSS_250
L24
VSS_251
L28
VSS_252
L3
VSS_253
L33
VSS_254
L49
VSS_255
M28
VSS_256
M42
VSS_257
M46
VSS_258
M49
VSS_259
M5
VSS_260
M50
VSS_261
M9
VSS_262
N11
VSS_263
N14
VSS_264
N17
VSS_265
N29
VSS_266
N32
VSS_267
N36
VSS_268
N39
VSS_269
N44
VSS_270
N49
VSS_271
N7
VSS_272
P19
VSS_273
P2
VSS_274
P23
VSS_275
P3
VSS_276
P50
VSS_277
R49
VSS_278
T39
VSS_279
T43
VSS_280
T47
VSS_281
U41
VSS_282
U45
VSS_283
U50
VSS_284
V2
VSS_285
V3
VSS_286
CRES TLINE_1p0
VSS
VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305
VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313
W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28
AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50
2
1
Secur ity Classification
Issued Date
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
Cus tom
2
Date: Sheet of
Compal Electronics, Inc.
CRESTLINE((6/6)-PWR/GND
LA -3 26 1P U MA
1
12 55Tuesday, M arch 27, 2007
0.4
5
DDR_A _DQS#[0.. 7]8
DDR_ A_D[0..63 ]8
DDR_A _DM[0..7]8
DDR_A _DQS[0..7 ]8
DDR_A _MA[0..14]7,8
D D
Lay out No te: Pl ac e near JP 34
+1.8V
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C458
C498
1
1
2
2
C C
B B
A A
Lay out No te: Pl ac e one ca p clo se to eve ry 2 pul lup res istors te rmina ted to +0.9 VS
+0.9V
0.1U_0402_16V4Z
1
2
C229
0.1U_0402_16V4Z
1
2
C239
RP27
RP29
RP32
RP31
RP33
RP35
R1742 56_0402_5%
0.1U_0402_16V4Z
DDR_A_MA5 DDR_A_MA8
DDR_A_MA1 DDR_A_MA3
DDR_A _RAS# DDR_C S0_DIMMA#
DDR_A_BS #0 DDR_A_MA10
DDR_A _CAS# DDR_A_W E#
DDR_C S1_DIMMA# M_ODT1
DDR_A_MA11
0612 a dd
5
2.2U_0805_16V4Z
C473
1
2
0.1U_0402_16V4Z
1
2
C250
1 4 2 3
56_0404_4P2R_5%
1 4 2 3
56_0404_4P2R_5%
1 4 2 3
56_0404_4P2R_5%
1 4 2 3
56_0404_4P2R_5%
1 4 2 3
56_0404_4P2R_5%
2 3 1 4
56_0404_4P2R_5%
1 2
2.2U_0805_16V4Z
C491
1
2
0.1U_0402_16V4Z
1
1
2
2
C272
C257
+0.9V
0.1U_0402_16V4Z
2.2U_0805_16V4Z
C465
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C281
C279
RP22 56_0404_4P2R_5%
DDR_A_BS #2
14
DDR_CKE 0_DIMMA
23
RP26 56_0404_4P2R_5%
DDR_A_MA7
14
DDR_A_MA6
23
RP25 56_0404_4P2R_5%
DDR_A_MA9
14
DDR_A_MA12
23
RP28 56_0404_4P2R_5%
DDR_A_MA4
14
DDR_A_MA2
23
RP30 56_0404_4P2R_5%
DDR_A_MA0
14
DDR_A_BS #1
23
RP34 56_0404_4P2R_5%
M_ODT0
14
DDR_A_MA13
23
RP24 56_0404_4P2R_5%
DDR_CKE 1_DIMMA
14
DDR_A_MA14
23
0.1U_0402_16V4Z
C255
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C274
4
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C280
C242
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
2
2
C268
2
C252
C241
La yout Note : Pl ac e the se re sis tor cl osely JP34 ,all tr ace len gth Max= 1.5"
C235
0.1U_0402_16V4Z
0317 add
1
+
C246 330U_D2_2.5VM_R 15
2
0.1U_0402_16V4Z
1
1
2
2
C227
C234
Secur ity Classification
Issued Date
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+1.8V
JP34
1
VREF
3
DDR_A _D4 DDR_A _D1
DDR_A _DQS#0 DDR_A _DQS0
DDR_A _D2 DDR_A _D3
DDR_A _D8 DDR_A _D14
DDR_A _DQS#1 DDR_A _DQS1
DDR_A _D9 DDR_A _D11 DDR_A _D15 DDR_A_D1 0
DDR_A _D16 DDR_A _D17
DDR_A _DQS#2 DDR_A _DQS2
DDR_A _D18 DDR_A _D19
DDR_A_DM 3
DDR_A _D26 DDR_A _D27
DDR_C KE0_DIMMA7
DDR_A_BS 28
DDR_A_BS 08
DDR_A_W E#8
DDR_A _CAS#8
DDR_CS1_D IMMA#7
M_ODT17
ICH_SMBDATA14,15,20
ICH_SMBCLK14,15,20
3
DDR_CKE 0_DIMMA
DDR_A_BS #2
DDR_A_MA12 DDR_A_MA9 DDR_A_MA7 DDR_A_MA8
DDR_A_MA5 DDR_A_MA3 DDR_A_MA1
DDR_A_MA10 DDR_A_BS #0 DDR_A_W E#
DDR_A _CAS# DDR_C S1_DIMMA#
M_ODT1
DDR_A _D37 DDR_A _D36
DDR_A _DQS#4 DDR_A _DQS4
DDR_A _D35 DDR_A _D32
DDR_A _D40 DDR_A _D44
DDR_A_DM 5
DDR_A _D41 DDR_A _D46
DDR_A _D49 DDR_A _D48
DDR_A _DQS#6 DDR_A _DQS6
DDR_A _D50
DDR_A _D61 DDR_A_D5 7 DDR_A _D60
DDR_A_DM 7
DDR_A _D59 DDR_A _D58
ICH_SMBDATA ICH_SMBCLK
+3VM
1
2
2.2U_0 603_6.3V4Z
2006/02/13 2006/03/10
C308
C311
Compal Secret Data
1
2
5
7
9
11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97
99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 203
conn@
0.1U_0402_16V4Z
Deciphered Date
VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS
VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD GND
FOX_ASOA426-M4R-TR
SO-DIMM A
REVERSE
Top side
VSS DQ4 DQ5 VSS
DM0
VSS DQ6 DQ7
VSS DQ12 DQ13
VSS
DM1
VSS
CK0
CK0#
VSS DQ14 DQ15
VSS
VSS DQ20 DQ21
VSS
DM2
VSS DQ22 DQ23
VSS DQ28 DQ29
VSS
DQS3#
DQS3
VSS DQ30 DQ31
VSS
NC/CKE1
VDD NC/A15 NC/A14
VDD
VDD
VDD
BA1
RAS#
VDD
ODT0
NC/A13
VDD
VSS DQ36 DQ37
VSS
DM4
VSS DQ38 DQ39
VSS DQ44 DQ45
VSS
DQS5#
DQS5
VSS DQ46 DQ47
VSS DQ52 DQ53
VSS
CK1
CK1#
VSS
DM6
VSS DQ54 DQ55
VSS DQ60 DQ61
VSS
DQS7#
DQS7
VSS DQ62 DQ63
VSS
SAO
SA1
GND
2
+1.8V
V_DDR _MCH_REF
2
DDR_A _D6
4
DDR_A _D0
6 8
DDR_A_DM 0
10 12
DDR_A _D5
14
DDR_A _D7
16 18
DDR_A _D13
20
DDR_A _D12
22 24
DDR_A_DM 1
26 28
M_CLK_DD R0
30
M_CLK_DDR#0
32 34 36 38 40
42
DDR_A _D20
44
DDR_A _D21
46 48 50
NC
A11
A7 A6
A4 A2 A0
S0#
NC
2
52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 204
DDR_A_DM 2
DDR_A _D23 DDR_A _D22
DDR_A _D28DDR_A _D29 DDR_A _D25DDR_A _D24
DDR_A _DQS#3 DDR_A _DQS3
DDR_A _D31 DDR_A _D30
DDR_CKE 1_DIMMA
DDR_A_MA14
DDR_A_MA11
DDR_A_MA6
DDR_A_MA4 DDR_A_MA2 DDR_A_MA0
DDR_A_BS #1 DDR_A _RAS# DDR_C S0_DIMMA#
M_ODT0 DDR_A_MA13
DDR_A _D39 DDR_A _D38
DDR_A_DM 4
DDR_A _D34 DDR_A _D33
DDR_A _D45 DDR_A _D43
DDR_A _DQS#5 DDR_A _DQS5
DDR_A _D47 DDR_A _D42
DDR_A _D52 DDR_A _D53
M_CLK_DD R1 M_CLK_DDR#1
DDR_A_DM 6
DDR_A _D51DDR_A _D54 DDR_A _D55
DDR_A _D56
DDR_A _DQS#7 DDR_A _DQS7
DDR_A _D62 DDR_A _D63
12
R455
R453
10K_0402_5%
10K_0402_5%
12
2.2U_0805_16V4Z
C363
1
2
M_CLK_DD R0 7 M_CLK_DD R#0 7
PM_EXTTS#0 7
DDR_C KE1_DIMMA 7
0612 a dd
DDR_A_BS 1 8 DDR_A _RAS# 8 DDR_C S0_DIMMA# 7
M_ODT0 7
M_CLK_DD R1 7 M_CLK_DD R#1 7
Title
Size Doc ument Number Re v
Cus tom
Date: Sheet of
Compal Electronics, Inc.
DDRII-SODIMM SLOT1
LA -3 26 1P U MA
1
C362
1
V_DDR _MCH_REF 7,14,42
0.4
13 55Tuesday, M arch 27, 2007
0.1U_0402_16V4Z
1
2
5
DDR_B _DQS#[0.. 7]8
DDR_ B_D[0..63 ]8
DDR_B _DM[0..7]8
DDR_B _DQS[0..7 ]8
DDR_B _MA[0..14]7 ,8
D D
C C
B B
A A
Lay out No te: Pl ac e near JP 10
+1.8V
2.2U_0805_16V4Z
2.2U_0805_16V4Z
0.1U_0402_16V4Z
C265
1
2
0.1U_0402_16V4Z
1
2
C179
RP14
1 4 2 3
56_0404_4P2R_5%
RP17
1 4 2 3
RP16
56_0404_4P2R_5%
1 4 2 3
RP18
56_0404_4P2R_5%
1 4 2 3
56_0404_4P2R_5%
RP19
1 4 2 3
RP23
56_0404_4P2R_5%
2 3 1 4
56_0404_4P2R_5%
1 2
R1743
56_0402_5%
2.2U_0805_16V4Z
C247
1
2
0.1U_0402_16V4Z
1
2
C186
2.2U_0805_16V4Z
C236
1
2
Lay out No te: Pl ac e one ca p clo se to eve ry 2 pul lup res istors te rmina ted to +0.9 VS
+0.9V
0.1U_0402_16V4Z
1
2
C176
DDR_B_MA1 DDR_B_MA3
DDR_B_BS #0 DDR_B_MA10
DDR_B_MA0 DDR_B_BS #1
DDR_B _RAS# DDR_C S2_DIMMB#
DDR_B _CAS# DDR_B_W E#
DDR_C S3_DIMMB# M_ODT2 M_ODT3
DDR_CKE 3_DIMMB
C159
1
2
0.1U_0402_16V4Z
1
1
2
2
C197
C213
+0.9V
RP10 56_0404_4P2R_5%
RP11 56_0404_4P2R_5%
RP12 56_0404_4P2R_5%
RP13 56_0404_4P2R_5%
RP15 56_0404_4P2R_5%
RP21 56_0404_4P2R_5%
RP9
56_0404_4P2R_5%
2.2U_0805_16V4Z
C164
1
2
0.1U_0402_16V4Z
1
2
C220
14 23
14 23
14 23
14 23
14 23
14 23
14 23
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C166
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C183
C210
DDR_B_MA9 DDR_B_MA12
DDR_B_MA14 DDR_B_MA11
DDR_B_MA5 DDR_B_MA8
DDR_B_MA7 DDR_B_MA6
DDR_B_MA4 DDR_B_MA2
DDR_B_MA13
DDR_B_BS #2 DDR_CKE 2_DIMMB
0.1U_0402_16V4Z
C219
1
2
0.1U_0402_16V4Z
1
2
C199
0612 a dd
5
0.1U_0402_16V4Z
C188
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C173
C218
La yout Note : Pl ac e the se re sis tor cl osely JP10 ,all tr ace len gth Max= 1.5"
4
C161
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C177
C163
Secur ity Classification
Issued Date
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+1.8V
JP10
1
VREF
3
11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97
99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 203
conn@
0.1U_0402_16V4Z
Deciphered Date
5 7 9
VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS
VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD GND
FOX_ASOA426-M4R-TR
SO-DIMM B STANDARD
Bottom side
DDR_B _D0 DDR_B _D1
DDR_B _DQS#0 DDR_B _DQS0
DDR_B _D2 DDR_B _D3
DDR_B _D8 DDR_B _D9
DDR_B _DQS#1 DDR_B _DQS1
DDR_B _D10 DDR_B _D11
DDR_B _D20
DDR_B _DQS#2 DDR_B _DQS2
DDR_B _D18 DDR_B _D19
DDR_B _D28
DDR_B_DM 3
DDR_B _D30 DDR_B _D31
DDR_CKE 2_DIMMB7
DDR_B _BS28
DDR_B _BS08
DDR_B _WE#8
DDR_B _CAS#8
DDR_CS3_D IMMB#7
M_ODT37
ICH_SMBDATA13,15,20
ICH_SMBCLK13,15,20
+3VM
0310 add
3
DDR_CKE 2_DIMMB
DDR_B_BS #2
DDR_B_MA12 DDR_B_MA9 DDR_B_MA8
DDR_B_MA5 DDR_B_MA3 DDR_B_MA1
DDR_B_MA10 DDR_B_BS #0 DDR_B_W E#
DDR_B _CAS# DDR_C S3_DIMMB#
M_ODT3
DDR_B _D32 DDR_B _D33
DDR_B _DQS#4 DDR_B _DQS4
DDR_B _D34 DDR_B _D35
DDR_B _D40 DDR_B _D41
DDR_B_DM 5
DDR_B _D42 DDR_B _D43
DDR_B _D48 DDR_B _D49
DDR_B _DQS#6 DDR_B _DQS6
DDR_B _D51 DDR_B _D50
DDR_B _D56 DDR_B _D61 DDR_B_D5 7
DDR_B_DM 7
DDR_B _D59 DDR_B _D58
ICH_SMBDATA ICH_SMBCLK
1
C312
2
2.2U_0 603_6.3V4Z
2006/02/13 2006/03/10
1
C301
2
Compal Secret Data
VSS DQ4 DQ5
VSS DM0
VSS DQ6 DQ7
VSS
DQ12 DQ13
VSS DM1
VSS
CK0
CK0#
VSS
DQ14 DQ15
VSS
VSS
DQ20 DQ21
VSS
DM2
VSS
DQ22 DQ23
VSS
DQ28 DQ29
VSS
DQS3#
DQS3
VSS
DQ30 DQ31
VSS
NC/CKE1
VDD
NC/A15 NC/A14
VDD
VDD
VDD
BA1
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36 DQ37
VSS DM4
VSS
DQ38 DQ39
VSS
DQ44 DQ45
VSS
DQS5#
DQS5
VSS
DQ46 DQ47
VSS
DQ52 DQ53
VSS
CK1
CK1#
VSS DM6
VSS
DQ54 DQ55
VSS
DQ60 DQ61
VSS
DQS7#
DQS7
VSS
DQ62 DQ63
VSS SAO
SA1 GND
2
+1.8V
V_DDR _MCH_REF
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
42 44 46 48 50
NC
52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90
A11
92
A7
94
A6
96 98
A4
100
A2
102
A0
104 106 108 110
S0#
112 114 116 118 120
NC
122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 204
2
DDR_B _D5 DDR_B _D4
DDR_B_DM 0
DDR_B _D6 DDR_B _D7
DDR_B _D12 DDR_B _D13
DDR_B_DM 1
M_CLK_DD R3 M_CLK_DDR#3
DDR_B _D14 DDR_B _D15
DDR_B _D21DDR_B _D17 DDR_B _D16
DDR_B_DM 2
DDR_B _D22 DDR_B _D23
DDR_B _D26 DDR_B _D24DDR_B _D25
DDR_B _DQS#3 DDR_B _DQS3
DDR_B _D29 DDR_B _D27
DDR_CKE 3_DIMMB
DDR_B_MA14
DDR_B_MA11 DDR_B_MA7 DDR_B_MA6
DDR_B_MA4 DDR_B_MA2 DDR_B_MA0
DDR_B_BS #1 DDR_B _RAS# DDR_C S2_DIMMB#
M_ODT2 DDR_B_MA13
DDR_B _D36 DDR_B _D37
DDR_B_DM 4
DDR_B _D39 DDR_B _D38
DDR_B _D44 DDR_B _D45
DDR_B _DQS#5 DDR_B _DQS5
DDR_B _D46 DDR_B _D47
DDR_B _D52 DDR_B _D53
M_CLK_DD R2 M_CLK_DDR#2
DDR_B_DM 6
DDR_B _D54 DDR_B _D55
DDR_B _D60
DDR_B _DQS#7 DDR_B _DQS7
DDR_B _D62 DDR_B _D63
10K_0402_5%
12
R254
2.2U_0805_16V4Z
0.1U_0402_16V4Z
1
1
C89
2
2
M_CLK_DD R3 7 M_CLK_DD R#3 7
PM_EXTTS#1 7
DDR_C KE3_DIMMB 7
0612 a dd
DDR_B_BS 1 8 DDR_B _RAS# 8 DDR_C S2_DIMMB# 7
M_ODT2 7
M_CLK_DD R2 7 M_CLK_DD R#2 7
R257
1 2
10K_0402_5%
Title
Size Doc ument Number Re v
Date: Sheet of
+3VM
Compal Electronics, Inc.
DDRII-SODIMM SLOT2
LA-3261P UMA
1
V_DDR _MCH_REF 7,13,42
C90
1
14 55Tuesday, M arch 27, 2007
0.4
5
PCI
SRC
CPU
CLK SEL1
1
1
FSLA
CLK SEL0
MHz
200
166
MHz
1000
100
MHz
33.30
33.3
+3VM
1 2
R1066 0_1206_5%
03/0 2 change
FSLC1FSLB
CLK SEL2
0
FSB Frequency Selet:
D D
CPU Driven
(Default)
*
Stuff
No Stuff
Stuff
667MHz
No Stuff
Stuff
800MHz
CPU_BSEL05
C C
CPU_BSEL15
B B
CPU_BSEL25
FSC
No Stuff
2.2K_0402_5%
FSA
0_0402_5%
0_0402_5%
10K_0402_5%
0_0402_5%
R1078
1 2
R1083
1 2
R1107
R1130
1 2
R1135
0529 change power plan e
A A
18P_0402_50V8J
14.31818MHZ_16P
2
C509
1
Y6
Rou ting th e trace at lea st 10 mil
R1107 R1135 R1083
R1074 R1086 R1098 R1113 R1139
R1139 R1135R1135 R1139
R1083
R1107
R1128
R1098
R1113
R1135 R1139
R1083
R1086
R1074
1 2
12
R1079
12
+VCCP
+VCCP
1K_0402_5%
12
R1086
1K_0402_5%@
R1098
1K_0402_5%@
1 2
1 2
R1105
1K_0402_5%
12
R1113
@
0_0402_5%
R1128
1K_0402_5%@
1 2
1 2
R1131
1K_0402_5%
12
R1139
@
0_0402_5%
FSB
R1098
R1107
R1113
R1074
@
1 2
56_0402_5%
MCH_CLKSEL0 7
MCH_CLKSEL1 7
MCH_CLKSEL2 7
For ITP_ EN, 0 = SRC8/SRC8#; 1 = ITP/IT P#
For 27_S EL, 0 = E nable DOT96 & SRC1,
For PCI2 _EN, 0 = Over clocking of CPU and SR C Allowed
CLK_XTAL_OUT
CLK_XTAL_IN
12
2
C505 18P_0402_50V8J
1
5
+3VS +3VS + 3VS
1 2
ITP_EN 27_SEL
1 2
R1128
R1074R1086
R1128
+VCCP
1111 Add CLRP 4,CLRP5 for 667/800 FS B select SHOR T CL RP5, NO SHORT CLRP 4 -- FSB 80 0 SHOR T CL RP4, NO SHORT CLRP 5 -- FSB 66 7
0216 Delete CLRP4,CLRP 5
CLKSATAREQ#20
CLK_DEBU G_PORT25,30
CLK_P CI_SIO29 CLK_PC I_TCG30 CLK_P CI_EC31
CLK_PCI_PCM25
CLK_P CI_ICH18
CLK_48M_ICH20
CLK_14M_ICH20 CLK_14M_SIO29 CLK_14M_KBC31
1= E nable S RC0 & 27MHz
1 = Over clock ing of CPU and SRC NOT allowed
R1245 10K_0402_5%
R1247 10K_0402_5%
@
+3VM_CK505
CLKREQ#_B7
1 2
1 2
4
1
C1165
10U_0805_10V4Z
2
R1690 10K_0402_5%
@
R1691 10K_0402_5%
4
R1693 475_0402_1%
R1077 33_0402_1%
1 2
1 2 1 2 1 2
1
C1166
0.1U_0402_16V4Z
2
+1.25VM_CK505
1 2
1 2
1 2 1 2 1 2
1 2
R1108 10K_0402_5%
1 2
PCI2_TME
R1246 10K_0402_5%
@
1 2
03/02 change
R1692475_0402_1%
R109722_0402_5%
12
R111412_0402_5%
12
R114012_0402_5% R111012_0402_5% R114112_0402_5%
R111722_0402_5%
CLK_XTAL_IN
CLK_XTAL_OUT
R108733_0402_1% R108833_0402_1% R108933_0402_1%
+1.25VM_CK505
1
C1167
0.1U_0402_16V4Z
2
+1.25VM
+3VM_CK505
PCI_CLK1
PCI2_TME
PCI_CLK3
27_SEL
ITP_EN
FSA
FSB
FSC
3
1
C1168
0.1U_0402_16V4Z
2
1
C1169
0.1U_0402_16V4Z
2
1
C1170
0.1U_0402_16V4Z
2
1
C1171
0.1U_0402_16V4Z
2
Pla ce cl ose to U7
R1068 0_1206_5%
1 2
C1172
10U_0805_10V4Z
U7
2
VDD_PCI
9
VDD48
16
VDDPLL3
61
VDDREF
39
VDDSRC
55
VDDCPU
12
VDD96_IO
20
VDDPLL3_IO
26
VDDSRC_IO
36
VDDSRC_IO
49
VDDCPU_IO
1
PCI0/CR#_A
3
PCI1/CR#_B
4
PCI2/TME
5
PCI3
6
PCI4/27_Select
7
PCIF5/ITP_EN
60
X1
59
X2
10
USB_48MHZ/FSLA
57
FSLB/TEST MODE
62
REF0/FSLC/TEST_SEL
45
VDDSRC_IO
42
GNDSRC
8
GNDPCI
11
GND48
15
GND
19
GND
52
GNDCPU
23
GNDSRC
29
GNDSRC
58
GNDREF
* Int ernal Pull-U p Resi stor ** In ternal Pull- Down R esistor
Secur ity Classification
Issued Date
0.1U_0402_16V4Z
1
C1173
2
SRC1/SE1/27MHz_NonSS
3
1
C1174
2
0.1U_0402_16V4Z
PCI_STOP#
CPU_STOP#
CPU1_F
CPU1#_F
SRC8/ITP
SRC8#/ITP#
SRC10#
SRC11/CR#_H
SRC11#/CR#_G
SRC7/CR#_F
SRC7#/CR#_E
SRC3/CR#_C
SRC3#/CR#_D
SRC2/SATA
SRC2#/SATA#
SRC1#/SE2/27MHz_SS
SRC0/DOT96
SRC0/DOT96#
CK_PWRGD/PD#
ICS9LPRS355_TSSOP64
2006/02/13 2006/03/10
SCLK
SDATA
CPU0
CPU0#
SRC10
SRC9
SRC9#
SRC6
SRC6#
SRC4
SRC4#
1
2
48
NC
64 63
38 37
54 53
51 50
47 46
35 34
33 32
30 31
44 43
41 40
27 28
24 25
21 22
17 18
13 14
56
10U_0805_10V4Z
1
C1353
2
R_CPU _BCLK R_CPU _BCLK#
R_MCH_BCLK R_MCH_BCLK#
R_CPU_XDP R_CPU_XDP#
R_PCIE_3GPLL # R_PCIE_3GPLL
CLKRE Q#_H R_CLKR EQ#_G
R_CLK _PCIE_MCard R_CLK _PCIE_MCard#
R_CLK _Rob R_CLK _Rob#
R_MCH_3GPLL R_MCH_3GPLL#
R_P CIE_ICH R_PCI E_ICH#
R_PCIE_SATA R_PCIE_SATA#
SSCD REFCLK SSCD REFCLK#
R_MC H_DREFCLK R_MC H_DREFCLK#
Compal Secret Data
0.1U_0402_16V4Z
1
C1354
2
0.1U_0402_16V4Z
R1070
R1072
R1075
R1081
R1033 0_0402_5%
R1143
R1111
R1115
R1695
R1694
R1093
R1095
R14 10K_04 02_5%
R17 475_0402_1%
R5 0_0402_5% R13 0_0402_5%
R1144
R1145
R1684
R1685
R1257
R1259
R1686 0_0402_5% R1687 0_0402_5%
R1688
R1689
Deciphered Date
+1.25VM_CK505
1
2
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
C1355
2
12
12
2
0_0402_5% 0_0402_5%
0_0402_5% 0_0402_5%
0_0402_5%
0_0402_5% 0_0402_5%
1 2
R149 10K_0402_5% 475_0402_1% 475_0402_1% R150 10K_0402_5%
1 2
0_0402_5% 0_0402_5%
+3VS
0_0402_5% 0_0402_5%
0_0402_5% 0_0402_5%
0_0402_5% 0_0402_5%
0_0402_5% 0_0402_5%
ICH_SMBCLK 13,1 4,20 ICH_SMBDATA 13,14,20
H_STP_PCI# 20 H_STP_CPU# 20
CLK_CP U_BCLK 4 CLK_CP U_BCLK# 4
CLK_MCH_BCLK 7 CLK_MCH_BCLK# 7
CLK_CPU_XDP 4 CLK_CPU_XDP# 4
CLK_P CIE_DOCK# 33 CLK_P CIE_DOCK 33
+3VS
CPPE# 33
CLKREQ#_G 25
+3VS
CLK_P CIE_MCARD 25 CLK_P CIE_MCARD# 25
CLKREQ#_E 25
0612 add for Robson
CLK_P CIE_Rob 25 CLK_P CIE_Rob# 25
CLK_MCH_3GPLL 7 CLK_MCH_3GPLL# 7
CLK_P CIE_ICH 2 0
CLK_P CIE_ICH# 20
CLK_PCIE_SATA 19 CLK_PCIE_SATA# 19
MCH_ SSCDREFCLK 7 MCH_ SSCDREFCLK# 7
CLK_M CH_DREFCLK 7 CLK_M CH_DREFCLK# 7
CK_PW RGD 20
1
C353
C357
C372
C373
C374
C375
C376
C378
C379
C380
CLK_48M_ICH
12
5P_0402_50V8C
CLK_14M_ICH
12
4.7P_0402_50V8C
CLK_P CI_ICH
12
4.7P_0402_50V8C
CLK_14M_KBC
12
4.7P_0402_50V8C
CLK_14M_SIO
12
4.7P_0402_50V8C
CLK_P CI_EC
12
4.7P_0402_50V8C
CLK_PC I_TCG
12
4.7P_0402_50V8C
CLK_PCI_PCM
12
4.7P_0402_50V8C
CLK_P CI_SIO
12
4.7P_0402_50V8C
CLK_DEBU G_PORT
12
5P_0402_50V8C
200 70 301 Ad d C AP for WWAN issue
0612 add for Robson
Title
Size Doc ument Number Re v
Date: Sheet of
Compal Electronics, Inc.
Clock generator
LA-3261P UMA
15 55Tuesday, M arch 27, 2007
1
0.4
A
CRT Connector
101 3 Add CRT ci rcuit
1 1
+5VS +5VS
1
5
M_HS YNC9
M_VSYNC9
2 2
R53 51K_0402_5%
P
A2Y
G
3
1 2
1 2
R54 51K_0402_5%
Pla ce cl ose to do cki ng connect or
L_BLUE33
L_GREEN33
L_RED33
0315 add
C359
1 2
0.1U_0402_16V4Z
U33 SN74AHCT1G125GW_SOT353-5
HSYN C_G_A
4
OE#
1
5
P
OE#
A2Y
G
U54 SN74AHCT1G125GW_SOT353-5
3
C370
1 2
0.1U_0402_16V4Z
VSYNC_ G_A
4
150_0402_1%
12
R171
@
R545
1 2
0_0603_5%
1 2
5P_0402_50V8C@
12
150_0402_1%
R173
@
R546
0_0603_5%
C351
R174
B
12
@
150_0402_1%
C313
C314
12P_0402_50V8C
1
1
2
2
D_H SYNC
D_V SYNC
1
1
C352
5P_0402_50V8C@
2
2
1
12P_0402_50V8C
2
D_H SYNC 33
D_V SYNC 33
R542
1 2
BK1608LL560-T 0603
R543
1 2
BK1608LL560-T 0603
R544
1 2
BK1608LL560-T 0603
@
C310
18P_0402_50V8J
12P_0402_50V8C
0315 add
C317
D_DDC DATA33
D_DDC CLK33
1
@
2
1
C316
2
C
F1
1.1A_6 VDC_FUSE
RED_R
GREEN_R
BLUE_R
1
C318
2
18P_0402_50V8J
18P_0402_50V8J
@
D18
2 1
21
CH491 D_SC59
0.1U_0402_16V4Z
C315
W=40m ils
1
2
JP2
6
11
1 7
12
2 8
13
3 9
14
4 10 15
5
SUYIN_0 70912FR0 15S207CR
conn@
+CRTVDD +CRTVDD
R162
2.2K_0402_5%
D_DDC DATA
D_DDC CLK
D
+CRTVDD+RCR T_VCC+5VS
BLUE_R GREEN_R RED_R
1
1
D4
DAN217_SC5 9
@
2
2
3
16 17
R2
1 2
2
G
S
2
G
1 3
D
S
RHU002N06_S OT323
2.2K_0402_5%
12
12
R183
2.2K_0402_5%
Q46
1 3
D
RHU002N06_S OT323
Q52
1
D19
D20
Place close to JP2
DAN217_SC5 9@
+CRTVDD
3
+3VS
DAN217_SC5 9
@
3
2
R4
1 2
2.2K_0402_5%
Pla ce cl ose to do cki ng connect or
DDC1_DAT A 9
DDC1_ CLK 9
E
layo ut n ote: D_H SYNC & D_VSY NC should b e routed to docking co nnector the n to VGA co nnector
TV-Out Connector
LUMA9,33
CRMA9,33
COMP9,33
12
12
3 3
la y o u t n
la y o u t n ote : T V-o ut si g na l s sho u ld b e r o ute d t o J P3 0 t h en to JP 1
la y o u t nl a y o ut n
4 4
R184
@
0315 add
150_0402_1%
150_0402_1%
ot e : TV - ou t s i gn a ls s h oul d b e r ou t ed to JP 3 0 t he n t o J P1
ot e : TV - ou t s i gn a ls s h oul d b e r ou t ed to JP 3 0 t he n t o J P1ot e : TV - ou t s i gn a ls s h oul d b e r ou t ed to JP 3 0 t he n t o J P1
@
R185
@
Cl
Cl ose to JP 1
os e t o J P1
ClCl
os e t o J P1o se to JP 1
12
R187
150_0402_1%
1
@
2
5.6P_0402_50V8D
C333
5.6P_0402_50V8D
1
2
C355
C354
@
0_0603_5%
R547
1 2
0_0603_5%
R548
1 2
0_0603_5%
R549
1 2
1
@
2
5.6P_0402_50V8D
Place close to JP1
DAN217_SC5 9
D3
@
DAN217 _SC59
1
2
3
@
D5
TV_LUMA
TV_CRMA
TV_COMP
DAN217_SC5 9
@
1
2
3
SUYIN_3 3007SR-07T1-C
+3VS
D1
1
2
3
JP1
1 2 3 4 5 6 7
conn@
+2.5VS +2.5VS
+2.5VS
12
DVI Transnitter
Secur ity Classification
Issued Date
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
R1369
CHB1608U301_ 0603
R497 10K_0402_5%
W= 20 m ils
AS
PEG_RXP19 PEG_RXN19
C
DVI_D VDD_2.5V
12
C178
C143
C150
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1.3K_0402_1%
C1043 C1042
R103
SDVOB_R+9 SDVOB_R-9
SDVOB_G+9 SDVOB_G-9
SDVOB_B+9 SDVOB_B-9
SDVOB_CLK+9 SDVOB_CLK-9
12
0.1U_0402_16V4Z
PLT_RST#7,18,22,30
R114
10K_0402_5%
0.1U_0402_16V4Z
SDVOB_INT-
0.1U_0402_16V4Z
1 2
2006/02/13 2006/07/26
DVI_A VDD_2.5V
C174
0.1U_0402_16V4Z
AS PLT_RST#
DVI_V SWING
12
R498
10K_0402_5%
Compal Secret Data
Deciphered Date
02/2 8 ch ange -->so lve DVI iss ue
R1367
1 2
KC FBM-L11-201209-221LMA30T_0805
0.1U_0402_16V4Z
DVI_A VDD_3V
DVI_D VDD_2.5V
U11
SDVOB_INT+ SDVOB_INT-
SDVOB_R+ SDVOB_R-
SDVOB_G+ SDVOB_G-
SDVOB_B+ SDVOB_B-
SDVOB_CLK+ SDVOB_CLK-
AS RESET# VSWING
ATPG SCEN
PAD
49
1
C140 22U_0805_6.3VAM
2
28
1
DVDD12DVDD
AVDD_PLL
DGND7DGND30AGND31AGND39AGND45TGND18TGND24AGND_PLL
D
21
TVDD15TVDD
AVDD36AVDD42AVDD
DVI_A VDD_2.5V
6
C141
32 33
37 38
40 41
43 44
46 47
3 2
25
27 26
C358
C371
R_DVI _CLK-SDVOB_INT+ R_DVI _CLK+ R_DVI_TX0­R_DVI_TX0+ R_DVI_TX1­R_DVI_TX1+ R_DVI_TX2­R_DVI_TX2+
DVI_DETECT
10K_0402_5%
SDVO_SDAT SDVO_SCLK
0.1U_0402_16V4Z
48
TDC0#
TDC0
TDC1#
TDC1
TDC2#
TDC2
HPDET
SC_DDC SD_DDC
SC_PROM SD_PROM
NC
NC
CH730 7C_LQFP48
35
34
0.1U_0402_16V4Z
0.1U_0402_16V4Z
13
TLC#
14
TLC
16 17 19 20 22 23
29
11 10
9 8
5
SPD
4
SPC
0830 Change to 3.9K oh m
Title
Size Doc ument Number Re v
Date: Sheet of
KC FBM-L11-201209-221LMA30T_0805
DVI_A VDD_3V
C368
R1673 0_0603_5% R1674 0_0603_5% R1675 0_0603_5% R1676 0_0603_5% R1677 0_0603_5% R1678 0_0603_5% R1679 0_0603_5% R1680 0_0603_5%
R172010K_0402_5%
@
1 2 1 2
R1721
@
C1371
56P_0402_50V
SDVO_SDAT SDVO_SCLK
R1368
1 2
1
C369 10U_0805_10V4Z
2
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
0620 change
SDVO_SDAT 7 SDVO_SCLK 7
+5VS
DVI_C LK 33 DVI_DAT 33
+3VS
DVI_DETECT 33
1226 Add C for DVI I2C
R144 5.6K_0402_5%
1 2
R142 5.6K_0402_5%
1 2
1113 Change to 5.6K oh m
Compal Electronics, Inc.
CRT & TVout Connector
LA -3 26 1P U MA
16 55Tuesday, M arch 27, 2007
E
DVI_C LK- 33 DVI_CLK+ 33 DVI_TX0- 33 DVI_TX0+ 33 DVI_TX1- 33 DVI_TX1+ 33 DVI_TX2- 33 DVI_TX2+ 33
+2.5VS
0.4
5
4
3
2
1
JP35
B+_LCD
C586 10U_1206_25V6M
C587 68P_0402_50V8J
40
40
39
39
38
38
37
37
36
36
35
35
34
34
33
33
32
32
31
31
30
30
29
29
28
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1
BKLT_PWM
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
LVDS CONN
41
41
42
D D
C C
42
43
43
44
44
45
45
46
46
ACES_88316-4000
conn@
2007 0209 Add 10uF for wavy is sue
1 2
1 2
1 2
10U_1206_25V6M
C1376
L62 KC FBM-L11-201209-221LMA30T _1210
LCDVD D
+3VS
+5VS_INV
TXCLK_U+ 9 TXCLK_U- 9
TXOUT_U2+ 9 TXOUT_U2- 9
TXOUT_U1+ 9 TXOUT_U1- 9
TXOUT_U0+ 9 TXOUT_U0- 9
TXOUT_L0- 9 TXOUT_L0+ 9
TXOUT_L1- 9 TXOUT_L1+ 9
TXOUT_L2- 9 TXOUT_L2+ 9
TXCLK_L- 9 TXCLK_L+ 9
0628 change si ze
12
ALS_EN 20
DDC2_ CLK 9 DDC2_DAT A 9
LCD POWER CIRCUIT
LCDV DD
12
R19
100_0402_1%
+3VALW
+3VS
LID_SW#20,32
Q5
R502
13
D
2
G
S
2
1 2
0_0402_5%
R1728
1 2
0_0402_5%@
R1729
1 2
LID_SW#
ENABLT9
0314 change
13
R474
1 2
47K_0402_5%
Q6 DTC124EK_SC59
+3V_U43
14
1
P
A
2
B
G
7
R501
1 2
100K_0402_1%
1
C29
2
0.1U_0402_16V4Z
+5VS
U43A SN74LVC08APW_TSS OP14
3
O
R360
100K_0402_5%
1 2
B+
RHU002N06_S OT323
ENAVDD9
100K_0402_1%
0314 add
Q8
AO3413_SOT23
D
S
1 3
R12
G
2
1 2
1M_0402_5%
C28
1 2
1
C31
4.7U_0805_10V4Z
2
0.1U_0402_16V7K
0216 Change C28 to 0.1 uF
Q53 DTA114YKA_SC59
13
Q36 BSS138_SOT23
+5VS_INV
47K
10K
2
13
D
2
G
S
+3VALWLCDVD D
1
C20
4.7U_0805_10V4Z@
2
B B
BLON_PWM9
R102 0_0402_5%
1 2
BKLT_PWM
Support 3V inverter
A A
Secur ity Classification
Issued Date
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/07/26
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
2
Date: Sheet of
Compal Electronics, Inc.
LCD CONN.
LA -3 26 1P U MA
17 55Tuesday, M arch 27, 2007
1
0.4
Loading...
+ 38 hidden pages