Mobile Merom uFCPGA with Intel
Crestline_PM+ICH8-M core logic
33
IBT00 LA-3261P UMA
2007-03-28
44
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2006/02/132006/03/10
REV:1A (MV2)
Compal Secret Data
Deciphered Date
D
Title
Size Doc ument NumberRe v
Cus tom
Date:Sheetof
Compal Electronics, Inc.
Cover Sheet
LA -3 26 1P U MA
E
155Wednesday, March 28, 2007
0.4
A
Compal confidential
File Name : LA-3261P
B
C
Chimay UMA
D
E
11
CRT & TV OUT
P16
LVDS Panel Interface
P17
Thermal Sensor
AD M1032ARMZ
P4
Fan c onn
P4
Intel Crestline MCH
SDV O
22
DVI (Docking)
P33
CH 7307 C
P16
DM I X4
PCI-E BUS
10/100/1000 LAN
Mini-Card
Intel 82566MM
P23
RJ 45/11 CONN
33
P24
LED
P30
CardBus Controller & PCMCIA conn
Ri coh R5C853 & R5C851
P25
Slot 0/Smart Card
1394 port
P28
6in1 Slot
PCI
daug hte r board
RTC CKT.
P19
Mo bile Merom
uFCPGA-478 CPU
H_ A#( 3.. 35)
H_ D#( 0..6 3)
FSB
667/800MH z 1.05V
FC BGA 1299
P7, 8, 9, 10, 11, 12
Intel ICH8-M
mB GA-676
P18, 19, 20, 21
SPI ROM & Debug port
16Mb*2 or 32Mb*1
P4, 5, 6
C- Link
SPI
LPC BUS
DDR2 667MHz 1. 8V
Dual Channel
USB2.0
Azalia
SATA Master
PATA Slave
P30
DDR2- SO-DIMM X2
BANK 0, 1, 2, 3
P13, 14
USB conn x2
(Docking)
FingerPrint er 2501B
USBx1
USB conn x3
BT Co nn
Mini-Card WWAN
P25P25
Audio CKT
AD1981HD
P26
SATA HDD Connector
P22
Multi-bay II Connector
P22
P33
P30
P28
P28
CK505
TSSOP- 64
Clock Generator
IC S 9LPR S355
P15
daug hte r board
MDC
P32
AMP & Audio Jack
MAX9710
P33
Docking CONN.
*RJ-45(LED*2)
*RJ-11(Pass Through)
*CRT
*COMPOSITE Video Out
*TVOUT
*DVI
*LINE IN
P27
*LINE OUT
Power OK CKT.
P35
44
Power On/Off CKT.
P32
TPM1.2
SLB9635TT
P30
Touch P ad CON N.
SMSC KBC 1070
SMSC KBC 1021-NU
P31
Int.KBD
P32P32
SMSC Super I/O
LPC47N217
COM1LPT
( Docking )( Docking )
P33P33
P29
*PCI-E x2
*Serial Port
*Parallel Port
*PS/2 x2
*USB x2
*DC JACK
DC/DC Interface CKT.
P34
A
TrackPoint CONN.
B
P32
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Device
MODEM / LAN
ECP
FL OPP Y DISK
AUDIO
(Cascade)
Unused
Unused
Unused
+3VM
+1.05VM
+1.25VM
O
O
O
O
X
X
CLOCK
O
O
O
O
X
X
IRQ
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
De vic e
Syste m Timer
Keyboa rd
N/A
Seri al po rt (COM2),L AN/Modem
Seri al port (COM1)
Audio /VGA
Floppy
Para llel port
Syst em CM OS/Real-tim e clock
Micr osoft ACPI
N/A, Momem,LAN
Mass str orag e contr ol/ PCI sim ple communi cation cont rol
syna ctic PS2 port Gl idePAD
Nume ric Data Process
Prim ary I DE interfac e,HDD
Seco ndar y IDE innt erface,CD-R OM
Mobi le I ntel Crestline E xpress Chip set Family
Micr osof t UA A Bus Dri ver for Hig h Definitio n Audio
Inte l 82 801H (ICH8 Fa mily) PCI E xpress Root Port -27D0
Broa dcom NetXtrem e Gigabit E thernet
Inte l 82 801H (ICH8 Fa mily)PCI Ex press Root Port - 27D2
Broa dcom 80 2.11b/g WLA N
Inte l 82 801H (ICH8 Fa mily)USB Un iversal Hos t Controll
Inte l 82 801H (ICH8 Fa mily)USB Un iversal Hos t Controll
Rico h R5C 853 Cardbus Control
Rico h R5 C853 Integrates FlashMedia Control
Rico h R5 C853 Gemcore bas ed SmartCar d Control
Inte l 82 801H (ICH8 Fa mily)PCI Ex press Root Port - 27D6
Inte l 82 801H (ICH8 Fa mily)USB Un iversal Hos t Controll
Inte l 82 801H (ICH8 Fa mily)USB Un iversal Hos t Controll
Inte l 82 801H (ICH8 Fa mily)USB2 E nhanced Hos t Controll
Inte l 82 801H (ICH8 Fa mily)USB Un iversal Hos t Controll
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Place these capac itors on L8
(Nort h side ,Secon dary L ayer)
Place these capac itors on L8
(Sort h side ,Secon dary L ayer)
Place these capac itors on L8
(Sort h side ,Secon dary L ayer)
0314 change to mo unt
330U_D2E_2.5VM _R7
+VCCP
1
C940
0.1U_0402_10V6K
2
4
+VCC_ CORE
1
+
C931
2
+VCC_ CORE
1
C899
10U_0805_6.3V6M
2
+VCC_ CORE
1
C907
10U_0805_6.3V6M
2
+VCC_ CORE
1
C915
10U_0805_6.3V6M
2
+VCC_ CORE
1
C923
10U_0805_6.3V6M
2
Near CPU CORE regulator
330U_D2E_2.5VM_R7
1
+
C932
C933
2
330U_D2E_2.5VM _R7
1
C941
0.1U_0402_10V6K
2
1
C900
10U_0805_6.3V6M
2
1
C908
10U_0805_6.3V6M
2
1
C916
10U_0805_6.3V6M
2
1
C924
10U_0805_6.3V6M
2
1
+
C935
2
330U_D2E_2.5VM_R7
1
C942
0.1U_0402_10V6K
2
1
+
2
1
C901
10U_0805_6.3V6M
2
1
C909
10U_0805_6.3V6M
2
1
C917
10U_0805_6.3V6M
2
1
C925
10U_0805_6.3V6M
2
330U_D2E_2.5VM _R7
1
+
C937
C936
2
330U_D2E_2.5VM _R7
1
C943
0.1U_0402_10V6K
2
3
1
C902
10U_0805_6.3V6M
2
1
C910
10U_0805_6.3V6M
2
1
C918
10U_0805_6.3V6M
2
1
C926
10U_0805_6.3V6M
2
ESR <= 1.5m ohm
Capacitor > 1980uF
1
1
+
+
C934
@
2
820U_E9_2_5V_M_R7
2
1
C944
0.1U_0402_10V6K
2
1
C903
10U_0805_6.3V6M
2
1
C911
10U_0805_6.3V6M
2
1
C919
10U_0805_6.3V6M
2
1
C927
10U_0805_6.3V6M
2
Plac e these inside
sock et cavity o n L8
(North side
Seco ndary)
1
C945
0.1U_0402_10V6K
2
1
C904
10U_0805_6.3V6M
2
1
C912
10U_0805_6.3V6M
2
1
C920
10U_0805_6.3V6M
2
1
C928
10U_0805_6.3V6M
2
2
1
C905
10U_0805_6.3V6M
2
1
C913
10U_0805_6.3V6M
2
1
C921
10U_0805_6.3V6M
2
1
C929
10U_0805_6.3V6M
2
1
C906
10U_0805_6.3V6M
2
1
C914
10U_0805_6.3V6M
2
1
C922
10U_0805_6.3V6M
2
1
C930
10U_0805_6.3V6M
2
1
Mid Frequence Decoupling
AA
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/132006/03/10
Compal Secret Data
Deciphered Date
Title
Size Doc ument NumberRe v
Cus tom
2
Date:Sheetof
Compal Electronics, Inc.
CRESTLINE((2/6)-DDR2 A/B CH
LA -3 26 1P U MA
855Tuesday, March 27, 2 007
1
0.4
5
For Crestli ne:2.4kohm
For Calero: 1.5Kohm
+3VS
M_COMP
M_LUMA
M_CRMA
R175
M_BLUE
M_GREEN
M_RED
R180
BLON_PWM
ENABLT
DDC2_ CLK
DDC2_DAT A
ENAVDD
2.4K_0402_1%
R1447
TXCLK_LTXCLK_L+
TXCLK_UTXCLK_U+
TXOUT_L0TXOUT_L1TXOUT_L2-
TXOUT_L0+
TXOUT_L1+
TXOUT_L2+
TXOUT_U0TXOUT_U1TXOUT_U2-
TXOUT_U0+
TXOUT_U1+
TXOUT_U2+
75_0402_1%
12
R94
12
75_0402_1%
BLON_PWM17
ENABLT17
DDC2_ CLK17
DDC2_DAT A17
ENAVDD17
DD
TXCLK_L-17
TXCLK_L+17
TXCLK_U-17
TXCLK_U+17
TXOUT_L0-17
TXOUT_L1-17
TXOUT_L2-17
TXOUT_L0+17
TXOUT_L1+17
TXOUT_L2+17
TXOUT_U0-17
TXOUT_U1-17
TXOUT_U2-17
TXOUT_U0+17
TXOUT_U1+17
TXOUT_U2+17
M_COMP
M_LUMA
0622 change value
CC
M_CRMA
M_BLUE
M_GREEN
M_RED
0314 change desig n
+3VS
0821
1013 change value
DDC1_ CLK16
DDC1_DAT A16
M_HS YNC1 6
M_VSYNC16
DDC1_ CLK
DDC1_DAT A
M_H SYNC
M_VSYNC
R165
R166
0821
BB
+3VS
1013 change value
2.2K_0402_5%
2.2K_0402_5%
DDC2_ CLK
DDC2_DAT A
R92
R158
12
12
TV-Out Termination/EMI Filter
M_COMP
M_LUMA
AA
M_COMP
M_LUMA
M_CRMA
1
2
C238
5.6P_0402_50V8D
C7
5.6P_0402_50V8D
1
1
2
2
0314 add
R9510K_0402_5%
12
R16010K_0402_5%
12
12
75_0402_1%
75_0402_1%
12
12
R177
R176
2.2K_0402_5%
12
75_0402_1%
12
30.1_0402_1%
12
30.1_0402_1%
L38
12
CHB1608U301_ 0603
L37
12
CHB1608U301_ 0603
L17
12
CHB1608U301_ 0603
C251
5.6P_0402_50V8D
0314 add
75_0402_1%
12
12
R182
R181
HS YNC
VSYN C
1.15K_0402_1%
For Crestli ne:1.3kohm
For Calero: 255ohm
5.6P_0402_50V8D
U15C
J40
H39
E39
E40
C37
D35
K40
L41
L43
N41
N40
D46
C45
D44
E42
G51
E51
F49
G50
E50
F48
G44
B47
B45
E44
A47
A45
E27
G27
K27
F27
J27
L27
M35
P33
H32
G32
K29
J29
F29
E29
K33
G35
F33
C32
E33
12
R1449
CRES TLINE_1p0
Pl a c e c l o
Pl a c e c l o s e t o U 15
Pl a c e c l oPl ace c lo
1
1
2
2
C243
C8
5.6P_0402_50V8D
Note: C RT / TV-out s hould rout e to JP30 fir st then to the JP1 & JP2 on system side.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
L28
12
HLC06 03CSCC39NJT_0603
L35
12
HLC06 03CSCC39NJT_0603
L27
12
HLC06 03CSCC39NJT_0603
1
C233
@
2
10P_0402_50V8J
3
C_RED _L
C_GRN _L
C_BLU_L
1
C193
22P_0402_50V8J
2
0314 change desig n
2006/02/132006/03/10
PE GC OMP tr ace w idth
and sp acing is 2 0/25 mils .
SDVOB_R- 16
SDVOB_G- 16
SDVOB_B- 16
SDVOB_CLK- 16
SDVOB_R+ 16
SDVOB_G+ 16
SDVOB_B+ 16
SDVOB_CLK+ 16
Pl a c e C
Pl a c e C lo sed to U1 5
Pl a c e CPl ace C
L31
12
HLC06 03CSCCR11JT_0603
L34
12
HLC06 03CSCCR11JT_0603
L26
12
HLC06 03CSCCR11JT_0603
1
1
C237
2
2
22P_0402_50V8J
C232
22P_0402_50V8J
@
Compal Secret Data
Deciphered Date
2
lo sed to U1 5
lo sed to U1 5lo sed to U1 5
1
C195
1
2
2
10P_0402_50V8J
10P_0402_50V8J
C244
@
2
10P_0402_50V8J
@
CFG[2:0] FSB Freq select
CFG5 (DMI select)
CFG6
CFG7 (CPU Strap)
CFG8 (Low power PCIE)
CFG9
(PCIE Graphics Lane Reversal)
CFG[11:10]
CFG[13:12] (XOR/ALLZ)
CFG16 (FSB Dynamic ODT)
SDVO_CTRLDATA
CFG19 (DMI Lane Reversal)
CFG20 (PCIE/SDVO concurrent)
RED
GREEN
BLUE
1
2
C245
RED33
GREEN 33
BLUE33
Title
Size Doc ument NumberRe v
Cus tom
Date:Sheet
1
Strap Pin Table
010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved
0 = DMI x 2
1 = DMI x 4
*
Reserved
0 = Reserved
1 = Mobile CPU
*
0 = Normal mode
1 = Low Power mode
*
0 = Reverse Lane
1 = Normal Operation
*
Reserved
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
4.7U_0805_10V4Z
1
C838
2
0316 add
0.47U_0603_10V7K
C836
C1119
C1120
1
2
+3VS_HV
C1136
0.47U_0603_10V7K
1
2
+1.8V
2.2U_0805 _16V4Z
4.7U_0805 _10V4Z
1
1
C837
2
2
R1671
12
10U_0805_10V4Z
+1.25VM
0_0805_5%
0.1U_0402 _16V4Z
1
2
2006/02/132006/03/10
Compal Secret Data
+1.25VS_DPLLB
0.1U_0402_16V4Z
+1.25VS_DMI
+1.25VS_PEGPLL
+1.25VS_DP LLA
220U_D2_4VM
1
C1227
+
2
Deciphered Date
22U_0805_6.3VAM
C1110
1
2
12
0.1U_0402 _16V4Z
C1117
1
2
0.1U_0402 _16V4Z
C1122
1
2
C1133
1
2
0.1U_0402_16V 4Z
+VCC_PEG
220U_D2_4VM
1
C1137
+
2
2
R1454
12
10U_FLC-453232-1 00K_0.25A_10%
1
C1231
2
+1.25VS
R1457
0_0603_5%
BLM18PG121SN1D_0 603
10U_0805_10V4Z
C1123
1
2
10U_0805_10V4Z
C1276
1
2
C1138
1
2
2
+1.25VS
0619 c hange
+1.25VS
L77
12
R1463
12
10U_FLC-453232-1 00K_0.25A_10%
0316 add
10U_0805_10V4Z
04/ 10 stu ff
R1465
0_0805_5%
R1467
@
0_0805_5%
+1.25VS
12
12
04/ 10 no stu ff
21
+VCCP
CH751H-40PT_S OD323-2
+3VS
1
+V1.25VS_AXF
0619 c hange value
+VCCP
+1.25VS
D12
Title
Size Documen t NumberRe v
Cust om
Date :Sheetof
+1.8V_SM_CK
10U_0603_6.3V6M
1
C1230
2
+1.5VS_TVDAC
+1.25VM_HPLL
C1134
0.1U_0402_16 V4Z
+1.25VM_MPLL
C1139
0.1U_0402_16 V4Z
+VCCP_ D
R1469
10_0402_5%
Compal Electronics, Inc.
CRESTLINE(4/6)-PWR
LA -3 26 1P U MA
1U_0603_10V4Z
10U_0805_10V4Z
C1112
C1111
1
1
2
2
12
0.1U_0402 _16V4Z
10U_0603_6.3V6M
1
C1115
2
0.022U_0402_16V7K
1
C1124
2
1
2
1
2
12
0.1U_0402_16V4Z
1
C1125
2
MBK2012121YZF _0805
1
C1135
10U_0805_10V4Z
2
MBK2012121YZF _0805
1
C1140
10U_0805_10V4Z
2
R1470
0_0402_5%
1
C1116
1
2
12
R1464
R1466
12
0_0805_5%
0_0805_5%
12
0_0603_5%
R1458
R1460
+1.25VM
12
+1.25VM
12
+3VS_HV
1055Tuesd ay, March 27, 2007
+1.25VS
R1455
+1.8V
+1.5VS
0.4
5
4
3
2
1
+VCCP
DD
22U_0805_6.3VAM
220U_D2_4VM_R15
1
C806
+
2
0317 change value
CC
0.22U_0402_10V4 Z
0.22U_0402_10V4 Z
C803
C796
1
2
1
1
2
2
+1.05VM
10U_0805_10V4Z
04/ 10 mo nit or N B cra ck
BB
0.22U_0402_10V4 Z
C1158
1
2
5
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C1159
1
1
2
2
+3VS
100K_0402_5%
MCHGN D4
Q123
@
RHU002N06_S OT323
0.22U_0402_10V4 Z
C1157
1
2
+3VS
AA
100K_0402_5%
R1701
@
MCHGN D6
Q118
@
RHU002N06_S OT323
CRAC K_GPIO28
13
D
12
2
G
S
+VCCP
0.1U_0402_16V4Z
C797
C798
1
2
10U_0805_10V4Z
C1154
C1155
1
1
2
2
0.1U_0402_16V4Z
C1160
C1161
1
2
04/ 10 mo nit or N B cra ck
101 3 n o insta ll
121 3 i nsta ll
012 9 i nsta ll
200 702 27 No inst all 200 702 28 Ch ange to +3VL
101 3 i ns tal l R 111 ,R113 ,R122 ,R13 2
121 3 N o- ins tal l R 111, R113 ,R122 ,R132
012 9 N o- ins tal l R 111, R113 ,R122 ,R132
200 702 27 In sta ll R111 ,R11 3,R12 2,R13 2
+3VL
R1702
CRAC K_GPIO28
12
13
D
12
100K_0402_5%
2
G
S
R1475
12
0_0603_5%
330U_D2E_2.5VM_R9
+1.8V
+1.05VM
1
C1286
C1175
1U_0603_10V4Z
Secur ity Classification
2
330U_D2E_2.5VM _R9
0316 change value
CRAC K_GPIO28 21,31
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/132006/03/10
Compal Secret Data
Deciphered Date
Title
Size Doc ument NumberRe v
Cus tom
2
Date:Sheetof
Compal Electronics, Inc.
CRESTLINE((6/6)-PWR/GND
LA -3 26 1P U MA
1
1255Tuesday, M arch 27, 2007
0.4
5
DDR_A _DQS#[0.. 7]8
DDR_ A_D[0..63 ]8
DDR_A _DM[0..7]8
DDR_A _DQS[0..7 ]8
DDR_A _MA[0..14]7,8
DD
Lay out No te:
Pl ac e near JP 34
+1.8V
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C458
C498
1
1
2
2
CC
BB
AA
Lay out No te:
Pl ac e one ca p clo se to eve ry 2 pul lup
res istors te rmina ted to +0.9 VS
+0.9V
0.1U_0402_16V4Z
1
2
C229
0.1U_0402_16V4Z
1
2
C239
RP27
RP29
RP32
RP31
RP33
RP35
R1742 56_0402_5%
0.1U_0402_16V4Z
DDR_A_MA5
DDR_A_MA8
DDR_A_MA1
DDR_A_MA3
DDR_A _RAS#
DDR_C S0_DIMMA#
DDR_A_BS #0
DDR_A_MA10
DDR_A _CAS#
DDR_A_W E#
DDR_C S1_DIMMA#
M_ODT1
DDR_A_MA11
0612 a dd
5
2.2U_0805_16V4Z
C473
1
2
0.1U_0402_16V4Z
1
2
C250
14
23
56_0404_4P2R_5%
14
23
56_0404_4P2R_5%
14
23
56_0404_4P2R_5%
14
23
56_0404_4P2R_5%
14
23
56_0404_4P2R_5%
23
14
56_0404_4P2R_5%
12
2.2U_0805_16V4Z
C491
1
2
0.1U_0402_16V4Z
1
1
2
2
C272
C257
+0.9V
0.1U_0402_16V4Z
2.2U_0805_16V4Z
C465
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C281
C279
RP22 56_0404_4P2R_5%
DDR_A_BS #2
14
DDR_CKE 0_DIMMA
23
RP26 56_0404_4P2R_5%
DDR_A_MA7
14
DDR_A_MA6
23
RP25 56_0404_4P2R_5%
DDR_A_MA9
14
DDR_A_MA12
23
RP28 56_0404_4P2R_5%
DDR_A_MA4
14
DDR_A_MA2
23
RP30 56_0404_4P2R_5%
DDR_A_MA0
14
DDR_A_BS #1
23
RP34 56_0404_4P2R_5%
M_ODT0
14
DDR_A_MA13
23
RP24 56_0404_4P2R_5%
DDR_CKE 1_DIMMA
14
DDR_A_MA14
23
0.1U_0402_16V4Z
C255
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C274
4
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C280
C242
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
2
2
C268
2
C252
C241
La yout Note :
Pl ac e the se re sis tor
cl osely JP34 ,all
tr ace len gth Max= 1.5"
C235
0.1U_0402_16V4Z
0317 add
1
+
C246
330U_D2_2.5VM_R 15
2
0.1U_0402_16V4Z
1
1
2
2
C227
C234
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Lay out No te:
Pl ac e one ca p clo se to eve ry 2 pul lup
res istors te rmina ted to +0.9 VS
+0.9V
0.1U_0402_16V4Z
1
2
C176
DDR_B_MA1
DDR_B_MA3
DDR_B_BS #0
DDR_B_MA10
DDR_B_MA0
DDR_B_BS #1
DDR_B _RAS#
DDR_C S2_DIMMB#
DDR_B _CAS#
DDR_B_W E#
DDR_C S3_DIMMB#M_ODT2
M_ODT3
DDR_CKE 3_DIMMB
C159
1
2
0.1U_0402_16V4Z
1
1
2
2
C197
C213
+0.9V
RP10 56_0404_4P2R_5%
RP11 56_0404_4P2R_5%
RP12 56_0404_4P2R_5%
RP13 56_0404_4P2R_5%
RP15 56_0404_4P2R_5%
RP21 56_0404_4P2R_5%
RP9
56_0404_4P2R_5%
2.2U_0805_16V4Z
C164
1
2
0.1U_0402_16V4Z
1
2
C220
14
23
14
23
14
23
14
23
14
23
14
23
14
23
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C166
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C183
C210
DDR_B_MA9
DDR_B_MA12
DDR_B_MA14
DDR_B_MA11
DDR_B_MA5
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA13
DDR_B_BS #2
DDR_CKE 2_DIMMB
0.1U_0402_16V4Z
C219
1
2
0.1U_0402_16V4Z
1
2
C199
0612 a dd
5
0.1U_0402_16V4Z
C188
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C173
C218
La yout Note :
Pl ac e the se re sis tor
cl osely JP10 ,all
tr ace len gth Max= 1.5"
4
C161
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C177
C163
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
For PCI2 _EN, 0 = Over clocking of CPU and SR C Allowed
CLK_XTAL_OUT
CLK_XTAL_IN
12
2
C505
18P_0402_50V8J
1
5
+3VS+3VS+ 3VS
12
ITP_EN27_SEL
12
R1128
R1074R1086
R1128
+VCCP
1111 Add CLRP 4,CLRP5 for 667/800 FS B select
SHOR T CL RP5, NO SHORT CLRP 4 -- FSB 80 0
SHOR T CL RP4, NO SHORT CLRP 5 -- FSB 66 7
0216 Delete CLRP4,CLRP 5
CLKSATAREQ#20
CLK_DEBU G_PORT25,30
CLK_P CI_SIO29
CLK_PC I_TCG30
CLK_P CI_EC31
CLK_PCI_PCM25
CLK_P CI_ICH18
CLK_48M_ICH20
CLK_14M_ICH20
CLK_14M_SIO29
CLK_14M_KBC31
1= E nable S RC0 & 27MHz
1 = Over clock ing of CPU and SRC NOT allowed
R1245
10K_0402_5%
R1247
10K_0402_5%
@
+3VM_CK505
CLKREQ#_B7
12
12
4
1
C1165
10U_0805_10V4Z
2
R1690
10K_0402_5%
@
R1691
10K_0402_5%
4
R1693475_0402_1%
R1077 33_0402_1%
12
12
12
12
1
C1166
0.1U_0402_16V4Z
2
+1.25VM_CK505
12
12
12
12
12
12
R1108
10K_0402_5%
12
PCI2_TME
R1246
10K_0402_5%
@
12
03/02 change
R1692475_0402_1%
R109722_0402_5%
12
R111412_0402_5%
12
R114012_0402_5%
R111012_0402_5%
R114112_0402_5%
R111722_0402_5%
CLK_XTAL_IN
CLK_XTAL_OUT
R108733_0402_1%
R108833_0402_1%
R108933_0402_1%
+1.25VM_CK505
1
C1167
0.1U_0402_16V4Z
2
+1.25VM
+3VM_CK505
PCI_CLK1
PCI2_TME
PCI_CLK3
27_SEL
ITP_EN
FSA
FSB
FSC
3
1
C1168
0.1U_0402_16V4Z
2
1
C1169
0.1U_0402_16V4Z
2
1
C1170
0.1U_0402_16V4Z
2
1
C1171
0.1U_0402_16V4Z
2
Pla ce cl ose to U7
R1068 0_1206_5%
12
C1172
10U_0805_10V4Z
U7
2
VDD_PCI
9
VDD48
16
VDDPLL3
61
VDDREF
39
VDDSRC
55
VDDCPU
12
VDD96_IO
20
VDDPLL3_IO
26
VDDSRC_IO
36
VDDSRC_IO
49
VDDCPU_IO
1
PCI0/CR#_A
3
PCI1/CR#_B
4
PCI2/TME
5
PCI3
6
PCI4/27_Select
7
PCIF5/ITP_EN
60
X1
59
X2
10
USB_48MHZ/FSLA
57
FSLB/TEST MODE
62
REF0/FSLC/TEST_SEL
45
VDDSRC_IO
42
GNDSRC
8
GNDPCI
11
GND48
15
GND
19
GND
52
GNDCPU
23
GNDSRC
29
GNDSRC
58
GNDREF
* Int ernal Pull-U p Resi stor
** In ternal Pull- Down R esistor
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
layo ut n ote: D_H SYNC & D_VSY NC should b e routed to docking co nnector the n to VGA co nnector
TV-Out Connector
LUMA9,33
CRMA9,33
COMP9,33
12
12
33
la y o u t n
la y o u t n ote : T V-o ut si g na l s sho u ld b e r o ute d t o J P3 0 t h en to JP 1
la y o u t nl a y o ut n
44
R184
@
0315 add
150_0402_1%
150_0402_1%
ot e : TV - ou t s i gn a ls s h oul d b e r ou t ed to JP 3 0 t he n t o J P1
ot e : TV - ou t s i gn a ls s h oul d b e r ou t ed to JP 3 0 t he n t o J P1ot e : TV - ou t s i gn a ls s h oul d b e r ou t ed to JP 3 0 t he n t o J P1
@
R185
@
Cl
Cl ose to JP 1
os e t o J P1
ClCl
os e t o J P1o se to JP 1
12
R187
150_0402_1%
1
@
2
5.6P_0402_50V8D
C333
5.6P_0402_50V8D
1
2
C355
C354
@
0_0603_5%
R547
12
0_0603_5%
R548
12
0_0603_5%
R549
12
1
@
2
5.6P_0402_50V8D
Place close to JP1
DAN217_SC5 9
D3
@
DAN217 _SC59
1
2
3
@
D5
TV_LUMA
TV_CRMA
TV_COMP
DAN217_SC5 9
@
1
2
3
SUYIN_3 3007SR-07T1-C
+3VS
D1
1
2
3
JP1
1
2
3
4
5
6
7
conn@
+2.5VS+2.5VS
+2.5VS
12
DVI Transnitter
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/132006/07/26
Compal Secret Data
Deciphered Date
Title
Size Doc ument NumberRe v
2
Date:Sheetof
Compal Electronics, Inc.
LCD CONN.
LA -3 26 1P U MA
1755Tuesday, M arch 27, 2007
1
0.4
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