HP 1660c brochure

The HP 1660C/CS/CP-Series
Benchtop Logic Analyzers

Technical Data

Get to the root cause of
problems quickly.

Identifying the cause of problems in
embedded microprocessor system
designs can be difficult. The
HP 1660C/CS/CP-series benchtop
logic analyzers have the features to
help the design team troubleshoot
hardware and find software defects
quickly . Team members can verify
critical hardware timing relation­ships, view processor mnemonics,
make analog parametric measure­ments, or functionally test their digi­tal design with stimulus.

An optional LAN interface enables
software designers to capture a real­time microprocessor trace and time­correlate it to source code in C++ or
other high-level languages on a PC
or workstation. For time-correlation
of source code, order the HP B3740A
Software Analysis package.

Oscilloscope Key Specifications
and Characteristics

____________________________________

Model Number HP 1660CS, HP 1661CS,

HP 1662CS & HP 1663CS

_______________________________________
Channels 2

_______________________________________
Maximum Sample 1 GSa/s per channel
Rate

_______________________________________
Bandwidth dc to 250 MHz

(dc coupled)

_______________________________________
Rise Time 1.4 ns

_______________________________________
Vertical Resolution 8 bits

_______________________________________
Memory Depth per 8k samples
Channel

_______________________________________

Logic Analyzer Key Specifications and Characteristics

_______________________________________________________________________

HP Model Number 1660C/CS/CP 1661C/CS/CP 1662C/CS/CP 1663C/CS/CP 1664A

________________________________________________________________________________
State and Timing 136 102 68 34 34
Channels

________________________________________________________________________________
Timing Analysis Conventional: 250 MHz all channels, 500 MHz half channels

Transitional: 125 MHz all channels, 250 MHz half channels
Glitch: 125 MHz half channels

________________________________________________________________________________
State Analysis Speed 100 MHz, all channels 50 MHz

________________________________________________________________________________
State Clocks/Qualifiers 6 6 4 2 2

________________________________________________________________________________
Memory Depth 4K per channel, 8K in half-channel modes
per Channel

________________________________________________________________________________
LAN Port Standard for CP Model, Option 015 for C/CS model N/A

________________________________________________________________________________

Pattern Generator Key Specifications and Characteristics

________________________________________________________________________________

HP Model Number 1660CP, 1661CP, 1662CP, 1663CP

________________________________________________________________________________
Maximum Clock Speed 200 MHz 100 MHz 50 MHz

________________________________________________________________________________
Number of Data Channels 16 32 32

________________________________________________________________________________
Memory Depth, in vectors 258,048 258,048 258,048

________________________________________________________________________________
“IF” Command No No Yes

________________________________________________________________________________

The combination of 100-MHz state,
500-MHz timing, 2-channel 250-MHz
BW scope, or 32-channel
200 M Vector/sec pattern generator,
internal hard disk drive, and LAN
make the HP 1660C/CS/CP-series
benchtop logic analyzers especially
well suited to finding problems at
the integration stage of prototype
hardware and software.

[1]

• The internal hard disk drive provides
quick storage and retrieval of files.

[1]

• 3.5-inch high-density flexible disk
drive supports both DOS and LIF
formats.

• LAN interface enables access to the
logic analyzer files via FTP or NFS.
Use X11 windows and display the
logic analyzer user interface on a PC
or workstation.

[1]

• The HP 1660C/CS/CP-series operating
system includes System Performance
Analysis (SPA). SPA provides state

histograms, state overview , and time
interval analysis.

• The HP E2450A Symbolic Download
Utility is included with the
HP 1660C/CS/CP-series. This utility
provides the capability to extract
symbolic information from popular
object module formats.

• Store data as ASCII files and screen
images in TIFF, PCX, and EPS
(encapsulated PostScript™) formats.

• New graphical trigger macros make
trigger setup easier.

• Centronics, RS-232 and HP-IB com­munications ports make connecting
to other devices easier than ever. All
of these come standard on all
HP 1660C/CS/CP-series models.

• Standard DIN mouse and keyboard
connectors. A mouse ships with
every HP 1660C/CS/CP-series.

[1]

[1] Please refer to HP 1664A Product
Specifications and Characteristics on page 9.

PostScript™ is a trademark of Adobe
Systems Incorporated.

This literature was published years prior to the establishment of Agilent Technologies as a company independent from Hewlett-Packard
and describes products or services now available through Agilent. It may also refer to products/services no longer supported by Agilent.
We regret any inconvenience caused by obsolete information. For the latest information on Agilent’s test and measurement products go to:

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Or in the US, call Agilent Technologies at 1-800-452-4844 (8am–8pm EST)

Discontinued Product— Support Information Only

HP 1660C/CS/CP­Series General­Product Information

_________________________

Human Interface

_________________________

Front Panel A knob and keypads

make up the front-

panel human interface.
Keys include control,
menu, display naviga­tion, and alpha-numer­ic entry functions.

_________________________

Mouse A DIN mouse is

shipped as standard
equipment. It provides
full instrument control.
Knob functionality is
replicated by holding
down the right button
and moving the mouse
left or right.

[1]

_________________________

Keyboard The logic analyzer can

also be operated using

a DIN keyboard. Order
the HP Logic Analyzer
Keyboard Kit, model
number HP E2427B.

[1]

_________________________

Input/Output, Control,
and Printing

_________________________

I/O Ports All units ship with a

Centronics parallel
printer port, RS-232,
and HP-IB as standard
equipment.

[1]

_________________________

LAN Interface An Ethernet LAN inter-

face is available as

option 015. The LAN
interface comes with
both Ethertwist and
ThinLan connectors.
The LAN supports FTP
and PC/NFS connec­tion protocols. It also
works with X11 win­dows packages.

[1][2]

_________________________

Program- Each instrument is fully

mability programmable from a

computer via HP-IB
and RS-232 connec­tions. This feature is
standard on all models.

_________________________

HP Printer Printers which use the
Support HP Printer Control

Language (PCL) and

have a parallel
Centronics, RS-232 or
HP-IB interface are
supported:

HP DeskJet, LaserJet,

QuietJet, PaintJet, and
ThinkJet models

_________________________

_________________________

Alternate The Epson FX80, LX80
Printer and MX80 printers with
Supported an RS-232 or Centronics

interface are supported

in the Epson 8-bit
graphics mode.

_________________________

Hard Copy Screen images can be
Output printed in black and

white from all menus
using the

Print

field.
State or timing listings
can be also be printed
in full or part (starting
from center screen)
using the

Print All

selection.

_________________________

Mass Storage Files
and Software

_________________________

Updating the The operating system
Operating resides in Flash ROM
System and can be updated

from the flexible disk
drive or from the
internal hard disk
drive. The HP 1664A
boots from disk and
requires only a disk
change to update the
operating system.

_________________________

Mass Storage Supported by an inter-

nal hard disk drive and
by a 1.44 Mbyte, 3.5­inch flexible disk drive.
Supports DOS and LIF
formats.

[1]

_________________________

Screen Image An image file of any
Files display screencan be

stored to disk via the
display's

Print

field.
Black & white TIFF,
Grayscale TIFF, PCX,
Encapsulated
PostScript™ (EPS), and
gray-scale TIFF file for­mats are available.

_________________________

ASCII Data State or timing listings
Files can be stored as ASCII

files on a disk via the
display's

Print

field.
These files are equiva­lent in character width
and line length to hard­copy listings printed via
the

Print All

selection.

_________________________

Configuration Logic analyzer and
and Data Files oscilloscope files

that include configura-

tion and data informa­tion (if present) are

encoded in a binary
format. They can be
stored to or loaded
from the hard disk drive
or a flexible disk.

[1]

_________________________

Recording of Binary format
Acquisition configuration/data files
and Storage are stored with the
Times time of acquisition and

the time of storage for
all models except the
HP 1664A, which does
not have a real-time
clock.

_________________________

Acquisition Arming

_________________________

Initiation Arming is started by

Run, Group Run,

or the

Port In BNC.

_________________________

Cross Arming Analyzer machines

and the oscilloscope
can cross-arm each
other.

[1]

_________________________

Output An output signal is

provided at the Port
Out BNC.

_________________________

Port In/Out

_________________________

PORT IN Port In is a standard
Signal and BNC connection.
Connection The input operates at

TTL logic signal levels.
Rising edges are valid
input signals.

_________________________

PORT OUT Port Out is a standard
Signal and BNC connection
Connection with TTL logic

signal levels. A rising
edge is asserted as a
valid output.

_________________________

Skew Adjustment
and Arming Times

_________________________

Skew Correction factors for

Adjustment nominal skew between

displayed timing and
oscilloscope signals
are built into the oper­ating system.
Additional correction
for unit-by-unit varia­tion can be made using
the

Skew

field. An
entered skew value
affects the next (not
the present) acquisition
display.

_________________________

2

[1] Please refer to HP 1664A Product Specifications

and Characteristics on page 9.

[2] LAN interface is standard for the HP 1660CP-series,

optional for the HP 1660C/CS-series.

_________________________

PORT IN 15 ns typical delay
Arms Logic from signal input to a

Analyzer

[3]

don't care

logic

analyzer trigger .

_________________________

PORT IN 40 ns typical delay
Arms from signal input to an

Oscilloscope

immediate

oscilloscope
trigger; not available
when oscilloscope is in
time-qualified pattern
triggering mode.

_________________________

Logic 120 ns typical delay
Analyzer from logic analyzer
Arms PORT trigger to signal
OUT

[3]

output.

_________________________

Oscilloscope 60 ns typical delay from
Arms PORT oscilloscope trigger to
OUT signal output.

_________________________
Operating Environment

_________________________

Power 115 Vac or 230 Vac,

–22% to +10%, single
phase, 48-66 Hz, 320 VA
max

_________________________

Temperature Instrument, 0° to 50°C

(+32°to 122°F). Disk
media, 10°to 40°C
(+50°to 104°F). Probes
and cables, 0°to 65°C
(+32°to 149°F)

_________________________

Humidity Instrument, up to 95%,

relative humidity at
+40°C (+140°F). Disk
media and hard drive,
8% to 85% relative
humidity.

_________________________

Altitude To 3,048 m (10,000 ft)

[1]

_________________________

Vibration: Random vibrations
Operating 5–500 Hz,

10 minute per axis,
~ 0.3 g (rms).

_________________________

Vibration: Random vibrations
Non Operating5–500 Hz,10 minutes per

axis,~ 2.41 g (rms); and
swept sine resonant
search, 5–500 Hz,

0.75 g (0-peak),
5 minute resonant dwell
@ 4 resonances per
axis.

_________________________

_________________________
Physical Factors

_________________________

Weight 28.6 lbs. (13 kg)

[1]

_________________________

Dimensions See figure 1

_________________________

Safety IEC 348/ HD 401,

UL 1244, and
CSA Standard C22.2
No. 231 (series M-89)

_________________________

EMC

CISPR 11:1990/EN 55011 (1991):

Group 1 Class A

IEC 801-2:1991/EN 50082-1 (1992):

4kV CD, 8 kV AD
IEC 801-3:1984/EN 50082-1 (1992): 3 V/m
IEC 801-4:1988/EN 50082-1 (1992): 1kV

_________________________

_________________________
Logic Analyzer Probes

_________________________

Input 100 kΩ ±2%
Resistance

_________________________

Input approx. 8 pF
Capacitance (see figure 2)

_________________________

Figure 2

_________________________

Minimum 500 mV peak-to-peak
Input Voltage
Swing

_________________________

Minimum 250 mV or 30% of input
Input amplitude, whichever is
Overdrive greater

_________________________

Threshold –6.0 V to +6.0 V in 50-mV
Range increments

_________________________

Threshold Threshold levels may be
Setting defined for pods

(17-channel groups) on
an individual basis

_________________________

Threshold ± (100 mV +3% of
Accuracy* threshold setting)

_________________________

Input ± 10 V about the
Dynamic threshold
Range

_________________________

Maximum ± 40 V peak
Input Voltage

_________________________

+5 V 1/3 amp maximum

Accessory per pod

Current

_________________________

Channel Each group of 34
Assignment channels (a pod pair)

can be assigned to
Analyzer 1, Analyzer 2
or remain unassigned.

_________________________

HP 1660C/CS/CP-Series
Logic Analyzer Specifications
and Characteristics

[1] Please refer to HP 1664A product specifications

and characteristics on page 9.

[3] Time may vary depending upon the mode of logic

analyzer operation.

* Warranted specification.

3

17.3 inches
(440 mm)

8.1 in.
(205 mm)

13.0 in.
(330 mm)

14.5 in.
(367 mm)

Figure 1

RT= 250Ω

High Frequency Model for Probe Inputs

RIN= 100kΩCTG= 1 pF Z0=

150Ω

C

COMP

= 7.5 pF

Weight 28.6 lbs (13 kg)

______________________________

State Analysis

_________________________

Maximum 100 MHz all models
State except HP 1664A,
Speed* which is 50 MHz

_________________________

Channel HP 1660C, CS, CP 136/68
Count

[4]

HP 1661C, CS, CP 102/51
HP 1662C, CS, CP 68/34
HP 1663C, CS, CP 34/17
HP 1664A 34/17

_________________________

Memory 4096/8192 samples
Depth per
Channel

[4]

_________________________

State Clocks

HP 1660C, CS, CP 6 clocks
HP 1661C, CS, CP 6 clocks
HP 1662C, CS, CP 4 clocks
HP 1663C, CS, CP 2 clocks
HP 1664A 2 clocks

Clocks can be used by
either one or two state
analyzers at any time,
except for the 1663C,
1663CS, 1663CP and
1664A models, which
can have only one
state or timing analyzer .
Clock edges can be
ORed together and
operate in single
phase, two-phase
demultiplexing, or two­phase mixed mode.
Clock edge is
selectable as positive,
negative, or both edges
for each clock.

_________________________

State Clock The high or low of up to
Qualifier 4 of the 6 clocks can be

ANDed or ORed with
the clock specification.

_________________________

Setup/Hold*

[5]

one clock, 3.5/0 ns to 0/3.5 ns
one edge (in 0.5 ns increments)

one clock, 4.0/0 ns to 0/4.0 ns
both edges (in 0.5 ns increments)

multi-clock, 4.5/0 ns to 0/4.5 ns
multi-edge (in 0.5 ns increments)

_________________________

Minimum 3.5 ns
State Clock
Pulse Width*

[5]

_________________________

Minimum 10.0 ns
Master to
Master
Clock Time*

[5]

_________________________

_________________________

Minimum 10.0 ns
Slave to
Slave
Clock Time

[5]

_________________________

Minimum 0.0 ns
Master to
Slave
Clock Time

[5]

_________________________

Minimum 4.0 ns
Slave to Master
Clock Time

[5]

_________________________

Clock 4.0/0 ns (fixed)
Qualifiers
Setup/Hold

[5]

_________________________

State Counts the number of
T agging

[6]

qualified states
between each stored
state. Measurement
can be shown relative
to the previous state or
relative to trigger . Max.
count is 4.29 ×109.

State Tag 0 to 4.29 × 10

9

Count
State Tag 1 count

Resolution

_________________________

Time Measures the time
T agging

[6]

between stored states,
relative to either the
previous state or to the
trigger . Max. time
between states is

34.4 sec. Min. time
between states is 8 ns.

Time Tag 8 ns to 34.4 seconds
Value ±(8 ns + 0.01% of time

tag value)

Time Tag 8 ns or 0.1%
Resolution (whichever is greater)

_________________________
Timing Analysis

_________________________

Conventional Data stored at selected
Timing sample rate across all

timing channels.

Maximum 250 MHz / 500 MHz
Timing
Speed

[4]

Channel HP 1660C, CS, CP 136/68
Count

[4]

HP 1661C, CS, CP102/51
HP 1662C, CS, CP 68/34
HP 1663C, CS, CP 34/17
HP 1664A 34/17

Sample 4 ns/2 ns minimum,
Period

[4]

8.38 ms maximum

Memory 4096/8192 samples
Depth per
Channel

[4]

Time Covered Sample period ×
by Data memory depth

16.3 µs min,

34.4 sec/68.6 sec max

_________________________

Transitional Sample is stored in
Timing acquisition memory

only when the data
changes. A time tag
stored with each
sample allows recon­struction of waveform
display. Time covered
by a full memory
acquisition varies with
the number of pattern
changes in the data.

Maximum 125 MHz/250 MHz
Timing
Speed

[4]

Channel HP 1660C, CS, CP, 136/68
Count

[4]

HP 1661C,CS, CP102/51
HP 1662C,CS, CP 68/34
HP 1663C,CS, CP 34/17
HP 1664A 34/17

Sample 8 ns/4 ns
Period

[4]

Time Covered 16.3 µs minimum,
by Data

[4]

9.7 hrs./6.5 hrs.
maximum

Maximum 34.4 s
Time
Between
Transitions

Number of 1023-2047/682-4094
Captured Depending on input
T ransitions

[4]

signals

_________________________

4

[4] Full Channel /Half Channel Modes
[5] Specified for an input signal VH= – 0.9V , VL = – 1.7V,

slew rate = 1V/ns, and threshold = –1.3V

[6] Time or-state-tagging (Count Time or Count State)

is available in the full-channel state mode. There is
no speed penalty for tag use. Memory is halved
when time or state tags are used unless a pod pair
(34-channel group) remains unassigned in the
Configuration menu.

* Warranted specification.