HP 13255 User Manual
BP
13255
MEMORY
Manual
Part
DATA
TECHNICAL
CONTROLLER
10.
PRINTED
JUN-23-81
MODULE
13255-912q9
1/.2S.;l
TERMINAL
INFORMATION
Printed
in
U.S.A.
HEWLETT
ifi
PACKARD
13255
Processor
(8085A-2)
Module
13255-91249/02
REV
FEB-14-82
1.0
2.0
INTRODUCTION.
The
processor
for
the
2747F
processor
trom
the
terminal
capability
OPERATING
A summary
contained
to
the
memory
and
data
ot
PARAMETERS.
of
operating
in
tables
(8085A-2)
terminal.
external
pertorms
bus
down
loading
1.0
Table
module
It
also
keyboard.
I/O
(backplane
code
parameters
through
1.0
Physical
functions
contains
The
operations
ass.bly).
in
a
RAM
tor
the
6.7
Parameter.
as
the
the
hardware
processor
on
other
!be
based
Processor
2647F.
..
in
controlling
to
intertace
retches
.adul.s
8085A-2
instructions
attached
lIOdule
(8085A-2) Module
has
unit
the
to
the
is
================================================================================
1
I
PART
NUMBER
1
1
NOMENCLATURE
Size
(L
x W x
1 +/-0.100
D)
Inche.
Weight 1
1 (Pounds) 1
/==============1==============================1======================1=========1
1 I 1 1 1
I 02640-60249 I
1 I I 1 1
1 I I 1 1
PROCESSOR
(8085A-2)
I 12.5 x 4.0 x 0.5 1 0·5 1
1 I 1 1 1
1==============================================================================1
I 1
1
1 I
NUMBER
OF
BACKPLANE
SLOTS
REQUIRED:
1 I
================================================================================
HP
13255
The
information
without
HEWLETl'-PACKARD
MATERIAL,
MERCHANTABILITY
shall
consequential
or
use
notice.
INCLUDING,
not
be
of
this
contained
MAKES
AND
liable
damages
material.
MEMORY
Manual
10
WARRANTY
BUT
lOT
FITNESS
for
errors
in
connection
CONTROLLER
Part
10.
PRIM'l'ED
MODULE
13255-912q9
JUH-23-81
IOTlCE
in
this
document
OF
AMY
LIMITED
FOR A PARTICULAR
contained
TO
with
THE
1/:IS-.;2
is
subject
KIND
herein
the
WITH
IMPLIED
PURPOSE.
furnishing,
to
REGARD
WARRANTIES
Hewlett-Packard
or
tor
change
TO
THIS
OF
incidental
performance,
or
This
photocopied
Packard
document
copyright.
Company.
NOTE:
contains
All
or
Copyright
This
series
rights
reproduced
document
Technical
proprietary
are
reserved.
without
c 1982 by
is
part
Information
information
No
part
the
prior
HEWLETT-PACKARD
of
the
2647F
Package
which
of
written
DATA
(HP
is
protected
this
COMPANY
document
consent
TERMINAL
13255).
may
of
Hewlett-
product
by
be
13255
Processor
(8085A-2) Module
1.0
INTRODUCTION.
13255-91249/02
REV
FEB-14-82
The
processor
(8085A-2)
aodule
functions
as
the
..
in
controllin,
unit
for
the
2747F
terminal.
It
also
contains
the
hardware
to
interface
the
processor
to
the
external
keyboard.
The
processor
f.tch
••
in.truction.
trom
memory
and
performs
I/O
operation.
on
other
.odul..
attached
to
the
terllinal
data
bus
(backplane
ass.bly).
'l'b.
8085A-2 lIOdule
has
the
capability
ot
down
loading
code
in
a
RAM
based
2647F.
2.0
OPERATING
PARAMETERS.
A
summary
of
operating
parameters
tor
the
Proces.or
(8085A-2) Modul.
i.
contained
in
tables
1.0
through
6.7
Table
1.0
Physical
Parameters
-===============================================================================
PART
1 I
Size
(L
x W x D) I Weisht
NUMBER
1
NOMENCLATURE
1
+/-0.100
Inches
I (Pounds)
==============1==============================1======================1=========
1 1 I
02640-60249 I
PROCESSOR
(8085A-2) I
12.5 x 4.0 x 0.5
I
0.5
I I I
I I I
I 1 1
==============================================================================
NUMBER
OF
BACKPLANE
SLOTS
REQUIRED:
1
================================================================================
13255
13255-91252/03
Rev JUN-23-81
Memory
Controller
Table
2.0
Reliability
and
Environmental
Information
===============================================================================-
1
1
Environmental:
( X )
HP
Class
B
()
Other:
1
1
I
Restrictions:
Type
tested
at
product
level
,
1
1==============================================================================
1
1
Failure
Rate:
4.774
(percent
per
1000
hours)
,
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Table
3.0
Power
Supply
and
Clock
Requirements
- Measured
(+/-
5%
Unless
Otherwise
Specified)
--------------------------------------------------------------------------------
-------------------------------------- ----------------------------------------
+5
Volt
Supply
+12
Volt
Supply
-12
Volt
Supply
-42
Volt
Supply
@
0.5
A
mA
NOT
APPLICABLE
NOT
APPLICABLE
NOT
APPLICABLE
-------------------------------------- ---------------------------------------
-------------------------------------- ---------------------------------------
115
volts
AC
220
volts
AC
A A
NOT
APPLICABLE
NOT
APPLICABLE
------------------------------------------------------------------------------
------------------------------------------------------------------------------
Clock
Frequency:
4.915
MHz
================================================================================
Table
4.0
Jumper
Definition
================================================================================
PCA
Function
I
I
Designation
I I
1=============1================================================================1
1 I I
I 1 I
1
Wl
1
RAM/ROM
Based
Terminal
(see
section
3.8)
I
I I ,
I I I
================================================================================
13255
Memory
Controller
Table
5.0
Connector
Information
13255-91252/04
Rev
JUN-23-81
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Connector
I
Signal
Signal
and
Pin
No.
I
Name
Description
------------- --------------
-------------------------------------------------
-------------
--------------
-------------------------------------------------
P1,
Pin
1
+5V
+5
Volt
Power
Supply
-2
GND
Ground
Common
Return
(Power and
Signal)
-3
SYSCLK
4.915
MHz
System
Clock
-4
Not Used
-5
ADDRO
Negative
True,
Address
Bit
0
-6
ADDR1
Negative
True,
Address
Bit
1
-1
ADDR2
Negative
True,
Address
Bit
2
-8
ADDR3
Negative
True,
Address
Bit
3
-9
ADDR4
Negative
True,
Address
Bit
4
-10
ADDR5
Negative
True,
Address
Bit
5
-11
ADDR6
Negative
True,
Address
Bit
6
-12
ADDR1
Negative
True,
Address
Bit
1
-13
ADDRa
Negative
True,
Address
Bit
8
-14
ADDR9
Negative
True,
Address
Bit
9
-15
ADDR10
Negative
True,
Address
Bit
10
-16
ADDR11
Negative
True,
Address
Bit
11
-11
ADDR12
Negative
True,
Address
Bit
12
-18
ADDR13
Negative
True,
Address
Bit
13
-19
ADDR14
Negative
True,
Address
Bit
14
-20
ADDR15
Negative
True,
Address
Bit
15
-21
10
Negative
True,
Input
Output/Memory
-22
GND
Ground
Common
Return
(Power and
Signal)
==============-=================================================================
13255
Memory
Controller
Table
5.0
Connector
Information
(cont)
13255-91252/05
Rev JUN-23-81
-----------------------------------------------.---------------------------------
-----------------------------
--------------------------------------------------
Connector
I
and
Pin
No.1
-------------
-------------
P1,
Pin
A
-B
-C
-D
-E
-F
-H
-J
-K
-L
-M
-N
-p
-R
-S
-T
-u
-v
-W
-x
-y
-z
Signal
Name
--------------
--------------
GND
PON
BUS
0
BUS
1
BUS
2
BUS
3
BUS
4
BUS
5
BUS
6
BUS
7
WRITE
WAIT
ADDR16
ADDR17
ADDR18
REQ
Signal
Description
-------------------------------------------------
-------------------------------------------------
Ground
Common
Return
(Power and
Signal)
Not Used
Not Used
Positive
True,
System Power
On
Negative
True,
Data
Bus
Bit
0
Negative
True,
Data
Bus
Bit
1
Negative
True,
Data
Bus
Bit
2
Negative
True,
Data
Bus
Bit
3
Negative
True,
Data
Bus
Bit
4
Negative
True,
Data
Bus
Bit
5
Negative
True,
Data
Bus
Bit
6
Negative
True,
Data
Bus
Bit
7
Negative
True,
Write/Read
Type
Cycle
Not Used
Negative
True,
Assert
Wait
State
Not Used
Not Used
Positive
True,
Address
Bit
16
Positive
True,
Address
Bit
17
Positive
True,
Address
Bit
18
Negative
True,
Request
(Bus
Data
Valid)
Not Used
-------------------------------------------------------------------------------
--------------------------------------------------------------------------------
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