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Manual
DATA
Part
TERMINAL
TECHNICAL
No.
13220-91087
REVISED
JAN···
()
4····B2
INFORMATION
Printed
in
HEWLETT~PACKARD
U.S.A.
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Part
No.
13220-91087
I~EVISED
JAN···
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NOTICE
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WARI~ANTY
NOT
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The
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1
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Failure
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===~==========~===~========~===================================================
Connector
1
and P in
No. 1
1==============1================
J1
Pin
···1
....
2
....
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....
4
·
..
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....
8
·-9
....
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0 I
....
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1
1
I
PRINTER
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1
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WRITE
1
1
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1
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DATA 2
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DATA
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DATA
I
I
DATA
I
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DATA
I
DATA
4.0
Signal
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ON/FAIL
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1
:5
4
S
6
7
Connector
InforMation
Signal
Description
=============================================\
**
PRINTER
Negative
Negative
Negative
Negative
LSB -Negative
MSB -Negative
**
True,
True,Power
True,
True,
Printer
Write
Fun~tion
True,
True,
Strobe
On/Failing
signal
select
Data
Data
bit
1
I
I
-14
·
..
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....
1·7
-1t3
-·19
"-20
....
21
·-22
..
-;~3
-24
"-25
-26
GND
PINT
AO
+SV
+SV
+SV
+SV
GND
GND
GND
GNU
GND
Set
printer
Negative
Negative
Vcc
Power
Power
Retul'n
contrast
True,
True,
Printer
Function
Interrupt
select
bit
0
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1.
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Pl'OC(~SS)Ol'
Module
13220-91.08'7/0S
Rev
JAN-()4-B2
Table
===============================================================================~
I
Connector
I
and
Pin
No.
I
\==============1================
I
J;:.~
I 1
I
\
Pin
\
\
I
I
I
I
\
I
I
I
........................................ -............
I
J~3
I
I
I
\
\
I --4
\
Pin
\
I I
I
\
I
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, _
.......... -........ -...........
\
J4
\
I
I
I
I
\
I
I
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Pin
I
-·1
-.~:~
-3
-4
-S
-6
-'7
-8
-9
-10
-1
-2
-3
-5
-6
....
'J
-8
....
1
....
2
·
..
·3
...
-4
·
..
·s
·
..
·6
....
·7
-·B
+5V
+SV
+12V
GND
GND
.. _ ...
_.
PWR
-1.2V
BATTERY
1
BATRET
'I
._.-
....
'''' .-..... -..................... -•• -.-.-
1 I
.....
__
HLFBRT
RETURN
........ _ ...........
FUL.L.BI~
RETURN
RETURN
iJ'f~:'ifi)rf
I
HORDR
-.
:1
.......... -............ -............... -............. -•.
\(EYO
KEYj
KEY2
KEY:~
I<EY4
KEYS
KEY6
Signal
NaMe
__
._
... _ ..
__
ON/FAIL
..
_.
__
....
__
. I
_._._.
.
4.0
.......... _ ......
T \
Connector
_.
-
InforMation
(Cont'd)
Signal
Description
==============================================
**
+SV
N/C
+5V
+1;':'~V
R€~t
Ret
Negative
-12V
Positive
I
Negative
I
..
-.--.-...... -.-
**
I
Negative
I
N/C
I
Return
I
Negative
I
Return
\
Return
I
Negative
I
Horizontal
**
Key
KE~y
Key
Key
Key
N/C
K(~~y
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POWER
Power
Power
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urn
SWEEP
KEYBOARD
Data
Data
Data
Data
Data
Dc:l
Data
SUPPL.Y
Power
01'
for'
True,
Power
Battery
Battery
....... -.............
_.-.-
**
true,
for
true,
for
for
True,
(LSB)
ta
(MSS)
**
Power
P
ow(~r
Power
........... , ..... -..........
Half
half
bright
Full
Video
Drive
Vertical
Drive
**
On/Failing
TerMinal
TerMinal
-.-.-
.. -....
Bright
twisted
Bright
twisted
signals
'''' .-...
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Video
Video
pair
Drive
.... _ .... -..... -.....
pair
_._.-
- -' -
..
_.-
I
·
..
·9
.... 1 ()
····1.1
....
12
================================~===============================================
KEYACT
GNI>
BELL..
+Sv
Key
Active
Pow(~r
Bell
+5v
Line
Power
Return
(Status
of
key
selected)
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j.
~5;.:!.2
0
Pr'oc(::~ssor'
Module
1
~5220'-91
Rev
08'7/06
JAN-()4'-B2
Table
~===============================================================================
Connector
and
pin
No. I
4.0
Signal
NaM€~
Connector
I
InforMation
(Cont'd)
Signal
Des;cr'iption
==============1================1==============================================
JS
Pin
....
j.
-.;~
"'~3
....
4
~~S
"~6
..
~'J
..
··8
..
~9
..
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·
..
·1 i
....
12
"~13
·
..
·14
....
1 S
-··16
....
j.
'J
....
18
·
..
·j.9
....
;?
0
--21
.. -;;!;,?
....
;:?~~
"-;?4
"-25
....
26
-~27
..
··;,?8
..
-29
-~3
()
"-31
"-3;.~
..
··33
....
~34
+SV
+SV
GN!)
GNl>
GND
DeDi
RD
(,(:'
.,,,:>
DM
SG
OCR1
+1;~V
--1;:!V
SD
RS
TR
GND
SHIEL.l)
DATA
COMM
**
N/C
+SV
Pod P
+SV
Pod
P()w(~r
P
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P()w(~r
Rat(:~
Nit
R
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Nit
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Di:l
ta
N/C
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Si~}na
NIt
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Rinq
+12V
'-1~~\)
Tr';HlSMl.
r~eqllest
Ready
Nit
N/C
NIt
N/C
N/C
N/C
Nit
N/C
Return
Shi(-.~ld
N/C
ow€~r
Power
R(~tul'n
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urn
Return
S~~lect
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V
(·~d
To
Send
S(?t
Rei:ld
Gr' 0 und
1
Ind:i.cator
Pod
Power
Pod
Power
t
t(~d
To
(20)
Ground
**
(23)
y
Data
Send
(3)
(5)
(6)
(7)
(~~2
(4)
( 1 )
)
(2)
(n)
denotes
the
RS-232
pin
nUMber
================================================================================
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1
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Pl'
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10'7
3.0
FUNCTIONAL
Refer
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parts
the
and
CONTROL.
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diagraMs
list
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lID,
AND
Clock
A
25.7715
video
74LS244
then
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clock
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shaped
for
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The
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tion
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It
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bus
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functions
also
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to
responds
when
to
DESCRIPTION
bl()ck
diagraM
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(fig.
MeMory,
I/O
MHz
10)
of
the
and
SECTION
crystal
frequency.
to
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seven
by
Q4
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the
ZaOA,
clock
datacoMM
Microprocessor
of
the
read
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interrupt
signal,
located
three
video
is
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by
its
associated
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chip
processor
write
two
externally
interrupt
service
NBUSREQ,
(fig.
4-8),
Major
c()ntrol.
attached
DRCX,
the
748163
has
divided
(U613)
perforMS
data
1),
scheMatic
COMponent
in
the
appendix.
sections
to
is
buffered
buffered
(Ub11)
circuitry
a
zero
by
uses
to
the
peA.
frOM
generated
current
routine.
allowing
location
of
the
by
dot
level
two
to
produce
Major
It
provides
and
to
execution
the
diagraMs
the
CRTC
the
rate
to
produce
to
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produce
baud
control
both
interrupts,
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CRTC
diagraM
The
following
Processor
which
CRTC
clock.
produce
0.4SV
a
rates.
and
addresses
MeMory
and
ZBOA
also
control
(figs.
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peA)
oscillates
and
again
This
3.6816
MHz,
a
SYMMetrical
and a one
1.8408
data
and
and
I/O
NNMI
cause
the
responds
of
the
2,3),
9)
and
describes
control
at
the
by
clock
which
level>
MHz
clock
Manipula-
control
ports.
and
NINT,
ZaOA
to
systeM
a
is
to
a
At
power
prograM
initializes
non-volatile
an
error
indicate
enters
a
por'ts.
Three
frOM
MeMory
abled
74LS244's
the
into
during
instructi()n
in
an
instruction
signal
was
respond
frOM
full
be
the
latch
th~:~
address
speed.
used
ZaOA
U610
ZBOA.,
up
MeMory
variables
is
detected
the
Major
Z80A.
six
fetch
used
within
by
installing
to
wait
and
(or
reset)
beginning
at
and
MeM()ry
failing
10()P
(CMOS)
a
series
ROM
responding
(U4'7,U57,U511)
The 1 of a decoder,
blocks,
a MeMory
by
read
the
each
NMl
fetch
to
provide
the
required
or
300
ns
frOM
[PROMs
or
ROMs
JUMper
one
cycle
ass()ciated
the
ZaOA
address
devices
and
of
or
RAM.
BK
by
the
signal.
is
less
an
early
tiMe.
enable
with
l()nger
gating
begins
OOOOH.
according
perforMS
beeps
After
to
inputs
buffer
bytes
TNRD
than
enable
are
450
WS
and
during
provides
executing
A
to
a
self
are
issued
inintialization
frOM
the
U76,
long.
and
that
ROMs
ns
reMoving
is
TNMREQ
Since
for
of
with
required
access
instructi()n
the
routine
inforMation
test
the
of
to
the
keyboard
address
used
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to
addressed
signals
the
tiMe
a
MeM()ry
the
ROM
access
t()
run
tiMes
JUMper
fetches.
required
instructions
is
executed
contained
ROM
and
keyboard
the
and
and
control
separate
ROM
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to
read
read,
allowing
tiMes
the
frOM
W6,
address
which
wait
frOM
which
RAM.
which
prograM
datacoMM
lines
prograM
is
en-
during
the
data
the
it
of
350
systeM
causes
The
quad
signal
in
If
an
NM1
to
ns
at
May
to
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13220
Processor
3.1.3
Module
I/O
Ports
CMUS
The
Z80A
I/O
addresses
accuMulator
used
to
configuration
respond
each
S
volts
Q3,
before
beCOMe
CMOS
May
be
standard
CMOS
within
tiMe
is
Makes
the
defined
contents.
replaced
read/COMpleMent/write
error
DATACOMM
is
capable
contents
access
data
the
CMOS
always
sure
l80A
since
froM
the
that
buses
at
If
by
the
of
the
appear
locations
is
stored.
I/O
cycle
RAM
is
on
t~e
during
power
power
an
HM7611
prOM
addressing
ZaOA
on
in
accessed.
CMOS
a
beCOMe
on.
on
configuration
PROM
cannot
2S6
appear
bits
the
Since
on
A8-A1S.
nonvolatile
the
tiMe a wait
Diodes
supply
power
pin.
off
undefined
During
(however
test
be
for
written).
different
address
CMOS
state
the
and
power
is
it
the
CMOS
bits
I/O
addresses
CMOS
RAM
is
is
generated
CR6-CR8
EMMitter
CMOS
is
reMains
off
the
to
be
fixed,
Must
be
self
13220-91087/08
Rev
input/output
AO-A7
RAM,
not
ensure
U73,
fast
that
follower
always
so
until
battery
the
realized
test
would
JAN-04-82
ports.
and
0-7FH
the
are
where
enough
(by
to
U6l0)
around
Circuit,
disabled
buses
Maintains
COMS
that
RAM
the
show
a
The
parallel
functions
laOA
selecting
unique
the
decoder.
The
therefore
status
USi4,
levels
(SD),
driver
(DM),
The
to-point
SY6SS1
to
required
as
four
the
tiMing
rising
The
status
are
signals
and
receiver,
(+-12V)
terMinal
1 (OCD1).
optional
datacoMM
environMent.
siMultaneously
tiMe
each
110
and
by
intervals
character
baud).
the
the
SY65S1.
detection
selectable
and
detected
overrun)
is
read
reception
to
when a
rates
SY6SS1.
Asynchronous
serial
conversion,
for
read
only
read/write
of
the
edge
of
addresses
inputs
forced
are
routed
U614,
and
ready
Received
control
subsysteM
(full-duplex)
(asynchronous).
is
fraMed
The
addition
of
The
(in
the
datacoMM
by
the
SY6SS1
the
ZaOA
character
are
set
serial
and
function.
6500
SELDC
of
of
the
to
their
vice
(TR),
receiver
operates
Characters
by a
of
fraMing
parity
by
Means
by
COMMunications
four
error
data
write
detection
COMMunication.
only
This
series
which
the
SY6SSl
devices.
SY6SS1
is
(U613)
produce
active
through
are
versa.
signals
~sed
request
another
to
TranSMitted
are:
1
(OCR1),
in
an
convert
to
asynChronous,
May
with
start
the
bits
(for
character
To
bit
fraMing
for
error
achieve
configuration
which
reports
of a status
is
received.
the
ZaOA
in
Interface
ports
is
done
The
inverted
are
undesirable
low
states
port.
frOM
send
(RS)
receive
and
clea~
be
tranSMitted
flow
hardware
and a stop
bits
the
for
received
detection)
Menu)
errors
register
The
an
internal
Adapter
and
baud
It
with
to
SY6551
frOM
AO-A7H.
while
RS-232
TTL
signals
and
d~ta
to
full-duplex,
occurring
bit
tranSMitted
characters
of
and
(parity,
in
data
reqister
perforMS
rate
generation
appears
address
COMpensate
is
selected
U24,
the
results
the
line
levels
are:
optional
(RD),
send
(eS).
and
over
synchronization
(2
stop
characters
the
character
is
also
fraMing,
the
SY6SS1
tranSMission
within
the
to
the
bit
TA2
for
the
1
of
and
necessary
driver,
to
RS-232
send
data
control
data
Mode
point-
received
randOM
bits
are
done
generated
and
which
and
the
by
8
at
is
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13220
Processor
Module
13220-91087/09
Rev
JAN-04-82
Rates
9600
The
lines
provide
are
selectable
baud.
datacoMM
to
connect
direct
power-on
terMinal
(esc
f)
is
the
disconnect
by
DM
which
displayed
host
to
when
halt
tranSMission
configuration).
strap
the
self
status
Upon
with
ModeM
test
lines
receipt
interrupt
the
datacoMM
clearing
character
for
delete
which
character
the
ready.
the
on
the
active
its
rate
to
detect
are
signal
interrupt
the
and
errors
status
the
hardware
TR
and
TR
line
ModeM.
causes
bOttoM
allows
The
default
for
active
of
(NINT)
interrupt,
places
to
(in
inputs
terMinal
Upon
is
the
(the
state
state
dual
the
a
character
it
(parity,
be
placed
the
datacoMM
and
outputs
to a host
handshaking
RS
lines
receipt
brought
The
presence
indicator
center
the
of
terMinal
terMinal
of
OCDl
being
speed
ModeMS. OCRl
presence
high
(+12V).
frOM
to
the
lBOA.
service
routine
and
into
the
fraMing
in
configuration
provide
COMputer
between
are
activated
of a ModeM
inactive
of a ModeM
"LED"
the
display.
to
tranSMit
May
ignore
is
controlled
low
of
the
(inactive).
loopback
datacoMM
This
which
if
no
errors
datacoMM
or
the
buffer.
the
disconnect
for
(an
causes
reads
buffer
overrun)
Menu) frOM
the
via
terMinal
to
indicate
.about
connection
asterisk
The
CS
data
CS
depending
by a configuration
is
Monitored
test
the
SY6SS1
the
the
are
present,
in
are
necessary
a ModeM,
and
escape
two
seconds
is
'*')
signal
and
goes
on
This
line
in
hood.
generates
ZaOA
to
SY6S51
RAM.
present
110
control
or
host.
that
the
sequence
detected
to
frOM
the
inactive
datacoMM
selects
datacoMM
All
ModeM
branch
status,
inputs
th~
Characters
cause
to
to
At
to
be
an
to
a
Teus
The
PORTS
reMaining
biderectional
loading.
enabled
U25
port
by
th~
(colUMn
More
(scan
for
forMS
returns
keyboard/display
address)
frOM
line
keystatus
they
for
range
are
each
of
I/O
bus
The
signal
all
the
keystatus
the
the
eRTC
count)
shift
later
of
read.
the
keyboard
ports
driver,
I/O
accesses
status
are
scan
frOM
register
first
addresses.
are
TNRD
port
of 8 keys
port
supplied
line
the
(a
The
colUMn
sixteen
buffered
U37.
selects
except
by U26
outputs
CRTC
high
display
This
the
located
at
(U26).
change,
bit
address
to
was
direction
CMOS
RAM
at
a
tiMe,
Four
(located
(row
keystates
indicating
is
rows
the
ZaOA
done
and
address
which
bits
at
address).
key
increMented
thereby
data
because
of
the
driver
datacOMM.
80H.
keys
of
the
address
As
the
are
clocked
active)
(during
scanning
bus
of
The
are
key
B8H)
row
by
the
data
bus
which
keystatus
deterMined
address
and
three
address
into
frOM
the
which
an NMI)
the
entire
is
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the
n
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hap
the
I«~~
y
enabled
blinking
sync
(~d
b Y
boa
l'
d / d i
and
latches
characters.
pulses
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a n
~;
P
:I.
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port
down
cI
i
the
also
t~:;
a
POl"
t d
signal
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soc i ate
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t (;H' Min
frequency.
d
c:
E~
which
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counter
i
l'
cui
w h e t h
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r
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han
c
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the
L3220-91
Rev
which
bell
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t
<.!;
blinkrate
OB'7
JAN-'O
counts
signal
bit
will
/10
4···82
is
S 0 f
b e
of
The
NNMI
externally
select
the
address
clears
latch
The
l'
(.:~
a d t h
with
the
f.·H\i:\bling NMI.
systeM
E~ V (~H'
the
signals
The
integral
the
printer
NPRINTER
the
printer
perforMing
TA1
and
status
is
enabled
printer
data
the
Ji
Each
pair
bit
pullup
pin
character
of
11
character
byte
bits
for
to
in
of
the
fifteen
character
the
data
dots
for
COMMand
expanded
(non-Maskable
by
a D
NENNMI
bit
TAO
latch,
status
tic
hardware.
discussed
printer
bus,
signal
via
a
write
data
for
is
lines
read
read
detected
back
TU1.
resistor
is
pulled
bytes
if
the
the
pair
the
following
saMe
horizontal
horizontal
font
in
and
printing.
to
print
and
cOMpressed
flip-flop
signal
is
the
disabling
port,
alb
1
elf)
It
above
the
is
active.
U16
and
operation
TDO-TD7
frOM
operations
by
TU1
will
R1.
low
in
the
being
character
indicates
a
1S
translates
the
character.
interrupt)
(half
of
the
data
input.
NMI,
U36,
located
k s i 9 n a 1 (
also
port
and
data
provides
also
at
address
being
The
half
of
to
selecting
the
printer
frOM
reading
be
low
When
by
printer
Made
the
the
printer
is
up
cell
the
byte
indicate
scan.
scans
by
1S
cell
the
horizontal
Each
30
bytes
Modes.
of
port
decoder,
This
while
VB
l.
A N
the
Monitors
latched
processor
U1S.
the
printer
the
on
the
printer
status
if
the
printer
forMed
of
the
is
state
the
Thus
of
fifteen
the
May
of
The
signal
U612).
Means
a
at
address
K)
f 0
inputs
the
98H
buffers
writes
Printer
particular
the
frOM
printer
is
therby
by
dot
scanned
of
every
state
character.
be
created.
dot
dot
data
printer
to
Port
clocking
that
write
f'
S Y n
c:
f~r
integral
in
control
with
upper
port.
the
is
connected
indicating
30
bytes
data
horizontally.
of
pairs
inforMation
are
is
also
the
addresses
a
to
90H
allows
h
l'
0 n i z i n g
the
data
the
data
address
function.
half
The
printer
not
of
needed
other
the
of.bytes
In
The
followed
ZaOA
the
latch
write
port
to
89H
the
the s of
datacoMM
printer
continuously
printer
and
is
specified
COMMands
lines
of
U1S
presence
and
connected
to
the
connection.
dot
data,
to
dot
while
interstitial
this
printer
into
able
to
is
Masked
B8H
to
8FH
while
port
sets
88H
the
ZaOA
twa
status
s~atus.
when
TAO
the
and
Printer
which
of
the
checking
due
processor
each
forM
The
the
first
seven
dots
correspond
way
any
buffers
vertical
by a print
print
to
l'
to
to
by
is
to
in
e
The
reMaining
video
inverted
section
to
TBUS
and
provide
one
the
port
for
clock
located
the
at
datacoMM
for
the
ASH
section.
latch
latches
(U3S).
SOMe
The
signals
NMODEM
to
signal
the
is
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0
Pr'ocf.~~:;~:;or
Module
13~?20·M·91
R
(~v
J
AN
OB7 /1.1
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4·-S;:!.
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MEMORY
The
Z80A
The
MeMory
OOOOH
2000H
4000H
6000H
BOOOH
AOOOH
CO
()
OH
SECTION
is
capable
Map
NMI
Service
S~~lf
for
TABLE
t€~st
of
this
code
addressing
processor
S.O
Routine
is'shown
TerMinal
65536
MeMory
(64K)
in
Map
the
bytes
table
U63
Function
l)at
..
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Configuration
Video
I
Internal
I
I
I
................
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I
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I
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I
I
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I
I
I I
I I
I
-
buffers
-
display
stack
-
systeM
ZDO
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I U41 : U42 : U43 : U44 :
keys
code
intrinsics
printer
-
............................
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MeMory I
variables
code
code
U6S
code
M'
........ M ...... _ .....................
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............................ _ .............. -................................. _ ..
U66
_.
_. M ... M .........
M.
.... .... ....
U67
....
_. _ ...
........
U68
-' -......................... -.................... _ .............................................................. _ ..
ZD4 : IDS
US1
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: ID6 :
ID7
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MeMory
below.
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16K
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data.
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As
can
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address
byte
ROMs
allocated
upper
41<
··
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M(-:~Mor
be
seen
for
which
into
six
bit
(or
for
of
that
y
frOM
the
MeMory
read-onlY-MeMory
controls
81<
TA12
EPROMs).
each
block
byte
for
ROM
is
the
blocks
each
Note
device
unusable).
(ROM).
terMinal
by
ROM
allows
even
Map
the
that
4B
K
This
operation.
74LS138
the
BK
if
it
of
MeMory
use
bytes
is
only
address
The
decoder
of
either
of
a
space
contains
ROM
has
the
space
U76. A JUMper
BI<
byte
address
4K
byte
space
ROM
been
ZaOA
or
(the
is
41<
is
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to
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opcode
ns
clock
During
G~nabling
n
~:)
even
thE'
an
indicate
used
to
fetch
froM
address
cycle
a MeMory
fro
M i:l d d
when
Z80t-1
instruction
that
provide
therby
shorter
th(~
addl'f.~Ssf:~d
l'
(0
S
s)
using
dati-'l
but:;
an
or
read
the
450
without
RandoM-acceSS-MeMory
The
RAM
subsysteM
16K
x 1
bit
150
ns
and
bits
Th(~
Wf':i.
during
TDO-TD7
I~AM~;;
te
clC:ce5se~)
a
discussed
ZUOA
A Z80A
address
TNMREQ
shifted
(TNRFSH
O's
low
I~EAD/WI~
access
location
going
through
is
are
shifted
in
turn.
strobes
address)
circuitry
100
ns
frOM
TNMREQ
signal
COMpleting
dynaMic
MiniMUM
respectively
ar'e
acce~)~;(~d
DMA
below.
ITE
high)
in
row
NCAS-strobes
to
access
NCAS.
the
has
by
(direct-MeMory-access)
Refer
to
RAM
between
low
the
the
the
through
This
address)
goes
RAM
(opcode)
instruction
an
early
allowing
300
ns
than
frOM
ROM.
r e
of
0
r'
e n
ns
EPRUMs.
been
RAMs.
cycle
in
the
to
is
initiated
COOOH
output
shift
output
the
produces
in
the
addressed
When
high
and
cycle.
fetch
fetch
enable
the
froM
enable
a MeMory
ROM
the
Data
()
wa
its
buP·fering.
designed
The
MK4116-2
tiMe
thl'(;:O(-?
to
of
provide
ways:
lBOA d
figure
and
of
register)
of
U77
shift
the
MUX-changes
colUMn
the
1'5
Z80A
are
of
use
read
TNMREQ
is
t
Note
around
320
U1'
ing
6.0
by
FFFFH
U77
goes
register
RAM
address
cell.
shifted
the
Z80A
cycle
the
of
(note
ROM
ROMs
is
being
with
that
operation)
and
r'f.~quired
,1
t e s a r
that
(-?
data
r
the
has a MiniMUM
ns.
the
U41-44
16K
bytes
by
the
a
l'efl'€-~sh
cycle.
for
RAM
tiMing.
lowering
(RAM
would
U510,
low
be
by
also.
address
high
DRCX.
causing
tiMing
RAM
sequence
address
and
Data
is
finish~d
ouput
through
activates
in
process.
addressed
an
access
an
opcode
without
TNRD
valid
(~q
signals
app('OXiMatf.~ly
u
ire d for M (-?
is
placed
MK4ll6-2
and
US1-S4
of
RAM
ZaOA
Each
the
for
c yc
Ie
TNMREQ
of
range).
causing
As
As
the
outputs
as
inputs
activates
on
accessing
the
the
NM1
This
tiMe
fetch
wait
til 0 r y
directly
(or
equivalent)
access
supply
data
M~?MOr'y
and
by
the
signal
l's
TNMREQ
clock
QA-QD
follows:
to
internal
MDO-MD7
the
shift
signal
signal
during
on
is
states.
go
active
rea
tiMe
storage.
read
the
three
at
Prior
to
goes
occurs,
to
NRAS-
colUMn
is
vaild
RAM
register
an
350
o~e
470
d s
on
of
data
or
CI~TC
is
an
to
be
low
go
RAM
the
If
the
along
the
with
output
operation.
transparent
inputs)
outputs
For
a
write
data
goes
The
on
low
TNRD
Z80A
TNMREQ
of
placing
are
the
strobing
signal
is
perforMing
U77
When
latch
enabled
operation,
data
bus.
will
(TNWR
to
enable
the
NMUX
beCOMes
the
RAM
until
ApproxiMately
the
data
be
high
d
read
reMains
the
transparent
signal
transparent)
outputs
TNRD
the
and
ZaOA
into
disabling
operation
high).
goes
on
TNMREQ
lowers
the
that
the
one
Z80A
internal
the
the
The
TNRD
latch,
high
is,
ZBOA
go
high
TNMREQ
clock
transparent
TNRD
(as
the
data
again.
and
data
line
signal
U62)
MUX
outputs
bus.
places
later
latch
is
during
goes
the
in
latch
is
gated
the
low)
follow
The
the
TNWR
the
so
lowered
with
read
the
the
latch
output
line
RAM.
RAM
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13220
Processor
Module
13220-91087/13
Rev
JAN-04-82
outputs
a
read
register
zaOA
The
every
The
perforM
The
following
decoded
TA7
RAS-MUX-CAS
signals
unaltered
byte
eRTC
Twice
0),
perforM
inforMation
the
and
will
and
(active
and
for
the
latch,
USiO.
onto
recirculate
addressing).
will
operation
to
REFRESH
nature
two
l8UA
dynaMic
ZaOA
while
current
activating
buffered
control
DMA
DMA
Maintains
and
reMain
does
DMA
per
the
NBUSREQ
DMA
reMain
low,
action.
address
U62,
TNBUSAK
the
bus
never
with
cOMplete
of
dynaMic
Milliseconds
has
a
built-in
RAM
each
executed
the
and
not
video
of
on
so
buffers
instruction
TNRFSH
sequence,
high
the
transparent
appear
row,
signal
enhanceMent
the
Machine
the
until
by
U79
buffered).
TBUSAK
on
as
well
enables
and
takes
Mode
be
on
TNMREQ
the
RAMs
to
refresh
a 7
eRTC).
NBUSAK
bit
the
and
refreshing
during
on
the
on
cycle
NBUSREQ
to
provide
U47,
the
bus
as
the
the
(see
the
l80A
going
cycle.
requires
guarantee
refresh
without
MeMory
fetch.
refresh
INMREQ
the
refresh
latch
bus.
scan
to
These
enables
enable
lines
the
and
character
The
by
tristating
line
section
signalling
is
signals
US?
and
and
upper
recirculating
data
high,
the
function
requiring
refresh
counter
signals
that
is
6
ZaOA
ZaOA
raised.
both
US11
the
enables
the
load
four
3.3
bus.
shifting
that
contents
While
is
are
row.
cycle,
not
and
is
activated
data
responds
its
The
IBUSAK
are
and
CRTC
the
signal
bits
line
for
The
each
to
extra
counter
the
output
brought
enabled
14
(if
address
that
NBUSAK
(active
used
enable
to
place
output
of
buffer,
More
provide
Since
the
starting
(see
to
the
to
to
the
cycle
1'5
row
of
which
instruction
on
MeMory
so
to
section
NBUSREQ
bus
tristate
the
the
DMA
inforMation
proceeds
through
Must
that
processor
address
low,
the
that
allow
and
is
signal
high)
video
lower
of
the
the
shift
address
U38,
the
be
row
are
signals
overhead.
is
increMented
is
bits
initiating
TNRD
contents
the
to
count
the
3.3
at
the
control
available
is
and
the
subsysteM
12
transparent
register,
out
as
for
shift
accessed
held.
which
being
TAU-
the
and
TNWR
are
accessed
froM
eRTC
for
inverted
TNBUSAK
address
bits
frOM U74
on
end
lines
of
to
More
of
and
of
the
DMA
ApproxiMately
the
line
load
signal
delayed
access
to
the
be
parallel
Upon
condition
through
rate
Signal
is
three
to
RAMs.
loading,
forces
the
the
four
clock
to
the
derived
dot
video
1he
loaded
the
shift
character
(LRC)
shift
frOM
tiMes
tiMing
load
on
shift
the
output
register.
signal
the
register
output
register
the
through
and
next
of
tiMes
of
through
character
U410
guarantee
causes
riSing
output
U77
to
The
next
before
the
in
RAS-CAS
edge
QD
go
three
the
start
CRTC
the
AND
rate
order
sufficient
low,
clock,
shift
of
is
high
causing
occurances
of
goes
gate
to
synchronize
address
register,
DRCX
and
the
high
U71U.
LCGAX,
(dot
QA
a's
of
video
enabling
The
which
set
U510,
rate
is
low.
to
be
DRCX
row
the
load
is
the
RAM
up
tiMe
to
clock).
THis
shifted
produce