Holtek Semiconductor Inc HT48C30, HT48C50, HT48C70, HT48C10 Datasheet

8-Bit Microcontroller Series

Features

•

Operating voltage: 2.4V ~5.2V

•

Bidirectional I/O lines with a selection of 18, 22, 32 and 56 lines

•

One interrupt input

•

Programmable timer/event counters with overflow interrupts and a selection of one 8-bit counter, one 8-bit and one 16-bit counters, or two 16-bit counters

•

On-chip crystal and RC oscillator

•

Watchdog timer

•

Program ROM with size selection of 1K

×14, 2K×14, 4K × 15 and 8K×16 bits

General Description

The HT48C10/48C30/48C50/48C70 are 8-bit high performance RISC-like microcontrollers, specifically designed for multiple I/O product applications. These devices are su itable for use in products such as remote controllers, fan/light controllers, washing machine controllers, scales, toys, and various subsystem controllers. They all contain a halt feature to reduce power consumption. The major differences between

HT48CXX/HT48RXX

•

Data RAM with size selection of 64×8, 96×8, 160

×8 and 224×8 bits

•

Halt function and wake-up feature to reduce power consumption

•

63 powerful instructions

•

Up to 0.5µs instruction cycle with 8MHz system clock at V

•

All instructions in 1 or 2 machine cycles

•

14-bit/15-bit/16-bit table read instructions

•

2-level/4-level/8-level subroutine nesting

•

Bit manipulation instructions

these microcontrollers are attributed to variations in sizes of the ROM and RAM, as well as bit number, counter number, I/O line number, and different level subroutine nesting. Roughly speaking, the HT48C10 is a microcontroller with most economic features and the HT48C70 is one with the most features of the four micro controllers.

=5V

1 25th May ’99

HT48CXX/HT48RXX

Selection Table

Mask version

Part No. HT48C10 HT48C30 HT48C50 HT48C70

Operating Voltage 2.4V~5.2V 2.4V~5.2V 2.4V~5.2V 2.4V~5.2V External Interrupt 1 1 1 1 Internal Interrupt 1 1 2 2 8-bit Timer/Event Counter 1 1 1 0 16-bit Timer/Event Counter 0 0 1 2 System Oscillator Crystal/RC Crystal/RC Crystal/RC Crystal/RC Watchdog Timer 1 1 1 1 ROM 1K

RAM I/O Lines 18 22 32 56

Instructions 63 63 63 63 Stack Levels 2 2 4 8 Operating Frequency 400kHz~8MHz 400kHz~8MHz 400kHz~8MHz 400kHz~8MHz Power Down Mode Table Read Instructions √√ √ √

×14 2K×14 4K×15 8K×16

×8

(40H~7FH)

√√ √ √

96×8

(20H~7FH)

160×8

(60H~FFH)

224×8

(20H~FFH)

OTP version

Part No. V

SYS

I/O Pull-high Mask version

HT48R11 3.0V~5.2V 400k~4MHz No HT48C10 HT48R12 3.0V~5.2V 400k~4MHz Yes HT48C10 HT48R31 3.0V~5.2V 400k~4MHz No HT48C30 HT48R32 3.0V~5.2V 400k~4MHz Yes HT48C30 HT48R50 3.0V~5.2V 400k~4MHz Yes HT48C50 HT48R51* 3.0V~5.2V 400k~4MHz No HT48C50

* Under development

2 25th May ’99

Block Diagram of HT48C70

HT48CXX/HT48RXX

3 25th May ’99

Pin Assignment

HT48CXX/HT48RXX

4 25th May ’99

HT48CXX/HT48RXX

Note: For the dice form, the TMR0 and TMR1 pads have to be bonded to VDD or VSS if t he TMR0

and/or TMR1 pad are not used. The (TMR0) The PC5 (TMR1) indicates that the TMR1 pad should be bonded to the PC5 pin.

INT indicates that the TMR0 pad should be bonded to the INT pin.

5 25th May ’99

Pin Description of HT48C10

HT48CXX/HT48RXX

Pin Name I/O

PA0~PA7 I/O

PB0~PB7 I/O

VSS — — Negative power supply, GND INT I — TMR I — Schmitt trigger input for timer/event counter

PC0~PC1 I/O

RES I — Schmitt trigger reset input, active low VDD — — Positive power supply

OSC1 OSC2

Mask

Option

Wake-up

Pull-high

or None

Pull-high

or None

Pull-high

or None

Crystal or

Function

Bidirectional 8-bit input/output ports Each bit can be configured as a wake-up input by mask option. Software instructions determi ne the CMOS output or schmitt trigger input with or without pull high resistor ( by mask option) .

Bidirectional 8-bit input/output ports Software instructions determine the CMOS output or schmitt trigger input with or without pull high resistor (by mask option).

External interrupt schmitt trigger in put with pull hig h resist or Edge trigger is activated dur ing hig h to low transition.

Bidirectional 2-bit input/output ports Software instructions determine the CMOS output or schmitt trigger input with or without pull high resistor (by mask option) .

OSC1 and OSC2 are con nected to an R C network or a crystal (by mask option) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock.

6 25th May ’99

Pin Description of HT48C30

HT48CXX/HT48RXX

Pin Name I/O

PA0~PA7 I/O

PB0~PB7 I/O

VSS — — Negative power supply, GND INT I — TMR I — Schmitt trigger input for timer/event counter

PC0~PC5 I/O

RES I — Schmitt trigger reset input, active low VDD — — Positive power supply

OSC1 OSC2

Mask

Option

Wake-up

Pull-high

or None

Pull-high

or None

Pull-high

or None

Crystal or

Function

Bidirectional 8-bit input/output ports Software instructions determine the CMOS output or schmitt trigger input with or without a pull high resistor (by mask option).

External interrupt schmitt trigger input with a pull high resistor. Edge triggered is activated on a high to low transition.

Bidirectional 6-bit input/output ports Software instructions determine the CMOS output or schmitt trigger input with or without a pull high resistor (by mask option).

OSC1 and OSC2 are con nected to an R C network or a crystal (by mask option) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock.

7 25th May ’99

Pin Description of HT48C50

HT48CXX/HT48RXX

Pin Name I/O

PA0~PA7 I/O

PB0~PB7 I/O

VSS — — Negative power supply, GND INT I — TMR0 I — Schmitt trigger input for timer/event counter 0

TMR1 I — Schmitt trigger input for timer/event counter 1

PC0~PC7 I/O

RES I — Schmitt trigger reset input, active low VDD — — Positive power supply

OSC1 OSC2

PD0~PD7 I/O

Mask

Option

Wake-up

Pull-high

or None

Pull-high

or None

Pull-high

or None

Crystal or

Pull-high

or None

Function

Bidirectional 8-bit input/output ports Software instructions determine the CMOS output or schmitt trigger input with or without a pull high resistor (by mask option).

External interrupt schmitt trigger input with a pull high resistor. Edge triggered is activated on a high to low transition.

Bidirectional 8-bit input/output ports Software instructions determine the CMOS output or schmitt trigger input with or without a pull high resistor (by mask option).

OSC1 and OSC2 are con nected to an R C network or a crystal (by mask option) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock.

Bidirectional 8-bit Input/Output port. Software instructions determine the CMOS output or schm itt trigger input with or without a pull high resistor (by mask option).

8 25th May ’99

Pin Description of HT48C70

HT48CXX/HT48RXX

Pin Name I/O

PA0~PA7 I/O

PB0~PB7 I/O

VSS — — Negative power supply, GND INT I — TMR0 I — Schmitt trigger input for timer/event counter 0

TMR1 I — Schmitt trigger input for timer/event counter 1

PC0~PC7 I/O

RES I — Schmitt trigger reset input, active low VDD — — Positive power supply

OSC1 OSC2

PD0~PD7 I/O

PE0~PE7 I/O

PF0~PF7 I/O

PG0~PG7 I/O

Mask

Option

Wake-up

Pull-high

or None

Pull-high

or None

Pull-high

or None

Crystal or

Pull-high

or None

Pull-high

or None

Pull-high

or None

Pull-high

or None

Function

Bidirectional 8-bit input/output ports Software instructions determine the CMOS output or schmitt trigger input (pull-high depends on mask option).

External interrupt schmitt trigger with pull high resistor Edge trigger is activated during high to low transition.

Bidirectional 8-bit input/output ports Software instructions determine the CMOS output or schmitt trigger input (pull-high depends on mask option).

OSC1 and OSC2 are con nected to an R C network or a crystal (by mask option) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock.

Bidirectional 8-bit input/output ports Software instructions determine the CMOS output or schmitt trigger input (pull-high depends on mask option).

9 25th May ’99

HT48CXX/HT48RXX

Absolu te Maxim um Ratings

Supply Voltage .......................VDD–0.3V to 5.5V Storage Temperature.................–50°C to 125°C

Input Voltag e .... ........ .....V

Note: These are stress ratings only. Stresses exceeding the range spe cified under “Absolute Maxi -

mum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme condition s may affect device reliability.

D.C. Characteristics Ta=25°C

–0.3V to VDD+0.3V Operating Temperature ..............–25°C to 70°C

Symbol Parameter

DD1

DD2

DD3

DD4

DD5

DD6

DD7

DD8

STB1

STB2

Operating Voltage — — 2.4 — 5.2 V Operating Current

(HT48C10 Crystal OSC)

Operating Current (HT48C10 RC OSC)

Operating Current (HT48C30 Crystal OSC)

Operating Current (HT48C30 RC OSC)

Operating Current (HT48C50 Crystal OSC)

Operating Current (HT48C50 RC OSC)

Operating Current (HT48C70 Crystal OSC)

Operating Current (HT48C70 RC OSC)

Standby Current (WDT Enabled)

Standby Current (WDT Disabled)

Test Conditions

3V 5V — 2 3 3V 5V — 1 2 3V 5V — 2 3 3V 5V — 1 2 3V 5V — 2.5 5 3V 5V — 1.5 3 3V 5V — 3.4 6 3V 5V — 2.1 4 3V 5V — — 10 3V 5V — — 2

Conditions

No load f

=4MHz

SYS

No load f

=2MHz

SYS

No load f

=4MHz

SYS

No load f

=2MHz

SYS

No load f

=4MHz

SYS

No load f

=2MHz

SYS

No load f

=4MHz

SYS

No load f

=2MHz

SYS

No load system halt

Min. Typ. Max. Unit

—0.71.5

—0.5 1

—0.71.5

—0.5 1

—1 2

— 0.75 1.5

—1.5 3

—1 2

—— 5

—— 1

µA

10 25th May ’99

HT48CXX/HT48RXX

Symbol Parameter

IL1

IH1

IL2

IH2

Input Low Voltage for I/ O ports

Input High Voltage for I/O Ports

Input Low Voltage (

TMR, TMR0, TMR1, INT)

Input High Voltage (

TMR, TMR0, TMR1, INT)

Input Low Voltage (RES)

Input High Voltage (RES)

I/O Ports Sink Current

I/O Ports Source Current

Pull-high Resistance of I/O Ports and

INT

Test Conditions

Conditions

Min. Typ. Max. Unit

3V — 0 — 0.9 5V — 0 — 1.5 3V — 2.1 — 3 5V — 3.5 — 5 3V — 0 — 0.7 5V — 0 — 1.3 3V — 2.3 — 3 5V — 3.8 — 5 3V — — 1.5 — 5V — — 2.5 — 3V — — 2.4 — 5V — — 4.0 — 3V V 5V V 3V V 5V V

=0.3V 1.5 4 —

=0.5V 4 10 —

=2.7V –1 –2 —

=4.5V –2 –4.5 —

3V — 40 60 80 5V — 10 30 50

Ω

11 25th May ’99

HT48CXX/HT48RXX

A.C. Characteristics Ta=25°C

Symbol Parameter

SYS1

SYS2

TIMER

WDTOSC

WDT1

WDT2

RES

SST

INT

System Clock (Crystal OSC)

System Clock (RC OSC)

Timer I/P Frequency (TMR, TMR0, TMR1)

Watchdog Oscillator — —

Watchdog Time-out Period (RC)

Watchdog Time-out Period (System Clock)

External Reset Low Pulse Width

System Start-up Timer Period

Interrupt Pulse Width — — 1 — — µs

Test Conditions

Conditions

Min. Typ. Max. Unit

3V — 400 — 4000 kHz 5V — 400 — 8000 kHz 3V — 400 — 2000 kHz 5V — 400 — 3000 kHz 3V — 0 — 4000 kHz 5V — 0 — 4000 kHz

45 90 180

µs

35 65 130

Without WDT

—

prescaler Without WDT

—

prescaler

—— 1——

12 23 45

91735

—1024— t

SYS

µs

Power-up or

—

Wake-up from

—1024— t

SYS

halt

Note: t

SYS

=1/f

SYS

12 25th May ’99

Functional Description

The four microcontrollers of the HT48C10/ HT48C30/HT48C50/HT48C70 are constructed using basically the same principles. Their differences lie in variati ons in sizes su ch as ROM and RAM as wel l as bit num ber, counter number , I/O line number , and different level subroutine nesting bit number. The following is a more detailed description of the system architectures of the four microcontrollers. Unless specified, the architecture stated below exists in these four microcontrollers.

Execution flow

The system clock is derived from either a crystal or an RC oscillator. It is internally divided into four non-overlapping clocks. Each instruction cycle consists of four system clock cycles.

Instruction fetching and execution are pipelined in such a way that a fetch takes one i nstruction cycle while decoding and execution takes the next instruction cycle. The pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction.

Program counter – PC

The program counter (PC) is of different sizes ranging from 10 b its to 1 3 b its acco rdin g to the microcontroller selected (10 bits for the HT48C10; 11 bits for the HT 48C30; 12 bits for the HT48C50; 13 bits for the HT48C70). It con-

HT48CXX/HT48RXX

trols a sequence in which the instructions stored in the program ROM are executed . The contents of the PC can specify 1024, 2048, 4096, or 8192 addresses at maximum, according to the microcontroller (HT48C10/HT48C30/ HT48C50/HT48C70) chosen.

After accessing a program memory word i n order to fetch an instruction code, the contents of the PC is incremented by one. The PC then points to the memory word consisting of the next instruction code.

When executing a jump instruction, conditional skip execution, loa ding a PCL register, a subroutine call, an initia l reset, an internal interrupt, an external interrupt, or returning from a subroutine, the PC manipulates a program transfer by loading the addres s corresponding to each instruction.

The conditional skip is activated by inst ructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction; otherwise it proceeds to the next instruction.

The lower byte of the PC (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination is within 256 locations.

For a control transfer to take place, an additional dummy cycle is required.

Execution flow

13 25th May ’99

Progr a m me mory – ROM

The program memory (ROM) is used to store the program instructions that are to be executed. It contains data, table, and interrupt entries, and is organized into 1024 4096

×15 bits, or 8192×16 bits according to the mi-

×14 bits, 2048×14 bits,

crocontroller (HT48C10/ HT48C30/HT48C50/ HT48C70) selected. These bits are all addressed by the PC and table pointer .

Certain locations in the ROM s tated belo w are reserved for special usage in the four microcontrollers except loca tion 00C H which is used for the HT48C50/HT48C70 exclusively.

•

Location 000H Location 000H is reserved for program in-

itialization. After chip reset, the progra m always begins execution at this area.

•

Location 004H Location 004H is reserved for external inter-

rupt service program. If the

INT input pin is activated, the interrupt is enabled, and the stack is not full, the program begins execution at location 004H.

•

Location 008H Location 008H is reserved for the timer/event

counter interrupt service program of the HT48C10/HT48C30 and for the timer/event counter 0 interrupt service program of the

HT48CXX/HT48RXX

Program memory

HT48C50/HT48C70. If the timer interrupt results from a timer/even t counter overflow of the HT48C10/HT48C30 or a timer/event counter 0 overflow of the HT48C50/HT48C70, and the interrupt is enabled, and the stack is not full, the program begins execution at location 008H.

Mode Contents of Program Counter (m bits)

Initial reset 0000H External interrupt 0004H Timer/event counter 0 overflow 0 008H Timer/event counter 1 overflow 0 00CH Skip PC+2 Loading PCL Low byte replaced by instruction code Jump, call branch Instruction code Return from subroutine Stack register

Notes: m=10 for the HT48C10

m=11 for the HT48C30 m=12 for the HT48C50 m=13 for the HT48C70

14 25th May ’99

HT48CXX/HT48RXX

•

Location 00CH Location 00CH is reserved for the timer/ event

counter 1 interrupt service program of the HT48C50/HT48C70 only. If the timer interrupt results from a timer/event counter 1 overflow, the interrupt is enabled, and the stack is not full, the program begins execution at location 00CH.

•

Table locati on Any location in the ROM can be used as a

look–up table. The instructio ns TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the sp ecified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defin ed, and the higher-order byte of the table word is transferred to the Table Higher-order byte register (TBLH). Th e TB LH i s read only. The Table Pointer (TBLP), on the other hand, is a read/write register (07H) used to indi cate the table location. B efore a ccessing th e tab le, the location should be placed in the TBLP. The TBLH is read only and canno t be restore d. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine is likely to be changed by the table read instruction used in the ISR. Errors will then occur. Hence, simultaneously using the table read instruction in the main routine and the ISR should be avoided. Nonetheless, if the application of the table read instruction

to both the main routin e and the ISR cannot be avoided, interrupts should be disabled prior to the table read instruction, and they should not be enabled until the TBLH is backed-up. All the table related instructions require 2 cycles to complete an operation. These areas may function as a normal program memory depend ing upon the user ’s requirements.

Stack register – STACK

The stack register is a special memory port used to save the contents of the PC. The stack can be organized into 2, 4, o r 8 levels according to the microcontroller selected (2 levels for the HT48C10/HT48C30, 4 levels for the HT48C50, 8 levels for the HT 48C70). The registe r is neither part of the da ta nor part of the program, and is neither readable nor writeable. Any activated level is indexed by a stack pointer (SP) and is neither readable nor writeable. At a subroutine call or inte rrupt acknowledgment , the contents of the PC is pushe d o nto the sta ck. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the contents of the PC is restored to its previous value from the stack. After chip reset, the SP will point to the top of the stack.

If the stack is full and a non-masked interrupt takes place, the interrupt request fl ag is record ed but the acknowledgment is still inhibited. After the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents the occurrence of stack overflow, allow-

Instruction(s)

*m~*8

∗7 ∗6 ∗5 ∗4 ∗3 ∗2 ∗1 ∗0

Ta ble Loc ation

TABRDC [m] Pm~P8 @7 @6 @5 @4 @3 @2 @1 @0 TABRDL [m] 1~1 @7 @6 @5 @4 @3 @2 @1 @0

Table locati on

Notes:

∗m~∗0: Bits of table location

@7~@0: Bits of table pointer Pm~P8: Bits of current Program Counter

15 25th May ’99

m=9 for the HT48C10 m=10 for the HT48C30 m=11 for the HT48C50 m=12 for the HT48C70

ing the programmer to use the structure easily. Likewise, if the stack is full and a CALL is subsequently executed, a stack overflow will occur and the first entry will be lost (only the most recent four return addresses will be stored).

Data memory – RAM

The data memory (RAM) is composed of bits ranging from 8 1 pending on the microcontroller chosen (HT48C10/ HT48C30/HT48C50/HT48C70). It is divided into two function al groups, i.e., special function registers and general purpose data memory (of 64 depending on the microcontroller selected (HT48C10/ HT48C30/HT48C50/HT48C70). Most components of the two functional groups are readable/writable, but some are read-only.

Of the two functional groups , the special function registers of the four mi crocontrollers consist of a program counter lower-order byte register (PCL;06H), an accumulator (ACC; 05H), a table pointer (TBLP;07H), a table higher-order byte register (TBLH;08H), a status register (STATUS;0AH), an interrupt control register (INT C;0BH), a wa tchdo g timer option setting register (WDTS;09H), an indirect addressing register (00H), a memory pointer register (MP;01H), a timer/event counter (TMR;0DH), a timer/event counter control register (TMRC;0EH), I/O registers (P A;12H,PB;14H, PC;16H), and I/O control registers (PAC;13H,PBC;15H,PCC;17H). But of the HT48C50/HT48C70, the following components are further divided into two or several sub-components. First, the indirect addressing register is divided into two registe rs involving indirect addressing register 0 (00H) and ind irect addressing register 1 (02H). Second, the memory pointer register is also comprised by two registers involving memory pointer register 0 (MP0;01H) and memory pointer register 1 (MP1;03H). Third, the timer/event counter register is organized by two registe rs according to different orders of byte, namely timer/event higher-order byte register and timer/event lower-order byte register, both of which are further divided into timer/event counter 0 higher-

×8, 113×8, 184×8, or 255×8, de-

×8, 96×8, 160×8, or 224×8 bits,

HT48CXX/HT48RXX

RAM mapping

order byte register (TMR0H; 0CH), timer/ event counter 1 higher-order byte register (TMR1H;0FH), timer/event counter 0 lowe r-order byte register (TMR0L;0DH), and timer/event counter 1 lowe r-order byte regi ste r (TMR1L;10H). Fourth, the timer/eve nt counte r control register is divided into two registers involving timer/event counter 0 control register

16 25th May ’99

HT48CXX/HT48RXX

(TMR0C;0EH) and timer/event counter 1 control register (TMR1C;11H). Fifth, the entire number of I/O registers is expanded from 3 to 6 (PA;12H,PB;14H,PC;16H,PD;18H,PE;1AH, PF;1CH,PG; 1EH). Finally, the number of I/O control registers is also doubled (PAC;13H, PBC;15H,PCC;17H,PDC;19H,PEC;1BH, PFC;1DH,PGC;1FH). The remaining space before the 20H of the four microcontrollers are all reserved for future expansion usage. Reading these remaining locations will return the result to 00H. The general purpose data memory, addressed from 40H~7FH of the HT48C10, 20H~7FH of the HT48C30, 60H~FFH of the HT48C50, or 20H~FFH of the HT48C70 according to the microcon troller selected, is used for data and control information under instruction commands.

All the RAM areas can directly execute arithmetic, logic, increment, decrem ent, and rotate operations. Except some dedicated bits, each bit in the RAM can be set and reset by the SET [m].i and CLR [m].i instructi ons, res pectivel y. These RAM areas are indirectly accessible through the memory pointer register(s) MP (01H) of the HT48C10/HT48C30 or MP0 (01H) and MP1 (03H) of the HT48C50/HT48C70.

Indirect addressing register

Of the four microcontrollers, the HT48C10/ HT48C30 make use of location 00H whereas the HT48C50/HT48C70 of locations 00H and 02H as indirect addressing registers that are not physically imple mente d. An y rea d/write ope ration of [00H] or of [00H] and [02H] accesses the RAM pointed to by MP (01H) or by MP0 (01H) and MP1 (03H) respectively according to the microcontroller chosen. Reading location 00H or 02H indirectly will return the result 00H. Writing it indirectly will, result to no operation.

The function of data movement between two indirect addre ssing registers is not suppo rted. The memory pointer register MP of the HT48C10/HT48C30 or MP0 and MP1 of the HT48C50/HT48C70 are of 7 bits or 8 bits wide respectively , and can be used to access the RAM

by combining the corresponding indirect addressing registers. The bit 7 of MP (HT48C10/HT48C30) is undefined and reading will return the result “1”. Any writing operation to MP will only transfer the lower 7-bit data to MP.

Accumulator ACC

The accumulator (AC C) relate s to the ALU o perations. It is also mapped to location 05H of the RAM and is capable of operating with immedi ate data. The data movement between two data memories will pass through the ACC.

Arithmetic and logic unit – ALU

This circuit performs 8-bit ari thm eti c and lo gic operations. It provides the following functions:

•

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

•

Logic operations (AND, OR, XOR, CPL)

•

Rotation (RL, RR, RLC, RRC)

•

Increment and Decrement (INC, DEC)

•

Branch decision (SZ, SNZ, SIZ, SDZ, etc.)

The ALU saves the results of the data operation and change the status register as well.

Status register – STATUS

The status registe r (0AH) i s of 8 bits wi de and consists of a zero flag (Z), a carry flag (C), an auxiliary carry flag (AC), an overflow flag (OV), a power down flag (PD) , and a watchdog ti meout flag (TO). The register also records the status information and controls the operation sequence.

Except the TO and PD flags, bits in the status register can all be altered by instructions, similar to the case with other registers. A ny data written into the status regi ste r wil l n ot ch ange the TO or PD flags. But the opera tions related to the status register m ay lead to different results from t hose int ended. The TO an d PD flag s can be changed by system power up, Watchdog Timer overflow, executing the HALT instruction, or clearing the W atchdog Timer . The Z, OV , AC, and C flags all reflect the status of the latest operations.

17 25th May ’99

HT48CXX/HT48RXX

On entering the interrupt sequence or executing the subroutine call, the sta tus registe r will not be automati cally pu shed o nto the sta ck . If the contents of the statu s is impo rtant an d the subroutine can corrup t the status register, the programmer should take preca ution s to save it properly.

Inte r r upt

The four microcon trollers all provide a n external interrupt and internal time r/event counte r interrupts. The interrupt control register (INTC;0BH) contains interrupt control bits for setting the enable/disable mode and the interrupt request flags.

Once an interrupt subroutine is serviced, the remaining interrupts will all be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flag will be recorded. If a certain interrupt requires servicing within the service routine, the progr ammer may set the EMI bit and the corresponding bit of INTC so as to allow interrupt nesting. If the st ack is full, the interrupt request will not be acknowledged, even

if the related interrupt is enabled, until the SP is decremented. If immediate servicing is desired, the stack should be prevented from becoming full.

All these interrupts have a wake-up cap abilit y. As an interrupt is serviced, a control transfe r occurs by pushing the PC on to the stack and then by branching it to subroutines at the specified location(s) in the ROM. Only the contents of the PC can be pushed onto the stack. If the contents of the register an d of the statu s register (STATUS) are altered by the interrupt service program which corrupts the desire d control sequence, the programmer should save these contents first.

The external interrupt is triggered by a high to low transition of the rupt request flag ( EIF; bit 4 of INTC) is then set. When the interrup t is e nabled , the stack is not full, and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will also be cleared to disable other interrupts.

Of the four microcontrollers, the internal timer/event counter interrupt of the HT48C1 0/ HT48C30 is initialized by setting the timer/

Labels Bits Function

C is set if the o peration res ults in a carry during an addition opera tion or if a

AC 1

OV 3

PD 4

TO 5

— 6 Undefined, read as 0 — 7 Undefined, read as 0

borrow does not take place during a subtraction operation; otherwise C is cleared. Also it is affected by a rotate through carry instruction.

AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z is set if the result of a n arithmetic or logic operati on is zero; otherwise Z is cleared.

OV is set if the opera tion res ults in a carry into the highe st-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.

PD is cleared by either a system power-up or executing the CLR WDT instruction. PD is set by executing the HALT instruction.

TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out.

INT, and the related inter-

Status register

18 25th May ’99

+ 41 hidden pages

Holtek Semiconductor Inc HT48C30, HT48C50, HT48C70, HT48C10 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

General Description

Selection Table

Block Diagram of HT48C70

Pin Assignment

Pin Description of HT48C10

Pin Description of HT48C30

Pin Description of HT48C50

Pin Description of HT48C70

Absolu te Maxim um Ratings

D.C. Characteristics Ta=25°C

A.C. Characteristics Ta=25°C

Functional Description