Provides VLCD pin to adjust LCD operating voltage
and max. VLCD voltage up to 7V
·
Provides three kinds of bias current programming
·
Control of TN-type and STN-type LCDs
·
208-pin QFP package
Applications
·
Leisure products
·
Games
·
Personal digital assistant
General Description
HT1660 is a peripheral device specially designed for I/O
type
max. display segment of the device are 3072 patterns
(96 segments and 32 commons). It also supports four
data bits interface, buzzer sound, Watchdog Timer or
time base timer functions. The HT1660 is a memory
mapping and multi-function LCD controller. Since the
used to expand the display capability. The
MCU
·
Cellular phone
·
Global positioning system
·
Consumer electronics
HT1660 can control TN-type (Twisted Nematic) or
STN-type (Super Twisted Nematic) LCDs. The software
configuration feature of the HT1660 make it suitable for
multiple LCD applications including LCD modules and
display subsystems. Only six lines (CS
,WR, DB0~DB3)
are required for the interface between the host controller
and the HT1660.
Rev. 1.301April 13, 2006
Block Diagram
O S C O
O S C I
C S
R D
W R
D B 0
D B 3
V D D
V S S
B Z
B Z
N o t e : C S : C h i p s e l e c t i o n
D i s p l a y R A M
C o n t r o l
&
T i m i n g
C i r c u i t
T o n e F r e q u e n c y
G e n e r a t o r
B Z , B Z : T o n e o u t p u t s
W R , R D : W R I T E c l o c k , R E A D c l o c k
D B 0 ~ D B 3 : D a t a b u s
C O M 0 ~ C O M 3 1 , S E G 0 ~ S E G 9 5 : L C D o u t p u t s
I R Q : T i m e b a s e o r W D T o v e r f l o w o u t p u t
L C D D r i v e r /
B i a s C i r c u i t
W a t c h d o g T i m e r
&
T i m e B a s e G e n e r a t o r
HT1660
C O M 0
C O M 3 1
S E G 0
S E G 9 5
V L C D
I R Q
Pin Assignment
C O M 2 2
C O M 2 1
C O M 2 0
C O M 1 9
C O M 1 8
C O M 1 7
C O M 1 6
O S C O
C O M 0
C O M 1
C O M 2
C O M 3
C O M 4
C O M 5
C O M 6
Chip selection input with pull-high resistor. When the CS
data and command read from or write to the HT1660 are disabled. The serial
interface circuit is also reset. But if the CS
I
the CS
pad, the data and command transmission between the host controller
and the HT1660 are all enabled.
READ clock input with pull-high resistor. Data in the RAM of the HT1660 are
clocked out on the falling edge of the RD
I
pear on the data line. The host controller can use the next rising edge to latch
the clocked out data.
WRITE clock input with pull-high resistor. Data on the DATA line are latched
I
into the HT1660 on the rising edge of the WR
Negative power supply for logic circuit, ground
¾
The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to
generate a system clock. If the system clock comes from an external clock
I
source, the external clock source should be connected to the OSCI pad. But
O
if an on-chip RC oscillator is selected, the OSCI and OSCO pads can be left
open.
Positive power supply for logic circuit
¾
OTime base or Watchdog Timer overflow flag, NMOS open drain output.
O2kHz or 4kHz frequency output pair (tristate output buffer)
Vary bias current pin
It is usually not connected
is at a logic low level and is input to
signal. The clocked out data will ap
HT1660
is logic high, the
-
signal.
Absolute Maximum Ratings
Supply Voltage...........................VSS-0.3V to VSS+5.5V
Input Voltage.............................V
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil
ity.