Holtek Semiconductor Inc HT0610 Datasheet
Features
·
Operating voltage: 2.4V~3.5V
·
33 common/120 segment LCD driver output
·
33´120=3960 bits capacity of built-in graphic display
data RAM (BGDRAM)
·
Master and slave mode available for multi-chip
operation
·
8-bit Parallel interface with general MCU
·
On-chip oscillator circuit for display clock, external
clock can also be used
·
Selectable multiplex ratio: 1/16, 1/32, 1/33
·
Selectable bias ratio: 1/5 or 1/7
·
External driving circuit for external bias supply
·
On-chip selectable voltage doublers and tripler
·
Wide rangeof operating temperature: -30°Cto85°C
·
S/W controlled electronic contrast control function
(16 levels)
General Description
The HT0610 is a driver and controller LSI for graphic
dot-matrix liquid crystal display systems. It has 33 common and 120 segment driver circuits. This chip is connected directly to an MCU, accepts 8-bit parallel display
data and stores an on-chip graphic display data RAM
(BGDRAM) of 33´120 bits. It provides a high-flexible
display section due to the one-to-one correspondence
HT0610
33´120 LCD Driver
·
External contrast control
·
Low power icon mode driven by com32
·
Four static icon driver circuit
·
High accuracy voltage regulator with temperature co
efficient (0.00%, -0.18%, -0.22%, -0.35%)
·
Low power consumption
-
Read/write mode 170mA (Typical)
-
Display mode 160mA (Typical)
-
Standby mode 15mA (Typical; Display off; internal
oscillator enable)
-
Standby mode < 1mA (Typical; Display off; external
oscillator enable)
·
CMOS process
·
TCP available
between BGDRAM bits and LCD panel pixels. It per
forms BGDRAM read/write operation with no externally
operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive an LCD, it is possible to make a display
system with minimal components.
-
-
Rev. 1.10 1 April 4, 2007
Block Diagram
HT0610
O S C 1
O S C 2
V D D
V S S
I B P
I C O
N 0 ~ I C O N 3
S t a t i c I c o n
C o n t r o l C i r c u i t
T i m i n g G e n e r a t o r
f o r D i s p l a y
S E G 0 ~ S E G 1 1 9
H i g h V o l t a g e C e l l L e v e l S h i f t e r
1 5 5 B i t s L a t c h
( 3 3 B i t s & 1 2 0 B i t s )
B G D R A M
1 2 0
3 3 B i t s
´
C o m m a n d D e c o d e r C i r c u i t
C o m m a n d I n t e r f a c e
C S ( C L K )
D C O M
R E S
C O M 0 ~ C O M 3 2
P a r a l l e l I n t e r f a c e
C E
L e v e l
S e l e c t o r
V L L 2
V L L 6
V C C A 1
L C D D r i v i n g
V o l t a g e G e n e r a t o r
D o u b l e r & T r i p l e r
V o l t a g e R e g u l a t o r ,
V o l t a g e D i v
C o n t r a s t C o n t r o l ,
T e m p e r a t u r e
C o m p e n s a t i o n
R W
D 0 ~ D 7
i d e r ,
C i r c u i t
V R
V F
C 2 P
C 2 N
C 1 P
C 1 N
D U M 2
D U M 1
C +
C V D D A
Operation of LCD Driver
Description of Block Diagram Module
Block Description
This module determines whether the input data is interpreted as data or command.
Data is directed to this module based upon the input of the DCOM pin. If DCOM High,
then data is written to BGDRAM ( Built-in Graphic Display data RAM). DCOM pin Low
Command Decoder and
Command Interface
Parallel Interface
Built-in Graphic Display
data RAM (BGDRAM)
Display Timing Generator
indicates that the input at D0~D7 is interpreted as a Command.
CE is the master chip selection signal. A High input enable the input lines ready to sam
ple signals.
RES pin of same function as Power On Reset (POR). Once RES received the reset sig
nal, all internal circuitry will back to its initial status. Refer to Command Description
section for more information.
The parallel interface consists of 8 bi-directional data lines (D0~D7), RW and CS. The
RW input High indicates a read operation from the BGDRAM. RW input Low indicates a
write to BGDRAM or Internal Command Registers depending on the status of DCOM
pin input.
The CS input serves as data latch signal (clock).
The BGDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The
size of the BGDRAM is determined by number of row times the number of column
(120´33 =3960 bits). Figure as followis a description of the BGDRAM address map. For
mechanical flexibility, re-mapping on both segment and common outputs are provided.
This module is an on chip low power RC oscillator circuitry. The oscillator frequency can
be selected in the range of 15kHz to 50kHz by external resistor. One can enable the cir
cuitry by software command. For external clock provided, feed the clock to OSC2 and
leave OSC1 open.
-
-
-
Rev. 1.10 2 April 4, 2007
Block Description
Static Icon Control Circuit
LCD Driving Voltage
Generator
120 Bit Latch/33 Bit Latch
Level Selector
HV Buffer Cell
(Level Shifter)
HT0610
This module generates the LCD waveform of the 4 annunciators and IBP signal. The
four independent static icons are enabled by software command. Icon signals are also
controlled by oscillator circuit, too.
This module generates the LCD voltage needed for display output. It takes a single sup
ply input and generates necessary bias voltages. It consists of:
·
Voltage doubler and voltage tripler
To generate the VCCA1 voltage. Either doubler or tripler can be enabled.
·
Voltage regulator
Feedback gaincontrol for initial LCD voltage. It can also be used with external contrast
control.
·
Voltage divider
Divide the LCD display voltage (VLL2~VLL6) from the regulator output. This is low
power consumption circuit, which can save the most display current compare with tra
ditional resistor ladder method.
·
Bias Ratio Selection circuitry
Software control of 1/5 and 1/7 bias ratios to match the characteristic of LCD panel.
·
Self adjust temperature compensation circuitry
Provide 4 different compensation grade selections to satisfy the various liquid crystal
temperature grades. The grading can be selected by software control.
·
Contrast Control Block
Software control of 16 voltage levels of LCD voltage.
·
External Contrast Control
By adjusting the gain control resistors connected externally, the contrast can be varied.
All blocks can be individually turned off if external voltage generator is employed.
153 bit long registers, which carry the display signal information. First 33 bits are Common driving signals and other 120 bits are Segment driving signals. Data will be input to
the HV-buffer Cell for bumping up to the required level.
Level selector is a control of the display synchronization. Display voltage can be separated into two sets and used with different cycles. Synchronization is important since it
selects the required LCD voltage level to the HV Buffer Cell for output signal voltage
pump.
HV Buffer Cell works as a level shifter that translates the low voltage output signal to the
required driving voltage. The output is shifted out with an internal FRM clock, which co
mes from the Display Timing Generator. The voltage levels are given by the level selec
tor which is synchronized with the internal M signal.
-
-
-
-
Rev. 1.10 3 April 4, 2007
Pin Assignment
D U M M Y
O S C 1
V C C A 1
D U M 2
O S C 2
D U M 1
V D D A
C
S ( C L K )
D C O M
D U M M Y
V S S
V S S
V L L 6
V L L 5
V L L 4
V L L 3
V L L 2
C 2 N
C 2 P
C 1 N
C 1 P
V S S
V S S
V S S
R E S
V D D
HT0610
D U M M Y
1 9 7
C O M 3 2
C O M 0
1 9 6
C O M 1
1 9 5
1 9 4
C O M 2
C O M 3
1 9 3
C O M 4
1
2
3
4
V R
5
V F
6
7
C -
8
C +
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
C E
2 4
D 7
2 5
D 6
2 6
D 5
2 7
D 4
2 8
D 3
2 9
D 2
3 0
D 1
3 1
D 0
3 2
3 3
3 4
R W
3 5
3 6
3 7
3 8
1 9 2
C O M 1 2
1 8 4
C O M 1 3
1 8 3
C O M 1 4
1 8 2
C O M 1 5
1 8 1
S E G 0
1 8 0
S E G 1
1 7 9
S E G 2
1 7 8
S E G 3
1 7 7
S E G 4
1 7 6
S E G 1 1 7
6 3
S E G 1 1 8
6 2
S E G 1 1 9
6 1
C O M 3 2
6 0
C O M 3 1
5 9
C O M 3 0
5 8
C O M 2 9
5 7
C O M 2 8
5 6
C O M 1 9
4 7
C O M 1 8
4 6
C O M 1 7
4 5
C O M 1 6
4 4
I C O N 0
4 3
I C O N 1
4 2
I C O N 2
4 1
I C O N 3
4 0
I B P
3 9
D U M M Y
Rev. 1.10 4 April 4, 2007
Pin Description
Pin Name I/O Description
VDD I
RES I Active low reset pin; reset all internal status of circuit (Same as power on reset)
VSS I VSS is ground
DCOM I
RW I
CS I
D0~D7 B Those bi-direction pins are used for DATA or command transferring.
CE I High input to this pin to enable the control pins on the driver.
OSC1 I
OSC2 O
C1P, C1N
C2P, C2N
VLL2~VLL6 O
DUM1, DUM2 O
C+, C-
VCCA1 O
VF, VR
COM0~COM32 O These pins provide the row driving signal to LCD panel
VDDA I
ICON1~ICON4 O There are four independent annunciator driving outputs
IBP O This pin combines with ICON1~ICON4 pins to form annunciator driving part.
SEG0~SEG119 O These 120 pins provide LCD column driving signal to LCD panel.
VDD is the positive supply to the digital control circuit and other circuitry in LCD bias voltage
generator (Must have same voltage level with VDDA)
If pull this pin ²High² then D0~D7 bi-direction bus is used for data transferring; If DCOM pin is
²Low² then D0~D7 bi-direction bus is used for command transferring.
If pull this pin high: Indicate we want to read the display data RAM or the internal state. If we
force this to Low: Indicate we want to write data to display data RAM or write some internal
state to registers.
This pin is normal low clock input. Data on D0~D7 bi-direction data bus are latched at the fall
ing edge of CS
Oscillator input pin.
For internal oscillator mode, this is an input for the internal low power RC oscillator circuit. In
this mode,an external resistor of certain value is placed between the OSC1 and OSC2 pins.
For external oscillator mode, OSC1 pin should be left open
Oscillator output pin
For internal oscillator mode, this is an output for the internal low power RC oscillator circuit.
External Oscillator input
For externaloscillator mode, OSC2 will be an input pin forexternal clock and no external resistor is needed.
If internal DC/DC converter is enabled, a capacitor is required to connect these two pins.
¾
If internal tripler is enabled, a capacitor is required to connect these two pins. Otherwise, leave
¾
these pin open.
Group ofvoltage level pins for driving the LCD panel. Theycan either be connected to external
driving circuit for external bias supply or connected internally to built-in divider circuit. For internal voltage divider enable, a 0.1mF capacitor to VSS is required on each pin.
If internal voltage divider is enable with 1/7 bias selected, a capacitor to VSS is required on
each pin. Otherwise, pull these two pin to VSS
If internal divider circuit is enable, a capacitor is required to connect between these two pin
¾
If internal DC/DC Converter is enabled, a 0.1mF capacitor from this pin to VSS is required. It
can also be an external bias input pin if internal DC/DC converter is not used
This is a feedback path for the gain control (external contrast control) of VLL1 to VLL6. For ad
justing the LCD driving voltage, it requires a feedback resistor placed between VR and VF, a
¾
gain control resistor placed between VF and VSS, a 10uF capacitor placed between VR and
VSS.
VDDA is the positive supply to the noise sensitive circuitry and must have same voltage level
with VDD
HT0610
-
-
Rev. 1.10 5 April 4, 2007
HT0610
Absolute Maximum Ratings
Supply Voltage ..........................VSS-0.3V to VSS+4.0V
Input Voltage .............................V
3V to VDD+0.3V
SS-0.
LCD Input Voltage..................................-0.3V to 10.5V
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil
ity.
HT0610 contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it
is advised that normal precaution to be taken to avoid application of any voltage higher than maximum rated voltages to
this high impedance circuit. For proper operation it is recommended that V
<or=(V
or V
IN
) < or = VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate
OUT
logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. This device may be light sensitive?
caution should be taken to avoid exposure of this device to any light source during normal operation. This device is not
radiation protected.
Storage Temperature ...........................-65°Cto150°C
Operating Temperature ..........................-30°Cto85°C
and Vout be constrained to the range VSS
IN
-
Electrical Characteristics
Symbol Parameter
Supply Voltage
V
Supply Current
I
RW
I
ON1
I
ON2
I
STB1
I
STB2
I
STB3
I
ICON
Operating Voltage
DD
Read/write Mode
Supply Current Drain from Pin VDDA
and VDD
Display on Mode
Supply Current Drain from Pin VDDA
and VDD
Display on Mode
Supply Current Drain from Pin VDDA
and VDD
Standby Mode Supply Current Drain
from Pin VDDA and VDD
Standby Mode Supply Current Drain
from Pin VDDA and VDD
Standby Mode Supply Current Drain
from Pin VDDA and VDD
Standby Mode Supply Current Drain
from Pin VDDA and VDD
Test Conditions
V
DD
2.4V~
VDDA=VDD 2.4 3.15 3.5 V
3.5V
Conditions
Min. Typ. Max. Unit
Measure with VDD fixed at
3.15V
Internal DC/DC converter on,
2.4V~
display on, tripler enable,
3.5V
read/write accessing,
t
=1MHz, Osc freq.=50kHz,
CYC
¾
170 200
1/33 duty, 1/7 bias
Internal DC/DC converter on,
display on, tripler enable,
2.4V~
read/write HALT,
3.5V
Osc freq.=50kHz, 1/33 duty,
¾
110 140
1/7 bias
Internal DC/DC converter on,
display on, tripler enable,
2.4V~
read/write HALT,
3.5V
Osc freq.=38.4kHz, 1/33 duty,
¾
100 120
1/7 bias
2.4V~
Display off, oscillator disabled,
3.5V
read/write HALT
Display off, oscillator enabled,
2.4V~
read/write HALT, external os
3.5V
cillator and frequency=50kHz
Display off, oscillator enabled,
2.4V~
read/write HALT, internal oscil
3.5V
lator and frequency=50kHz
Low power I
2.4V~
tor enable, read/write HALT,
3.5V
internal oscillator and fre
CON
mode, oscilla
-
-
-
-
300 500 nA
¾
0.6 1
¾
23 30
¾
25 30
¾
quency=50kHz
Ta=25°C
mA
mA
mA
mA
mA
mA
Rev. 1.10 6 April 4, 2007
HT0610
Symbol Parameter
V
DD
VLCD Voltage (Absolute Value Referenced to VSS)
V
Generator Output Voltage at Pin
LCC1
VCCA1
LCD Driving Voltage
LCD Driving Voltage
V
Generator Output Voltage at Pin
LCC2
VCCA1
V
LCD Driving Voltage Input at Pin
LCD
VCCA1
2.4V~
3.5V
2.4V~
3.5V
2.4V~
3.5V
Output Voltage
V
V
V
V
Output High Voltage at Pin D0~D7,
OH1
ICON1~ICON4, IBP and OSC2
Output Low Voltage at Pin D0~D7,
OL1
ICON1~ICON4, IBP and OSC2
LCD Driving Voltage Source at PinVR2.4V~
R1
LCD Driving Voltage Source at PinVR2.4V~
R2
2.4V~
3.5V
2.4V~
3.5V
3.5V
3.5V
Input Voltage
V
CS, D0~D7, RW, DCOM, OSC1 and
IH1
OSC2
Input Low Voltage at Pin RES, CE,
Input High Voltage at Pin RES, CE,
V
CS, D0~D7, RW, DCOM, OSC1 and
IL1
OSC2
2.4V~
3.5V
2.4V~
3.5V
LCD Display Voltage
V
LL6
V
LL5
V
V
V
LCD Driving Voltage Output from Pin
LL4
VLL6~VLL2
LL3
LL2
2.4V~
3.5V
2.4V~
3.5V
2.4V~
3.5V
2.4V~
3.5V
2.4V~
3.5V
Test Conditions
Conditions
Display on, internal DC/DC
converter enable, tripler en
able, oscillator and fre
quency=50kHz, regulator
enable, divider enable
I
£100mA
OUT
Display on, internal DC/DC
converter enable, doubler en
able, oscillator and fre
quency=50kHz, regulator
enable, divider enable
I
£100mA
OUT
Internal DC/DC converter dis
able
I
=100mA
OUT
I
=100mA
OUT
Regulator enable, I
OUT
=50mA
Regulator disable
¾
¾
1/5 bias ratio, voltage divider
enable, regulator enable
Min. Typ. Max. Unit
-
-
¾ 3´VDD
10.5 V
-
-
¾ 2´VDD
5
0.8´
VDD
0
0
¾
0.8´
VDD
0
¾
¾
¾
¾
¾
Floating
¾
¾
VR
7V
10.5 V
VDD V
0.2´
VDD
VCCA1 V
¾
VDD V
0.2´
VDD
¾
¾ 0.8´VR ¾
¾ 0.6´VR ¾
¾ 0.4´VR ¾
¾ 0.2´VR ¾
V
V
V
V
V
V
V
V
Rev. 1.10 7 April 4, 2007
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