Before servicing this chassis, it is important that the service technician read the “Safety
Precautions” and “Product Safety Notices” in this service manual.
No.0240
«MODELNAMES»
L32VP03E
L32VP03U
Data contained within this Service
manual is subject to alteration for
improvement.
ATTENTION:
Avant d’effectuer l’entretien du châssis, le technicien doit lire les «Précautions de sécurité»
et les «Notices de sécurité du produit» présentés dans le présent manuel.
VORSICHT:
Vor Öffnen des Gehäuses hat der Service-Ingenieur die „Sicherheitshinweise“ und „Hinweise
zur Produktsicherheit“ in diesem Wartungshandbuch zu lesen.
Les données fournies dans le présent
manuel d’entretien peuvent faire l’objet
de modifications en vue de perfectionner
le produit.
Die in diesem Wartungshandbuch
enthaltenen Spezifikationen können sich
zwecks Verbesserungen ändern.
17MB35 Main Board consists of MSTAR concept. This IC is capable of handling Audio
processing, video processing, Scaling-Display processing, 3D comb filter, OSD and text
processing, 8 bit dual LVDS transmitter.
TV supports PAL, SECAM, NTSC colour standards and multiple transmission standards
as B/G, D/K, I/I’, and L/L’ including German and NICAM stereo.
Sound system output is supplying 2x10W (10%THD) for stereo 8
Supported peripherals are:
1 RF input VHF1, VHF3, UHF @ 75Ohm(Common)
1 Side AV (SVHS, CVBS, HP, R/L_Audio) (Common)
2 SCART sockets(Common)
1 YPbPr (Common)
1 PC input(Optional)
4 HDMI 1.3 input(2 HDMI inputs are common, 4 inputs are optional)
1 Stereo audio input for PC(Common)
1 Line out(Common)
1 Subwoofer out(Common)
1 S/PDIF output(Common)
1 Side S-Video(Optional)
1 Headphone(Common)
1 Common interface(Optional)
1 Digital USB(Opional)
1 Analog USB(Opional)
1 RS232(Optional)
1 Smart card connector(Optional)
speakers.
2. TUNER
A horizontal mounted and Digital Half-Nim tuner is used in the product, which covers 3
Bands(From 48MHz to 862MHz for COFDM, from 45.25MHz to 863.25MHz for CCIR
CH). The tuning is available through the digitally controlled I2C bus (PLL). Below you
will find info on the Tuner in use.
2.1.General description of TDTC-G101D:
The Tuner covers 3 Bands(from 48MHz to 862MHz for COFDM, from 45.25MHz to
863.25MHz for CCIR CH). Band selection and Tuning are performed digitally via the I2C
bus.
2.2.Features of TDTC-G101D:
x Digital Half-NIM tuner for COFDM
x Covers 3 Bands(From 48MHz to 862MHz for COFDM,
x From 45.25MHz to 863.25MHz for CCIR CH)
x Including IF AGC with SAW Filter
x Bandwidth Switching (7/8 MHz) possible
x DC/DC Converter built in for Tuning Voltage
x Internal(or External) RF AGC, Antenna Power Optional
2.3.Pinning:
3. AUDIO AMPLIFIER STAGE WITH MP7722
3.1.General Description
17MB35 uses a 20W Class D Stereo Single Ended Audio Amplifer for audio. The
MP7722 is a stereo 20W Class D Audio Amplif
fully integrated audio amplifiers which dramatically reduces solution size by integrating
the following:
x 180mSRZHU026)(7V
x Startup / Shutdown pop elimination
x Short circuit protection
x Mute / Standby
The MP7722 utilizes a single ended output structure capable of delivering 2 x 20W into
4 speakers. MPS Class D Audio Amplifiers exhibit the high fidelity of a Class A/B
amplifier at efficiencies greater than 90%. The circuit is based on the MPS’ proprietary
variable frequency topology that delivers low distortion, fast response time and operates
on a single power supply.
3.2.Features
x 2 x 20W Output at VDD = 24V into a 4ORDG
x THD+N = 0.06% at 1W, 8
x 93% Efficiency at 20W
ier. It is one of MPS’ second generation of
x Low Noise (190μV Typical)
x Switching Frequency Up to 1MHz
x 9.5V to 24V Operation from a Single Supply
x Integrated Startup and Shutdown Pop Elimination Circuit
x Thermal and Short Circuit Protection
x Integrated 180m6ZLWFKHV
x Mute/Standby Modes (Sleep)
x Thermally Enhanced 20-Pin TSSOP Package with Exposed Pad
3.3.Applications
x Surround Sound DVD Systems
x Televisions
x Flat Panel Monitors
x Multimedia Computers
x Home Stereo Systems
3.4.Absolute Ratings
3.4.1.Electrical Characteristics
3.4.2.Operating Specifications
3.5.Pinning
4. POWER STAGE
The DC voltages required at various parts of the chassis and inverters are provided by a
main power supply unit. The power supply generates 33V, 24V, 12V, 5V, 3,3V and 5V,
3,3V stand by mode DC voltages. Power stage which is on-chasis generates 1,26V
stand by voltage and 8V, 2,6V, 1,8V and 1V supplies for other different parts of the
chassis.
5. MICROCONTROLLER (MSTAR)
5.1.General Descripction
The MST6WB7GQ-3 is a high performance and fully integrated IC for multifunction LCD monitor/TV with resolutions up to full HD (1920x1080). It is
configured with an integrated triple-ADC/PLL, an integrated DVI/HDCP/HDMI
receiver, a multi-standard TV video and audio decoder, two video de-interlacers, two
scaling engines, the MStarACE-3 color engine, an on-screen display controller, an 8-bit
MCU and a built-in output panel interface. By use of external frame buffer, PIP/POP is
provided for multimedia applications. Furthermore, 3-D video decoding and processing
are fulfilled for high-quality TV applications. To further reduce system costs, the
MST6WB7GQ-3 also integrates intelligent power management control capability for
green-mode requirements and spread-spectrum support for EMI management.
5.2.General Features
LCD TV controller with PIP/POP display functions
x Input supports up to UXGA & 1080P
x Panel supports up to full HD (1920x1080)
x TV decoder with 3-D comb filter
x Multi-standard TV sound demodulator and decoder
x 10-bit triple-ADC for TV and RGB/YPbPr
x 10-bit video data processing
x Integrated DVI/HDCP/HDMI compliant receiver
x High-quality dual scaling engines & dual 3-D video de-interlacers
x 3-D video noise reduction
x Full function PIP/PBP/POP
x MStarACE-3 picture/color processing engine
x Embedded On-Screen Display (OSD) controler engine
x Built-in MCU supports PWM & GPIO
x Built-in dual-link 8/10-bit LVDS transmitter
x 5-volt tolerant inputs
x Low EMI and power saving features
x 296-pin LQFP
NTSC/PAL/SECAM Video Decoder
x Supports NTSC M, NTSC-J, NTSC-4.43, PAL (B,D,G,H,M,N,I,Nc), and SECAM
x Automatic TV standard detection
x Motion adaptive 3-D comb filter for NTSC/PAL
x 8 configurable CVBS & Y/C S-video inputs
x Supports Teletext level-1.5, WSS, VPS, Closed-caption, and V-chip
x Macrovision detection
x CVBS video output
Video IF for Multi-Standard Analog TV
x Digital low IF architecture
x Stepped-gain PGA with 26 dB tuning range and 1 dB tuning resolution
x Maximum IF analog gain of 37dB in addition to digital gain
x Programmable TOP to accommodate different tuner gain to optimize noise and
linearity performance
Multi-Standard TV Sound Decoder
x Supports BTSC/NICAM/A2/EIA-J demodulation and decoding
x FM stereo & SAP demodulation
x L/Rx4, mono, and SIF audio inputs
x L/Rx3 loudspeaker and line outputs
x Supports sub-woofer output
x Built-in audio output DAC’s
x Audio processing for loudspeaker channel, including volume, balance, mute,
tone, EQ, and virtual stereo/surround
x Optional advanced surround available (Dolby1, SRS2, BBE3… etc)
Digital Audio Interface
x I2S digital audio input & output
x S/PDIF digital audio input & output
x HDMI audio channel processing capability
x Programmable delay for audio/video synchronization
Analog RGB Compliant Input Ports
x Three analog ports support up to UXGA
x Supports HDTV RGB/YPbPr/YCbCr
x Supports Composite Sync and SOG (Sync-on-Green) separator
x Automatic color calibration
DVI/HDCP/HDMI Compliant Input Port
x Two HDMI input ports with built-in switch
x Supports TMDS clock up to 225MHz @ 1080P 60Hz with 12-bit deep-color
resolution
x Single link on-chip DVI 1.0 compliant receiver
x High-bandwidth Digital Content Protection(HDCP) 1.1 compliant receiver
6. SIL9185 3:1 HDMI 1.3 Switch
6.1.General Desription
The SiI9185A is the first generation of TMDS switch device supporting Revision 1.3 of
the HDMI Specification (HDMI Consortium; June 2006). With three HDMI inputs and a
single output, the SiI9185A provides a low-cost method of adding additional HDMI ports
to the latest Digital TVs. New DTVs can easily connect to the many HDMI sources
coming on the market, including DVDs, STB, game consoles, PCs, camcorders, and
digital still cameras. The SiI9185A is a fully HDMI compliant device providing a simple,
lowcost method of retransmitting protected digital audio and video, giving end-users a
truly all-digital experience. Built-in backward compatibility with DVI 1.0 allows HDMI
systems to connect to any DVI 1.0 source. The SiI9185A provides additional integrated
features to help lower system cost and provide enhanced features to the end consumer.
To lower system cost, the SiI9185A provides a complete solution for switching sink-side
HDMI signals. This includes DDC switching, individual HPD control, and 5V sense. The
addition of these features eliminates additional external components, helping to lower
cost. For source-side applications, the SiI9185A DDC switching can be bypassed with
an external 4-channel I2C-bus switch(e.g., Texas Instruments PCA95445) to allow clock
stretching.
6.2.Features
x Three-input, single-output HDMI switcher
x Integrated TMDS® receiver and transmi
transmitting 2.25Gbps:
x Support 60Hz, 12-bit or 720p/1080i, 120Hz, 12-bit
x Buil
x Pre-emphasi
x DVI 1.0, HDCP 1.1 and HDMI compliant receiver and transmitter
x Uses HDMI-compliant TMDS core recovery and retransmission, unlike TMDS
x Built-in Cons support:
x HDM
x Integra
dable support even at deep-color resolutions
s
switches, which use high-spee
I lowers cost for adding CEC support to DTV
l requirements on system microcontroller speeds design
d analog switches and degrade TMDS signals
t cores capable of receiving and
6.3.Absolute Maximum Ratings
6.4.Pinning
Configuration Pins
7. QAM DEMODULATOR – STV0297E
7.1.General Desription
The STV0297E is a complete single-chip QAM (quadrature amplitude modulation)
demodulation and FEC (forward error correction) solution that performs sampled IF to
transport stream (MPEG-2 or MPEG-4) block processing of QAM signals. It is intended
for the digital transmission of compressed television, sound, and data services over
cable. It is fully compliant with ITU-T J83 Annexes A/C or DVB-C specification
bitstreams (ETS 300 429, “Digital broadcasting systems for television, sound and data
services – Framing structure, channel coding and modulation - Cable Systems”). It can
handle square (16, 64, 256-QAM) and non-square (32, 128-QAM) constellations.
Japanese DBS systems require a transport stream multiplex frame (TSMF) layer to
carry digital signals over cable systems. When the recovered transport stream is a
multiplex frame, the STV0297E post-processes it to extract a single transport stream.
Automatic detection of the TSMF layer is provided. The chip integrates an analog-todigital converter that delivers the required performance to handle up to 256-QAM signals
in a direct IF sampling architecture, thus eliminating the need for external
downconversion.
7.2.Features
x Decodes ITU-T J.83-Annexes A/C and DVB-C bit streams
x Processes Japanese transport stream multiplex frame (TSMF)
x High-performance integrated A/D converter suitable for direct IF architecture in all
QAM (quadrature amplitude modulation) modes
x Supports 16, 32, 64, 128 and 256 point constellations
x Small footprint package: (10 x 10 mm²)
x Very low power consumption
x Full digital demodulation
x Variable symbol rates
x Front derotator for better low symbol rate performance and relaxed tuner
constraints
x Integrated matched filtering
x Robust integrated adaptive pre and post equalizer
x On-chip FEC A/C with ability to bypass individual blocks
x 10 programmable GPIO
x Two AGC outputs suitable for delayed AGC applications (sigma-delta outputs)
x Integrated signal quality monitors, plus lock indicator and interrupt function
mapped to GPIO pin
x Improved signal acquisition
x System clock generated on-chip from quartz crystal
x Low frequency crystal operations 4, 16, 25 - 30 MHz
x 4 I2C addresses
x Easy control and monitoring via 2-wire fast I2C bus
7.3.Absolute Maximum Ratings
7.4.Pinning
8. HY5DV281622DT-5 DDR SDRAM 128M
8.1.General Description
The Hynix HY5DV281622 is a 134,217,728-bit CMOS Double Data Rate(DDR)
Synchronous DRAM, ideally suited for the point-to-point applications which requires high
bandwidth. The Hynix 8Mx16 DDR SDRAMs offer fully synchronous operations
referenced to both rising and falling edges of the clock. While all addresses and control
inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,Data
strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 2-bit prefetched to achieve very high
bandwidth. All input and output voltage levels are compatible with SSTL_2.
8.2.Features
x 3.3V for VDD and 2.5V for VDDQ power supply
x All inputs and outputs are compatible with SSTL_2 interface
x JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch
x Fully differential clock inputs (CK, /CK) operation
x Double data rate interface
x Source synchronous - data transaction aligned to bidirectional data strobe (DQS)
x x16 device has 2 bytewide data strobes (LDQS, UDQS) per each x8 I/O
x Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers
when write (centered DQ)
x Data(DQ) and Write masks(DM) latched on the both rising and falling edges of
the data strobe
x All addresses and control inputs except Data, Data strobes and Data masks
latched on the rising edges of the clock
x Write mask byte controls by LDM and UDM
x Programmable /CAS latency 3 / 4 supported
x Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode
x Internal 4 bank operations with single pulsed /RAS
x tRAS Lock-Out function supported
x Auto refresh and self refresh supported
x 4096 refresh cycles / 32ms
x Full, Half and Matched Impedance(Weak) strength driver option controlled by
EMRS
8.3.Absolute Maximum Ratings
8.4.Pinning
9. IS42S16100C1 SDRAM
9.1.General Description
ISSI’s 16Mb Synchronous DRAM IS42S16100C1 is organized as a 524,288-word x 16bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed
data transfer using pipeline architecture. All inputs and outputs signals refer to the rising
edge of the clock input.
9.2.Features
x Clock frequency: 200, 166, 143 MHz
x Fully synchronous; all signals referenced to a positive clock edge
x Two banks can be operated simultaneously and independently
x Dual internal bank controlled by A11 (bank select)
x Single 3.3V power supply
x LVTTL interface
x Programmable burst length (1, 2, 4, 8, full page)
x Programmable burst sequence:Sequential/Interleave
x 4096 refresh cycles every 64 ms
x Random column address every clock cycle
x Programmable CAS latency (2, 3 clocks)
x Burst read/write and burst read/single write operations capability
x Burst termination by burst stop and precharge command
x Byte controlled by LDQM and UDQM
x Industrial temperature up to 143 MHz
x Packages 400-mil 50-pin TSOP-II, 60-ball fBGA
x Lead-free package option
9.3.Pinning
10.SAW FILTER
10.1. IF Filter for Audio Applications – Epcos K9656M
10.1.1.Standart:
xB/G
xD/K
xI
xL/L’
10.1.2.Features:
x TV IF audio filter with two channels
x Channel 1 (L’) with one pass band for sound carriers at 40,40 MHz (L’) and 39,75
MHz (L’- NICAM)
x Channel 2 (B/G,D/K,L,I) with one pass band for sound carriers between 32,35
The 24LC01/02 is a 1K/2K-bit serial read/write non-volatile memory device using the
CMOS floating gate process. Its 1024/2048 bits of memory are organized into 128/256
words and each word is 8 bits. The device is optimized for use in many industrial and
commercial applications where low power and low voltage operation are essential. Up to
eight HT24LC01/02 devices may be connected to the same two-wire bus. The
HT24LC01/02 is guaranteed for 1M erase/write cycles and 40-year data retention.
11.2. Features
x Operating voltage: 2.4V~5.5V
x Low power consumption
x Operation: 5mA max.
x Standby: 5mA max.
x Internal organization
x 1K (HT24LC01):128´8
x 2K (HT24LC02): 256´8
x 2-wire serial interface
x Write cycle time: 5ms max.
x Automatic erase-before-write operation
x Partial page write allowed
x 8-byte Page write modes
x Write operation with built-in timer
x Hardware controlled write protection
x 40-year data retention
x 106 erase/write cycles per word
x 8-pin DIP/SOP package
x 8-pin TSSOP (HT24LC02 only)
x Commerical temperature range (0°C to +70°C)
11.3. Electrical Specifications
11.4. Pinning
12.32K Smart Serial EEPROM – 24C32
12.1. General Description
The Microchip Technology Inc. 24C32 is a 4K x 8 (32K bit) Serial Electrically Erasable
PROM. This device has been developed for advanced, low power applications such as
personal communications or data acquisition. The 24C32 features an input cache for
fast write loads with a capacity of eight 8-byte pages, or 64 bytes. It also features a fixed
4K-bit block of ultra-high endurance memory for data that changes frequently. The
24C32 is capable of both random and sequential reads up to the 32K boundary.
Functional address lines allow up to eight 24C32 devices on the same bus, for up to
256K bits address space. Advanced CMOS technology makes this device ideal for lowpower non-volatile code and data applications. The 24C32 is available in the standard 8pin plastic DIP and 8-pin surface mount SOIC package.
12.2. Features
x Voltage operating range: 4.5V to 5.5V
x Peak write current 3 mA at 5.5V
x Maximum read current 150 μA at 5.5V
x Standby current 1 μA typical
x Industry standard two-wire bus protocol, I2C compatible
x Including 100 kHz and 400 kHz modes
x Self-timed write cycle (including auto-erase)
x Power on/off data protection circuitry
x Endurance: 10,000,000 Erase/Write cycles guaranteed for High Endurance
Block, 1,000,000 E/W cycles guaranteed for Standard Endurance Block
x 8 byte page, or byte modes available
x 1 page x 8 line input cache (64 bytes) for fast write loads
x Schmitt trigger, filtered inputs for noise suppression
x Output slope control to eliminate ground bounce
x 2 ms typical write cycle time, byte or page
x Up to 8 chips may be connected to the same bus for up to 256K bits total
memory
x Electrostatic discharge protection > 4000V
x Data retention > 200 years
x 8-pin PDIP/SOIC packages
x Temperature ranges: Commercial (C): 0°C to +70°C, Industrial (I): -40°C to
+85°C
12.3Absolute Maximum Ratings and Electrical Characteristics
12.4Pinning
13.512K CMOS Serial Flash – MX25L512
13.1. General Description
The MX25L512 is a CMOS 524,288 bit serial Flash memory, which is configured as
65,536 x 8 internally. The MX25L512 feature a serial peripheral interface and software
protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock
input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the
device is enabled by CS# input. The MX25L512 provide sequential read operation on
whole chip. After program/erase command is issued, auto program/ erase algorithms
which program/ erase and verify the specified page or sector/block locations will be
executed. Program command is executed on page (256 bytes) basis, and erase
command is executes on chip or sector (4K-bytes). To provide user with ease of
interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via
WIP bit. When the device is not in operation and CS# is high, it is put in standby mode
and draws less than 10uA DC current. The MX25L512 utilize MXIC's proprietary
memory cell, which reliably stores memory contents even after 100,000 program and
erase cycles.
13.2. Features
GENERAL
x Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3
x 524,288 x 1 bit structure
x 16 Equal Sectors with 4K byte each
x Any Sector can be erased individually
x Single Power Supply Operation
x 2.7 to 3.6 volt for read, erase, and program operations
x Latch-up protected to 100mA from -1V to Vcc +1V
x Low Vcc write inhibit is from 1.5V to 2.5V
PERFORMANCE
x High Performance
x Fast access time: 85MHz serial clock (15pF + 1TTL Load) and 66MHz serial
clock (30pF + 1TTL Load)
x Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
x Fast erase time: 60ms(typ.) and 120ms(max.)/sector (4K-byte per sector) ;
1s(typ.) and 2s(max.)/chip(512Kb)
x Low Power Consumption
x Low active read current: 12mA(max.) at 85MHz, 8mA(max.) at 66MHz and
4mA(max.) at 33MHz
x Low active programming current: 15mA (max.)
x Low active erase current: 15mA (max.)
x Low standby current: 10uA (max.)
x Deep power-down mode 1uA (typical)
x Minimum 100,000 erase/program cycles
SOFTWARE FEATURES
x Input Data Format
x 1-byte Command code
x Block Lock protection
x The BP0~BP1 status bit defines the size of the area to be software protected
against Program and Erase instructions.
x Auto Erase and Auto Program Algorithm
x Automatically erases and verifies data at selected sector
x Automatically programs and verifies data at selected page by an internal
algorithm that automatically times the program pulse widths (Any page to be
programed should have page in the erased state first)
x Status Register Feature
x Electronic Identification
x JEDEC 2-byte Device ID
x RES command, 1-byte Device ID
HARDWARE FEATURES
x SCLK Input
x Serial clock input
x SI Input
x Serial Data Input
x SO Output
x Serial Data Output
x WP# pin
x Hardware write protection
x HOLD# pin pause the chip without diselecting the chip
x PACKAGE
x 8-pin SOP (150mil)
x All Pb-free devices are RoHS Compliant
13.3Absolute Maximum Ratings
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