Before servicing this chassis, it is important that the service technician read the “Safety
Precautions” and “Product Safety Notices” in this service manual.
No.0240
«MODELNAMES»
L32VP03E
L32VP03U
Data contained within this Service
manual is subject to alteration for
improvement.
ATTENTION:
Avant d’effectuer l’entretien du châssis, le technicien doit lire les «Précautions de sécurité»
et les «Notices de sécurité du produit» présentés dans le présent manuel.
VORSICHT:
Vor Öffnen des Gehäuses hat der Service-Ingenieur die „Sicherheitshinweise“ und „Hinweise
zur Produktsicherheit“ in diesem Wartungshandbuch zu lesen.
Les données fournies dans le présent
manuel d’entretien peuvent faire l’objet
de modifications en vue de perfectionner
le produit.
Die in diesem Wartungshandbuch
enthaltenen Spezifikationen können sich
zwecks Verbesserungen ändern.
17MB35 Main Board consists of MSTAR concept. This IC is capable of handling Audio
processing, video processing, Scaling-Display processing, 3D comb filter, OSD and text
processing, 8 bit dual LVDS transmitter.
TV supports PAL, SECAM, NTSC colour standards and multiple transmission standards
as B/G, D/K, I/I’, and L/L’ including German and NICAM stereo.
Sound system output is supplying 2x10W (10%THD) for stereo 8
Supported peripherals are:
1 RF input VHF1, VHF3, UHF @ 75Ohm(Common)
1 Side AV (SVHS, CVBS, HP, R/L_Audio) (Common)
2 SCART sockets(Common)
1 YPbPr (Common)
1 PC input(Optional)
4 HDMI 1.3 input(2 HDMI inputs are common, 4 inputs are optional)
1 Stereo audio input for PC(Common)
1 Line out(Common)
1 Subwoofer out(Common)
1 S/PDIF output(Common)
1 Side S-Video(Optional)
1 Headphone(Common)
1 Common interface(Optional)
1 Digital USB(Opional)
1 Analog USB(Opional)
1 RS232(Optional)
1 Smart card connector(Optional)
speakers.
2. TUNER
A horizontal mounted and Digital Half-Nim tuner is used in the product, which covers 3
Bands(From 48MHz to 862MHz for COFDM, from 45.25MHz to 863.25MHz for CCIR
CH). The tuning is available through the digitally controlled I2C bus (PLL). Below you
will find info on the Tuner in use.
2.1.General description of TDTC-G101D:
The Tuner covers 3 Bands(from 48MHz to 862MHz for COFDM, from 45.25MHz to
863.25MHz for CCIR CH). Band selection and Tuning are performed digitally via the I2C
bus.
2.2.Features of TDTC-G101D:
x Digital Half-NIM tuner for COFDM
x Covers 3 Bands(From 48MHz to 862MHz for COFDM,
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x From 45.25MHz to 863.25MHz for CCIR CH)
x Including IF AGC with SAW Filter
x Bandwidth Switching (7/8 MHz) possible
x DC/DC Converter built in for Tuning Voltage
x Internal(or External) RF AGC, Antenna Power Optional
2.3.Pinning:
3. AUDIO AMPLIFIER STAGE WITH MP7722
3.1.General Description
17MB35 uses a 20W Class D Stereo Single Ended Audio Amplifer for audio. The
MP7722 is a stereo 20W Class D Audio Amplif
fully integrated audio amplifiers which dramatically reduces solution size by integrating
the following:
x 180mSRZHU026)(7V
x Startup / Shutdown pop elimination
x Short circuit protection
x Mute / Standby
The MP7722 utilizes a single ended output structure capable of delivering 2 x 20W into
4 speakers. MPS Class D Audio Amplifiers exhibit the high fidelity of a Class A/B
amplifier at efficiencies greater than 90%. The circuit is based on the MPS’ proprietary
variable frequency topology that delivers low distortion, fast response time and operates
on a single power supply.
3.2.Features
x 2 x 20W Output at VDD = 24V into a 4ORDG
x THD+N = 0.06% at 1W, 8
x 93% Efficiency at 20W
ier. It is one of MPS’ second generation of
Page 9
x Low Noise (190μV Typical)
x Switching Frequency Up to 1MHz
x 9.5V to 24V Operation from a Single Supply
x Integrated Startup and Shutdown Pop Elimination Circuit
x Thermal and Short Circuit Protection
x Integrated 180m6ZLWFKHV
x Mute/Standby Modes (Sleep)
x Thermally Enhanced 20-Pin TSSOP Package with Exposed Pad
3.3.Applications
x Surround Sound DVD Systems
x Televisions
x Flat Panel Monitors
x Multimedia Computers
x Home Stereo Systems
3.4.Absolute Ratings
3.4.1.Electrical Characteristics
Page 10
3.4.2.Operating Specifications
3.5.Pinning
Page 11
4. POWER STAGE
The DC voltages required at various parts of the chassis and inverters are provided by a
main power supply unit. The power supply generates 33V, 24V, 12V, 5V, 3,3V and 5V,
3,3V stand by mode DC voltages. Power stage which is on-chasis generates 1,26V
stand by voltage and 8V, 2,6V, 1,8V and 1V supplies for other different parts of the
chassis.
5. MICROCONTROLLER (MSTAR)
5.1.General Descripction
The MST6WB7GQ-3 is a high performance and fully integrated IC for multifunction LCD monitor/TV with resolutions up to full HD (1920x1080). It is
configured with an integrated triple-ADC/PLL, an integrated DVI/HDCP/HDMI
receiver, a multi-standard TV video and audio decoder, two video de-interlacers, two
scaling engines, the MStarACE-3 color engine, an on-screen display controller, an 8-bit
MCU and a built-in output panel interface. By use of external frame buffer, PIP/POP is
provided for multimedia applications. Furthermore, 3-D video decoding and processing
are fulfilled for high-quality TV applications. To further reduce system costs, the
MST6WB7GQ-3 also integrates intelligent power management control capability for
green-mode requirements and spread-spectrum support for EMI management.
5.2.General Features
LCD TV controller with PIP/POP display functions
x Input supports up to UXGA & 1080P
x Panel supports up to full HD (1920x1080)
x TV decoder with 3-D comb filter
x Multi-standard TV sound demodulator and decoder
x 10-bit triple-ADC for TV and RGB/YPbPr
x 10-bit video data processing
x Integrated DVI/HDCP/HDMI compliant receiver
x High-quality dual scaling engines & dual 3-D video de-interlacers
x 3-D video noise reduction
x Full function PIP/PBP/POP
x MStarACE-3 picture/color processing engine
x Embedded On-Screen Display (OSD) controler engine
x Built-in MCU supports PWM & GPIO
x Built-in dual-link 8/10-bit LVDS transmitter
x 5-volt tolerant inputs
x Low EMI and power saving features
x 296-pin LQFP
NTSC/PAL/SECAM Video Decoder
x Supports NTSC M, NTSC-J, NTSC-4.43, PAL (B,D,G,H,M,N,I,Nc), and SECAM
x Automatic TV standard detection
x Motion adaptive 3-D comb filter for NTSC/PAL
Page 12
x 8 configurable CVBS & Y/C S-video inputs
x Supports Teletext level-1.5, WSS, VPS, Closed-caption, and V-chip
x Macrovision detection
x CVBS video output
Video IF for Multi-Standard Analog TV
x Digital low IF architecture
x Stepped-gain PGA with 26 dB tuning range and 1 dB tuning resolution
x Maximum IF analog gain of 37dB in addition to digital gain
x Programmable TOP to accommodate different tuner gain to optimize noise and
linearity performance
Multi-Standard TV Sound Decoder
x Supports BTSC/NICAM/A2/EIA-J demodulation and decoding
x FM stereo & SAP demodulation
x L/Rx4, mono, and SIF audio inputs
x L/Rx3 loudspeaker and line outputs
x Supports sub-woofer output
x Built-in audio output DAC’s
x Audio processing for loudspeaker channel, including volume, balance, mute,
tone, EQ, and virtual stereo/surround
x Optional advanced surround available (Dolby1, SRS2, BBE3… etc)
Digital Audio Interface
x I2S digital audio input & output
x S/PDIF digital audio input & output
x HDMI audio channel processing capability
x Programmable delay for audio/video synchronization
Analog RGB Compliant Input Ports
x Three analog ports support up to UXGA
x Supports HDTV RGB/YPbPr/YCbCr
x Supports Composite Sync and SOG (Sync-on-Green) separator
x Automatic color calibration
DVI/HDCP/HDMI Compliant Input Port
x Two HDMI input ports with built-in switch
x Supports TMDS clock up to 225MHz @ 1080P 60Hz with 12-bit deep-color
resolution
x Single link on-chip DVI 1.0 compliant receiver
x High-bandwidth Digital Content Protection(HDCP) 1.1 compliant receiver
Page 13
6. SIL9185 3:1 HDMI 1.3 Switch
6.1.General Desription
The SiI9185A is the first generation of TMDS switch device supporting Revision 1.3 of
the HDMI Specification (HDMI Consortium; June 2006). With three HDMI inputs and a
single output, the SiI9185A provides a low-cost method of adding additional HDMI ports
to the latest Digital TVs. New DTVs can easily connect to the many HDMI sources
coming on the market, including DVDs, STB, game consoles, PCs, camcorders, and
digital still cameras. The SiI9185A is a fully HDMI compliant device providing a simple,
lowcost method of retransmitting protected digital audio and video, giving end-users a
truly all-digital experience. Built-in backward compatibility with DVI 1.0 allows HDMI
systems to connect to any DVI 1.0 source. The SiI9185A provides additional integrated
features to help lower system cost and provide enhanced features to the end consumer.
To lower system cost, the SiI9185A provides a complete solution for switching sink-side
HDMI signals. This includes DDC switching, individual HPD control, and 5V sense. The
addition of these features eliminates additional external components, helping to lower
cost. For source-side applications, the SiI9185A DDC switching can be bypassed with
an external 4-channel I2C-bus switch(e.g., Texas Instruments PCA95445) to allow clock
stretching.
6.2.Features
x Three-input, single-output HDMI switcher
x Integrated TMDS® receiver and transmi
transmitting 2.25Gbps:
x Support 60Hz, 12-bit or 720p/1080i, 120Hz, 12-bit
x Buil
x Pre-emphasi
x DVI 1.0, HDCP 1.1 and HDMI compliant receiver and transmitter
x Uses HDMI-compliant TMDS core recovery and retransmission, unlike TMDS
x Built-in Cons support:
x HDM
x Integra
dable support even at deep-color resolutions
s
switches, which use high-spee
I lowers cost for adding CEC support to DTV
l requirements on system microcontroller speeds design
d analog switches and degrade TMDS signals
t cores capable of receiving and
6.3.Absolute Maximum Ratings
Page 14
6.4.Pinning
Configuration Pins
Page 15
7. QAM DEMODULATOR – STV0297E
7.1.General Desription
The STV0297E is a complete single-chip QAM (quadrature amplitude modulation)
demodulation and FEC (forward error correction) solution that performs sampled IF to
transport stream (MPEG-2 or MPEG-4) block processing of QAM signals. It is intended
for the digital transmission of compressed television, sound, and data services over
cable. It is fully compliant with ITU-T J83 Annexes A/C or DVB-C specification
bitstreams (ETS 300 429, “Digital broadcasting systems for television, sound and data
services – Framing structure, channel coding and modulation - Cable Systems”). It can
handle square (16, 64, 256-QAM) and non-square (32, 128-QAM) constellations.
Page 16
Japanese DBS systems require a transport stream multiplex frame (TSMF) layer to
carry digital signals over cable systems. When the recovered transport stream is a
multiplex frame, the STV0297E post-processes it to extract a single transport stream.
Automatic detection of the TSMF layer is provided. The chip integrates an analog-todigital converter that delivers the required performance to handle up to 256-QAM signals
in a direct IF sampling architecture, thus eliminating the need for external
downconversion.
7.2.Features
x Decodes ITU-T J.83-Annexes A/C and DVB-C bit streams
x Processes Japanese transport stream multiplex frame (TSMF)
x High-performance integrated A/D converter suitable for direct IF architecture in all
QAM (quadrature amplitude modulation) modes
x Supports 16, 32, 64, 128 and 256 point constellations
x Small footprint package: (10 x 10 mm²)
x Very low power consumption
x Full digital demodulation
x Variable symbol rates
x Front derotator for better low symbol rate performance and relaxed tuner
constraints
x Integrated matched filtering
x Robust integrated adaptive pre and post equalizer
x On-chip FEC A/C with ability to bypass individual blocks
x 10 programmable GPIO
x Two AGC outputs suitable for delayed AGC applications (sigma-delta outputs)
x Integrated signal quality monitors, plus lock indicator and interrupt function
mapped to GPIO pin
x Improved signal acquisition
x System clock generated on-chip from quartz crystal
x Low frequency crystal operations 4, 16, 25 - 30 MHz
x 4 I2C addresses
x Easy control and monitoring via 2-wire fast I2C bus
7.3.Absolute Maximum Ratings
Page 17
7.4.Pinning
8. HY5DV281622DT-5 DDR SDRAM 128M
8.1.General Description
The Hynix HY5DV281622 is a 134,217,728-bit CMOS Double Data Rate(DDR)
Synchronous DRAM, ideally suited for the point-to-point applications which requires high
bandwidth. The Hynix 8Mx16 DDR SDRAMs offer fully synchronous operations
referenced to both rising and falling edges of the clock. While all addresses and control
inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,Data
strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 2-bit prefetched to achieve very high
bandwidth. All input and output voltage levels are compatible with SSTL_2.
Page 18
8.2.Features
x 3.3V for VDD and 2.5V for VDDQ power supply
x All inputs and outputs are compatible with SSTL_2 interface
x JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch
x Fully differential clock inputs (CK, /CK) operation
x Double data rate interface
x Source synchronous - data transaction aligned to bidirectional data strobe (DQS)
x x16 device has 2 bytewide data strobes (LDQS, UDQS) per each x8 I/O
x Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers
when write (centered DQ)
x Data(DQ) and Write masks(DM) latched on the both rising and falling edges of
the data strobe
x All addresses and control inputs except Data, Data strobes and Data masks
latched on the rising edges of the clock
x Write mask byte controls by LDM and UDM
x Programmable /CAS latency 3 / 4 supported
x Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode
x Internal 4 bank operations with single pulsed /RAS
x tRAS Lock-Out function supported
x Auto refresh and self refresh supported
x 4096 refresh cycles / 32ms
x Full, Half and Matched Impedance(Weak) strength driver option controlled by
EMRS
8.3.Absolute Maximum Ratings
Page 19
8.4.Pinning
9. IS42S16100C1 SDRAM
9.1.General Description
ISSI’s 16Mb Synchronous DRAM IS42S16100C1 is organized as a 524,288-word x 16bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed
data transfer using pipeline architecture. All inputs and outputs signals refer to the rising
edge of the clock input.
9.2.Features
x Clock frequency: 200, 166, 143 MHz
x Fully synchronous; all signals referenced to a positive clock edge
x Two banks can be operated simultaneously and independently
Page 20
x Dual internal bank controlled by A11 (bank select)
x Single 3.3V power supply
x LVTTL interface
x Programmable burst length (1, 2, 4, 8, full page)
x Programmable burst sequence:Sequential/Interleave
x 4096 refresh cycles every 64 ms
x Random column address every clock cycle
x Programmable CAS latency (2, 3 clocks)
x Burst read/write and burst read/single write operations capability
x Burst termination by burst stop and precharge command
x Byte controlled by LDQM and UDQM
x Industrial temperature up to 143 MHz
x Packages 400-mil 50-pin TSOP-II, 60-ball fBGA
x Lead-free package option
9.3.Pinning
10.SAW FILTER
10.1. IF Filter for Audio Applications – Epcos K9656M
10.1.1.Standart:
xB/G
xD/K
xI
xL/L’
10.1.2.Features:
x TV IF audio filter with two channels
x Channel 1 (L’) with one pass band for sound carriers at 40,40 MHz (L’) and 39,75
MHz (L’- NICAM)
x Channel 2 (B/G,D/K,L,I) with one pass band for sound carriers between 32,35
The 24LC01/02 is a 1K/2K-bit serial read/write non-volatile memory device using the
CMOS floating gate process. Its 1024/2048 bits of memory are organized into 128/256
words and each word is 8 bits. The device is optimized for use in many industrial and
commercial applications where low power and low voltage operation are essential. Up to
eight HT24LC01/02 devices may be connected to the same two-wire bus. The
HT24LC01/02 is guaranteed for 1M erase/write cycles and 40-year data retention.
11.2. Features
x Operating voltage: 2.4V~5.5V
x Low power consumption
x Operation: 5mA max.
x Standby: 5mA max.
x Internal organization
x 1K (HT24LC01):128´8
x 2K (HT24LC02): 256´8
x 2-wire serial interface
x Write cycle time: 5ms max.
x Automatic erase-before-write operation
x Partial page write allowed
x 8-byte Page write modes
x Write operation with built-in timer
x Hardware controlled write protection
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x 40-year data retention
x 106 erase/write cycles per word
x 8-pin DIP/SOP package
x 8-pin TSSOP (HT24LC02 only)
x Commerical temperature range (0°C to +70°C)
11.3. Electrical Specifications
Page 25
11.4. Pinning
12.32K Smart Serial EEPROM – 24C32
12.1. General Description
The Microchip Technology Inc. 24C32 is a 4K x 8 (32K bit) Serial Electrically Erasable
PROM. This device has been developed for advanced, low power applications such as
personal communications or data acquisition. The 24C32 features an input cache for
fast write loads with a capacity of eight 8-byte pages, or 64 bytes. It also features a fixed
4K-bit block of ultra-high endurance memory for data that changes frequently. The
24C32 is capable of both random and sequential reads up to the 32K boundary.
Functional address lines allow up to eight 24C32 devices on the same bus, for up to
256K bits address space. Advanced CMOS technology makes this device ideal for lowpower non-volatile code and data applications. The 24C32 is available in the standard 8pin plastic DIP and 8-pin surface mount SOIC package.
12.2. Features
x Voltage operating range: 4.5V to 5.5V
x Peak write current 3 mA at 5.5V
x Maximum read current 150 μA at 5.5V
x Standby current 1 μA typical
x Industry standard two-wire bus protocol, I2C compatible
x Including 100 kHz and 400 kHz modes
Page 26
x Self-timed write cycle (including auto-erase)
x Power on/off data protection circuitry
x Endurance: 10,000,000 Erase/Write cycles guaranteed for High Endurance
Block, 1,000,000 E/W cycles guaranteed for Standard Endurance Block
x 8 byte page, or byte modes available
x 1 page x 8 line input cache (64 bytes) for fast write loads
x Schmitt trigger, filtered inputs for noise suppression
x Output slope control to eliminate ground bounce
x 2 ms typical write cycle time, byte or page
x Up to 8 chips may be connected to the same bus for up to 256K bits total
memory
x Electrostatic discharge protection > 4000V
x Data retention > 200 years
x 8-pin PDIP/SOIC packages
x Temperature ranges: Commercial (C): 0°C to +70°C, Industrial (I): -40°C to
+85°C
12.3Absolute Maximum Ratings and Electrical Characteristics
Page 27
12.4Pinning
Page 28
13.512K CMOS Serial Flash – MX25L512
13.1. General Description
The MX25L512 is a CMOS 524,288 bit serial Flash memory, which is configured as
65,536 x 8 internally. The MX25L512 feature a serial peripheral interface and software
protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock
input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the
device is enabled by CS# input. The MX25L512 provide sequential read operation on
whole chip. After program/erase command is issued, auto program/ erase algorithms
which program/ erase and verify the specified page or sector/block locations will be
executed. Program command is executed on page (256 bytes) basis, and erase
command is executes on chip or sector (4K-bytes). To provide user with ease of
interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via
WIP bit. When the device is not in operation and CS# is high, it is put in standby mode
and draws less than 10uA DC current. The MX25L512 utilize MXIC's proprietary
memory cell, which reliably stores memory contents even after 100,000 program and
erase cycles.
13.2. Features
GENERAL
x Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3
x 524,288 x 1 bit structure
x 16 Equal Sectors with 4K byte each
x Any Sector can be erased individually
x Single Power Supply Operation
x 2.7 to 3.6 volt for read, erase, and program operations
x Latch-up protected to 100mA from -1V to Vcc +1V
x Low Vcc write inhibit is from 1.5V to 2.5V
PERFORMANCE
x High Performance
x Fast access time: 85MHz serial clock (15pF + 1TTL Load) and 66MHz serial
clock (30pF + 1TTL Load)
x Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
x Fast erase time: 60ms(typ.) and 120ms(max.)/sector (4K-byte per sector) ;
1s(typ.) and 2s(max.)/chip(512Kb)
x Low Power Consumption
x Low active read current: 12mA(max.) at 85MHz, 8mA(max.) at 66MHz and
4mA(max.) at 33MHz
x Low active programming current: 15mA (max.)
x Low active erase current: 15mA (max.)
x Low standby current: 10uA (max.)
x Deep power-down mode 1uA (typical)
x Minimum 100,000 erase/program cycles
Page 29
SOFTWARE FEATURES
x Input Data Format
x 1-byte Command code
x Block Lock protection
x The BP0~BP1 status bit defines the size of the area to be software protected
against Program and Erase instructions.
x Auto Erase and Auto Program Algorithm
x Automatically erases and verifies data at selected sector
x Automatically programs and verifies data at selected page by an internal
algorithm that automatically times the program pulse widths (Any page to be
programed should have page in the erased state first)
x Status Register Feature
x Electronic Identification
x JEDEC 2-byte Device ID
x RES command, 1-byte Device ID
HARDWARE FEATURES
x SCLK Input
x Serial clock input
x SI Input
x Serial Data Input
x SO Output
x Serial Data Output
x WP# pin
x Hardware write protection
x HOLD# pin pause the chip without diselecting the chip
x PACKAGE
x 8-pin SOP (150mil)
x All Pb-free devices are RoHS Compliant
13.3Absolute Maximum Ratings
Page 30
14.Integrated DVB-T Receiver
14.1General Description
CT216T is a highly integrated single chip for DVB-T compliant STB solution. Compared
with Cheertek's previous generations of STB receiver devices. CT216T further interates
COFDM demodulator USB 2.0 HS host controller, memory card reader, 1/2-bit SPIFlash
interface, audio DAC, PWM in/out and SAR-ADC functions. In additiont special
enhangements are provided such as MPEG-4 video decoding, 16-bit OSD with anti-
Page 31
flickering, HW JPEG decoding, flesh tone and black-white extensions, and improvement
of small video quality.
CT216T includes COFDM demodulator transport stream de-multiplexer, DVB-CSA
compliant de-scrambler, RISC MPUs, MPEG-1/2/4 AV decoder, digital T\/ encoder,
audio DACs, USB 2.0 HS host controller, memory card reader, smart card reader, CI
controller and other peripherals.
Cli216T is designed in focus on the market of single tuner input product which makes, it
a cost effective solution. Supports include free to air, conditional access for SC (Smart
card) and CI portable devices, PVR, LCD TV, and other DVB-T applications.
14.2Features
COFDM Demodulator
x ETSI EN 300 744 DVB-T NorDig Unified 1.0.3, and D-book compliant
x Automatic spectral inversion, detection
x Integrated ADC
x Direct IF (36.167 MHz or 43.75 MHz) or low IF (4.57 MHz) supported
x Single IF AGC or dual RF/lF AGC controls with ǻȈ modulabon
x Impulsive noise cancellation
x Carrier acquisition range: ±400 kHz (extensible to ±600 kHz in 8MHz BW)
x Adjacent channel interference (ACI) filter,for supporting 6, 7, and 8MHz channels
with one 8MHz analog filter
x Co-channel interterence (CCl) supression
x RF signal strength monitor
MPU
x Three 32-bit RISC MPU run up to 166MHz with total 448DMIPS
x 8KB I-Cache and 8KB D-Cache
x Two general purpose timers
x Watchdog timer
x DSU for source level debug
Memory
x 6-bit SDRAM controller supports up to 32MB (16MB for l28-pin)
x Unified memory architecture
x Parallel flash (216-pin only)
x 1/2-bit SPI flash
Transport De-multiplexing
x TS, PES, and ES demultiplexing
x OneTS path
x CI CAM interface (216-pin only)
x 32 general purpose PID filters
x 32 Section filters
x CRC-32 accelerator
Page 32
x DVB-CSA de-scramblers
Video Decoding and Processing
x MPEG-2 MP@ML
x MPEG-4 SP&ASP
x PAL/NTSC format conversion
x 3:2 pull down
x Zoom in/out from 1/16X to 16X
x HW JPEG decode
x 4/8/16-bit OSD with anti-flickering
x On chip NTSC/PAL TV encoder
x CVBS, S-VHS, and component video
x VBI insertion for Teletext, CC and WSS
x ITU-R BT.601 and ITU-R BT.656 outputs
x Flesh tone extension
x Black/white extension,
Audio Decoding and Processing
x MPEG-1: layer 1/2/3
x MPEG-2: layer 1/2
x Decode MPEG-2 and MPEG-1 audio at sampling frequency of 16K, 22.05K, 24K,
32K, 44.1K, and 48KHz
x Decode CU-DA at sampling frequency of 44.1 KHz
x SPDIF out for AC-3 by-pass
x Embedded 2 channels audio DAC for L/R outputs
x Digital mute control and volume adjustment
OSD(On Screen Display)
x There are total 9 display planes: border; background. video. RS1 (Rectangle Strip
1), RS2, OSD, RS3, RS4, and cursor.
x 4/8l16-bit OSD with anti-flickering and anti-flutter
x Support alpha-blending per color
x Adjustable brightness control in window
x Bitmap OSD
x Support horizontal pixel duplication to enlarge bitmap automatically
x Support sub-region redraw to facilitate bitmap display.
Digitnal TV Encoder
x NTSC-M, PAL-B, D, G, H, I, Nc, M encoding
x Four video DACs to provide 6 configuration output: modes
x Support CVBS, S-VHS. and component video outs
x VBI insertion for Teletext, CC and WSS
x Color burst amplitude control
x Programmable sync. level
x On chip, color-bar generator
Page 33
High Speed I/O
x USB 2.0 HS host controller
x Memory card reader with SD, MMC, and MS interfaces
x Compliant with SD spec. 1.1 and MMC spec. 4.0 with 1-bit & 4-bit modes.
x Compliant with Memory Stick Pro format spec. 1.02 and Memory stick format
spec 1.43 with 1-bit and 4-bit modes.
Peripherals
x Up to 3 full duplex UART with 16-byte FIFO
x 2-wire serial (2WS) in master mode .. .
x Up to 2 IS0-7816 compliant SC (1 in 128-pin, can also be used as UART)
x 5 digits 7-Segrnent LED control
x 5x3 two-dimension key scan
x 2 SAR-ADC input
x 4 PWM input/output
x 1 HW IR command decode
x GPIO
Electrical and Physical Characteristics
x Capable of using single 27MHz clock input crystal
x 1.8V and 3.3V dual power supply
x Power standby mode
x PQFP-128 (CT216T-Z) or LQFP-216 (CT216T-R) package
13.3Absolute Maximum Rating and Electrical Characteristics
Page 34
Page 35
15.IC DESCRIPTIONS
15.1. LM1117
15.1.1.General Description
The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at
800mA of load current. It has the same pin-out as National Semiconductor’s industry
standard LM317. The LM1117 is available in an adjustable version, which can set the
output voltage from 1.25V to 13.8V with only two external resistors. In addition, it is also
available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V. The LM1117 offers
current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap
reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is
available in SOT- 223, TO-220, and TO-252 D-PAK p
tantalum capacitor is required at the output to improve the transient response and
stability.
15.1.2.Features
x Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions
x Space Saving SOT-223 Package
x Current Limiting and Thermal Protection
x Output Current 800mA
x Line Regulation 0.2% (Max)
x Load Regulation 0.4% (Max)
x Temperature Range
x LM1117 0°C to 125°C
x LM1117I -40°C to 125°C
DFNDJHV $ PLQLPXP RI ȝ)
15.1.3.Applications
x 2.85V Model for SCSI-2 Active Termination
x Post Regulator for Switching DC/DC Converter
x High Efficiency Linear Regulators 15
x 32” TFT TV Service Manual 10/01/2005
x Battery Charger
x Battery Powered Instrumentation
15.1.4.Absolute Maximum Ratings
Page 36
15.1.5.Pinning
15.2. 74HCT4053
15.2.1.General Description
The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin
compatible with the HEF4053B. It is specified in compliance with JEDEC standard no.
7A. The 74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer
with a common enable input (E). Each multiplexer/demultiplexer has two independent
inputs/outputs (nY0 and nY1), a common input/output (nZ) and three digital select inputs
(Sn). With E LOW, one of the two switches is selected (low-impedance ON-state) by S1
to S3. With E HIGH, all switches are in the high-impedance OFF-state, independent of
S1 to S3. VCC and GND are the supply voltage pins for the digital control inputs (S1 to
S3 and E). The VCC to GND ranges are 2.0 V to 10.0 V for 74HC4053 and 4.5 V to 5.5
V for 74HCT4053. The analog inputs/outputs (nY0 and nY1, and nZ) can swing between
VCC as a positive limit and VEE as a negative limit. VCC - VEE may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically
ground).
15.2.2.Features
x Low ON resistance:
x 80 W (typical) at VCC - VEE = 4.5 V
x 70 W (typical) at VCC - VEE = 6.0 V
x 60 W (typical) at VCC - VEE = 9.0 V
x Logic level translation:
x To enable 5 V logic to communicate with ±5 V analog signals
x Typical ‘break before make’ built in
x Complies with JEDEC standard no. 7A
x ESD protection: HBM EIA/JESD22-A114-C exceeds 2000 V, MM
EIA/JESD22-A115-A exceeds 200 V
x Multiple package options
x Specified from -40 °C to +85 °C and from -40 °C to +125 °C
15.2.3.Applications
x Analog multiplexing and demultiplexing
x Digital multiplexing and demultiplexing
x Signal gating
Page 37
15.2.4.Absolute Maximum Ratings
15.2.5.Pinning
15.3. NUP4004M5
15.3.1.General Description
This 5-Pin bi-directional transient suppressor array is designed for applications requiring
transient overvoltage protection capability. It is intended for use in transient voltage and
Page 38
ESD sensitive equipment such as computers, printers, cell phones, medical equipment,
and other applications. Its integrated design provides bi-directional protection for four
separate lines using a single TSOP-5 package. This device is ideal for situations where
board space is a premium.
15.3.2.Features
x Bi-directional Protection for Four Lines in a Single TSOP-5 Package
x Low Leakage Current
x Low Capacitance
x Provides ESD Protection for JEDEC Standards JESD22
x Machine Model = Class C
x Human Body Model = Class 3B
x Provides ESD Protection for IEC 61000-4-2, 15 kV (Air), 8 kV (Contact)
x This is a Pb-Free Device
15.3.3.Absolute Maximum Ratings
15.3.4.Pinning
Page 39
15.4. FDN336P
15.4.1.General Description
The ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM),
organized by 8 bits.This device can operate in two modes: Transmit Only mode and I2C
bidirectional mode. When powered, the device is in Transmit Only mode with EEPROM
data clocked out from the rising edge of the signal applied on VCLK. The device will
switch to the I2C bidirectional mode upon the falling edge of the signal applied on SCL
pin. The ST24LC21 cannot switch from the I2C bidirectional mode to the Transmit Only
mode (except when the power supply is removed). The device operates with a power
supply value as low as 2.5V. Both Plastic Dual-in-Line and Plastic Small Outline
packages are available.
15.4.2.Features
x 1 MILLION ERASE/WRITE CYCLES
x 40 YEARS DATA RETENTION
x 2.5V to 5.5V SINGLE SUPPLY VOLTAGE
x 400k Hz COMPATIBILITY OVER the FULL RANGE of SUPPLY VOLTAGE
x TWO WIRE SERIAL INTERFACE I2C BUS COMPATIBLE
x PAGE WRITE (up to 8 BYTES)
x BYTE, RANDOM and SEQUENTIAL READ MODES
x SELF TIMED PROGRAMMING CYCLE
x AUTOMATIC ADDRESS INCREMENTING
x ENHANCED ESD/LATCH UP PERFORMANCES
15.4.3.Absolute Maximum Ratings
15.4.4.Pinning
Page 40
15.5. TL062 -
15.5.1.General Description
Low-power JFET-input operational amplifier
15.5.2.Features
x Very Low Power Consumption
x Typical Supply Current . . . 200 μA (Per Amplifier)
x Wide Common-Mode and Differential Voltage Ranges
x Low Input Bias and Offset Currents
x Common-Mode Input Voltage Range Includes VCC+
x Output Short-Circuit Protection
x High Input Impedance . . . JFET-Input Stage
x Internal Frequency Compensation
x Latch-Up-Free Operation
x High Slew Rate . . . 3.5 V/μs Typ
15.5.3.Absolute Maximum Ratings
Page 41
15.5.4.Pinning
15.6. PI5V330
15.6.1.General Description
Pericom Semiconductor.s PI5V series of mixed signal video circuits are produced in the
Company.s advanced CMOS low-power technology, achieving industry leading
performance.ThePI5V330isatruebidirectionalQuad2-channel
multiplexer/demultiplexer that is recommended for both RGB and composite video
switching applications. The VideoSwitch. can be driven from a current output RAMDAC
or voltage output composite video source. Low ON-resistance and wide bandwidth
make it ideal for video and other applications. Also this device has exceptionally high
current capability which is far greater than most analog switches offered today. A single
5V supply is all that is required for operation. The PI5V330 offers a high-performance,
low-cost solution to switch between video sources. The application section describes the
PI5V330 replacing the HC4053 multiplier and buffer/amplifier.
15.6.2.Features
x High-performance, low-cost solution to switch between video sources
x Wide bandwidth: 200 MHz
x Low ON-resistance: 3
x Low crosstalk at 10 MHz: .58 dB
x Ultra-low quiescent power (0.1 μA typical)
x Single supply operation: +5.0V
x Fast switching: 10 ns
x High-current output: 100 mA
x Packages available:
x 16-pin 300-mil wide plastic SOIC (S)
x 16-pin 150-mil wide plastic SOIC (W)
x 16-pin 150-mil wide plastic QSOP (Q)
15.6.3.Absolute Maximum Ratings
Page 42
15.6.4.Pinning
15.7. AZC099-04S
15.7.1.General Description
AZC099-04S is a high performance and low cost design which includes surge rated
diode arrays to protect high speed data interfaces. The AZC099-04S family has been
specifically designed to protect sensitive components, which are connected to data and
transmission lines, from over-voltage caused by Electrostatic Discharging (ESD),
Electrical Fast Transients (EFT), and Lightning.
AZC099-04S is a unique design which includes surge rated, low capacitance steering
diodes and a unique design of clamping cell which is an equivalent TVS diode in a
single package. During transient conditions, the steering diodes direct the transient to
either the power supply line or to the ground line. The internal unique design of clamping
cell prevents over-voltage on the power line, protecting any downstream components.
AZC099-04S may be used to meet the ESD immunity requirements of IEC 61000-4-2,
Level 4 (± 15kV air, ±8kV contact discharge).
15.7.2.Features
x ESD Protect for 4 high-speed I/O channels
x Provide ESD protection for each channel to IEC 61000-4-2 (ESD) ±15kV (air),
±8kV (contact) IEC 61000-4-4 (EFT) (5/50ns) Level-3, 20A for I/O, 40A for Power
IEC 61000-4-5 (Lightning) 4A (8/20ȝV
x 5V operating voltage /RZFDSDFLWDQFHS)W\SLFDO
x Fast turn-on and Low clamping voltage
x Array of surge rated diodes with internal equivalent TVS diode
x Small package saves board space
x Solid-state silicon-avalanche and active circuit triggering technology
Page 43
15.7.3.Absolute Maximum Ratings
15.7.4.Pinning
15.8. TDA1308
15.8.1.General Description
The TDA1308; TDA1308A is an integrated class-AB stereo headphone driver contained
in an SO8, DIP8 or a TSSOP8 plastic package. The TDA1308AUK is available in an 8
bump wafer level chip-size package (WLCSP8). The device is fabricated in a 1 mm
Complementary Metal Oxide Semiconductor (CMOS) process and has been primarily
developed for portable digital audio applications. The difference between the TDA1308
and the TDA1308A is that the TDA1308A can be used at low supply voltages.
15.8.2.Features
x Wide temperature range
x No switch ON/OFF clicks
x Excellent power supply ripple rejection
x Low power consumption
x Short-circuit resistant
x High performance
x High signal-to-noise ratio
Page 44
x High slew rate
x Low distortion
x Large output voltage swing
15.8.3.Absolute Maximum Ratings
15.8.4.Pinning
15.9. ST3222
15.9.1.General Description
The ST3222 is a 3V powered EIA/TIA-232 and V.28/V.24 communications interface with
low power requirements and high data-rate capabilities. ST3222 has a proprietary low
dropout transmitter output stage providing true RS-232 performance from 3 to 3.6V
power supplies. The device requires only four small 0.1mF standard external capacitors
for operating from 3V supply. The ST3222 has two receivers and two drivers. The
ST3222 features a 1mA shutdown mode that reduces power consumption and extends
battery life in portable systems. Its receivers can remain active in shutdown mode,
allowing external devices such as modems to be monitored using only 1mA supply
current. The device is guaranteed to run at data rates of 250Kbps while maintaining RS232 output levels.
15.9.2.Features
x 300mA SUPPLY CURRENT
x 250Kbps MINIMUM GUARENTEED DATA RATE
x 6V/ms MINIMUM GUARANTEED SLEW RATE
x MEET EIA/TIA-232 SPECIFICATIONS DOWN TO 3V
x AVAILABLE IN SO-18 AND TSSOP20
Page 45
15.9.3.Absolute Maximum Ratings
15.9.4.Pinning
15.10.LM358D
15.10.1. General Description
The LM158 series consists of two independent, high gain, internally frequency
compensated operational amplifiers which were designed specifically to operate from a
Page 46
single power supply over a wide range of voltages. Operation from split power supplies
is also possible and the low power supply current drain is independent of the magnitude
of the power supply voltage. Application areas include transducer amplifiers, dc gain
blocks and all the conventional op amp circuits which now can be more easily
implemented in single power supply systems. For example, the LM158 series can be
directly operated off of the standard +5V power supply voltage which is used in digital
systems and will easily provide the required interface electronics without requiring the
additional ±15V power supplies. The LM358 and LM2904 are available in a chip sized
package (8-Bump micro SMD) using National’s micro SMD package technology.
15.10.2. Features
x Available in 8-Bump micro SMD chip sized package,
x Internally frequency compensated for unity gain
x Large dc voltage gain: 100 dB
x Wide bandwidth (unity gain): 1 MHz (temperature compensated)
x Wide power supply: Single supply: 3V to 32V or dual supplies: ±1.5V to ±16V
x Low supply current drain (500 μA)—essentially independent of supply voltage
x Low input offset voltage: 2 mV
x Input common-mode voltage range includes ground
x Differential input voltage range equal to the power supply voltage
x Large output voltage swing
15.10.3. Absolute Maximum Ratings
Page 47
15.10.4. Pinning
15.11.74LCX244
15.11.1. General Description
The LCX244 contains eight non-inverting buffers with 3-STATE outputs. The device may
be employed as a memory address driver, clock driver and bus-oriented
transmitter/receiver. The LCX244 is designed for low voltage (2.5V or 3.3V) VCC
applications with capability of interfacing to a 5V signal environment. The LCX244 is
fabricated with an advanced CMOS technology to achieve high speed operation while
maintaining CMOS low power dissipation.
15.11.2. Features
x 5V tolerant inputs and outputs
x 2.3V to 3.6V VCC specifications provided
x 6.5ns Tpd max. (VCC=3.3V), 10μA ICCmax.
x Power down high impedance inputs and outputs
x Supports live insertion/withdrawal
x ±24mA output drive (VCC=3.0V)
x Implements patented noise/EMI reduction circuitry
x Latch-up performance exceeds 500mA
x ESD performance:Human body model>2000V, Machine model>200V
x Leadless DQFN package
15.11.3. Absolute Maximum Ratings
Page 48
15.11.4. Pinning
15.12.74LCX245
15.12.1. General Description
The LCX245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and
is intended for bus oriented applications. The device is designed for low voltage (2.5V
and 3.3V) VCC applications with capability of interfacing to a 5V signal environment.
The T/R input determines the direction of data flow through the device. The OE input
disables both the A and B ports by placing them in a high impedance state.
The LCX245 is fabricated with an advanced CMOS technology to achieve high speed
operation while maintaining CMOS low power dissipation.
15.12.2. Features
x 5V tolerant inputs and outputs
x 2.3V to 3.6V VCC specifications provided
x 7.0ns tPDmax. (VCC=3.3V), 10μA ICCmax.
x Power down high impedance inputs and outputs
x Supports live insertion/withdrawal
x ±24mA output drive (VCC=3.0V)
x Implements patented noise/EMI reduction circuitry
x Latch-up performance exceeds 500mA
x ESD performance: Human body model>2000V, Machine model>200V
x Leadless DQFN package
Page 49
15.12.3. Absolute Maximum Ratings
15.12.4. Pinning
15.13.FSA3157
15.13.1. General Description
The NC7SB3157 / FSA3157 is a high-performance, single- pole / double-throw (SPDT)
analog switch or 2:1 multiplexer/ de-multiplexer bus switch. The device is fabricated with
advanced sub-micron CMOS technology to achieve high-speed enable and disable
times and low on resistance. The break-beforemake select circuitry prevents disruption
of signals on the B Port due to both switches temporarily being enabled during select pin
switching. The device is specified to operate over the 1.65 to 5.5V VCC operating range.
Page 50
The control input tolerates voltages up to 5.5V, independent of the VCC operating
range.
15.13.2. Features
x Useful in both analog and digital applications
x Space-saving, SC70 6-lead surface mount package
x Ultra-small, MicroPak™ Pb-free leadless package
x /RZ2Q5HVLVWDQFHȍRQW\SLFDODW99&&
x Broad VCC operating range: 1.65V to 5.5V
x Rail-to-rail signal handling
x Power-down, high-impedance control input
x Over-voltage tolerance of control input to 7.0V
x Break-before-make enable circuitry
x 250 MHz, 3dB bandwidth
15.13.3. Absolute Maximum Ratings
15.13.4. Pinning
Page 51
15.14.FMS6145
15.14.1. General Description
The FMS6145 Low-Cost Video Filter (LCVF) is intended to replace passive LC ¿OWHUV
and drivers with a low-cost integrated device. Five 4th-order ¿OWHUV provide improved
image quality compared to typical 2nd or 3rd-order passive solutions. The FMS6145
may be directly driven by a DC-coupled DAC output or an AC-coupled signal. Internal
diode clamps and bias circuitry may be used if AC-coupled inputs are required. The
outputs can drive AC- or DC-FRXSOHGVLQJOHȍRU GXDOȍORDGV'&FRXSOLQJWKH
outputs removes the need for output coupling capacitors. The input DC levels are offset
approximately +280mV at the output.
15.14.2. Features
x Five 4th-order 8MHz (SD) ¿OWHUV
x Drives single,AC- or DC-FRXSOHGYLGHRORDGV9SSȍ
x Drives dual, AC- or DC-FRXSOHGYLGHRORDGV9SSȍ
x Transparent input clamping
x AC- or DC-coupled inputs
x AC- or DC-coupled outputs
x DC-coupled outputs eliminate AC-coupling capacitors
x 5V only
x Robust 8kV ESD protection
x Lead-free TSSOP-14 package
15.14.3. Absolute Maximum Ratings
15.14.4. Pinning
Page 52
15.15.MT48LC4M16A2TG8E
15.15.1. General Description
The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing
67,108,864 bits. It is internally configured as a quad-bank DRAM with a synchronous
interface (all signals are registered on the positive edge of the clock signal, CLK). Each
of the x4’s 16,777,216-bit banks is organized as 4,096 rows by 1,024 columns by 4 bits.
Each of the x8’s 16,777,216-bit banks is organized as 4,096 rows by 512 columns by 8
bits. Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns
by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at
a selected location and continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration of an ACTIVE command,
which is then ollowed by a READ or WRITE command. The address bits registered
coincident with the ACTIVE command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0-A11 select the row).
15.15.2. Features
x PC66-, PC100- and PC133-compliant
x 143 MHz, graphical 4 Meg x 16 option
x Fully synchronous; all signals registered on positive edge of system clock
x Internal pipelined operation; column address can be changed every clock cycle
x Internal banks for hiding row access/precharge
x Programmable burst lengths: 1, 2, 4, 8 or full page
x Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and AutO
Refresh Modes
x Self Refresh Modes: standard and low power
x 64ms, 4,096-cycle refresh
x LVTTL-compatible inputs and outputs
x Single +3.3V ±0.3V power supply
15.15.3. Absolute Maximum Ratings
Page 53
15.15.4. Pinning
15.16.MP1583
15.16.1. General Description
The MP1583 is a step-down regulator with a built in internal Power MOSFET. It
achieves 3A continuous output current over a wide input supply range with excellent
load and line regulation.
Current mode operation provides fast transient response and eases loop stabilization.
Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown.
Adjustable soft-start reduces the stress on the input source at turn-on. In shutdown
mode the regulator draws 20μA of supply current.
The MP1583 requires a minimum number of readily available external components to
complete a 3A step down DC to DC converter solution.
Page 54
15.16.2. Features
x 3A Output Current
x Programmable Soft-Start
x 100m,QWHUQDO3RZHU026)(76ZLWFK
x Stable with Low ESR Output Ceramic Capacitors
x Up to 95% Efficiency
x 20μA Shutdown Mode
x Fixed 385KHz frequency
x Thermal Shutdown
x Cycle-by-Cycle Over Current Protection
x Wide 4.75 to 23V operating Input Range
x Output Adjustable From 1.22 to 21V
x Under Voltage Lockout
x Available in 8 pin SOIC Package
x 3A Evaluation Board Available
15.16.3. Absolute Maximum Ratings
15.16.4. Pinning
Page 55
15.17.MP2112
15.17.1. General Description
The MP2112 is a 1MHz constant frequency, current mode, PWM step-down converter.
The device integrates a main switch and a synchronous rectifier for high efficiency
without an external Schottky diode. It is ideal for powering portable equipment that
powered by a single cell Lithium-Ion (Li+) battery. The MP2112 can supply 1A of load
current from a 2.5V to 6V input voltage. The output voltage can be regulated as low as
0.6V. The MP2112 can also run at 100% duty cycle for low dropout applications.
The MP2112 is available in a space-saving 6-pin QFN package.
15.17.2. Features
x High Efficiency: Up to 95%
x 1MHz Constant Switching Frequency
x 1A Available Load Current
x 2.5V to 6V Input Voltage Range
x Output Voltage as Low as 0.6V
x 100% Duty Cycle in Dropout
x Current Mode Control
x Short Circuit Protection
x Thermal Fault Protection
x <0.1μA Shutdown Current
x Space Saving 3mm x 3mm QFN6 Package
15.17.3. Absolute Maximum Ratings
15.17.4. Pinning
Page 56
15.18.STLITE49M
15.18.1. General Description
The ST7LITE49M is a member of the ST7 microcontroller family. All ST7 devices are
based on a common industry-standard 8-bit core, featuring an enhanced instruction set.
The ST7LITE49M features FLASH memory with byte-by-byte In-Circuit Programming
(ICP) and In-Application Programming (IAP) capability. Under software control, the
ST7LITE49M device can be placed in Wait, Slow, or Halt mode, reducing power
consumption when the application is in idle or standby state. The enhanced instruction
set and addressing modes of the ST7 offer both power and flexibility to software
developers, enabling the design of highly efficient and compact application code. In
addition to standard 8-bit data management, all ST7 microcontrollers feature true bit
manipulation, 8x8 unsigned multiplication and indirect addressing modes. The
ST7LITE49M features an on-chip Debug Module (DM) to support In-Circuit Debugging
(ICD). For a description of the DM registers, refer to the ST7 ICC Protocol Reference
Manual.
15.18.2. Features
x Memories: 4 Kbytes single voltage extended Flash (XFlash) Program memory
with Read-out protection In-Circuit Programming and In-Application programming
(ICP and IAP) Endurance: 10K write/erase cycles guaranteed Data retention: 20
years at 55 °C, 384 bytes RAM, 128 bytes data EEPROM with read-out
protection, 300K write/erase cycles guaranteed, data retention: 20 years at 55 °C.
x Clock, Reset and Supply Management: 3-level low voltage supervisor (LVD) for
main supply and an auxiliary voltage detector (AVD) for safe power-on/off, Clock
sources: Internal trimmable 8 MHz RC oscillator, auto wake-up internal low
power, low frequency oscillator, crystal/ceramic resonator or external clock, Five
power saving modes: Halt, Active-Halt, Auto Wake-up from Halt, Wait and Slow
x I/O Ports: Up to 24 multifunctional bidirectional I/Os, 8 high sink outputs
x 5 timers: Configurable watchdog timer, Dual 8-bit Lite Timers with prescaler, 1
real time base and 1 input capture, Dual 12-bit Auto-reload Timers with 4 PWM
outputs, input capture, output compare, dead-time generation and enhanced one
pulse mode functions
x Communication interface: I²C multimaster interface
x A/D converter: 10 input channels
x Interrupt management: 13 interrupt vectors plus TRAP and RESET
x Instruction set: 8-bit data manipulation, 63 basic instructions with illegal opcode
detection, 17 main addressing modes, 8 x 8 unsigned multiply instructions
x Development tools: Full HW/SW development package, DM (Debug Module)
15.18.3. Absolute Maximum Ratings
Page 57
15.18.4. Pinning
Page 58
15.19.MAX809LTR
15.19.1. General Description
The MAX809 and MAX810 are cost-effective system supervisor circuits designed to
monitor VCC in digital systems and provide a reset signal to the host processor when
necessary. No external components are required. The reset output is driven active
within 10 _sec of VCC falling through the reset voltage threshold. Reset is maintained
active for a timeout period which is trimmed by the factory after VCC rises above the
reset threshold. The MAX810 has an active-high RESET output while the MAX809 has
an active-low RESET output. Both devices are available in SOT-23 and SC-70
packages. The MAX809/810 are optimized to reject fast transient glitches on the VCC
line. Low supply current of 0.5 _A (VCC = 3.2 V) makes these devices suitable for
battery powered applications.
15.19.2. Features
x Precision VCC Monitor for 1.5 V, 2.5 V, 3.0 V, 3.3 V, and 5.0 V Supplies
x Precision Monitoring Voltages from 1.2 V to 4.9 V Available in 100 mV Steps
x Four Guaranteed Minimum Power-On Reset Pulse Width Available (1 ms, 20 ms,
100 ms, and 140 ms)
x RESET Output Guaranteed to VCC = 1.0 V.
x Low Supply Current
x Compatible with Hot Plug Applications
x VCC Transient Immunity
x No External Components
x Wide Operating Temperature: -40°C to 105°C
x Pb-Free Packages are Available
15.19.3. Absolute Maximum Ratings
Page 59
15.19.4. Pinning
16.SERVICE MENU SETTINGS
In order to reach service menu, First Press “MENU” Then press the remote control
code, which is “4725”. In DTV mode, first press “MENU” and select “TV SETUP”.
Then, press “4725”.
16.1. Video Setup
Panel Info <..................................>
32_LC_SAC1
Blue Background <.....>
If “Menu” selected, “Blue Background” item is seen in “Feature”
menu.
If “Yes” selected, “Blue Background” is on and not seen in
“Feature” menu
Film Mode <.....>
If “Yes” selected, “Film Mode” feature is active.
Dynamic Contrast <.....>
If “Yes” selected, “Dynamic Contrast” feature is active.
Game Mode <...........>
If “Yes” selected, “Game Mode” feature is active
SRGB For PC <...........>
If “Yes” selected, PCs can use SRGB option.
Dynamic Noise Reduction<...........>
If “Yes” selected, “Dynamic Noise Reduction” feature is active
WSS Option<...........>
If “Yes” selected, WSS Option can be used
16.2. AudioSetup
BG<.....>
Europe
Page 60
New Zelland
Australia
No
DK<.....>
I<.....>
L<.....>
Equalizer <.....>
If “Yes” selected, “Equalizer” item is seen in “Sound” menu.
Headphone <.....>
If “Yes” selected, “Headphone” item is seen in “Sound” menu.
Power On/Off Melody <.....>
If “Yes” selected, when power on/off conditions, the power on/off
melody can be heard.
Dynamic Bass <.....>Value between 0 to 12
Effect<.....> Value between 0 to 7
Audio Delay ,offset <.....> Value between 0 to 190
Audio Setup Cont...2
Carrier mute<.......> Value between 0 to 28
Headphone Sound Select <.......>
Always Active Select
Always Inactive Select
Menu
Always Main Menu
Always PIP/PAP Window
Sound Mode Detect Time <.......> Value between 0 to 255
Noise Reduction Threshold <.......> Value between 0 to 255
Noise Reduction Time <.......> Value between 0 to 15
AVL Attack Time <.......> Value between 0 to 255
AVL Release Time <.......> Value between 0 to 255
Prescales ( AVL On)
FM Prescale<.......> Value between 0 to 255
AM Prescale <.......> Value between 0 to 255
NICAM Prescale <.......> Value between 0 to 255
SCART Prescale <.......> Value between 0 to 255
FAV Prescale <.......> Value between 0 to 255
DTV Prescale <.......> Value between 0 to 255
HDMI Prescale <.......> Value between 0 to 255
YPbPr/PC Prescale <.......> Value between 0 to 255
An. USB Prescale <.......> Value between 0 to 255
Dig. USB Prescale <.......> Value between 0 to 255
Prescales ( AVL Off)
FM Prescale<.......> Value between 0 to 255
AM Prescale <.......> Value between 0 to 255
NICAM Prescale <.......> Value between 0 to 255
SCART Prescale <.......> Value between 0 to 255
FAV Prescale <.......> Value between 0 to 255
DTV Prescale <.......> Value between 0 to 255
HDMI Prescale <.......> Value between 0 to 255
YPbPr/PC Prescale <.......> Value between 0 to 255
Page 61
An. USB Prescale <.......> Value between 0 to 255
Dig. USB Prescale <.......> Value between 0 to 255
Clipping Levels ( AVL On)
FM Clipping <.......> Value between 0 to 255
AM Clipping <.......> Value between 0 to 255
NICAM Clipping <.......> Value between 0 to 255
SCART Clipping <.......> Value between 0 to 255
FAV Clipping <.......> Value between 0 to 255
DTV Clipping <.......> Value between 0 to 255
HDMI Clipping <.......> Value between 0 to 255
YPbPr/PC Clipping <.......> Value between 0 to 255
An. USB Clipping <.......> Value between 0 to 255
Dig. USB Clipping <.......> Value between 0 to 255
Clipping Levels ( AVL Off)
FM Clipping <.......> Value between 0 to 255
AM Clipping <.......> Value between 0 to 255
NICAM Clipping <.......> Value between 0 to 255
SCART Clipping <.......> Value between 0 to 255
FAV Clipping <.......> Value between 0 to 255
DTV Clipping <.......> Value between 0 to 255
HDMI Clipping <.......> Value between 0 to 255
YPbPr/PC Clipping <.......> Value between 0 to 255
An. USB Clipping <.......> Value between 0 to 255
Dig. USB Clipping <.......> Value between 0 to 255
16.3. Service Scan/Tuning Setup
First Search for L/L’ <.......>
ATS Delay Time (ms) <.......> Value between 0 to +200
RC Group 1
RC Group 2
RC Group 3
RC Group 4
RC Group 5
RC Group 6
Double Digit Key <.......>
Protection <.......>
Led Type <.......>
1 Led 1 Color
1 Led 2 Color
2 Led 2 Color
1 Led 3 Color
2 Led 3 Color
200 Programme <.......>
If “Yes” selected, totaly 200 programmes can be used.
TouchPad <.......>
If “Yes” selected, TouchPad can be used.
If “Yes” selected, first time TV opens by asking APS.
If “Yes” selected, TV opens with Burn-In mode. This mode is
If “Yes” selected, Channel is automatically stored.
If “Yes” selected,Unicode characters can be read in the USB
If “Yes” selected, Sorce List Menu appears on the screen
If “Yes” selected, Remote Control commandsthe TV via
If “Yes” selected, Double Digit Button on RC activates.
If “Yes” selected,short circuit protection activates.
Page 63
Teletext Options
TXT Darkness <.......> Value between 0 to +63
TXT Type <.......>
TXT Language <.......>
No Txt Warning <.......>
Txt Subtitle <.......>
Optional Features
Default Zoom <.......>
Menu Timeout <.......>
Backlight <.......>
100 Step Slider <.......>
Analog USB Enabled <.......>
Menu Double Size <.......>
CEC Enable <.......>
Digital USB Hotplug <.......>
Fasttext&Toptext
No
Default
Fastext
Toptext
Menu
West
East
Cyrillic
Turk/Gre
Arabic
Persian
Auto
If “Yes” selected, “No Txt Transmission” warning appears on
the screen when pressing txt button from RC.
If “Yes” selected, Teletext subtitles can be seen.
Menu
16:9
4:3
Panaromic
14:9 Zoom
Menu
15 Sec
30 Sec
60 Sec
No Time
If “Yes” selected, “Backlight” feature is active.
If “Yes” selected, 64 step sliders will become 100 step sliders.
If “Yes” selected, “Analog USB” option is active.
If “Yes” selected, menu sizes increases.
If “Yes” selected, “CEC” feature is active.
If “Yes” selected, “Digital USB Hotplug” feature is active.
Page 64
PIP Options
Pip <......>
AV PIP
No PIP
PC PIP
Hotel Options <......>
Hotel TV <......>
If “Yes” selected, “Hotel TV” feature is active.
IR Smartloader <......>
If “Yes” selected, “IR Smartloader” feature is active.
16.5. External Source Settings
TV <.......>
DTV <.......>
Ext 2 <.......>
Ext 2 S <.......>
FAV <.......>
BAV <.......>
S-Video <.......>
HDMI 1 <.......>
HDMI 2 <.......>
HDMI 3 <.......>
HDMI 4 <.......>
YPbPr <.......>
PC <.......>
16.6. Preset
User Ad.j
ADC Adj.
Service Adj.
All Adj.
Init Factory Channels.
16.7. NVM Edit
NVM-edit addr. (hex)
NVM-edit data (hex)
NVM-data dec
16.8. Programming
HDMI DDC Update Mode <.......>
HDCP Key Update Mode <.......>
Software Bypass <.......>
If “On” selected, speaker effects are bypassed.
LVDS Clock Step <.......> Value between 0 to +255
Memory Clock Step <.......> Value between 0 to +255
DTV Download <.......>
If “On” selected, DTV software can be updated from SCART.
Page 65
DSUB9 Download <.......>
If “On” selected, DTV software can be updated from DSUB9.
16.9. Diagnostic
Eeprom I2C
Tuner I2C
IF I2C
HDMI I2C
DTV RS232
16.10.Product Info
17.SOFTWARE UPDATE DESCRIPTION
16.117MB35 Analog Part Software Update With Bootloader Procedure
1.1 The File Types Used By The Bootloader
All file types that used by the bootloader software are listed below:
1. The Binary File : It has “.bin” extension and it is the tv application. Its size is 1920
Kb.
2. The Config Binary File : It has “.cin extension and it is the config of the tv
application. Its size may be 64 Kb or a few times 64 Kb.
3. The Test Script File : It has “.txt” extension and it is the test script that is parsed
and executed by the bootloader. It don’t have to be any times of 64 Kb.
4. The Test Binary File : It has “.tin” extension and it is used and written by the test
groups. It is run to understand the problem part of the hardware.
Alltough a file that is used by the bootloader can be had any one of these extensions, its
name has to be “VESTEL_S” and it has to be located in the root directory of the usb
device.
1.2 Usage of The Bootloader
1. The starting to pass through : The chassis is only powered up.
2. The starting to download something : When chassis is powered up the menu key has
to be pushed.Before the chassis is powered up and if any usb device is plugged to the
usb port, the programme is downloaded from usb firstly.
Any usb device is plugged to usb port , user must open hyperterminal in the pc and
connect pc to chassis via Mstar debug tool and any one of scart,dsub9 or I2c
connectors. Serial connection settings are listed below:
-Bit per second: 115200
-Data bits: 8
Page 66
-Parity: None
-Stop bits: 1
-Flow control: None
In this case the bootloader sofware puts “C” character to uart. After repeating “C”
characters are seen in the hyperterminal user can send any file to chassis by selecting
Transfer -> Send File menu item and choosing “
1K Xmodem” from protocol section.
Figure 1. The Sample Output Before Sending The File
2. EEProm update
To Update eeprom content via uart scart,dsub9 or i2c with Mstar tool can used.
Serial connection settings are listed below:
-Bit per second: 9600
-Data bits: 8
-Parity: None
-Stop bits: 1
-Flow control: None
Programming menu item is choosed in the service menu and switch “HDCP Key Update
Mode” from off to on.
Page 67
Figure 2. The Programming Service Menu
After then you must see Xmodem menu in the hyperterminal.To download hdcp key
press k or to download eeprom content press w.
Figure 3. Xmodem Menu
If the repeated “C” characters are seen you can transfer file content via select Transfer>Send File and choose “Xmodem” protocol and click the “Send” button.
Page 68
Figure 4. The Starting To Send
16.217MB30 HDCP key upload procedure.
1) Turn on TV set.
2) Open a COM connection using fallowing parameters and select ISP COM Port
No
1. In the HyperTerminal Menu, click the “Connect” button.
2. Exit the Stby Mode.
3. The “Space” button on the keyboard must be pressed, when the following window can
be seen.
Selection Window
4. Press the “2” button on the keyboard for choosing “2. Upgrade Application with
Xmodem”.
5. Repeating “C” characters are seen in the “HyperTerminal” menu.
The Sample Output Before Sending The File
Page 71
6. Click the “Send” button on the HyperTerminal
7. Select the “Filename xxxx_slot1.img” using “Browse”.
8. Choose the “1K Xmodem” from “Protocol” option.
Selection of File
File and Protocol Selection Window
Note: In the Software updating Procedure section, when the first “C” character is seen,
the filename selection process must be finished before 10 seconds. If the process can
not be finished, the file sending operation will be cancelled. The following figure shows
this situation.
Page 72
Capture of Receving Data Failing
9. When sending the file the following window must be seen.
Capture of Sending Process
10. After the sending process the following HyperTerminal window must be seen.
Page 73
Capture of End of The Sending Process
11. For sending second program file, the Software Updating Procedure must be
repeated from the step X. Select the “Filename xxxx_slot2.img” using “Browse”.
12. After sending the second program file, the Software Updating Procedure will be
succesful.
Note: After the File Sending Process,
1. Upgrade Application with FUM
2. Upgrade Application with Xmodem, options must be seen.
End of The Sending Process
Page 74
Checking Of The New Software
1. Turn off and on the TV.
2. Enter the “Setup” submenu in the “DTV Menu”.
3. Choose the “Configuration” option.
4. For controlling new software, check the “Receiver Upgrade” option.
16.417MB35 Digital Software Update From USB
Software upgrade is possible via USB disk by folowing the steps below.
1. Copy the bin file, including higher version than the software loaded in flash, into
the USB flash memory root directory. This file should be named up.bin.
2. Insert the USB disk.
3. Digital module performs version and CRC check. If version and CRC check is
successful, then a message prompt appears to notify user about new version. If
the user confirms loading of new version, upgrade.bin file is written into flash
unused slot.
4. Digital module disables the previous software in the flash and then a system
reset is performed.
5. After the reset, digital module starts with new software.
Revert operation:
With revert operation, it is possible to downgrade the software.
Revert operation is very similar to upgrade process. In the revert operation, file name
should be f_up.bin. Also user confirmation is not asked.
1. Copy the bin file into the USB flash memory root directory. This file should be
named force_upgrade.bin.
2. Insert the USB disk.
3. A lower version than the software in flash can be loaded with revert operation.
Digital module performs only CRC check. If CRC check is successful, then
force_upgrade.bin file is written into flash unused slot.
4. Digital module disables the previous software in the flash.
5. A message prompt is displayed to notify user about end of revert process.
6. Power off/on is required to start digital module with the new software.
For controlling new software, check the “Receiver Upgrade” option.
18.BLOCK DIAGRAMS
18.1. General Block Diagram
Page 75
Page 76
18.2. Power Management
Page 77
18.3. Integrated DVB-T Receiver Block Diagram
Page 78
18.4. MSTAR Block Diagram
Page 79
FOR ALL PARTS PLEASE MAKE
CONTACT WITH ASWO
FOR YOUR LOCAL OUTLET GO TO
www.aswo.com
Page 80
No.0240
ExplodedView
Page 81
LG
AIF
12
DIF1
11
DIF2
10
IF_AGC
9
AS
8
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SDA
SCL
RF_AGC
7
B2
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TDTC-G101D
TU102
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IFOUT-
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DTOS403LH172A
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L116
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IF_AGC_DVB_IN
ADDRESS_SEL_TUNER
5V_TUN
SDA_TUNER
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RF_AGC
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TP151
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R502
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This partmustbeplacednearthetuner
R126
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47P
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C587
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47R
R127
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SCL_TUN
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SDA_TUN
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100N
C136
ANT_CTRL
12
1
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R505
10K
IF_AGC_DVB
TUNER SUPPLYOPSION
F116
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!! !Enaz 1.8cm2altta ve üstte so˜ utma alan’ b’rak’lmal’.