Hitachi H8S/2215 Hardware Manual

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Hitachi Single-Chip Microcomputer

H8S/2215 Series

Hardware Manual

ADE-602-217B Rev. 3.0 10/04/02 Hitachi Ltd.

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high qua lity and reliability or where its failure or malfunction m a y dir ectly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no respon sib ility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.

Rev. 3.0, 10/02, page ii of lviii

General Precautions on the Handling of Products

1. Treatment of NC Pins Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malf unction may occur.

3. Processing before Initialization Note: When power is first supplied, the product’s state is undefined. The states of internal

circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Address Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these address. Do not access these registers: the system’s operation is not guaranteed if they are accessed.

Rev. 3.0, 10/02, page iii of lviii

Rev. 3.0, 10/02, page iv of lviii

Configuration of this Manual

This manual comprises the fo llowing items:

1. Precautions in Relation to this Product

2. Configuration of this Manual

3. Overview

4. Table of Contents

5. Summary

6. Description of Functional Modules

• CPU and System-Control Modules

• On-chip Peripheral Modules The configuration of the functional description of each module differs according to the module.

However, the generic style includes the following items: i) Features ii) I/O pins iii) Description of Registers iv) Description of Operation v) Usage: Points for Caution

When designing an app lication system that includes this LSI, take the points for caution into account. Each section includes points for caution in relation to the descriptions given, and points for caution in usage are given, as required, as the final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

• Product-type codes and external dimensions

• Major revisions or addenda in this version of the manual (only for revised versions)

The history of revisions is a summary of sections that have been revised and sections that have been added to earlier versions. This does not include all of the revised contents. For details, confirm by referring to the main description of this manual.

10.Appendix/Appendices

Rev. 3.0, 10/02, page v of lviii

Rev. 3.0, 10/02, page vi of lviii

Preface

This LSI is a high-performance microcomputer (MCU) made up of the H8S/2000 CPU with Hitachi's original architecture as its co r e, and th e perip heral functions required to configure a system.

The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a 16-Mbyte linear address space. The instruction set of the H8S/2000 CPU maintains upward compatibility at the object level with the H8/300 and H8/300H CPUs. This allows the H8/300, H8/300L, or H8/300H user to easily utilize the H8S/2000 CPU.

This LSI is equipped with ROM, RAM, a direct memory access controller (DMAC), a bus master for a data transfer controller (DTC), a 16-bit timer pulse unit (TPU), an 8-bit timer (TMR), a watchdog timer (WDT), a universal serial bus (USB), two types of serial communication interfaces (SCIs), an A/D converter, a D/A converter, and I/O ports as on-chip peripheral modules for system configuration.

A single-power flash memory (F-ZTAT

) version and masked ROM version are available for this LSI's ROM. The F-ZTAT version provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. This is particularly applicable to application devices with specifications that will most probably change.

This manual describes this LSI's hardware.

Note: * F-ZTAT

is a trademark of Hitachi, Ltd.

Target Users: This manual was written for users who will be using the H8S/2215 Ser ies in the

design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the h ardware fun ctions and electrical

characteristics of the H8S/2215 Series to the target users. Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description of th e instruction set.

Notes on reading this manual:

• In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics.

• In order to understand the details of the CPU's functions

Read the H8S/2600 Series, H8S/2000 Series Programming Manual.

Rev. 3.0, 10/02, page vii of lviii

• In order to understand the details of a register when its name is known

Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial v alues of the registers are summarized in Appen dix A, On-Chip I/O Register.

Examples: Register name: The following notation is used for cases when the same or a

similar function, e.g. 16-bit timer pulse unit or serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number)

Bit order: The MSB is on the left and the LSB is on the right.

Related Manuals: The latest versions of all related manuals ar e available from our web site.

Please ensure you have the latest versions of all documents you require. http://www.hitachisemiconductor.com/

H8S/2215 Series manuals:

Manual Title ADE No.

H8S/2215 Series Hardware Manual This manual H8S/2600 Series, H8S/2000 Series Programming Manual ADE-602-083

User's manuals for development tools:

Manual Title ADE No.

H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual

H8S, H8/300 Series Simulator Debugger (for Windows) Users Manual ADE-702-085 H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi Debugging

Interface Tutorial Hitachi Embedded Workshop User's Manual ADE-702-201

ADE-702-247

ADE-702-231

Rev. 3.0, 10/02, page viii of lviii

List of Items Revised or Added for This Version

Section

1.1 Overview

• On-chip memory

• ComPact Package

1.2 Internal Block Diagram

Figure 1.1 Internal Block Diagram

Page

Description

ROM Product Code ROM RAM Remarks

F-ZTAT Version

Masked ROM Version

HD64F2215 256 kbytes 16 kbytes SCI boot version HD64F2215U 256 kbytes 16 kbytes USB boot version HD6432215A 256 kbytes 16 kbytes In planning HD6432215B 128 kbytes 16 kbytes  HD6432215C 64 kbytes 8 kbytes 

Remarks column amended (Incorrect) Under development

(Correct)



2 Figure amended

NMI FWE* USPND USD+ USD-

VBUS

Interrupts controller

USB

1.3 Pin Arrangement Figure 1.2 Pin

Arrangement (TFP-120)

Note added to figure Note: * The FWE pin is only provided in the flash memory

version.

Figure amended

XTAL

VSS

74737271706968

NMI

FWE*

MD1

MD0

Note added to figure Note: * The FWE pin is only provided in the flash memory

version.

Rev. 3.0, 10/02, page ix of lviii

Section

Page

Description

1.3 Pin Arrangement Figure 1.3 Pin

Arrangement (BP-112)

Figure replaced

23456789 1110

(Reserve)

PD1/D9

PD4/D12

PD7/D15

VSS

PC3/A3

PC6/A6

PB1/A9

PB4/A12

PB7/A15

(Reserve)

PE6/D6

PD0/D8

PD3/D11

PD6/D14

PC1/A1

PC4/A4

PC7/A7

PB3/A11

PB6/A14

PA1/

A17/TxD2

PA2/

A18/RxD2

PE3/D3

PE5/D5

PE7/D7

PD5/D13

PC0/A0

PC2/A2

PB0/A8

PB5/A13

PA0/A16

P10/

TIOCA0/

A20/VM

P11/

TIOCB0/

A21/VP

PE0/D0

PE2/D2

PE4/D4

PD2/D10

VCC

PC5/A5

PB2/A10

PA3/ A19/

SCK2/

SUSPND

P12/

TIOCC0/

TCLKA/

A22/RCV

P13/

TIOCD0/

TCLKB/

A23/VPO

P14/

TIOCA1/

TMS

PG4/

TDO

PG3/

TDI

PE1/D1

TCK

BP-112

(Top view)

P15/

TIOCB1/

P42/AN2

TCLKC/

FSE0

P16/TIO

CA2/

AVSS

TIOCB2/

TCLKD/

P17/

P97/

AN15/DA1

P43/AN3

P96/

AN14/

DA0

PG1/

PG2/

PG0

P70/ TMRI01/ TMCI01/

USPND

Vref

P40/AN0

P41/AN1

P71/

P72/

TMO0/

P73/

TMO1/

P35/

SCK1/

PF3/

MD2

NMI

PLLVCC

DrVCC

VBUS

AVCC

P74/

P34/RxD1

(Reserve)

P36

P33/TxD1

P31/RxD0

P32/

SCK0/

PF0/

PF5/

XTAL

MD0

DrVSS

USD+

P30/TxD0

PF2/

PF6/

EXTAL

VSS

MD1

XTAL48

PLLVSS

USD-

PF1/

PF4/

PF7/

VCC

FWE*

EXTAL48

PLLCAP

(Reserve)

1.5 Pin Functions 11

3.4 Memory Map in Each

Operating Mode Figure 3.1 Memory Map

in Each Operating Mode for HD64F2215, HD64F2215U, and HD6432215A

5.4.1 External Interrupts

Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0

Note added Note: * The FWE pin is only provided in the flash memory

version.

Table amended

Pin No.

Type Symbol TFP-120 BP-112 I/O Function

System Control

FWE

69 H11 Input Pin for use by flash memory. This pin

is only used in the flash memory version. In the mask ROM version it should be fixed at 0.

Description amended Figures 3.1 to 3.3 show the memory map in each operating

mode for HD64F2215,

HD64F2215U, HD6432215A,

HD6432215B, and HD6432215C.

Figure amended (Incorrect) IRQn input

(Correct)

IRQn input

Rev. 3.0, 10/02, page x of lviii

Section

Page

Description

7.1 Features Figure 7.1 Block Diagram

of DMAC

7.4.9 DMAC Bus Cycles (Dual Address Mode)

9.1.4 Pin Functions Table 9.8 P11 Pin

Function Table 9.9 P10 Pin

Function

9.2.5 Pin Functions Table 9.13 P33 Pin

Function

142

182, 184

224

227

Figure amended

Internal interrupts

TGI0A TGI1A TGI2A TXI0 RXI0 TXI1 RXI1 ADI

Control logic

Note added Note: * TEND output cannot be used with this LSI. Address amended

(Incorrect) Other than (B’1111) (Correct) Other than (

B’1110 to B’1111)

Address amended (Incorrect) Other than (B’1111)

(Correct) Other than (

B’1101 to B’1111)

Pin function amended

TE 0 1 P33DDR 0 Pin function P33 input P33 output TxD1 output

Table 9.16 P30 Pin Function

9.8.3 Port C Register (PORTC)

10.1 Features Table 10.1 TPU

Functions

228

244

265

Pin function amended

TE 0 1 P30DDR 0 Pin function P30 input P30 output TxD0 output

Note added Note: * Determined by the states of pins PC7 to PC0. Channel 0 amended

Item Channel 0 Channel 1 Channel 2

General registers/buffer registers

TGRC_0 TGRD_0

not possible not possible

Rev. 3.0, 10/02, page xi of lviii

Section

Page

Description

13.3.9 Serial Extended Mode Register 0 (SEMR_0)

Figure 13.3 Examples of Base Clock when Average Transfer Rate is Selected

375

Figure amended

1234567

1234 56789101112131415 16

234567828 29

1234567

1234 56789101112131415 16

2534

20 21 22 23 24

1234

567

26 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1 2 3 4 5 6 7 8

18 19 20 21 2322 24 25 27 30 31 32 33 3428 29

4567891011121314151617

123

When ø = 16 MHz

Base clock with 115.196 kbps average transfer rate

1234 65 7 8 9 12 13 14 15 1610 11

1.8431 MHz

2 MHz

123456789101112 13141516

(average)

Base clock

16 MHz/8 = 2 MHz

2 MHz × (47/51)= 1.8431 MHz

1 bit = base clock × 16*

Average transfer rate = 1.8431 MHz/16= 115.196 kbps

Average error = -0.004%

18 19 20 21 2322 24 25 26 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1

1234567891011121314151617

Base clock with 460.784 kbps average transfer rate

1234 65 7 8 9 12 13 14 15 1610 11

7.3725 MHz

8 MHz

123456789101112 13141516

(average)

Base clock

16 MHz/2 = 8 MHz

8 MHz × (47/51)= 7.3725 MHz

1 bit = base clock × 16*

Average transfer rate = 7.3725 MHz/16= 460.784 kbps

Average error = -0.004%

242512 5678

11 12 13 14 15 16 17 18 19 20 21 2322

12345678910

Base clock with 720 kbps average transfer rate

12 345 67 8

5.76 MHz

8 MHz

123 45 678

(average)

Base clock

16 MHz/2 = 8 MHz

8 MHz × (18/25)= 5.76 MHz

Average transfer rate = 5.76 MHz/8= 720 kbps

Average error = ±0%

1 bit = base clock × 8*

As the base clock synchronization varies, so does the length of one bit.

Note:

Rev. 3.0, 10/02, page xii of lviii

Section

Page

Description

Figure 13.4 Example of Average Transfer Rate Setting with TPU Clock Input

374

Newly added

56789101112

234

12345678

9101112 1

2345678910111213 12345678910111213

1 1

Main clock: 16 MHz

TIOCA1(TPU_1) output = 8 MHz

TMDR_1 = TMDR_2 = H'C2 [PWM mode 1]

TCR_1 = H'20 [TCNT_1 incremented on rising edge of ø/1, TCNT_1 cleared by TGRA_1 compare match]

TGRB_1 = H'0000, TGRA_1 = H'0001

TIOR_1 = H'21 [1 output on TGRB_1 compare match, TIOCA1 initial output 0, 0 output on TGRA_1 compare match]

TCR_2 = H'2C [TCNT_2 incremented on falling edge of TCLKA (TIOCA1), TCNT_2 cleared by TGRA_2 compare match]

TGRB_2 = H'0000, TGRA_2 = H'000C

TIOR_2 = H'21 [1 output on TGRB_2 compare match, TIOCA2 initial output 0, 0 output on TGRA_2 compare match]

Example for 921.6 kbps when ø = 16 MHz

Generation of clock with 923.077 kbps average transfer rate by means of TPU

(1) An 8 MHz base clock provided by TPU_1 is multiplied by 12/13 by TPU_2 to generate a 7.3846 MHz base clock

(2) By making 1 bit = 8 base clocks, the average transfer rate is made 7.3846 MHz/8 = 923.077 kbps.

Sample TPU and SCI settings

SEMR_0 = H'0C (ABCS = 1, ACS2-0 = B'100)

12345678

TIOCA2 (TPU_2) output

1234 678

8 MHz

7.3846 MHz 1 bit = 8 base clocks*

12345678

= 7.3846 MHz

= 8 MHz x 12/13

Internal base clock

Average error relative to 921.6 kbps = +0.16%

Average transfer rate = 7.3846 MHz/8 = 923.077 kbps

Note: * As the base clock synchronization varies, so does the length of one bit.

Rev. 3.0, 10/02, page xiii of lviii

Section

Page

Description

13.7 SCI Select Function Figure 13.24 Example of

Communication Using the SCI Select Function

Figure 13.25 Operation of Communication Using the SCI Select Function

14.3.2 IDCODE Register (IDCODE)

Table 14.3 IDCODE Register Configuration

406

407

422

Added Note: * The selection signals (SEL_A and SEL_B) of the LSI

must be switched while the serial clock (M_SCK) is high after the end bit of the transm it data has been send. Note that one selection signal can be brought low at the same tim e.

Figure title amended Added

Note: * The selection signals (SEL_A and SEL_B) of the LSI must be switched while the serial clock (M_SCK) is high after the end bit of the transm it data has been send. Note that one selection signal can be brought low at the same tim e.

3rd line changed as follows The HD64F2215, HD64F2215U, HD6432215A,

HD6432215B, and HD6432215C output fixed codes H’0002200F, H’0003200F, H’001B200F, and H’001C200F, respectively, from the TDO.

Code amended (Incorrect) HD64F2215 code

(Correct) HD64F2215 code,

HD64F2215U code

15.1 Features Endpoint configuratio n

•

selectable

433 Replaced

The FIFO buffer for bulk transfer and isochronous transfer has a double-buffer configuration

Total 1288-byte FIFO —EP0s fixed: Control_setup FIFO, 8 bytes —EP0i fixed: Control_in FIFO, 64 bytes —EP0o fixed: Control_out FIFO, 64 bytes —EPn selectable: Interrupt_in FIFO, variable 0 to 64 bytes —EPn selectable: Bulk_in FIFO, 64 bytes x 2 (double-buffer configuration) —EPn selectable: Bulk_out FIFO, 64 bytes x 2 (double-buffer configuration) —EPn selectable: Isochronous_in FIFO, variable 0 to 128 bytes x 2 (double-buffer configuration) —EPn selectable: Isochronous_out FIFO, variable 0 to 128 bytes x 2 (double-buffer configuration) —EPn selectable: Bulk_in FIFO, 64 bytes x 2 (double-buffer configuration) —EPn selectable: Bulk_out FIFO, 64 bytes x 2 (double-buffer configuration) —EPn selectable: Interrupt_in FIFO, variable 0 to 64 bytes

Rev. 3.0, 10/02, page xiv of lviii

Section

Page

Description

15.1 Features

• Maximum Configuration, InterfaceNumber, and AlternateSetting configuration specifications of this LSI Configuration

Figure 15.1 Block Diagram of USB

15.3.1 USB Endpoint

Information Registers 00_0 to 22_4 (UEPIR00_0 to UEPIR22_4)

434

435

438

Endpoint configuration based on Bluetooth standard 1.0 can be specified.

Deleted Newly added

Maximum Configuration, InterfaceNumber, an d

•

AlternateSetting configuration specificatio ns of this LSI Configuration 1 ----- InterfaceNumber 0 to 2 ----AlternateSetting 0 to 7 ----- EP0, EP1 to EP8

Figure amented

1288-byte FIFO

EP0o

EP2iEP0s

EP2o

EP3i

EP3oEP1i

EP4i

EP4oEP0i

EP5i

Explanation added to 23th line as follows UEPIR is used to set

23 kinds of endpoint (EPINFO data).

• UEPIRnn_0 439

Replaced

•••• UEPIRnn_0

Bit Bit Name Initial Value R/W Description

D39 –D36 — R/W Endpoint number (4-bit configuration, settable

to4

32D35

D34

10D33

D32

— —

R/W R/W

values: 0 to 8) 0000: Control transfer (EP0) 0001 to 1000: Other than Control transfer (EP1 to

EP8) There are restrictions on settable endpoint

numbers according to the Interface number and Alternate number to which the endpoint belongs.

Restriction 1: Set different endpoint numbers

under one Alternate. However, there is no problem with

use of the same endpoint number if the transfer directions (IN/OUT) are different. (Ex: Alt0 -- EP1, EP2i, EP2o)

Restriction 2: Do not set the same endpoint

number under different Interface numbers. (Ex: Int0 -- Alt0 -- EP1, EP2, Int1 -- Alt0 -- EP3)

Configuration number to which endpoint belongs (2-bit configuration, settable values: 0, 1)

00: Control transfer 01: Other than Control transfer Interface number to which endpoint belongs (2-bit

configuration, settable values: 0 to 2) 00: Control transfer 00 to 10: Other than Control transfer

Rev. 3.0, 10/02, page xv of lviii

Section

Page

Description

15.3.1 USB Endpoint Information Registers 00_0 to 22_4 (UEPIR00_0 to UEPIR22_4)

UEPIRnn_1

•

UEPIRnn_2

•

440

Replaced

UEPIRnn_1

Bit Bit Name Initial Value R/W Description

7 to5D31 –D29 — R/W Alternate number to which endpoint belongs (3-bit

43D28

D27

2D26 — R/W Endpoint transfer direction (1-bit configuration)

10D25

D24

UEPIRnn_2

Bit Bit Name Initial Value R/W Description

7 to0D23 –D16 — R/W Endpoint maximum packet size (D25 to D16 10-bit

— —

R/W R/W

configuration, settable values: 0 to 7) 000: Control transfer 001 to 111: Other than Control transfer Endpoint transfer type (2-bit configuration) 00: Control(UEPIR00) 01: Isochronous(UEPIR04 to UEPIR19) 10: Bulk(UEPIR02,UEPIR03,UEPIR20,UEPIR21) 11: Interrupt(UEPIR01,UEPIR22)

0: out (UEPIR00,03,05,07,09,11,13,15,17,19,21) 1: in (UEPIR01,02,04,06,08,10,12,14,16,18,20,22) Endpoint maximum packet size (D25 to D16 10-bit

configuration) Control transfer = 64 only (UEPIR00) Interrupt transfer = 0 to 64 (UEPIR01, UEPIR22) Bulk transfer = 0 or 64 (UEPIR02, UEPIR03,

UEPIR20, UEPIR21) Isochronous transfer = 0 to 128 (UEPIR04 to

UEPIR19)

configuration) Control transfer = 64 only (UEPIR00)Interrupt transfer = 0 to 64 (UEPIR01, UEPIR22) Bulk transfer = 0 or 64 (UEPIR02,UEPIR03, UEPIR20, UEPIR21) Isochronous transfer = 0 to 128 (UEPIR04 to UEPIR19)

• UEPIRnn_3 441

• UEPIRnn_4

Table 15.2 EPINFO Data

444

Settings

Replaced

UEPIRnn_3

Bit Bit Name Initial Value R/W Description

7 to0D15 –D8 — R/W Endpoint internal address (D15 to D0 16-bit

UEPIRnn_4

Bit Bit Name Initial Value R/W Description

7 to0D7 –D0 — R/W Endpoint internal address (D15 to D0 16-bit

configuration) Set UEPIR00_3, UEPIR00_4 = H'0000 Set UEPIR01_3, UEPIR01_4 = H'0001

: Set UEPIR21_3, UEPIR21_4 = H'0015 Set UEPIR22_3, UEPIR22_4 = H'0016

configuration) Set UEPIR00_3, UEPIR00_4 = H'0000 Set UEPIR01_3, UEPIR01_4 = H'0001

: Set UEPIR21_3, UEPIR21_4 = H'0015 Set UEPIR22_3, UEPIR22_4 = H'0016

Note amended Notes:*5

Maximum packet size of Isochronous transfer must be from 0 to 128.

Rev. 3.0, 10/02, page xvi of lviii

Section

Page

Description

15.3.11 USB Endpoint Data Register 0s (UEDR0s)

15.3.12 USB Endpoint Data Register 0i (UEDR0i)

15.3.13 USB Endpoint Data Register 0o (UEDR0o)

15.3.14 USB Endpoint Data Register 1i (UEDR1i)

15.3.15 USB Endpoint Data Register 2i (UEDR2i)

15.3.16 USB Endpoint Data Register 2o (UEDR2o)

457

458

2nd line changed as follows (Incorrect) Endpoint0

(Correct) Endpoint0

s 9th line changed as follows (Incorrect) Endpoint0

(Correct) Endpoint0

i 15th line changed as follows (Incorrect) Endpoint0

(Correct) Endpoint0

o 2nd line changed as follows (Incorrect) Endpoint1

(Correct) Endpoint1

i 8th line changed as follows (Incorrect) Endpoint2

(Correct) Endpoint2

i 14th line changed as follows (Incorrect) Endpoint2

(Correct) Endpoint2

15.3.17 USB Endpoint Data Register 3i (UEDR3i)

15.3.18 USB Endpoint Data Register 3o (UEDR3o)

15.3.19 USB Endpoint Data Register 4i (UEDR4i)

15.3.20 USB Endpoint Data Register 4o (UEDR4o)

15.3.21 USB Endpoint Data Register 5i (UEDR5i)

15.3.22 USB Endpoint Receive Data Size Register 0o (UESZ0o)

459

460

2nd line changed as follows (Incorrect) Endpoint3

(Correct) Endpoint3

i 9th line changed as follows (Incorrect) Endpoint3

(Correct) Endpoint3

o 15th line changed as follows (Incorrect) Endpoint4

(Correct) Endpoint4

i 2nd line changed as follows (Incorrect) Endpoint4

(Correct) Endpoint4

o 7th line changed as follows (Incorrect) Endpoint5

(Correct) Endpoint5

i 13th line changed as follows (Incorrect) Endpoint0

(Correct) Endpoint0

Rev. 3.0, 10/02, page xvii of lviii

Section

Page

Description

15.3.23 USB Endpoint Receive Data Size Register 2o (UESZ2o)

15.3.24 USB Endpoint Receive Data Size Register 3o (UESZ3o)

15.3.25 USB Endpoint Receive Data Size Register 4o (UESZ4o)

461

2nd line changed as follows (Incorrect) Endpoint2

(Correct) Endpoint2

o 4th line changed as follows (Incorrect) The FIFO for endpoint 2 out transfer has a dual-

FIFO configuration (Correct) The FIFO for endpoint 2

o (for Bulk_out transfer) has

a dual-FIFO configuration

line changed as follows

7 (Incorrect) Endpoint3

(Correct) Endpoint3o 9th line changed as follows (Incorrect) The FIFO for endpoint 3 out transfer has a dual-

FIFO configuration. (Correct) The FIFO for endpoint 3

o (for Isochronous_out

transfer) has a dual-FIFO configuration.

line changed as follows

12 (Incorrect) Endpoint4

(Correct) Endpoint4o

15.3.30 USB Interrupt Enable Register 0 (UIER0)

15.3.34 USB Interrupt Select Register 0 (UISR0)

470

472

14th line changed as follows (Incorrect) The FIFO for endpoint 4 out transfer has a dual-

FIFO configuration. (Correct) The FIFO for endpoint 4o (for Bulk_out transfer) has a dual-FIFO configuration.

Bit table amended

Bit Bit Name Initial Value R/W Description

7 BRSTE 0 R/W Enables the BRST interrupt. 6 — 0RReserved

This bit is always read as 0. 5 EP1iTRE 0 R/W Enables the EP1iTR interrupt. 4 EP1iTSE 0 R/W Enables the EP1iTS interrupt.

Bit table amended

Bit Bit Name Initial Value R/W Description

7 BRSTS 0 R/W Selects the BRST interrupt output pin. 6 — 0RReserved

This bit is always read as 0. 5 EP1iTRS 0 R/W Selects the EP1iTR interrupt output pin. 4 EP1iTSS 0 R/W Selects the EP1iTS interrupt output pin. 3 EP0oTSS 0 R/W Selects the EP0oTS interrupt output pin. 2 EP0iTRS 0 R/W Selects the EP0iTR interrupt output pin. 1 EP0iTSS 0 R/W Selects the EP0iTS interrupt output pin. 0 SetupTSS 0 R/W Selects the SetupTS interrupt output pin.

Rev. 3.0, 10/02, page xviii of lviii

Section

Page

Description

15.3.42 USB Test Register 1 (UTSTR1)

Table 15.4 Relationship between the UTSTR1 Settings and Pin Inputs

479

480

Bit table amended and Note added

Bit Bit Name Initial Value R/W Description

76VBUS

UBPM

5 to 3 — 0 R Reserved

RCV

Note:* An asterisk indicates an undefined value.

—

Internal/External Transceiver Input Signal Monitor Bits

VBUS: Monitors VBUS pin

UBPM: Monitors UBPM pin

These bits are always read as 0 and cannot be

modified.

Internal/External Transceiver Input Signal Monitor Bits

RCV: Monitors the RCV signal of the internal/external

transceiver

VP: Monitors the VP signal of the internal/external

transceiver

VM: Monitors the VM signal of the internal/external

transceiver

UTSTR1 Monitor value amended

UTSTR1 Monitor

RCV VP VM

000 0/1 0 0 X00 001 110 X11 X00 001 110 X11 0 0/1 X 0X0/1 0/1 X X X0/1X XX0/1

15.3.44 Module Stop

481 Control Register B (MSTPCRB)

Section title amended

Rev. 3.0, 10/02, page xix of lviii

Section

Page

Description

15.5.9 Isochronous–Out Transfer (Dual-FIFO) (When EP3o is Specified as Endpoint)

Figure 15.21 EP3o Isochronous-Out Transfer Operation

507

Figure amended

USB function

Receive SOF

Switch to FIFO

Receive OUT token

Receive data from the host

Receive data

error?

Set EP3o normal

receive status to 1

(Set internal EP3o TS to 1)

B-side UIFR1/EP3oTS, EP3oTF update

FIFO A

Yes

Set EP3o abnormal

receive status to 1

(Set internal EP3o TF to 1)

Receive SOF

Switch to FIFO

Receive OUT token

Receive data from the host

Receive data

error?

Yes

Set EP3o normal

receive status to 1

(Set Internal EP3o TS to 1

A-side UIFR1/EP3oTS, EP3oTF update

FIFO B

Set EP3o abnormal

)

receive status to 1

(Set Internal EP3o TF to 1)

15.5.10 Processing of

508 USB Standard Commands and Class/Vendor Commands

Rev. 3.0, 10/02, page xx of lviii

11th line changed as follows (Incorrect) EXIROx pin

(Correct) EXIROx

Section

Page

Description

15.8 USB External Circuit Example

Figure 15.27 USB External Circuit in BusPowered Mode (When OnChip Transceiver is Used)

Figure 15.28 USB External Circuit in SelfPowered Mode (When OnChip Transceiver is Used)

Figure 15.29 USB External Circuit in BusPowered Mode (W hen External Transceiver is Used)

Figure 15.30 USB External Circuit in SelfPowered Mode (W hen External Transceiver is Used)

521 to 524

Note *3 amended

In HD64F2215, HD6432215A, HD6432215B, and HD6432215C, Pxx should be assigned

to an output port as the D+ pull-up control pin. In HD64F2215U, in which on-chip ROM can be programmed by using the USB, P36 should be used as the D+ pull-up control pin.

15.9.7 EP3o Isochronous Transfer Figure 15.32 EP3o Date Reception

528

Figure amended

[In frame N]

Receive USB data (1)

[In frame N+1]

Receive USB data (2)

[In frame N+2]

Receive USB data (3)

EP3o FIFO A

Data (1) Modify

EP3o FIFO B

———

EP3o FIFO A Internal flag (A-side)

Data (1)

EP3o FIFO B

Data (2)

EP3o FIFO A Internal flag (A-side)

Data (3)

EP3o FIFO B

Data (2)

Internal flag (A-side) UIFR1

TSTF

Internal flag (B-side)

Next frame

TSTF

Internal flag (B-side)

TSTF

Next frame

TSTF

Internal flag (B-side)

TSTF

Modify

No change

——

UIFR1

A-side flag update

TSTF

Can be read

Data (1) can be read in frame [N+1]

UIFR1

B-side flag update

Can be read

TSTF

Data (2) can only be read in frame [N+2]

Rev. 3.0, 10/02, page xxi of lviii

Section

Page

Description

15.9.8 Reset 529

16.3.3 A/D Control

538 Register (ADCR)

Explanation amended to 2nd line chang ed as foll ow s A manual reset should not be performed during USB

communication as the LSI will stop with the USD+USD- pin state maintained.This USB module uses synchronous reset for some registers. The reset state of these registers must be cancelled after the clock oscillation stabilizatio n time has passed. At initialization, reset must be cancelled using the following procedure.

Table amended

Bit Bit Name Initial Value R/W Description

54—

—

32CKS1

CKS000

10—

—

1 1

——Reserved

These bits are always read as 1 cannot be modified.

R/W

Clock Select 0 and 1

R/W

These bits specify the A/D conversion time. The conversion time should be changed only when ADST =

0. Specify a setting that gives a value within the range shown in table 24.7.

00: Conversion time = 530 states (max.) 01: Conversion time = 266 states (max.) 10: Conversion time = 134 states (max.) 11: Conversion time = 68 states (max.)

The conversion time setting should exceed the conversion time shown in section 24.6, A/D Converter Characteristics.

——Reserved

These bits are always read as 1 cannot be modified.

18. RAM 555

Lineup added

Product Class ROM Type RAM Size RAM Address

H8S/2215 series

HD64F2215 HD64F2215U HD6432215A

HD6432215B HD6432215C

Flash memory Version

Masked ROM Version

16 kbytes H'FFB000 to H'FFEFBF

H'FFFFC0 to H'FFFFFF

8 kbytes H'FFD000 to H'FFEFBF

H'FFFFC0 to H'FFFFFF

Rev. 3.0, 10/02, page xxii of lviii

Section

Page

Description

19.1 Features

• Size

Two flash memory

•

operating modes

• Automatic bit rate adjustment

(SCI boot

mode)

19.2 Mode Transitions

559

Table newly added

Product Category

H8S/2215 Series HD64F2215,HD64F2215U

Description added

Boot mode



(SCI boot mode: HD64F2215, USB boot

mode: HD64F2215U)

 User program mode

On-board programming/erasing can be done in boot mode in which the boot program built into the chip is started for erase or programming of the entire flash memory. In normal user program mode, individual blocks can be erased or programmed.

 With data transfer in

bit rate can be automatically adjusted to match the transfer bit rate of the host

Figure amended

ROM Size ROM Addresses

256 kbytes

H'000000 to H'03FFFF

(Modes 6 and 7)

SCI boot mode, this LSI’s

Figure 19.2 Flash Memory State Transitions

Table 19.1 Differences between Boot Mode and User Program Mode

19.2 Mode Transitions

Figure 19.3 Boot Mode Figure 19.4 Boot Mode

560

561 562

User

program mode

SCI,USB

Boot mode

On-board programming mode

(Incorrect) Boot Mode (Correct)

SCI,USB Boot Mode

Description amended in 5th line of "2. Programming control program transfer" in Figure 19.3, Boot Mode

When boot mode is entered, the boot program in this LSI (originally incorporated in the chip) is started and the programming control program in the host is transferre d to RAM via SCI

or USB

Figures 1 to 4 amended (Incorrect) SCI

(Correct) SCI

or USB

Rev. 3.0, 10/02, page xxiii of lviii

Section

Page

Description

19.4 Input/Output Pins Table 19.2 Pin

Configuration

19.6 On-Board Programming Modes

Table 19.3 Setting OnBoard Programming Modes

19.6.1 SCI Boot Mode (HD64F2215)

564

571

571 to 574

Figure amended

Pin Name I/O Function

RES Input Reset FWE Input Flash program/erase protection by hardware MD2,MD1,MD0 Input Sets this LSI's operating mode PF3,PF0,P16,

P14 TxD2 Output Serial transmit data output RxD2 Input Serial receive data input USB+,USB- Input/Output USB data output VBUS Input USB cable connection/disconnection detection UBPM Input USB bus power mode/self power mode setting USPND Output USB suspend output P36 Output D+ pull-up control

Input Sets this LSI's operating mode in

programmer mode

(Incorrect) Boot mode (Correct)

SCI boot mode(HD64F2215)

USB boot mode(HD64F2215U)

Amended (Incorrect) Boot Mode

(Correct) SCI Boot Mode

HD64F2215 and HD64F2215U

HD64F2215

HD64F2215U

Figure 19.6 SCI System Configuration in Boot Mode

19.6.2 USB Boot Mode (HD64F2215U)

19.8.1 Program/ProgramVerify

572 Figure amended

01X MD2 to 0*

Note added to figure Note: * FWE pin and mode pin input must satisfy the mode

programming setup time (t when a reset is released.

575 to

Newly added

579 583

33th line changed as follows Verify data can be read in words from the address to which a

dummy write was performed.

FWE*

H8S/2215 Series

Flash memory

= 200 ns)

MDS

19.8.2 Erase/Erase-Verify 585

Rev. 3.0, 10/02, page xxiv of lviii

11th line changed as follows Verify data can be read in

words from the address to which a

dummy write was performed.

Section

Page

Description

21.1.2 Low-Power

Control Register (LPWRCR)

21.2.2 Inputting an

External Clock

21.6.1 Connecting a

Ceramic Resonator Figure 21.6 Connection

of Ceramic Resonator

598

601

602

Bit name amended

Bit Bit Name Initial Value R/W Description

7 to4— 0 R/W These bits can be read from or written to, but the write

3 RFCUT 0 R/W Built-in Feedback Resistor Control:

value should always be 0.

Selects whether the oscillator’s built-in feedback resistor and duty adjustment circuit are used with external clock input. This bit should not be accessed when a crystal oscillator is used.

After this bit is set when using external clock input, a transition should initially be made to software standby mode. Switching between use and non-use of the oscillator’s built-in feedback resistor and dut y adjustment circuit is performed when the transition is made to software standby mode.

0: System clock oscillator’s built-in feedback resistor

and duty adjustment circuit are used

1: System clock oscillator’s built-in feedback resistor

and duty adjustment circuit are not used

3rd line changed as follows

The external clock input conditions when the duty adjustment circuit is not used are shown in table

21.4. When the duty adjustment circuit is not used, note that the maximum operating frequency = T

depends on the external clock input waveform. For example, if t = 6.25 ns, the maximum operating frequency becomes 13.3 MHz depending on the clcok cycle time of 75 ns.

EXL

= 31.25ns and t

EXH

= t

EXr

EXf

Condition amended

EXTAL48

XTAL48

Ceramic

Resonator

Ta = 0 to 70 C Contact the representative mentioned below for details of Rf and Rd values.

Ceramic resonator: CSTCW48M0X11 -R (Murata Manufacturing Co.,Ltd.)

23.3 Register States in Each Operating Mode

24.2 Power Supply Voltage and Operating Frequency Range

Figure 24.1 Power Supply Voltage and Operating Ranges

642, 643, 645, 648

Manual reset amendment: Register Names UCTLR to UESTL1, UEDR0i, UEDR1i, UEDR2i, UEDR3i, UEDR4i, UEDR5i, UIFR0 to UTSTRF, ABWCR to BCRL, FLMCR1 to EBR2

(Incorrect) Initialized (Correct)



650 Newly added to figure

(3) When USB boot program is executed by HD64F2215U

16.0

13.0

system clock

2.7 3.0

f(MHz)

With operation of USB operating clock (48 MHz) provided by PLL3 multiplication

PLLVcc, DrVcc, AVcc (V)

3.6

Rev. 3.0, 10/02, page xxv of lviii

Section

Page

Description

24.3 DC Characteristics Table 24.2 DC

Characteristics

24.4.4 Timing of On-Chip Supporting Modules

Figure 24.21 Boundary Scan TCK Input Timing

24.8 Flash Memory Characteristics

Table 24.11 Flash Memory Characteristics

651 Table amended

Item Symbol Min Typ Max Unit

Schmitt IRQ0 to IRQ5 V trigger input voltage

Input high voltage

IRQ7 V

RES , STBY ,

NMI, MD2 to MD0, TRST , TCK, TMS, TDI, VBUS, UBPM ,

FWE* EXTAL,

EXTAL48, Ports 1, 3, 7, and A to G

Ports 4 and 9 VCC 0.8 — AVCC + 0.3 V

668 Figure amended

TCK

672

Table amended

673

Item Symbol Min Typ Max Unit

Programming time* Erase time* Reprogramming count N Data retention time

1,*3,*5

1 *2,*4

Test

–

VCC × 0.2 ——V

——VCC ⋅ 0.8 V

–

– V

VCC × 0.05 ——V

VCC × 0.9 — V

VCC ×× 0.8 — V

tcyc

TCKH

TCKL

— 10 200 ms/128 bytes — 50 1000 ms/block 100 10,000 100 Times

WEC

10 ——Year

DRP

+ 0.3 V

Conditions

B. Product Model Lineup 679

Notes added *6 Minimum number of times for which all characteristics are guaranteed after rewriting. (Guarantee range is 1 to minimum value.)

*7 Reference value for 25°C (as a guideline, rewriting should normally function up to this value).

*8 Data retention characteristic when rewriting is performed within the specification range, including the minimum value.

Linup added

Product Class

H8S/2215 Flash memory

Version

Masked ROM Version

Product Type Name Marking Package (code)

HD64F2215 HD64F2215TE 120 pin TQFP (TFP-120)

HD64F2215BR 112 pin P-LFBGA (BP-112) HD64F2215UTE 120 pin TQFP(TEP-120)HD64F2215U HD64F2215UBR 112 pin P-LFBGA(BP-112)

HD6432215A HD6432215A(***)TE 120 pin TQFP (TFP-120)

HD6432215A(***)BR 112 pin P-LFBGA (BP-112)

HD6432215B HD6432215B(***)TE 120 pin TQFP (TFP-120)

HD6432215B(***)BR 112 pin P-LFBGA (BP-112)

HD6432215C HD6432215C(***)TE 120 pin TQFP (TFP-120)

HD6432215C(***)BR 112 pin P-LFBGA (BP-112)

Rev. 3.0, 10/02, page xxvi of lviii

Section

Page

Description

C. Package Dimensions Figure C.2 BP-112 Package Dimension

680

Replaced

B C

0.20

10.00

4 ×

0.2

10.00

0.15

Unit: mm

0.20

0.80

1110987654321

1.00

0.80

112 × φ0.50 ± 0.05

φ0.08

A B C D E F G H

J K L

0.10

1.40 Max

0.40 ± 0.05

Hitachi Code JEDEC JEITA Mass

(reference value)

BP-112 – –

0.3 g

Rev. 3.0, 10/02, page xxvii of lviii

Rev. 3.0, 10/02, page xxviii of lviii

Contents

Section 1 Overview............................................................................................1

1.1 Overview...........................................................................................................................1

1.2 Internal Block Diagram.....................................................................................................2

1.3 Pin Arrangement...............................................................................................................3

1.4 Pin Functions in Each Operating Mode............................................................................5

1.5 Pin Functions ....................................................................................................................10

Section 2 CPU....................................................................................................19

2.1 Features.............................................................................................................................19

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU..................................20

2.1.2 Differences from H8/300 CPU ............................................................................21

2.1.3 Differences from H8/300H CPU..........................................................................21

2.2 CPU Operating Modes......................................................................................................22

2.2.1 Normal Mode.......................................................................................................22

2.2.2 Advanced Mode...................................................................................................23

2.3 Address Space...................................................................................................................26

2.4 Register Configuration......................................................................................................27

2.4.1 General Registers.................................................................................................28

2.4.2 Program Counter (PC).........................................................................................29

2.4.3 Extended Control Register (EXR).......................................................................29

2.4.4 Condition-Code Register (CCR)..........................................................................30

2.4.5 Initial Register Values..........................................................................................32

2.5 Data Formats.....................................................................................................................32

2.5.1 General Register Data Formats............................................................................32

2.5.2 Memory Data Formats.........................................................................................34

2.6 Instruction Set...................................................................................................................35

2.6.1 Table of Instructions Classified by Function.......................................................36

2.6.2 Basic Instruction Formats....................................................................................45

2.7 Addressing Modes and Effective Address Calculation .....................................................46

2.7.1 Register Direct—Rn.............................................................................................47

2.7.2 Register Indirect—@ERn....................................................................................47

2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) ..............47

2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn..47

2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32....................................47

2.7.6 Immediate—#xx:8, #xx:16, or #xx:32.................................................................48

2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)....................................48

2.7.8 Memory Indirect—@@aa:8................................................................................48

2.7.9 Effective Address Calculation .............................................................................49

2.8 Processing States...............................................................................................................52

Rev. 3.0, 10/02, page xxix of lviii

2.9 Usage Notes.......................................................................................................................53

2.9.1 Note on TAS Instruction Usage...........................................................................53

2.9.2 STM/LTM Instruction Usage...............................................................................53

2.9.3 Note on Bit Manipulation Instructions.................................................................54

Section 3 MCU Operating Modes......................................................................55

3.1 Operating Mode Selection.................................................................................................55

3.2 Register Descriptions ........................................................................................................56

3.2.1 Mode Control Register (MDCR)..........................................................................56

3.2.2 System Control Register (SYSCR) ......................................................................57

3.3 Operating Mode Descriptions............................................................................................58

3.3.1 Mode 4 .................................................................................................................58

3.3.2 Mode 5 .................................................................................................................58

3.3.3 Mode 6 .................................................................................................................59

3.3.4 Mode 7 .................................................................................................................59

3.3.5 Pin Functions........................................................................................................ 59

3.4 Memory Map in Each Operating Mode.............................................................................61

Section 4 Exception Handling.............................................................................65

4.1 Exception Handling Types and Priority ............................................................................65

4.2 Exception Sources and Exception Vector Table ...............................................................65

4.3 Reset..................................................................................................................................67

4.3.1 Reset Types..........................................................................................................67

4.3.2 Reset Exception Handling....................................................................................68

4.3.3 Interrupts after Reset............................................................................................69

4.3.4 State of On-Chip Peripheral Modules after Reset Release...................................69

4.4 Traces...................................................................................................................... ..........70

4.5 Interrupts ........................................................................................................................... 70

4.6 Trap Instruction.................................................................................................................71

4.7 Stack Status after Exception Handling..............................................................................72

4.8 Notes on Use of the Stack .................................................................................................73

Section 5 Interrupt Controller............................................................................75

5.1 Features ............................................................................................................................. 75

5.2 Input/Output Pins ..............................................................................................................77

5.3 Register Descriptions ........................................................................................................77

5.3.1 Interrupt Priority Registers A to G, I to K, M

(IPRA to IPRG, IPRI to IPRK, IPRM).................................................................78

5.3.2 IRQ Enable Register (IER)...................................................................................79

5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL).....................................80

5.3.4 IRQ Status Register (ISR)....................................................................................82

5.4 Interrupt Sources ...............................................................................................................83

5.4.1 External Interrupts................................................................................................83

Rev. 3.0, 10/02, page xxx of lviii

+ 715 hidden pages

Hitachi H8S/2215 Hardware Manual

Specifications and Main Features

Frequently Asked Questions

User Manual