Hitachi H8S/2215 Hardware Manual

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Page 1

Hitachi Single-Chip Microcomputer

H8S/2215 Series

Hardware Manual

ADE-602-217B Rev. 3.0 10/04/02 Hitachi Ltd.

Page 2

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high qua lity and reliability or where its failure or malfunction m a y dir ectly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no respon sib ility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.

Rev. 3.0, 10/02, page ii of lviii

Page 3

General Precautions on the Handling of Products

1. Treatment of NC Pins Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malf unction may occur.

3. Processing before Initialization Note: When power is first supplied, the product’s state is undefined. The states of internal

circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Address Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these address. Do not access these registers: the system’s operation is not guaranteed if they are accessed.

Rev. 3.0, 10/02, page iii of lviii

Page 4

Rev. 3.0, 10/02, page iv of lviii

Page 5

Configuration of this Manual

This manual comprises the fo llowing items:

1. Precautions in Relation to this Product

2. Configuration of this Manual

3. Overview

4. Table of Contents

5. Summary

6. Description of Functional Modules

• CPU and System-Control Modules

• On-chip Peripheral Modules The configuration of the functional description of each module differs according to the module.

However, the generic style includes the following items: i) Features ii) I/O pins iii) Description of Registers iv) Description of Operation v) Usage: Points for Caution

When designing an app lication system that includes this LSI, take the points for caution into account. Each section includes points for caution in relation to the descriptions given, and points for caution in usage are given, as required, as the final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

• Product-type codes and external dimensions

• Major revisions or addenda in this version of the manual (only for revised versions)

The history of revisions is a summary of sections that have been revised and sections that have been added to earlier versions. This does not include all of the revised contents. For details, confirm by referring to the main description of this manual.

10.Appendix/Appendices

Rev. 3.0, 10/02, page v of lviii

Page 6

Rev. 3.0, 10/02, page vi of lviii

Page 7

Preface

This LSI is a high-performance microcomputer (MCU) made up of the H8S/2000 CPU with Hitachi's original architecture as its co r e, and th e perip heral functions required to configure a system.

The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a 16-Mbyte linear address space. The instruction set of the H8S/2000 CPU maintains upward compatibility at the object level with the H8/300 and H8/300H CPUs. This allows the H8/300, H8/300L, or H8/300H user to easily utilize the H8S/2000 CPU.

This LSI is equipped with ROM, RAM, a direct memory access controller (DMAC), a bus master for a data transfer controller (DTC), a 16-bit timer pulse unit (TPU), an 8-bit timer (TMR), a watchdog timer (WDT), a universal serial bus (USB), two types of serial communication interfaces (SCIs), an A/D converter, a D/A converter, and I/O ports as on-chip peripheral modules for system configuration.

A single-power flash memory (F-ZTAT

) version and masked ROM version are available for this LSI's ROM. The F-ZTAT version provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. This is particularly applicable to application devices with specifications that will most probably change.

This manual describes this LSI's hardware.

Note: * F-ZTAT

is a trademark of Hitachi, Ltd.

Target Users: This manual was written for users who will be using the H8S/2215 Ser ies in the

design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the h ardware fun ctions and electrical

characteristics of the H8S/2215 Series to the target users. Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description of th e instruction set.

Notes on reading this manual:

• In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics.

• In order to understand the details of the CPU's functions

Read the H8S/2600 Series, H8S/2000 Series Programming Manual.

Rev. 3.0, 10/02, page vii of lviii

Page 8

• In order to understand the details of a register when its name is known

Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial v alues of the registers are summarized in Appen dix A, On-Chip I/O Register.

Examples: Register name: The following notation is used for cases when the same or a

similar function, e.g. 16-bit timer pulse unit or serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number)

Bit order: The MSB is on the left and the LSB is on the right.

Related Manuals: The latest versions of all related manuals ar e available from our web site.

Please ensure you have the latest versions of all documents you require. http://www.hitachisemiconductor.com/

H8S/2215 Series manuals:

Manual Title ADE No.

H8S/2215 Series Hardware Manual This manual H8S/2600 Series, H8S/2000 Series Programming Manual ADE-602-083

User's manuals for development tools:

Manual Title ADE No.

H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual

H8S, H8/300 Series Simulator Debugger (for Windows) Users Manual ADE-702-085 H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi Debugging

Interface Tutorial Hitachi Embedded Workshop User's Manual ADE-702-201

ADE-702-247

ADE-702-231

Rev. 3.0, 10/02, page viii of lviii

Page 9

List of Items Revised or Added for This Version

Section

1.1 Overview

• On-chip memory

• ComPact Package

1.2 Internal Block Diagram

Figure 1.1 Internal Block Diagram

Page

Description

ROM Product Code ROM RAM Remarks

F-ZTAT Version

Masked ROM Version

HD64F2215 256 kbytes 16 kbytes SCI boot version HD64F2215U 256 kbytes 16 kbytes USB boot version HD6432215A 256 kbytes 16 kbytes In planning HD6432215B 128 kbytes 16 kbytes  HD6432215C 64 kbytes 8 kbytes 

Remarks column amended (Incorrect) Under development

(Correct)



2 Figure amended

NMI FWE* USPND USD+ USD-

VBUS

Interrupts controller

USB

1.3 Pin Arrangement Figure 1.2 Pin

Arrangement (TFP-120)

Note added to figure Note: * The FWE pin is only provided in the flash memory

version.

Figure amended

XTAL

VSS

74737271706968

NMI

FWE*

MD1

MD0

Note added to figure Note: * The FWE pin is only provided in the flash memory

version.

Rev. 3.0, 10/02, page ix of lviii

Page 10

Section

Page

Description

1.3 Pin Arrangement Figure 1.3 Pin

Arrangement (BP-112)

Figure replaced

23456789 1110

(Reserve)

PD1/D9

PD4/D12

PD7/D15

VSS

PC3/A3

PC6/A6

PB1/A9

PB4/A12

PB7/A15

(Reserve)

PE6/D6

PD0/D8

PD3/D11

PD6/D14

PC1/A1

PC4/A4

PC7/A7

PB3/A11

PB6/A14

PA1/

A17/TxD2

PA2/

A18/RxD2

PE3/D3

PE5/D5

PE7/D7

PD5/D13

PC0/A0

PC2/A2

PB0/A8

PB5/A13

PA0/A16

P10/

TIOCA0/

A20/VM

P11/

TIOCB0/

A21/VP

PE0/D0

PE2/D2

PE4/D4

PD2/D10

VCC

PC5/A5

PB2/A10

PA3/ A19/

SCK2/

SUSPND

P12/

TIOCC0/

TCLKA/

A22/RCV

P13/

TIOCD0/

TCLKB/

A23/VPO

P14/

TIOCA1/

TMS

PG4/

TDO

PG3/

TDI

PE1/D1

TCK

BP-112

(Top view)

P15/

TIOCB1/

P42/AN2

TCLKC/

FSE0

P16/TIO

CA2/

AVSS

TIOCB2/

TCLKD/

P17/

P97/

AN15/DA1

P43/AN3

P96/

AN14/

DA0

PG1/

PG2/

PG0

P70/ TMRI01/ TMCI01/

USPND

Vref

P40/AN0

P41/AN1

P71/

P72/

TMO0/

P73/

TMO1/

P35/

SCK1/

PF3/

MD2

NMI

PLLVCC

DrVCC

VBUS

AVCC

P74/

P34/RxD1

(Reserve)

P36

P33/TxD1

P31/RxD0

P32/

SCK0/

PF0/

PF5/

XTAL

MD0

DrVSS

USD+

P30/TxD0

PF2/

PF6/

EXTAL

VSS

MD1

XTAL48

PLLVSS

USD-

PF1/

PF4/

PF7/

VCC

FWE*

EXTAL48

PLLCAP

(Reserve)

1.5 Pin Functions 11

3.4 Memory Map in Each

Operating Mode Figure 3.1 Memory Map

in Each Operating Mode for HD64F2215, HD64F2215U, and HD6432215A

5.4.1 External Interrupts

Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0

Note added Note: * The FWE pin is only provided in the flash memory

version.

Table amended

Pin No.

Type Symbol TFP-120 BP-112 I/O Function

System Control

FWE

69 H11 Input Pin for use by flash memory. This pin

is only used in the flash memory version. In the mask ROM version it should be fixed at 0.

Description amended Figures 3.1 to 3.3 show the memory map in each operating

mode for HD64F2215,

HD64F2215U, HD6432215A,

HD6432215B, and HD6432215C.

Figure amended (Incorrect) IRQn input

(Correct)

IRQn input

Rev. 3.0, 10/02, page x of lviii

Page 11

Section

Page

Description

7.1 Features Figure 7.1 Block Diagram

of DMAC

7.4.9 DMAC Bus Cycles (Dual Address Mode)

9.1.4 Pin Functions Table 9.8 P11 Pin

Function Table 9.9 P10 Pin

Function

9.2.5 Pin Functions Table 9.13 P33 Pin

Function

142

182, 184

224

227

Figure amended

Internal interrupts

TGI0A TGI1A TGI2A TXI0 RXI0 TXI1 RXI1 ADI

Control logic

Note added Note: * TEND output cannot be used with this LSI. Address amended

(Incorrect) Other than (B’1111) (Correct) Other than (

B’1110 to B’1111)

Address amended (Incorrect) Other than (B’1111)

(Correct) Other than (

B’1101 to B’1111)

Pin function amended

TE 0 1 P33DDR 0 Pin function P33 input P33 output TxD1 output

Table 9.16 P30 Pin Function

9.8.3 Port C Register (PORTC)

10.1 Features Table 10.1 TPU

Functions

228

244

265

Pin function amended

TE 0 1 P30DDR 0 Pin function P30 input P30 output TxD0 output

Note added Note: * Determined by the states of pins PC7 to PC0. Channel 0 amended

Item Channel 0 Channel 1 Channel 2

General registers/buffer registers

TGRC_0 TGRD_0

not possible not possible

Rev. 3.0, 10/02, page xi of lviii

Page 12

Section

Page

Description

13.3.9 Serial Extended Mode Register 0 (SEMR_0)

Figure 13.3 Examples of Base Clock when Average Transfer Rate is Selected

375

Figure amended

1234567

1234 56789101112131415 16

234567828 29

1234567

1234 56789101112131415 16

2534

20 21 22 23 24

1234

567

26 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1 2 3 4 5 6 7 8

18 19 20 21 2322 24 25 27 30 31 32 33 3428 29

4567891011121314151617

123

When ø = 16 MHz

Base clock with 115.196 kbps average transfer rate

1234 65 7 8 9 12 13 14 15 1610 11

1.8431 MHz

2 MHz

123456789101112 13141516

(average)

Base clock

16 MHz/8 = 2 MHz

2 MHz × (47/51)= 1.8431 MHz

1 bit = base clock × 16*

Average transfer rate = 1.8431 MHz/16= 115.196 kbps

Average error = -0.004%

18 19 20 21 2322 24 25 26 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1

1234567891011121314151617

Base clock with 460.784 kbps average transfer rate

1234 65 7 8 9 12 13 14 15 1610 11

7.3725 MHz

8 MHz

123456789101112 13141516

(average)

Base clock

16 MHz/2 = 8 MHz

8 MHz × (47/51)= 7.3725 MHz

1 bit = base clock × 16*

Average transfer rate = 7.3725 MHz/16= 460.784 kbps

Average error = -0.004%

242512 5678

11 12 13 14 15 16 17 18 19 20 21 2322

12345678910

Base clock with 720 kbps average transfer rate

12 345 67 8

5.76 MHz

8 MHz

123 45 678

(average)

Base clock

16 MHz/2 = 8 MHz

8 MHz × (18/25)= 5.76 MHz

Average transfer rate = 5.76 MHz/8= 720 kbps

Average error = ±0%

1 bit = base clock × 8*

As the base clock synchronization varies, so does the length of one bit.

Note:

Rev. 3.0, 10/02, page xii of lviii

Page 13

Section

Page

Description

Figure 13.4 Example of Average Transfer Rate Setting with TPU Clock Input

374

Newly added

56789101112

234

12345678

9101112 1

2345678910111213 12345678910111213

1 1

Main clock: 16 MHz

TIOCA1(TPU_1) output = 8 MHz

TMDR_1 = TMDR_2 = H'C2 [PWM mode 1]

TCR_1 = H'20 [TCNT_1 incremented on rising edge of ø/1, TCNT_1 cleared by TGRA_1 compare match]

TGRB_1 = H'0000, TGRA_1 = H'0001

TIOR_1 = H'21 [1 output on TGRB_1 compare match, TIOCA1 initial output 0, 0 output on TGRA_1 compare match]

TCR_2 = H'2C [TCNT_2 incremented on falling edge of TCLKA (TIOCA1), TCNT_2 cleared by TGRA_2 compare match]

TGRB_2 = H'0000, TGRA_2 = H'000C

TIOR_2 = H'21 [1 output on TGRB_2 compare match, TIOCA2 initial output 0, 0 output on TGRA_2 compare match]

Example for 921.6 kbps when ø = 16 MHz

Generation of clock with 923.077 kbps average transfer rate by means of TPU

(1) An 8 MHz base clock provided by TPU_1 is multiplied by 12/13 by TPU_2 to generate a 7.3846 MHz base clock

(2) By making 1 bit = 8 base clocks, the average transfer rate is made 7.3846 MHz/8 = 923.077 kbps.

Sample TPU and SCI settings

SEMR_0 = H'0C (ABCS = 1, ACS2-0 = B'100)

12345678

TIOCA2 (TPU_2) output

1234 678

8 MHz

7.3846 MHz 1 bit = 8 base clocks*

12345678

= 7.3846 MHz

= 8 MHz x 12/13

Internal base clock

Average error relative to 921.6 kbps = +0.16%

Average transfer rate = 7.3846 MHz/8 = 923.077 kbps

Note: * As the base clock synchronization varies, so does the length of one bit.

Rev. 3.0, 10/02, page xiii of lviii

Page 14

Section

Page

Description

13.7 SCI Select Function Figure 13.24 Example of

Communication Using the SCI Select Function

Figure 13.25 Operation of Communication Using the SCI Select Function

14.3.2 IDCODE Register (IDCODE)

Table 14.3 IDCODE Register Configuration

406

407

422

Added Note: * The selection signals (SEL_A and SEL_B) of the LSI

must be switched while the serial clock (M_SCK) is high after the end bit of the transm it data has been send. Note that one selection signal can be brought low at the same tim e.

Figure title amended Added

Note: * The selection signals (SEL_A and SEL_B) of the LSI must be switched while the serial clock (M_SCK) is high after the end bit of the transm it data has been send. Note that one selection signal can be brought low at the same tim e.

3rd line changed as follows The HD64F2215, HD64F2215U, HD6432215A,

HD6432215B, and HD6432215C output fixed codes H’0002200F, H’0003200F, H’001B200F, and H’001C200F, respectively, from the TDO.

Code amended (Incorrect) HD64F2215 code

(Correct) HD64F2215 code,

HD64F2215U code

15.1 Features Endpoint configuratio n

•

selectable

433 Replaced

The FIFO buffer for bulk transfer and isochronous transfer has a double-buffer configuration

Total 1288-byte FIFO —EP0s fixed: Control_setup FIFO, 8 bytes —EP0i fixed: Control_in FIFO, 64 bytes —EP0o fixed: Control_out FIFO, 64 bytes —EPn selectable: Interrupt_in FIFO, variable 0 to 64 bytes —EPn selectable: Bulk_in FIFO, 64 bytes x 2 (double-buffer configuration) —EPn selectable: Bulk_out FIFO, 64 bytes x 2 (double-buffer configuration) —EPn selectable: Isochronous_in FIFO, variable 0 to 128 bytes x 2 (double-buffer configuration) —EPn selectable: Isochronous_out FIFO, variable 0 to 128 bytes x 2 (double-buffer configuration) —EPn selectable: Bulk_in FIFO, 64 bytes x 2 (double-buffer configuration) —EPn selectable: Bulk_out FIFO, 64 bytes x 2 (double-buffer configuration) —EPn selectable: Interrupt_in FIFO, variable 0 to 64 bytes

Rev. 3.0, 10/02, page xiv of lviii

Page 15

Section

Page

Description

15.1 Features

• Maximum Configuration, InterfaceNumber, and AlternateSetting configuration specifications of this LSI Configuration

Figure 15.1 Block Diagram of USB

15.3.1 USB Endpoint

Information Registers 00_0 to 22_4 (UEPIR00_0 to UEPIR22_4)

434

435

438

Endpoint configuration based on Bluetooth standard 1.0 can be specified.

Deleted Newly added

Maximum Configuration, InterfaceNumber, an d

•

AlternateSetting configuration specificatio ns of this LSI Configuration 1 ----- InterfaceNumber 0 to 2 ----AlternateSetting 0 to 7 ----- EP0, EP1 to EP8

Figure amented

1288-byte FIFO

EP0o

EP2iEP0s

EP2o

EP3i

EP3oEP1i

EP4i

EP4oEP0i

EP5i

Explanation added to 23th line as follows UEPIR is used to set

23 kinds of endpoint (EPINFO data).

• UEPIRnn_0 439

Replaced

•••• UEPIRnn_0

Bit Bit Name Initial Value R/W Description

D39 –D36 — R/W Endpoint number (4-bit configuration, settable

to4

32D35

D34

10D33

D32

— —

R/W R/W

values: 0 to 8) 0000: Control transfer (EP0) 0001 to 1000: Other than Control transfer (EP1 to

EP8) There are restrictions on settable endpoint

numbers according to the Interface number and Alternate number to which the endpoint belongs.

Restriction 1: Set different endpoint numbers

under one Alternate. However, there is no problem with

use of the same endpoint number if the transfer directions (IN/OUT) are different. (Ex: Alt0 -- EP1, EP2i, EP2o)

Restriction 2: Do not set the same endpoint

number under different Interface numbers. (Ex: Int0 -- Alt0 -- EP1, EP2, Int1 -- Alt0 -- EP3)

Configuration number to which endpoint belongs (2-bit configuration, settable values: 0, 1)

00: Control transfer 01: Other than Control transfer Interface number to which endpoint belongs (2-bit

configuration, settable values: 0 to 2) 00: Control transfer 00 to 10: Other than Control transfer

Rev. 3.0, 10/02, page xv of lviii

Page 16

Section

Page

Description

15.3.1 USB Endpoint Information Registers 00_0 to 22_4 (UEPIR00_0 to UEPIR22_4)

UEPIRnn_1

•

UEPIRnn_2

•

440

Replaced

UEPIRnn_1

Bit Bit Name Initial Value R/W Description

7 to5D31 –D29 — R/W Alternate number to which endpoint belongs (3-bit

43D28

D27

2D26 — R/W Endpoint transfer direction (1-bit configuration)

10D25

D24

UEPIRnn_2

Bit Bit Name Initial Value R/W Description

7 to0D23 –D16 — R/W Endpoint maximum packet size (D25 to D16 10-bit

— —

R/W R/W

configuration, settable values: 0 to 7) 000: Control transfer 001 to 111: Other than Control transfer Endpoint transfer type (2-bit configuration) 00: Control(UEPIR00) 01: Isochronous(UEPIR04 to UEPIR19) 10: Bulk(UEPIR02,UEPIR03,UEPIR20,UEPIR21) 11: Interrupt(UEPIR01,UEPIR22)

0: out (UEPIR00,03,05,07,09,11,13,15,17,19,21) 1: in (UEPIR01,02,04,06,08,10,12,14,16,18,20,22) Endpoint maximum packet size (D25 to D16 10-bit

configuration) Control transfer = 64 only (UEPIR00) Interrupt transfer = 0 to 64 (UEPIR01, UEPIR22) Bulk transfer = 0 or 64 (UEPIR02, UEPIR03,

UEPIR20, UEPIR21) Isochronous transfer = 0 to 128 (UEPIR04 to

UEPIR19)

configuration) Control transfer = 64 only (UEPIR00)Interrupt transfer = 0 to 64 (UEPIR01, UEPIR22) Bulk transfer = 0 or 64 (UEPIR02,UEPIR03, UEPIR20, UEPIR21) Isochronous transfer = 0 to 128 (UEPIR04 to UEPIR19)

• UEPIRnn_3 441

• UEPIRnn_4

Table 15.2 EPINFO Data

444

Settings

Replaced

UEPIRnn_3

Bit Bit Name Initial Value R/W Description

7 to0D15 –D8 — R/W Endpoint internal address (D15 to D0 16-bit

UEPIRnn_4

Bit Bit Name Initial Value R/W Description

7 to0D7 –D0 — R/W Endpoint internal address (D15 to D0 16-bit

configuration) Set UEPIR00_3, UEPIR00_4 = H'0000 Set UEPIR01_3, UEPIR01_4 = H'0001

: Set UEPIR21_3, UEPIR21_4 = H'0015 Set UEPIR22_3, UEPIR22_4 = H'0016

configuration) Set UEPIR00_3, UEPIR00_4 = H'0000 Set UEPIR01_3, UEPIR01_4 = H'0001

: Set UEPIR21_3, UEPIR21_4 = H'0015 Set UEPIR22_3, UEPIR22_4 = H'0016

Note amended Notes:*5

Maximum packet size of Isochronous transfer must be from 0 to 128.

Rev. 3.0, 10/02, page xvi of lviii

Page 17

Section

Page

Description

15.3.11 USB Endpoint Data Register 0s (UEDR0s)

15.3.12 USB Endpoint Data Register 0i (UEDR0i)

15.3.13 USB Endpoint Data Register 0o (UEDR0o)

15.3.14 USB Endpoint Data Register 1i (UEDR1i)

15.3.15 USB Endpoint Data Register 2i (UEDR2i)

15.3.16 USB Endpoint Data Register 2o (UEDR2o)

457

458

2nd line changed as follows (Incorrect) Endpoint0

(Correct) Endpoint0

s 9th line changed as follows (Incorrect) Endpoint0

(Correct) Endpoint0

i 15th line changed as follows (Incorrect) Endpoint0

(Correct) Endpoint0

o 2nd line changed as follows (Incorrect) Endpoint1

(Correct) Endpoint1

i 8th line changed as follows (Incorrect) Endpoint2

(Correct) Endpoint2

i 14th line changed as follows (Incorrect) Endpoint2

(Correct) Endpoint2

15.3.17 USB Endpoint Data Register 3i (UEDR3i)

15.3.18 USB Endpoint Data Register 3o (UEDR3o)

15.3.19 USB Endpoint Data Register 4i (UEDR4i)

15.3.20 USB Endpoint Data Register 4o (UEDR4o)

15.3.21 USB Endpoint Data Register 5i (UEDR5i)

15.3.22 USB Endpoint Receive Data Size Register 0o (UESZ0o)

459

460

2nd line changed as follows (Incorrect) Endpoint3

(Correct) Endpoint3

i 9th line changed as follows (Incorrect) Endpoint3

(Correct) Endpoint3

o 15th line changed as follows (Incorrect) Endpoint4

(Correct) Endpoint4

i 2nd line changed as follows (Incorrect) Endpoint4

(Correct) Endpoint4

o 7th line changed as follows (Incorrect) Endpoint5

(Correct) Endpoint5

i 13th line changed as follows (Incorrect) Endpoint0

(Correct) Endpoint0

Rev. 3.0, 10/02, page xvii of lviii

Page 18

Section

Page

Description

15.3.23 USB Endpoint Receive Data Size Register 2o (UESZ2o)

15.3.24 USB Endpoint Receive Data Size Register 3o (UESZ3o)

15.3.25 USB Endpoint Receive Data Size Register 4o (UESZ4o)

461

2nd line changed as follows (Incorrect) Endpoint2

(Correct) Endpoint2

o 4th line changed as follows (Incorrect) The FIFO for endpoint 2 out transfer has a dual-

FIFO configuration (Correct) The FIFO for endpoint 2

o (for Bulk_out transfer) has

a dual-FIFO configuration

line changed as follows

7 (Incorrect) Endpoint3

(Correct) Endpoint3o 9th line changed as follows (Incorrect) The FIFO for endpoint 3 out transfer has a dual-

FIFO configuration. (Correct) The FIFO for endpoint 3

o (for Isochronous_out

transfer) has a dual-FIFO configuration.

line changed as follows

12 (Incorrect) Endpoint4

(Correct) Endpoint4o

15.3.30 USB Interrupt Enable Register 0 (UIER0)

15.3.34 USB Interrupt Select Register 0 (UISR0)

470

472

14th line changed as follows (Incorrect) The FIFO for endpoint 4 out transfer has a dual-

FIFO configuration. (Correct) The FIFO for endpoint 4o (for Bulk_out transfer) has a dual-FIFO configuration.

Bit table amended

Bit Bit Name Initial Value R/W Description

7 BRSTE 0 R/W Enables the BRST interrupt. 6 — 0RReserved

This bit is always read as 0. 5 EP1iTRE 0 R/W Enables the EP1iTR interrupt. 4 EP1iTSE 0 R/W Enables the EP1iTS interrupt.

Bit table amended

Bit Bit Name Initial Value R/W Description

7 BRSTS 0 R/W Selects the BRST interrupt output pin. 6 — 0RReserved

This bit is always read as 0. 5 EP1iTRS 0 R/W Selects the EP1iTR interrupt output pin. 4 EP1iTSS 0 R/W Selects the EP1iTS interrupt output pin. 3 EP0oTSS 0 R/W Selects the EP0oTS interrupt output pin. 2 EP0iTRS 0 R/W Selects the EP0iTR interrupt output pin. 1 EP0iTSS 0 R/W Selects the EP0iTS interrupt output pin. 0 SetupTSS 0 R/W Selects the SetupTS interrupt output pin.

Rev. 3.0, 10/02, page xviii of lviii

Page 19

Section

Page

Description

15.3.42 USB Test Register 1 (UTSTR1)

Table 15.4 Relationship between the UTSTR1 Settings and Pin Inputs

479

480

Bit table amended and Note added

Bit Bit Name Initial Value R/W Description

76VBUS

UBPM

5 to 3 — 0 R Reserved

RCV

Note:* An asterisk indicates an undefined value.

—

Internal/External Transceiver Input Signal Monitor Bits

VBUS: Monitors VBUS pin

UBPM: Monitors UBPM pin

These bits are always read as 0 and cannot be

modified.

Internal/External Transceiver Input Signal Monitor Bits

RCV: Monitors the RCV signal of the internal/external

transceiver

VP: Monitors the VP signal of the internal/external

transceiver

VM: Monitors the VM signal of the internal/external

transceiver

UTSTR1 Monitor value amended

UTSTR1 Monitor

RCV VP VM

000 0/1 0 0 X00 001 110 X11 X00 001 110 X11 0 0/1 X 0X0/1 0/1 X X X0/1X XX0/1

15.3.44 Module Stop

481 Control Register B (MSTPCRB)

Section title amended

Rev. 3.0, 10/02, page xix of lviii

Page 20

Section

Page

Description

15.5.9 Isochronous–Out Transfer (Dual-FIFO) (When EP3o is Specified as Endpoint)

Figure 15.21 EP3o Isochronous-Out Transfer Operation

507

Figure amended

USB function

Receive SOF

Switch to FIFO

Receive OUT token

Receive data from the host

Receive data

error?

Set EP3o normal

receive status to 1

(Set internal EP3o TS to 1)

B-side UIFR1/EP3oTS, EP3oTF update

FIFO A

Yes

Set EP3o abnormal

receive status to 1

(Set internal EP3o TF to 1)

Receive SOF

Switch to FIFO

Receive OUT token

Receive data from the host

Receive data

error?

Yes

Set EP3o normal

receive status to 1

(Set Internal EP3o TS to 1

A-side UIFR1/EP3oTS, EP3oTF update

FIFO B

Set EP3o abnormal

)

receive status to 1

(Set Internal EP3o TF to 1)

15.5.10 Processing of

508 USB Standard Commands and Class/Vendor Commands

Rev. 3.0, 10/02, page xx of lviii

11th line changed as follows (Incorrect) EXIROx pin

(Correct) EXIROx

Page 21

Section

Page

Description

15.8 USB External Circuit Example

Figure 15.27 USB External Circuit in BusPowered Mode (When OnChip Transceiver is Used)

Figure 15.28 USB External Circuit in SelfPowered Mode (When OnChip Transceiver is Used)

Figure 15.29 USB External Circuit in BusPowered Mode (W hen External Transceiver is Used)

Figure 15.30 USB External Circuit in SelfPowered Mode (W hen External Transceiver is Used)

521 to 524

Note *3 amended

In HD64F2215, HD6432215A, HD6432215B, and HD6432215C, Pxx should be assigned

to an output port as the D+ pull-up control pin. In HD64F2215U, in which on-chip ROM can be programmed by using the USB, P36 should be used as the D+ pull-up control pin.

15.9.7 EP3o Isochronous Transfer Figure 15.32 EP3o Date Reception

528

Figure amended

[In frame N]

Receive USB data (1)

[In frame N+1]

Receive USB data (2)

[In frame N+2]

Receive USB data (3)

EP3o FIFO A

Data (1) Modify

EP3o FIFO B

———

EP3o FIFO A Internal flag (A-side)

Data (1)

EP3o FIFO B

Data (2)

EP3o FIFO A Internal flag (A-side)

Data (3)

EP3o FIFO B

Data (2)

Internal flag (A-side) UIFR1

TSTF

Internal flag (B-side)

Next frame

TSTF

Internal flag (B-side)

TSTF

Next frame

TSTF

Internal flag (B-side)

TSTF

Modify

No change

——

UIFR1

A-side flag update

TSTF

Can be read

Data (1) can be read in frame [N+1]

UIFR1

B-side flag update

Can be read

TSTF

Data (2) can only be read in frame [N+2]

Rev. 3.0, 10/02, page xxi of lviii

Page 22

Section

Page

Description

15.9.8 Reset 529

16.3.3 A/D Control

538 Register (ADCR)

Explanation amended to 2nd line chang ed as foll ow s A manual reset should not be performed during USB

communication as the LSI will stop with the USD+USD- pin state maintained.This USB module uses synchronous reset for some registers. The reset state of these registers must be cancelled after the clock oscillation stabilizatio n time has passed. At initialization, reset must be cancelled using the following procedure.

Table amended

Bit Bit Name Initial Value R/W Description

54—

—

32CKS1

CKS000

10—

—

1 1

——Reserved

These bits are always read as 1 cannot be modified.

R/W

Clock Select 0 and 1

R/W

These bits specify the A/D conversion time. The conversion time should be changed only when ADST =

0. Specify a setting that gives a value within the range shown in table 24.7.

00: Conversion time = 530 states (max.) 01: Conversion time = 266 states (max.) 10: Conversion time = 134 states (max.) 11: Conversion time = 68 states (max.)

The conversion time setting should exceed the conversion time shown in section 24.6, A/D Converter Characteristics.

——Reserved

These bits are always read as 1 cannot be modified.

18. RAM 555

Lineup added

Product Class ROM Type RAM Size RAM Address

H8S/2215 series

HD64F2215 HD64F2215U HD6432215A

HD6432215B HD6432215C

Flash memory Version

Masked ROM Version

16 kbytes H'FFB000 to H'FFEFBF

H'FFFFC0 to H'FFFFFF

8 kbytes H'FFD000 to H'FFEFBF

H'FFFFC0 to H'FFFFFF

Rev. 3.0, 10/02, page xxii of lviii

Page 23

Section

Page

Description

19.1 Features

• Size

Two flash memory

•

operating modes

• Automatic bit rate adjustment

(SCI boot

mode)

19.2 Mode Transitions

559

Table newly added

Product Category

H8S/2215 Series HD64F2215,HD64F2215U

Description added

Boot mode



(SCI boot mode: HD64F2215, USB boot

mode: HD64F2215U)

 User program mode

On-board programming/erasing can be done in boot mode in which the boot program built into the chip is started for erase or programming of the entire flash memory. In normal user program mode, individual blocks can be erased or programmed.

 With data transfer in

bit rate can be automatically adjusted to match the transfer bit rate of the host

Figure amended

ROM Size ROM Addresses

256 kbytes

H'000000 to H'03FFFF

(Modes 6 and 7)

SCI boot mode, this LSI’s

Figure 19.2 Flash Memory State Transitions

Table 19.1 Differences between Boot Mode and User Program Mode

19.2 Mode Transitions

Figure 19.3 Boot Mode Figure 19.4 Boot Mode

560

561 562

User

program mode

SCI,USB

Boot mode

On-board programming mode

(Incorrect) Boot Mode (Correct)

SCI,USB Boot Mode

Description amended in 5th line of "2. Programming control program transfer" in Figure 19.3, Boot Mode

When boot mode is entered, the boot program in this LSI (originally incorporated in the chip) is started and the programming control program in the host is transferre d to RAM via SCI

or USB

Figures 1 to 4 amended (Incorrect) SCI

(Correct) SCI

or USB

Rev. 3.0, 10/02, page xxiii of lviii

Page 24

Section

Page

Description

19.4 Input/Output Pins Table 19.2 Pin

Configuration

19.6 On-Board Programming Modes

Table 19.3 Setting OnBoard Programming Modes

19.6.1 SCI Boot Mode (HD64F2215)

564

571

571 to 574

Figure amended

Pin Name I/O Function

RES Input Reset FWE Input Flash program/erase protection by hardware MD2,MD1,MD0 Input Sets this LSI's operating mode PF3,PF0,P16,

P14 TxD2 Output Serial transmit data output RxD2 Input Serial receive data input USB+,USB- Input/Output USB data output VBUS Input USB cable connection/disconnection detection UBPM Input USB bus power mode/self power mode setting USPND Output USB suspend output P36 Output D+ pull-up control

Input Sets this LSI's operating mode in

programmer mode

(Incorrect) Boot mode (Correct)

SCI boot mode(HD64F2215)

USB boot mode(HD64F2215U)

Amended (Incorrect) Boot Mode

(Correct) SCI Boot Mode

HD64F2215 and HD64F2215U

HD64F2215

HD64F2215U

Figure 19.6 SCI System Configuration in Boot Mode

19.6.2 USB Boot Mode (HD64F2215U)

19.8.1 Program/ProgramVerify

572 Figure amended

01X MD2 to 0*

Note added to figure Note: * FWE pin and mode pin input must satisfy the mode

programming setup time (t when a reset is released.

575 to

Newly added

579 583

33th line changed as follows Verify data can be read in words from the address to which a

dummy write was performed.

FWE*

H8S/2215 Series

Flash memory

= 200 ns)

MDS

19.8.2 Erase/Erase-Verify 585

Rev. 3.0, 10/02, page xxiv of lviii

11th line changed as follows Verify data can be read in

words from the address to which a

dummy write was performed.

Page 25

Section

Page

Description

21.1.2 Low-Power

Control Register (LPWRCR)

21.2.2 Inputting an

External Clock

21.6.1 Connecting a

Ceramic Resonator Figure 21.6 Connection

of Ceramic Resonator

598

601

602

Bit name amended

Bit Bit Name Initial Value R/W Description

7 to4— 0 R/W These bits can be read from or written to, but the write

3 RFCUT 0 R/W Built-in Feedback Resistor Control:

value should always be 0.

Selects whether the oscillator’s built-in feedback resistor and duty adjustment circuit are used with external clock input. This bit should not be accessed when a crystal oscillator is used.

After this bit is set when using external clock input, a transition should initially be made to software standby mode. Switching between use and non-use of the oscillator’s built-in feedback resistor and dut y adjustment circuit is performed when the transition is made to software standby mode.

0: System clock oscillator’s built-in feedback resistor

and duty adjustment circuit are used

1: System clock oscillator’s built-in feedback resistor

and duty adjustment circuit are not used

3rd line changed as follows

The external clock input conditions when the duty adjustment circuit is not used are shown in table

21.4. When the duty adjustment circuit is not used, note that the maximum operating frequency = T

depends on the external clock input waveform. For example, if t = 6.25 ns, the maximum operating frequency becomes 13.3 MHz depending on the clcok cycle time of 75 ns.

EXL

= 31.25ns and t

EXH

= t

EXr

EXf

Condition amended

EXTAL48

XTAL48

Ceramic

Resonator

Ta = 0 to 70 C Contact the representative mentioned below for details of Rf and Rd values.

Ceramic resonator: CSTCW48M0X11 -R (Murata Manufacturing Co.,Ltd.)

23.3 Register States in Each Operating Mode

24.2 Power Supply Voltage and Operating Frequency Range

Figure 24.1 Power Supply Voltage and Operating Ranges

642, 643, 645, 648

Manual reset amendment: Register Names UCTLR to UESTL1, UEDR0i, UEDR1i, UEDR2i, UEDR3i, UEDR4i, UEDR5i, UIFR0 to UTSTRF, ABWCR to BCRL, FLMCR1 to EBR2

(Incorrect) Initialized (Correct)



650 Newly added to figure

(3) When USB boot program is executed by HD64F2215U

16.0

13.0

system clock

2.7 3.0

f(MHz)

With operation of USB operating clock (48 MHz) provided by PLL3 multiplication

PLLVcc, DrVcc, AVcc (V)

3.6

Rev. 3.0, 10/02, page xxv of lviii

Page 26

Section

Page

Description

24.3 DC Characteristics Table 24.2 DC

Characteristics

24.4.4 Timing of On-Chip Supporting Modules

Figure 24.21 Boundary Scan TCK Input Timing

24.8 Flash Memory Characteristics

Table 24.11 Flash Memory Characteristics

651 Table amended

Item Symbol Min Typ Max Unit

Schmitt IRQ0 to IRQ5 V trigger input voltage

Input high voltage

IRQ7 V

RES , STBY ,

NMI, MD2 to MD0, TRST , TCK, TMS, TDI, VBUS, UBPM ,

FWE* EXTAL,

EXTAL48, Ports 1, 3, 7, and A to G

Ports 4 and 9 VCC 0.8 — AVCC + 0.3 V

668 Figure amended

TCK

672

Table amended

673

Item Symbol Min Typ Max Unit

Programming time* Erase time* Reprogramming count N Data retention time

1,*3,*5

1 *2,*4

Test

–

VCC × 0.2 ——V

——VCC ⋅ 0.8 V

–

– V

VCC × 0.05 ——V

VCC × 0.9 — V

VCC ×× 0.8 — V

tcyc

TCKH

TCKL

— 10 200 ms/128 bytes — 50 1000 ms/block 100 10,000 100 Times

WEC

10 ——Year

DRP

+ 0.3 V

Conditions

B. Product Model Lineup 679

Notes added *6 Minimum number of times for which all characteristics are guaranteed after rewriting. (Guarantee range is 1 to minimum value.)

*7 Reference value for 25°C (as a guideline, rewriting should normally function up to this value).

*8 Data retention characteristic when rewriting is performed within the specification range, including the minimum value.

Linup added

Product Class

H8S/2215 Flash memory

Version

Masked ROM Version

Product Type Name Marking Package (code)

HD64F2215 HD64F2215TE 120 pin TQFP (TFP-120)

HD64F2215BR 112 pin P-LFBGA (BP-112) HD64F2215UTE 120 pin TQFP(TEP-120)HD64F2215U HD64F2215UBR 112 pin P-LFBGA(BP-112)

HD6432215A HD6432215A(***)TE 120 pin TQFP (TFP-120)

HD6432215A(***)BR 112 pin P-LFBGA (BP-112)

HD6432215B HD6432215B(***)TE 120 pin TQFP (TFP-120)

HD6432215B(***)BR 112 pin P-LFBGA (BP-112)

HD6432215C HD6432215C(***)TE 120 pin TQFP (TFP-120)

HD6432215C(***)BR 112 pin P-LFBGA (BP-112)

Rev. 3.0, 10/02, page xxvi of lviii

Page 27

Section

Page

Description

C. Package Dimensions Figure C.2 BP-112 Package Dimension

680

Replaced

B C

0.20

10.00

4 ×

0.2

10.00

0.15

Unit: mm

0.20

0.80

1110987654321

1.00

0.80

112 × φ0.50 ± 0.05

φ0.08

A B C D E F G H

J K L

0.10

1.40 Max

0.40 ± 0.05

Hitachi Code JEDEC JEITA Mass

(reference value)

BP-112 – –

0.3 g

Rev. 3.0, 10/02, page xxvii of lviii

Page 28

Rev. 3.0, 10/02, page xxviii of lviii

Page 29

Contents

Section 1 Overview............................................................................................1

1.1 Overview...........................................................................................................................1

1.2 Internal Block Diagram.....................................................................................................2

1.3 Pin Arrangement...............................................................................................................3

1.4 Pin Functions in Each Operating Mode............................................................................5

1.5 Pin Functions ....................................................................................................................10

Section 2 CPU....................................................................................................19

2.1 Features.............................................................................................................................19

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU..................................20

2.1.2 Differences from H8/300 CPU ............................................................................21

2.1.3 Differences from H8/300H CPU..........................................................................21

2.2 CPU Operating Modes......................................................................................................22

2.2.1 Normal Mode.......................................................................................................22

2.2.2 Advanced Mode...................................................................................................23

2.3 Address Space...................................................................................................................26

2.4 Register Configuration......................................................................................................27

2.4.1 General Registers.................................................................................................28

2.4.2 Program Counter (PC).........................................................................................29

2.4.3 Extended Control Register (EXR).......................................................................29

2.4.4 Condition-Code Register (CCR)..........................................................................30

2.4.5 Initial Register Values..........................................................................................32

2.5 Data Formats.....................................................................................................................32

2.5.1 General Register Data Formats............................................................................32

2.5.2 Memory Data Formats.........................................................................................34

2.6 Instruction Set...................................................................................................................35

2.6.1 Table of Instructions Classified by Function.......................................................36

2.6.2 Basic Instruction Formats....................................................................................45

2.7 Addressing Modes and Effective Address Calculation .....................................................46

2.7.1 Register Direct—Rn.............................................................................................47

2.7.2 Register Indirect—@ERn....................................................................................47

2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) ..............47

2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn..47

2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32....................................47

2.7.6 Immediate—#xx:8, #xx:16, or #xx:32.................................................................48

2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)....................................48

2.7.8 Memory Indirect—@@aa:8................................................................................48

2.7.9 Effective Address Calculation .............................................................................49

2.8 Processing States...............................................................................................................52

Rev. 3.0, 10/02, page xxix of lviii

Page 30

2.9 Usage Notes.......................................................................................................................53

2.9.1 Note on TAS Instruction Usage...........................................................................53

2.9.2 STM/LTM Instruction Usage...............................................................................53

2.9.3 Note on Bit Manipulation Instructions.................................................................54

Section 3 MCU Operating Modes......................................................................55

3.1 Operating Mode Selection.................................................................................................55

3.2 Register Descriptions ........................................................................................................56

3.2.1 Mode Control Register (MDCR)..........................................................................56

3.2.2 System Control Register (SYSCR) ......................................................................57

3.3 Operating Mode Descriptions............................................................................................58

3.3.1 Mode 4 .................................................................................................................58

3.3.2 Mode 5 .................................................................................................................58

3.3.3 Mode 6 .................................................................................................................59

3.3.4 Mode 7 .................................................................................................................59

3.3.5 Pin Functions........................................................................................................ 59

3.4 Memory Map in Each Operating Mode.............................................................................61

Section 4 Exception Handling.............................................................................65

4.1 Exception Handling Types and Priority ............................................................................65

4.2 Exception Sources and Exception Vector Table ...............................................................65

4.3 Reset..................................................................................................................................67

4.3.1 Reset Types..........................................................................................................67

4.3.2 Reset Exception Handling....................................................................................68

4.3.3 Interrupts after Reset............................................................................................69

4.3.4 State of On-Chip Peripheral Modules after Reset Release...................................69

4.4 Traces...................................................................................................................... ..........70

4.5 Interrupts ........................................................................................................................... 70

4.6 Trap Instruction.................................................................................................................71

4.7 Stack Status after Exception Handling..............................................................................72

4.8 Notes on Use of the Stack .................................................................................................73

Section 5 Interrupt Controller............................................................................75

5.1 Features ............................................................................................................................. 75

5.2 Input/Output Pins ..............................................................................................................77

5.3 Register Descriptions ........................................................................................................77

5.3.1 Interrupt Priority Registers A to G, I to K, M

(IPRA to IPRG, IPRI to IPRK, IPRM).................................................................78

5.3.2 IRQ Enable Register (IER)...................................................................................79

5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL).....................................80

5.3.4 IRQ Status Register (ISR)....................................................................................82

5.4 Interrupt Sources ...............................................................................................................83

5.4.1 External Interrupts................................................................................................83

Rev. 3.0, 10/02, page xxx of lviii

Page 31

5.4.2 Internal Interrupts ................................................................................................84

5.5 Interrupt Exception Handling Vector Table......................................................................84

5.6 Interrupt Control Modes and Interrupt Operation.............................................................87

5.6.1 Interrupt Control Mode 0.....................................................................................87

5.6.2 Interrupt Control Mode 2.....................................................................................89

5.6.3 Interrupt Exception Handling Sequence..............................................................91

5.6.4 Interrupt Response Times....................................................................................92

5.6.5 DTC Activation by Interrupt................................................................................93

5.7 Usage Notes......................................................................................................................95

5.7.1 Contention between Interrupt Generation and Disabling.....................................95

5.7.2 Instructions that Disable Interrupts......................................................................96

5.7.3 Times when Interrupts are Disabled....................................................................96

5.7.4 Interrupts during Execution of EEPMOV Instruction..........................................96

Section 6 Bus Controller....................................................................................99

6.1 Features.............................................................................................................................99

6.2 Input/Output Pins..............................................................................................................101

6.3 Register Descriptions........................................................................................................101

6.3.1 Bus Width Control Register (ABWCR)...............................................................101

6.3.2 Access State Control Register (ASTCR).............................................................102

6.3.3 Wait Control Registers H and L (WCRH, WCRL)..............................................103

6.3.4 Bus Control Register H (BCRH) .........................................................................107

6.3.5 Bus Control Register L (BCRL) ..........................................................................108

6.3.6 Pin Function Control Register (PFCR)................................................................109

6.4 Bus Control.......................................................................................................................110

6.4.1 Area Divisions .....................................................................................................110

6.4.2 Bus Specifications................................................................................................111

6.4.3 Bus Interface for Each Area.................................................................................112

6.4.4 Chip Select Signals..............................................................................................113

6.5 Basic Timing.....................................................................................................................114

6.5.1 On-Chip Memory (ROM, RAM) Access Timing................................................114

6.5.2 On-Chip Peripheral Module Access Timing........................................................115

6.5.3 External Address Space Access Timing ..............................................................116

6.6 Basic Bus Interface......................................................................................................... ..117

6.6.1 Data Size and Data Alignment.............................................................................117

6.6.2 Valid Strobes........................................................................................................118

6.6.3 Basic Timing ........................................................................................................119

6.6.4 Wait Control ........................................................................................................128

6.7 Burst ROM Interface.........................................................................................................130

6.7.1 Basic Timing ........................................................................................................130

6.7.2 Wait Control ........................................................................................................132

6.8 Idle Cycle..........................................................................................................................133

6.9 Bus Release.......................................................................................................................136

Rev. 3.0, 10/02, page xxxi of lviii

Page 32

6.10 Bus Arbitration..................................................................................................................138

6.10.1 Operation..............................................................................................................138

6.10.2 Bus Transfer Timing ............................................................................................138

6.10.3 External Bus Release Usage Note........................................................................139

6.11 Resets and the Bus Controller ...........................................................................................139

Section 7 DMA Controller.................................................................................141

7.1 Features ............................................................................................................................. 141

7.2 Register Configuration......................................................................................................143

7.3 Register Descriptions ........................................................................................................145

7.3.1 Memory Address Registers (MAR)......................................................................145

7.3.2 I/O Address Register (IOAR)...............................................................................145

7.3.3 Execute Transfer Count Register (ETCR)............................................................146

7.3.4 DMA Control Register (DMACR) .......................................................................147

7.3.5 DMA Band Control Register (DMABCR)...........................................................153

7.3.6 DMA Write Enable Register (DMAWER) ..........................................................161

7.4 Operation...........................................................................................................................163

7.4.1 Transfer Modes ....................................................................................................163

7.4.2 Sequential Mode...................................................................................................164

7.4.3 Idle Mode.............................................................................................................167

7.4.4 Repeat Mode ........................................................................................................168

7.4.5 Normal Mode.......................................................................................................172

7.4.6 Block Transfer Mode ...........................................................................................175

7.4.7 DMAC Activation Sources ..................................................................................180

7.4.8 Basic DMAC Bus Cycles.....................................................................................181

7.4.9 DMAC Bus Cycles (Dual Address Mode)...........................................................182

7.4.10 DMAC Multi-Channel Operation ........................................................................186

7.4.11 Relation between the DMAC, External Bus Requests, Refresh Cy cles,

and the DTC.........................................................................................................187

7.4.12 NMI Interrupts and DMAC.................................................................................. 188

7.4.13 Forced Termination of DMAC Operation............................................................189

7.4.14 Clearing Full Address Mode ................................................................................189

7.5 Interrupts ........................................................................................................................... 191

7.6 Usage Notes.......................................................................................................................192

7.6.1 DMAC Register Access during Operation...........................................................192

7.6.2 Module Stop.........................................................................................................193

7.6.3 Medium-Speed Mode...........................................................................................193

7.6.4 Activation Source Acceptance .............................................................................193

7.6.5 Internal Interrupt after End of Transfer:...............................................................194

7.6.6 Channel Re-Setting ..............................................................................................194

Section 8 Data Transfer Controller (DTC) ........................................................195

8.1 Features ............................................................................................................................. 195

Rev. 3.0, 10/02, page xxxii of lviii

Page 33

8.2 Register Descriptions........................................................................................................197

8.2.1 DTC Mode Register A (MRA)............................................................................197

8.2.2 DTC Mode Register B (MRB).............................................................................198

8.2.3 DTC Source Address Register (SAR)..................................................................198

8.2.4 DTC Destination Address Register (DAR)..........................................................198

8.2.5 DTC Transfer Count Register A (CRA) ..............................................................198

8.2.6 DTC Transfer Count Register B (CRB)...............................................................199

8.2.7 DTC Enable Registers (DTCERA to DTCERF)..................................................199

8.2.8 DTC Vector Register (DTVECR)........................................................................200

8.3 Activation Sources............................................................................................................201

8.4 Location of Register Information and DTC Vector Table................................................202

8.5 Operation ..........................................................................................................................205

8.5.1 Normal Mode.......................................................................................................206

8.5.2 Repeat Mode........................................................................................................208

8.5.3 Block Transfer Mode...........................................................................................209

8.5.4 Chain Transfer .....................................................................................................210

8.5.5 Interrupts..............................................................................................................211

8.5.6 Operation Timing.................................................................................................211

8.5.7 Number of DTC Execution States .......................................................................212

8.6 Procedures for Using DTC................................................................................................214

8.6.1 Activation by Interrupt.........................................................................................214

8.6.2 Activation by Software........................................................................................214

8.7 Examples of Use of the DTC............................................................................................215

8.7.1 Normal Mode.......................................................................................................215

8.7.2 Software Activation.............................................................................................215

8.8 Usage Notes......................................................................................................................216

8.8.1 Module Stop.........................................................................................................216

8.8.2 On-Chip RAM .....................................................................................................216

8.8.3 DTCE Bit Setting.................................................................................................216

8.8.4 DMAC Transfer End Interrupt.............................................................................216

Section 9 I/O Ports.............................................................................................217

9.1 Port 1.................................................................................................................................221

9.1.1 Port 1 Data Direction Register (P1DDR).............................................................221

9.1.2 Port 1 Data Register (P1DR)................................................................................221

9.1.3 Port 1 Register (PORT1)......................................................................................222

9.1.4 Pin Functions .......................................................................................................222

9.2 Port 3.................................................................................................................................224

9.2.1 Port 3 Data Direction Register (P3DDR).............................................................225

9.2.2 Port 3 Data Register (P3DR)................................................................................225

9.2.3 Port 3 Register (PORT3)......................................................................................226

9.2.4 Port 3 Open-Drain Control Register (P3ODR)....................................................226

9.2.5 Pin Functions .......................................................................................................227

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9.3 Port 4.................................................................................................................................228

9.3.1 Port 4 Register (PORT4)......................................................................................228

9.3.2 Pin Function.........................................................................................................228

9.4 Port 7.................................................................................................................................229

9.4.1 Port 7 Data Direction Register (P7DDR).............................................................229

9.4.2 Port 7 Data Register (P7DR)................................................................................229

9.4.3 Port 7 Register (PORT7)......................................................................................230

9.4.4 Pin Functions........................................................................................................ 230

9.5 Port 9.................................................................................................................................232

9.5.1 Port 9 Register (PORT9)......................................................................................232

9.5.2 Pin Function.........................................................................................................232

9.6 Port A ................................................................................................................................232

9.6.1 Port A Data Direction Register (PADDR) ........................................................... 233

9.6.2 Port A Data Register (PADR)..............................................................................233

9.6.3 Port A Register (PORTA)....................................................................................234

9.6.4 Port A MOS Pull-Up Control Register (PAPCR) ................................................234

9.6.5 Port A Open Drain Control Register (PAODR)...................................................235

9.6.6 Pin Functions........................................................................................................ 235

9.6.7 Port A Input Pull-Up MOS Function ...................................................................237

9.7 Port B ................................................................................................................................ 237

9.7.1 Port B Data Direction Register (PBDDR)............................................................238

9.7.2 Port B Data Register (PBDR)...............................................................................238

9.7.3 Port B Register (PORTB)..................................................................................... 239

9.7.4 Port B MOS Pull-Up Control Register (PBPCR).................................................239

9.7.5 Pin Functions........................................................................................................ 240

9.7.6 Port B Input Pull-Up MOS Function...................................................................241

9.8 Port C ................................................................................................................................ 243

9.8.1 Port C Data Direction Register (PCDDR)............................................................243

9.8.2 Port C Data Register (PCDR)...............................................................................243

9.8.3 Port C Register (PORTC)..................................................................................... 244

9.8.4 Port C Pull-Up MOS Control Register (PCPCR).................................................244

9.8.5 Pin Functions........................................................................................................ 244

9.8.6 Port C Input Pull-Up MOS Function....................................................................246

9.9 Port D ................................................................................................................................246

9.9.1 Port D Data Direction Register (PDDDR) ........................................................... 247

9.9.2 Port D Data Register (PDDR)..............................................................................247

9.9.3 Port D Register (PORTD)....................................................................................248

9.9.4 Port D Pull-up MOS Control Register (PDPCR).................................................248

9.9.5 Pin Functions........................................................................................................ 248

9.9.6 Port D Input Pull-Up MOS Function ...................................................................250

9.10 Port E.................................................................................................................................250

9.10.1 Port E Data Direction Register (PEDDR)............................................................251

9.10.2 Port E Data Register (PEDR)...............................................................................251

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9.10.3 Port E Register (PORTE).....................................................................................252

9.10.4 Port E Pull-up MOS Control Register (PEPCR)..................................................252

9.10.5 Pin Functions .......................................................................................................253

9.10.6 Port E Input Pull-Up MOS State..........................................................................254

9.11 Port F.................................................................................................................................255

9.11.1 Port F Data Direction Register (PFDDR) ............................................................256

9.11.2 Port F Data Register (PFDR)...............................................................................256

9.11.3 Port F Register (PORTF).....................................................................................257

9.11.4 Pin Functions .......................................................................................................257

9.12 Port G................................................................................................................................259

9.12.1 Port G Data Direction Register (PGDDR)...........................................................259

9.12.2 Port G Data Register (PGDR)..............................................................................260

9.12.3 Port G Register (PORTG)....................................................................................260

9.12.4 Pin Functions .......................................................................................................260

Section 10 16-Bit Timer Pulse Unit (TPU)........................................................263

10.1 Features.............................................................................................................................263

10.2 Input/Output Pins..............................................................................................................267

10.3 Register Descriptions........................................................................................................268

10.3.1 Timer Control Register (TCR).............................................................................269

10.3.2 Timer Mode Register (TMDR)............................................................................273

10.3.3 Timer I/O Control Register (TIOR).....................................................................274

10.3.4 Timer Interrupt Enable Register (TIER)..............................................................284

10.3.5 Timer Status Register (TSR)................................................................................286

10.3.6 Timer Counter (TCNT)........................................................................................288

10.3.7 Timer General Register (TGR)............................................................................288

10.3.8 Timer Start Register (TSTR)................................................................................289

10.3.9 Timer Synchro Register (TSYR) .........................................................................290

10.4 Interface to Bus Master.....................................................................................................291

10.4.1 16-Bit Registers ...................................................................................................291

10.4.2 8-Bit Registers .....................................................................................................291

10.5 Operation ..........................................................................................................................293

10.5.1 Basic Functions....................................................................................................293

10.5.2 Synchronous Operation........................................................................................297

10.5.3 Buffer Operation..................................................................................................299

10.5.4 PWM Modes........................................................................................................302

10.5.5 Phase Counting Mode..........................................................................................305

10.6 Interrupts...........................................................................................................................311

10.6.1 Interrupt Source and Priority ...............................................................................311

10.6.2 DTC Activation....................................................................................................312

10.6.3 DMAC Activation................................................................................................312

10.6.4 A/D Converter Activation....................................................................................312

10.7 Operation Timing..............................................................................................................313

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10.7.1 Input/Output Timing ............................................................................................313

10.7.2 Interrupt Signal Timing........................................................................................316

10.8 Usage Notes.......................................................................................................................320

Section 11 8-Bit Timers (TMR).........................................................................327

11.1 Features .............................................................................................................................327

11.2 Input/Output Pins ..............................................................................................................329

11.3 Register Descriptions ........................................................................................................329

11.3.1 Timer Counters (TCNT).......................................................................................329

11.3.2 Time Constant Registers A (TCORA) .................................................................329

11.3.3 Time Constant Registers B (TCORB)..................................................................329

11.3.4 Time Control Registers (TCR).............................................................................329

11.3.5 Timer Control/Status Registers (TCSR)...............................................................332

11.4 Operation...........................................................................................................................334

11.4.1 Pulse Output.........................................................................................................334

11.5 Operation Timing..............................................................................................................335

11.5.1 TCNT Incrementation Timing..............................................................................335

11.5.2 Setting of Compare Match Flags CMFA and CMFB...........................................336

11.5.3 Timer Output Timing...........................................................................................336

11.5.4 Timing of Compare Match Clear .........................................................................336

11.5.5 Timing of TCNT External Reset..........................................................................337

11.5.6 Timing of Overflow Flag (OVF) Setting..............................................................338

11.6 Operation with Cascaded Connection ...............................................................................339

11.6.1 16-Bit Counter Mode ...........................................................................................339

11.6.2 Compare Match Count Mode............................................................................... 339

11.7 Interrupts ...........................................................................................................................340

11.7.1 Interrupt Sources and DTC Activation.................................................................340

11.7.2 A/D Converter Activation....................................................................................340

11.8 Usage Notes.......................................................................................................................341

11.8.1 Contention between TCNT Write and Clear........................................................341

11.8.2 Contention between TCNT Write and Increment.................................................342

11.8.3 Contention between TCOR Write and Compare Match.......................................343

11.8.4 Contention between Compare Matches A and B..................................................344

11.8.5 Switching of Internal Clocks and TCNT Operation.............................................344

11.8.6 Mode Setting with Cascaded Connection.............................................................346

Section 12 Watchdog Timer ..............................................................................347

12.1 Features .............................................................................................................................347

12.2 Register Descriptions ........................................................................................................348

12.2.1 Timer Counter (TCNT)........................................................................................348

12.2.2 Timer Control/Status Register (TCSR)................................................................348

12.2.3 Reset Control/Status Register (RSTCSR)............................................................350

12.3 Operation...........................................................................................................................351

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12.3.1 Watchdog Timer Mode........................................................................................351

12.3.2 Timing of Setting of Watchdog Timer Overflow Flag (WOVF).........................352

12.3.3 Interval Timer Mode............................................................................................353

12.3.4 Timing of Setting of Overflow Flag (OVF).........................................................353

12.4 Interrupts...........................................................................................................................354

12.5 Usage Notes......................................................................................................................354

12.5.1 Notes on Register Access.....................................................................................354

12.5.2 Contention between Timer Counter (TCNT) Write and Increment.....................355

12.5.3 Changing Value of CKS2 to CKS0......................................................................356

12.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode................356

12.5.5 Internal Reset in Watchdog Timer Mode.............................................................356

Section 13 Serial Communication Interface ......................................................357

13.1 Features.............................................................................................................................357

13.1.1 Block Diagram.....................................................................................................358

13.2 Input/Output Pins..............................................................................................................361

13.3 Register Descriptions........................................................................................................361

13.3.1 Receive Shift Register (RSR) ..............................................................................361

13.3.2 Receive Data Register (RDR)..............................................................................362

13.3.3 Transmit Data Register (TDR).............................................................................362

13.3.4 Transmit Shift Register (TSR).............................................................................362

13.3.5 Serial Mode Register (SMR)................................................................................363

13.3.6 Serial Control Register (SCR)..............................................................................365

13.3.7 Serial Status Register (SSR) ................................................................................367

13.3.8 Smart Card Mode Register (SCMR)....................................................................370

13.3.9 Serial Extended Mode Register 0 (SEMR_0)......................................................371

13.3.10 Bit Rate Register (BRR) ......................................................................................375

13.4 Operation in Asynchronous Mode....................................................................................381

13.4.1 Data Transfer Format...........................................................................................381

13.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 383

13.4.3 Clock....................................................................................................................384

13.4.4 SCI Initialization (Asynchronous Mode).............................................................384

13.4.5 Data Transmission (Asynchronous Mode)...........................................................385

13.4.6 Serial Data Reception (Asynchronous Mode)......................................................388

13.5 Multiprocessor Communication Function.........................................................................391

13.5.1 Multiprocessor Serial Data Transmission............................................................392

13.5.2 Multiprocessor Serial Data Reception .................................................................394

13.6 Operation in Clocked Synchronous Mode........................................................................396

13.6.1 Clock....................................................................................................................397

13.6.2 SCI Initialization (Clocked Synchronous Mode).................................................397

13.6.3 Serial Data Transmission (Clocked Synchronous Mode)....................................398

13.6.4 Serial Data Reception (Clocked Synchronous Mode)..........................................400

13.6.5 Simultaneous Serial Data Transmission and Reception

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(Clocked Synchronous Mode)..............................................................................403

13.7 SCI Select Function...........................................................................................................405

13.8 Interrupts ...........................................................................................................................408

13.8.1 Interrupts in Normal Serial Communication Interface Mode...............................408

13.9 Usage Notes.......................................................................................................................409

13.9.1 Break Detection and Processing (Asynchronous Mode Only).............................409

13.9.2 Mark State and Break Detection (Asynchronous Mode Only).............................409

13.9.3 Receive Error Flags and Transmit Operations

(Clocked Synchronous Mode Only)..................................................................... 410

13.9.4 Restrictions on Use of DMAC or DTC................................................................410

13.9.5 Operation in Case of Mode Transition.................................................................410

13.9.6 Switching from SCK Pin Function to Port Pin Function: ....................................413

Section 14 Boundary Scan Function..................................................................417

14.1 Features .............................................................................................................................417

14.2 Pin Configuration..............................................................................................................419

14.3 Register Descriptions ........................................................................................................420

14.3.1 Instruction Register (INSTR)...............................................................................420

14.3.2 IDCODE Register (IDCODE)..............................................................................422

14.3.3 BYPASS Register (BYPASS)..............................................................................422

14.3.4 Boundary Scan Register (BSCANR)....................................................................422

14.4 Boundary Scan Function Operation..................................................................................431

14.4.1 TAP Controller..................................................................................................... 431

14.5 Usage Notes.......................................................................................................................431

Section 15 Universal Serial Bus Interface (USB)..............................................433

15.1 Features .............................................................................................................................433

15.2 Input/Output Pins ..............................................................................................................436

15.3 Register Descriptions ........................................................................................................437

15.3.1 USB Endpoint Information Registers 00_0 to 22_4

(UEPIR00_0 to UEPIR22_4)...............................................................................438

15.3.2 USB Control Register (UCTLR)..........................................................................445

15.3.3 USB DMAC Transfer Request Register (UDMAR)............................................449

15.3.4 USB Device Resume Register (UDRR)...............................................................450

15.3.5 USB Trigger Register 0 (UTRG0) .......................................................................451

15.3.6 USB Trigger Register 1 (UTRG1) .......................................................................452

15.3.7 USBFIFO Clear Register 0 (UFCLR0)................................................................453

15.3.8 USBFIFO Clear Register 1 (UFCLR1)................................................................454

15.3.9 USB Endpoint Stall Register 0 (UESTL0)...........................................................455

15.3.10 USB Endpoint Stall Register 1 (UESTL1)...........................................................456

15.3.11 USB Endpoint Data Register 0s (UEDR0s).........................................................457

15.3.12 USB Endpoint Data Register 0i (UEDR0i)..........................................................457

15.3.13 USB Endpoint Data Register 0o (UEDR0o)........................................................457

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15.3.14 USB Endpoint Data Register 1i (UEDR1i)..........................................................458

15.3.15 USB Endpoint Data Register 2i (UEDR2i)..........................................................458

15.3.16 USB Endpoint Data Register 2o (UEDR2o)........................................................458

15.3.17 USB Endpoint Data Register 3i (UEDR3i)..........................................................459

15.3.18 USB Endpoint Data Register 3o (UEDR3o)........................................................459

15.3.19 USB Endpoint Data Register 4i (UEDR4i)..........................................................459

15.3.20 USB Endpoint Data Register 4o (UEDR4o)........................................................460

15.3.21 USB Endpoint Data Register 5i (UEDR5i)..........................................................460

15.3.22 USB Endpoint Receive Data Size Register 0o (UESZ0o)...................................460

15.3.23 USB Endpoint Receive Data Size Register 2o (UESZ2o)...................................461

15.3.24 USB Endpoint Receive Data Size Register 3o (UESZ3o)...................................461

15.3.25 USB Endpoint Receive Data Size Register 4o (UESZ4o)...................................461

15.3.26 USB Interrupt Flag Register 0 (UIFR0)...............................................................461

15.3.27 USB Interrupt Flag Register 1 (UIFR1)...............................................................464

15.3.28 USB Interrupt Flag Register 2 (UIFR2)...............................................................466

15.3.29 USB Interrupt Flag Register 3 (UIFR3)...............................................................468

15.3.30 USB Interrupt Enable Register 0 (UIER0)...........................................................470

15.3.31 USB Interrupt Enable Register 1 (UIER1)...........................................................470

15.3.32 USB Interrupt Enable Register 2 (UIER2)...........................................................471

15.3.33 USB Interrupt Enable Register 3 (UIER3)...........................................................471

15.3.34 USB Interrupt Select Register 0 (UISR0)............................................................472

15.3.35 USB Interrupt Select Register 1 (UISR1)............................................................472

15.3.36 USB Interrupt Select Register 2 (UISR2)............................................................473

15.3.37 USB Interrupt Select Register 3 (UISR3)............................................................473

15.3.38 USB Data Status Register (UDSR)......................................................................474

15.3.39 USB Configuration Value Register (UCVR).......................................................475

15.3.40 USB Time Stamp Registers H, L (UTSRH, UTSRL)..........................................476

15.3.41 USB Test Register 0 (UTSTR0) ..........................................................................477

15.3.42 USB Test Register 1 (UTSTR1) ..........................................................................479

15.3.43 USB Test Registers 2 and A to F (UTSTR2, UTSRA to UTSRF).......................480

15.3.44 Module Stop Control Register B (MSTPCRB)....................................................481

15.4 Interrupt Sources...............................................................................................................482

15.5 Communication Operation................................................................................................484

15.5.1 Initialization.........................................................................................................484

15.5.2 USB Cable Connection/Disconnection................................................................485

15.5.3 Suspend and Resume Operations.........................................................................489

15.5.4 Control Transfer...................................................................................................492

15.5.5 Interrupt-In Transfer: (EP1i is specified as Endpoint).........................................499

15.5.6 Bulk-In Transfer (Dual FIFOs): (EP2i is specified as Endpoint).........................500

15.5.7 Bulk-Out Transfer (Dual FIFOs): (EP2o is specified as Endpoint).....................502

15.5.8 Isochronous–In Transfer (Dual-FIFO) (When EP3i is Specified as Endpoint)....504

15.5.9 Isochronous–Out Transfer (Dual-FIFO) (When EP3o is Specified as Endpoint) 506

15.5.10 Processing of USB Standard Commands and Class/Vendor Commands ............508

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15.5.11 Stall Operations....................................................................................................508

15.6 DMA Transfer Specifications............................................................................................513

15.6.1 Overview..............................................................................................................513

15.6.2 On-Chip DMAC Settings.....................................................................................513

15.6.3 EP2i and EP4i DMA Transfer..............................................................................513

15.6.4 EP2o and EP4o DMA Transfer............................................................................513

15.6.5 EP2iPKTE, EP4iPKTE, EP2oRDFN and EP4oRDFN Bits of UTRG.................514

15.7 Endpoint Configuration Example......................................................................................516

15.8 USB External Circuit Example .........................................................................................521

15.9 Usage Notes.......................................................................................................................525

15.9.1 Operating Frequency............................................................................................525

15.9.2 Bus Interface ........................................................................................................525

15.9.3 Setup Data Reception...........................................................................................525

15.9.4 FIFO Clear ...........................................................................................................525

15.9.5 IRQ6 Interrupt......................................................................................................525

15.9.6 Data Register Overread or Overwrite...................................................................526

15.9.7 EP3o Isochronous Transfer..................................................................................527

15.9.8 Reset.....................................................................................................................529

15.9.9 EP0 Interrupt Assignment....................................................................................529

15.9.10 Level Shifter for VBUS and IRQx Pins...............................................................529

15.9.11 USB Endpoint Data Read and Write....................................................................529

15.9.12 Restrictions for Software Standby Mode Transition............................................530

15.9.13 USB External Circuit Example ............................................................................532

Section 16 A/D Converter..................................................................................533

16.1 Features .............................................................................................................................533

16.2 Input/Output Pins ..............................................................................................................535

16.3 Register Descriptions ........................................................................................................535

16.3.1 A/D Data Registers A to D (ADDRA to ADDRD)..............................................535

16.3.2 A/D Control/Status Register (ADCSR)................................................................536

16.3.3 A/D Control Register (ADCR) .............................................................................538

16.4 Interface to Bus Master ..................................................................................................... 539

16.5 Operation...........................................................................................................................540

16.5.1 Single Mode.........................................................................................................540

16.5.2 Scan Mode............................................................................................................541

16.5.3 Input Sampling and A/D Conversion Time..........................................................542

16.5.4 External Trigger Input Timing.............................................................................544

16.6 Interrupts ...........................................................................................................................544

16.7 A/D Conversion Precision Definitions..............................................................................545

16.8 Usage Notes.......................................................................................................................547

16.8.1 Permissible Signal Source Impedance..................................................................547

16.8.2 Influences on Absolute Precision.........................................................................547

16.8.3 Range of Analog Power Supply and Other Pin Settings......................................547

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16.8.4 Notes on Board Design........................................................................................548

16.8.5 Notes on Noise Countermeasures........................................................................548

Section 17 D/A Converter..................................................................................551

17.1 Features.............................................................................................................................551

17.2 Input/Output Pins..............................................................................................................552

17.3 Register Description..........................................................................................................552

17.3.1 D/A Data Register (DADR)................................................................................552

17.3.2 D/A Control Register (DACR) ............................................................................553

17.4 Operation ..........................................................................................................................553

Section 18 RAM ................................................................................................555

Section 19 Flash Memory (F-ZTAT Version)...................................................557

19.1 Features.............................................................................................................................557

19.2 Mode Transitions..............................................................................................................559

19.3 Block Configuration..........................................................................................................563

19.4 Input/Output Pins..............................................................................................................564

19.5 Register Descriptions........................................................................................................564

19.5.1 Flash Memory Control Register 1 (FLMCR1).....................................................565

19.5.2 Flash Memory Control Register 2 (FLMCR2).....................................................566

19.5.3 Erase Block Register 1 (EBR1) ...........................................................................567

19.5.4 Erase Block Register 2 (EBR2) ...........................................................................568

19.5.5 RAM Emulation Register (RAMER)...................................................................569

19.5.6 Serial Control Register X (SCRX).......................................................................570

19.6 On-Board Programming Modes........................................................................................571

19.6.1 SCI Boot Mode(HD64F2215)..............................................................................571

19.6.2 USB Boot Mode (HD64F2215U)........................................................................575

19.6.3 Programming/Erasing in User Program Mode.....................................................581

19.7 Flash Memory Emulation in RAM ...................................................................................582

19.8 Flash Memory Programming/Erasing...............................................................................583

19.8.1 Program/Program-Verify.....................................................................................583

19.8.2 Erase/Erase-Verify...............................................................................................585

19.9 Program/Erase Protection .................................................................................................587

19.9.1 Hardware Protection ............................................................................................587

19.9.2 Software Protection..............................................................................................587

19.9.3 Error Protection....................................................................................................587

19.10 Interrupt Handling when Programming/Erasing Flash Memory.......................................588

19.11 Programmer Mode............................................................................................................588

19.12 Power-Down States for Flash Memory.............................................................................589

19.13 Flash Memory Programming and Erasing Precautions .....................................................589

19.14 Note on Switching from F-ZTAT Version to Masked ROM Version ..............................591

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Section 20 Masked ROM...................................................................................593

20.1 Features .............................................................................................................................593

Section 21 Clock Pulse Generator .....................................................................595

21.1 Register Descriptions ........................................................................................................596

21.1.1 System Clock Control Register (SCKCR)............................................................596

21.1.2 Low-Power Control Register (LPWRCR)............................................................598

21.2 System Clock Oscillator....................................................................................................599

21.2.1 Connecting a Crystal Resonator...........................................................................599

21.2.2 Inputting an External Clock .................................................................................600

21.3 Duty Adjustment Circuit...................................................................................................601

21.4 Medium-Speed Clock Divider...........................................................................................601

21.5 Bus Master Clock Selection Circuit..................................................................................601

21.6 USB Operating Clock........................................................................................................602

21.6.1 Connecting a Ceramic Resonator.........................................................................602

21.6.2 Inputting an 48-MHz External Clock...................................................................602

21.6.3 Pin Handling when 48-MHz External Clock is not Needed

(On-chip PLL Circuit is Used).............................................................................603

21.7 PLL Circuit for USB ......................................................................................................... 603

21.8 Usage Notes.......................................................................................................................604

21.8.1 Note on Crystal Resonator ...................................................................................604

21.8.2 Note on Board Design..........................................................................................604

21.8.3 Note on Switchover of External Clock................................................................. 605

Section 22 Power-Down Modes ........................................................................607

22.1 Register Descriptions ........................................................................................................610

22.1.1 Standby Control Register (SBYCR).....................................................................610

22.1.2 System Clock Control Register (SCKCR)............................................................612

22.1.3 Module Stop Control Registers A to C (MSTPCRA to MSTPCRC)...................612

22.2 Medium-Speed Mode........................................................................................................614

22.3 Sleep Mode........................................................................................................................615

22.3.1 Transition to Sleep Mode.....................................................................................615

22.3.2 Exiting Sleep Mode..............................................................................................615

22.4 Software Standby Mode....................................................................................................615

22.4.1 Transition to Software Standby Mode..................................................................615

22.4.2 Clearing Software Standby Mode........................................................................616

22.4.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode...616

22.4.4 Software Standby Mode Application Example ....................................................617

22.5 Hardware Standby Mode...................................................................................................618

22.5.1 Transition to Hardware Standby Mode................................................................618

22.5.2 Clearing Hardware Standby Mode.......................................................................618

22.5.3 Hardware Standby Mode Timing.........................................................................619

22.5.4 Hardware Standby Mode Timings .......................................................................619

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22.6 Module Stop Mode ...........................................................................................................620

22.7 ø Clock Output Disabling Function ..................................................................................620

22.8 Usage Notes......................................................................................................................621

22.8.1 I/O Port Status......................................................................................................621

22.8.2 Current Dissipation during Oscillation Stabilization Wait Period.......................621

22.8.3 DMAC and DTC Module Stop............................................................................621

22.8.4 On-Chip Supporting Module Interrup t ................................................................621

Section 23 List of Registers...............................................................................623

23.1 Register Addresses (Address Order).................................................................................623

23.2 Register Bits......................................................................................................................632

23.3 Register States in Each Operating Mode ..........................................................................642

Section 24 Electrical Characteristics .................................................................649

24.1 Absolute Maximum Ratings .............................................................................................649

24.2 Power Supply Voltage and Operating Frequency Range..................................................650

24.3 DC Characteristics ............................................................................................................651

24.4 AC Characteristics ............................................................................................................654

24.4.1 Clock Timing.......................................................................................................655

24.4.2 Control Signal Timing .........................................................................................656

24.4.3 Bus Timing ..........................................................................................................658

24.4.4 Timing of On-Chip Supporting Modules.............................................................664

24.5 UBS Characteristics..........................................................................................................670

24.6 A/D Conversion Characteristics........................................................................................671

24.7 D/A Conversion Characteristics........................................................................................672

24.8 Flash Memory Characteristics...........................................................................................672

24.9 Usage Note........................................................................................................................673

Appendix ..........................................................................................................675

A. I/O Port States in Each Processing State...........................................................................675

B. Product Model Lineup ......................................................................................................679

C. Package Dimensions.........................................................................................................680

Index ..........................................................................................................683

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Figures

Section 1 Overview

Figure 1.1 Internal Block Diagram ............................................................................................... 2

Figure 1.2 Pin Arrangement (TFP-120)........................................................................................ 3

Figure 1.3 Pin Arrangement (BP-112).......................................................................................... 4

Section 2 CPU

Figure 2.1 Exception Vector Table (Normal Mode) ................................................................... 23

Figure 2.2 Stack Structure in Normal Mode ............................................................................... 23

Figure 2.3 Exception Vector Table (Advanced Mode) ............................................................... 24

Figure 2.4 Stack Structure in Advanced Mode ........................................................................... 25

Figure 2.5 Memory Map............................................................................................................. 26

Figure 2.6 CPU Registers ...........................................................................................................27

Figure 2.7 Usage of General Registers ....................................................................................... 28

Figure 2.8 Stack .......................................................................................................................... 29

Figure 2.9 General Register Data Formats (1)............................................................................ 32

Figure 2.9 General Register Data Formats (2)............................................................................ 33

Figure 2.10 Memory Data Formats............................................................................................... 34

Figure 2.11 Instruction Formats (Examples) ................................................................................46

Figure 2.12 Branch Address Specification in Memory Indirect Mode ......................................... 49

Figure 2.13 State Transitions ........................................................................................................ 53

Section 3 MCU Operating Modes

Figure 3.1 Memory Map in Each Operating Mode for HD64F2215, HD64F2215U, and

HD6432215A ............................................................................................................61

Figure 3.2 Memory Map in Each Operating Mode for HD6432215B........................................ 62

Figure 3.3 Memory Map in Each Operating Mode for HD6432215C........................................ 63

Section 4 Exception Handling

Figure 4.1 Reset Sequence (Modes 2 and 3: Not available in this LSI)...................................... 68

Figure 4.2 Reset Sequence (Mode 4).......................................................................................... 69

Figure 4.3 Stack Status after Exception Handling ......................................................................72

Figure 4.4 Operation when SP Value is Odd .............................................................................. 73

Section 5 Interrupt Controller

Figure 5.1 Block Diagram of Interrupt Controller ...................................................................... 76

Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0 .............................................................. 83

Figure 5.3 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0.... 88

Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 2.... 90

Figure 5.5 Interrupt Exception Handling .................................................................................... 91

Figure 5.6 Interrupt Control for DTC and DMAC...................................................................... 93

Figure 5.7 Contention between Interrupt Generation and Disabling ..........................................96

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Section 6 Bus Controller

Figure 6.1 Block Diagram of Bus Controller............................................................................ 100

Figure 6.2 Overview of Area Divisions.................................................................................... 110

Figure 6.3 CSn Signal Output Timing (n = 0 to 7) ................................................................... 113

Figure 6.4 On-Chip Memory Access Cycle.............................................................................. 114

Figure 6.5 Pin States during On-Chip Memory Access............................................................ 115

Figure 6.6 On-Chip Peripheral Module Access Cycle.............................................................. 115

Figure 6.7 Pin States during On-Chip Peripheral Module Access............................................ 116

Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space) ........................... 117

Figure 6.9 Access Sizes and Data Alignment Control (16-Bit Access Space) ......................... 118

Figure 6.10 Bus Timing for 8-Bit 2-State Access Space ............................................................ 119

Figure 6.11 Bus Timing for 8-Bit 3-State Access Space (Except Area 6).................................. 120

Figure 6.12 Bus Timing for Area 6 ............................................................................................ 121

Figure 6.13 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access)...... 122

Figure 6.14 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) ....... 123

Figure 6.15 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access)............................ 124

Figure 6.16 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access)...... 125

Figure 6.17 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) ....... 126

Figure 6.18 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access)............................ 127

Figure 6.19 Example of Wait State Insertion Timing................................................................. 129

Figure 6.20 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1).................. 131

Figure 6.21 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0).................. 131

Figure 6.22 Example of Idle Cycle Operation (1) ...................................................................... 133

Figure 6.23 Example of Idle Cycle Operation (2) ...................................................................... 134

Figure 6.24 Relationship between Chip Select (CS) and Read (RD) ......................................... 134

Figure 6.25 Bus-Released State Transition Timing.................................................................... 137

Section 7 DMA Controller

Figure 7.1 Block Diagram of DMAC ....................................................................................... 142

Figure 7.2 Areas for Register Re-Setting by DTC (Example: Channel 0A)............................. 161

Figure 7.3 Operation in Sequential Mode................................................................................. 165

Figure 7.4 Example of Sequential Mode Setting Procedure..................................................... 166

Figure 7.5 Operation in Idle Mode ........................................................................................... 167

Figure 7.6 Example of Idle Mode Setting Procedure ............................................................... 168

Figure 7.7 Operation in Repeat Mode ...................................................................................... 170

Figure 7.8 Example of Repeat Mode Setting Procedure........................................................... 171

Figure 7.9 Operation in Normal Mode ..................................................................................... 173

Figure 7.10 Example of Normal Mode Setting Procedure.......................................................... 174

Figure 7.11 Operation in Block Transfer Mode (BLKDIR = 0) ................................................. 176

Figure 7.12 Operation in Block Transfer Mode (BLKDIR = 1) ................................................. 177

Figure 7.13 Operation Flow in Block Transfer Mode ................................................................ 178

Figure 7.14 Example of Block Transfer Mode Setting Procedure.............................................. 179

Figure 7.15 Example of DMA Transfer Bus Timing.................................................................. 181

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Figure 7.16 Example of Short Address Mode Transfer .............................................................. 182

Figure 7.17 Example of Full Address Mode (Cycle Steal) Transfer........................................... 183

Figure 7.18 Example of Full Address Mode (Burst Mode) Transfer..........................................183

Figure 7.19 Example of Full Address Mode (Block Transfer Mode) Transfer........................... 184

Figure 7.20 Example of DREQ Level Activated Normal Mode Transfer ..................................185

Figure 7.21 Example of DREQ Level Activated Block Transfer Mode Transfer....................... 186

Figure 7.22 Example of Multi-Channel Transfer........................................................................ 187

Figure 7.23 Example of Procedure for Continuing Transfer on Channel Interrupted

by NMI Interrupt ..................................................................................................... 188

Figure 7.24 Example of Procedure for Forcibly Terminating DMAC Operation ....................... 189

Figure 7.25 Example of Procedure for Clearing Full Address Mode.......................................... 190

Figure 7.26 Block Diagram of Transfer End/Transfer Break Interrupt....................................... 191

Figure 7.27 DMAC Register Update Timing.............................................................................. 192

Figure 7.28 Contention between DMAC Register Update and CPU Read................................. 193

Section 8 Data Transfer Controller (DTC)

Figure 8.1 Block Diagram of DTC ........................................................................................... 196

Figure 8.2 Block Diagram of DTC Activation Source Control ................................................ 201

Figure 8.3 Correspondence between DTC Vector Address and Register Information ............. 202

Figure 8.4 Correspondence between DTC Vector Address and Register Information ............. 203

Figure 8.5 Flowchart of DTC Operation................................................................................... 205

Figure 8.6 Memory Mapping in Normal Mode ........................................................................207

Figure 8.7 Memory Mapping in Repeat Mode..........................................................................208

Figure 8.8 Memory Mapping in Block Transfer Mode............................................................. 209

Figure 8.9 Chain Transfer Memory Map..................................................................................210

Figure 8.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode).................... 211

Figure 8.11 DTC Operation Timing

(Example of Block Transfer Mode, with Block Size of 2) ..................................... 212

Figure 8.12 DTC Operation Timing (Example of Chain Transfer).............................................212

Section 10 16-Bit Timer Pulse Unit (TPU)

Figure 10.1 Block Diagram of TPU............................................................................................ 264

Figure 10.2 16-Bit Register Access Operation [Bus Master ↔ TCNT (16 Bits)] ...................... 291

Figure 10.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)].................. 291

Figure 10.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)].............. 292

Figure 10.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)]........292

Figure 10.6 Example of Counter Operation Setting Procedure................................................... 293

Figure 10.7 Free-Running Counter Operation ............................................................................ 294

Figure 10.8 Periodic Counter Operation.....................................................................................294

Figure 10.9 Example of Setting Procedure for Waveform Output by Compare Match .............. 295

Figure 10.10 Example of 0 Output/1 Output Operation.............................................................. 295

Figure 10.11 Example of Toggle Output Operation.................................................................... 296

Figure 10.12 Example of Input Capture Operation Setting Procedure........................................ 296

Figure 10.13 Example of Input Capture Operation .....................................................................297

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Figure 10.14 Example of Synchronous Operation Setting Procedure......................................... 298

Figure 10.15 Example of Synchronous Operation...................................................................... 299

Figure 10.16 Compare Match Buffer Operation......................................................................... 299

Figure 10.17 Input Capture Buffer Operation............................................................................. 300

Figure 10.18 Example of Buffer Operation Setting Procedure................................................... 300

Figure 10.19 Example of Buffer Operation (1)........................................................................... 301

Figure 10.20 Example of Buffer Operation (2)........................................................................... 301

Figure 10.21 Example of PWM Mode Setting Procedure .......................................................... 303

Figure 10.22 Example of PWM Mode Operation (1) ................................................................. 303

Figure 10.23 Example of PWM Mode Operation (2) ................................................................. 304

Figure 10.24 Example of PWM Mode Operation (3) ................................................................. 305

Figure 10.25 Example of Phase Counting Mode Setting Procedure........................................... 306

Figure 10.26 Example of Phase Counting Mode 1 Operation .................................................... 307

Figure 10.27 Example of Phase Counting Mode 2 Operation .................................................... 308

Figure 10.28 Example of Phase Counting Mode 3 Operation .................................................... 309

Figure 10.29 Example of Phase Counting Mode 4 Operation .................................................... 310

Figure 10.30 Count Timing in Internal Clock Operation............................................................ 313

Figure 10.31 Count Timing in External Clock Operation........................................................... 313

Figure 10.32 Output Compare Output Timing............................................................................ 314

Figure 10.33 Input Capture Input Signal Timing........................................................................ 314

Figure 10.34 Counter Clear Timing (Compare Match)............................................................... 315

Figure 10.35 Counter Clear Timing (Input Capture) .................................................................. 315

Figure 10.36 Buffer Operation Timing (Compare Match).......................................................... 315

Figure 10.37 Buffer Operation Timing (Input Capture) ............................................................. 316

Figure 10.38 TGI Interrupt Timing (Compare Match) ............................................................... 316

Figure 10.39 TGI Interrupt Timing (Input Capture) ................................................................... 317

Figure 10.40 TCIV Interrupt Setting Timing.............................................................................. 317

Figure 10.41 TCIU Interrupt Setting Timing.............................................................................. 318

Figure 10.42 Timing for Status Flag Clearing by CPU............................................................... 318

Figure 10.43 Timing for Status Flag Clearing by DTC or DMAC Activation ........................... 319

Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................ 320

Figure 10.45 Contention between TCNT Write and Clear Operations....................................... 321

Figure 10.46 Contention between TCNT Write and Increment Operations ............................... 321

Figure 10.47 Contention between TGR Write and Compare Match........................................... 322

Figure 10.48 Contention between Buffer Register Write and Compare Match .......................... 322

Figure 10.49 Contention between TGR Read and Input Capture ............................................... 323

Figure 10.50 Contention between TGR Write and Input Capture .............................................. 323

Figure 10.51 Contention between Buffer Register Write and Input Capture.............................. 324

Figure 10.52 Contention between Overflow and Counter Clearing............................................ 324

Figure 10.53 Contention between TCNT Write and Overflow................................................... 325

Section 11 8-Bit Timers (TMR)

Figure 11.1 Block Diagram of 8-Bit Timer ................................................................................ 328

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Figure 11.2 Example of Pulse Output......................................................................................... 334

Figure 11.3 Count Timing for Internal Clock Input.................................................................... 335

Figure 11.4 Count Timing for External Clock Input................................................................... 335

Figure 11.5 Timing of CMF Setting ........................................................................................... 336

Figure 11.6 Timing of Timer Output .......................................................................................... 336

Figure 11.7 Timing of Compare Match Clear............................................................................. 337

Figure 11.8 Timing of Clearance by External Reset ...................................................................337

Figure 11.9 Timing of OVF Setting............................................................................................ 338

Figure 11.10 Contention between TCNT Write and Clear ........................................................... 341

Figure 11.11 Contention between TCNT Write and Increment.................................................... 342

Figure 11.12 Contention between TCOR Write and Compare Match..........................................343

Section 12 Watchdog Timer

Figure 12.1 Block Diagram of WDT .......................................................................................... 347

Figure 12.2 Operation in Watchdog Timer Mode....................................................................... 351

Figure 12.3 Timing of WOVF Setting ........................................................................................ 352

Figure 12.4 Operation in Interval Timer Mode........................................................................... 353

Figure 12.5 Timing of OVF Setting............................................................................................ 353

Figure 12.6 Format of Data Written to TCNT and TCSR ..........................................................354

Figure 12.7 Format of Data Written to RSTCSR (Example of WDT0)...................................... 355

Figure 12.8 Contention between TCNT Write and Increment.................................................... 356

Section 13 Serial Communication Interface

Figure 13.1 Block Diagram of SCI_0 ......................................................................................... 359

Figure 13.2 Block Diagram of SCI_1 and SCI_2 ....................................................................... 360

Figure 13.3 Examples of Base Clock when Average Transfer Rate is Selected ......................... 373

Figure 13.4 Example of Average Transfer Rate Setting with TPU Clock Input......................... 374

Figure 13.5 Data Format in Asynchronous Communication

(Example with 8-Bit Data, Parity, Two Stop Bits) .................................................. 381

Figure 13.6 Receive Data Sampling Timing in Asynchronous Mode......................................... 383

Figure 13.7 Relationship between Output Clock and Transfer Data Phase

(Asynchronous Mode).............................................................................................384

Figure 13.8 Sample SCI Initialization Flowchart........................................................................385

Figure 13.9 Example of Operation in Transmission in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit) ....................................................386

Figure 13.10 Sample Serial Transmission Flowchart..................................................................387

Figure 13.11 Example of SCI Operation in Reception

(Example with 8-Bit Data, Parity, One Stop Bit)................................................... 388

Figure 13.12 Sample Serial Reception Data Flowchart (1)......................................................... 390

Figure 13.12 Sample Serial Reception Data Flowchart (2)......................................................... 391

Figure 13.13 Example of Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A)........................................... 392

Figure 13.14 Sample Multiprocessor Serial Transmission Flowchart.........................................393

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Figure 13.15 Example of SCI Operation in Reception

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) .............................. 394

Figure 13.16 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 395

Figure 13.16 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 396

Figure 13.17 Data Format in Synchronous Communication (For LSB-First)............................. 397

Figure 13.18 Sample SCI Initialization Flowchart ..................................................................... 398

Figure 13.19 Sample SCI Transmission Operation in Clocked Synchronous Mode .................. 399

Figure 13.20 Sample Serial Transmission Flowchart ................................................................. 400

Figure 13.21 Example of SCI Operation in Reception ............................................................... 401

Figure 13.22 Sample Serial Reception Flowchart....................................................................... 402

Figure 13.23 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations....... 404

Figure 13.24 Example of Communication Using the SCI Select Function................................. 406

Figure 13.25 Operation of Communication Using the SCI Select Function............................... 407

Figure 13.26 Example of Clocked Synchronous Transmission by DTC .................................... 410

Figure 13.27 Sample Flowchart for Mode Transition during Transmission............................... 411

Figure 13.28 Port Pin State of Asynchronous Transmission Using Internal Clock .................... 412

Figure 13.29 Port Pin State of Synchronous Transmission Using Internal Clock ...................... 412

Figure 13.30 Sample Flowchart for Mode Transition during Reception .................................... 413

Figure 13.31 Operation when Switching from SCK Pin Function to Port Pin Function ............ 414

Figure 13.32 Operation when Switching from SCK Pin Function to Port Pin Function

(Example of Preventing Low-Level Output)......................................................... 415

Section 14 Boundary Scan Function

Figure 14.1 Block Diagram of Boundary Scan Function............................................................ 418

Figure 14.2 Boundary Scan Register Configuration................................................................... 423

Figure 14.3 TAP Controller Status Transition............................................................................ 431

Figure 14.4 Recommended Reset Signal Design........................................................................ 432

Figure 14.5 Serial Data Input/Output ......................................................................................... 432

Section 15 Universal Serial Bus Interface (USB)

Figure 15.1 Block Diagram of USB ........................................................................................... 435

Figure 15.2 Example of Endpoint Configuration based on Bluetooth Standard......................... 442

Figure 15.3 USB Initialization.................................................................................................... 484

Figure 15.4 USB Cable Connection

(When USB Module Stop or Software Standby is not Used).................................. 485

Figure 15.5 USB Cable Connection (When USB Module Stop or Software Standby is Used).. 486 Figure 15.6 USB Cable Disconnection

(When USB Module Stop or Software Standby is not Used).................................. 487

Figure 15.7 USB Cable Disconnection

(When USB Module Stop or Software Standby is Used)........................................ 488

Figure 15.8 Suspend Operation .................................................................................................. 489

Figure 15.9 Resume Operation from Up-Stream........................................................................ 490

Figure 15.10 Operation when Remote-Wakeup Function is Used.............................................. 491

Figure 15.11 Control Transfer Stage Configuration ................................................................... 492

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Figure 15.12 Setup Stage Operation ........................................................................................... 493

Figure 15.13 Data Stage Operation (Control-In)......................................................................... 495

Figure 15.14 Data Stage Operation (Control-Out) ......................................................................496

Figure 15.15 Status Stage Operation (Control-In) ......................................................................497

Figure 15.16 Status Stage Operation (Control-Out).................................................................... 498

Figure 15.17 EP1i Interrupt-In Transfer Operation..................................................................... 499

Figure 15.18 EP2i Bulk-In Transfer Operation........................................................................... 501

Figure 15.19 EP2o Bulk-In Transfer Operation.......................................................................... 503

Figure 15.20 EP3i Isochronous-In Transfer Operation ............................................................... 505

Figure 15.21 EP3o Isochronous-Out Transfer Operation............................................................507

Figure 15.22 Forcible Stall by Firmware .................................................................................... 510

Figure 15.23 Automatic Stall by USB Function Module............................................................ 512

Figure 15.24 EP2iPKTE Operation in UTRG0........................................................................... 514

Figure 15.25 EP2oRDFN Operation in UTRG0 ......................................................................... 515

Figure 15.26 Endpoint Configuration Example .......................................................................... 516

Figure 15.27 USB External Circuit in Bus-Powered Mode

(When On-Chip Transceiver is Used).................................................................... 521

Figure 15.28 USB External Circuit in Self-Powered Mode

(When On-Chip Transceiver is Used).................................................................... 522

Figure 15.29 USB External Circuit in Bus-Powered Mode

(When External Transceiver is Used) .................................................................... 523

Figure 15.30 USB External Circuit in Self-Powered Mode

(When External Transceiver is Used) .................................................................... 524

Figure 15.31 10-Byte Data Reception......................................................................................... 527

Figure 15.32 EP3o Data Reception ............................................................................................. 528

Figure 15.33 Transition to and from Software Standby Mode.................................................... 531

Figure 15.34 USB Software Standby Mode Transition Timing.................................................. 532

Section 16 A/D Converter

Figure 16.1 Block Diagram of A/D Converter............................................................................534

Figure 16.2 Access to ADDR (When Reading H’AA40) ...........................................................539

Figure 16.3 A/D Conversion Timing (Single-Chip Mode, Channel 1 Selected) ........................541

Figure 16.4 A/D Conversion Timing (Scan Mode, Channels AN0 to AN3 Selected)................ 542

Figure 16.5 A/D Conversion Timing .......................................................................................... 543

Figure 16.6 External Trigger Input Timing................................................................................. 544

Figure 16.7 A/D Conversion Precision Definitions (1)............................................................... 546

Figure 16.8 A/D Conversion Precision Definitions (2)............................................................... 546

Figure 16.9 Example of Analog Input Circuit ............................................................................ 547

Figure 16.10 Example of Analog Input Protection Circuit ........................................................... 549

Figure 16.11 Analog Input Pin Equivalent Circuit ....................................................................... 549

Section 17 D/A Converter

Figure 17.1 Block Diagram of D/A Converter............................................................................551

Figure 17.2 Example of D/A Converter Operation ..................................................................... 554

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Section 19 Flash Memory (F-ZTAT Version)

Figure 19.1 Block Diagram of Flash Memory........................................................................... 558

Figure 19.2 Flash Memory State Transitions.............................................................................. 559

Figure 19.3 Boot Mode............................................................................................................... 561

Figure 19.4 User Program Mode ................................................................................................ 562

Figure 19.5 Flash Memory Block Configuration........................................................................ 563

Figure 19.6 SCI System Configuration in Boot Mode ............................................................... 572

Figure 19.7 System Configuration Diagram when Using USB Boot Mode............................... 576

Figure 19.8 Programming/Erasing Flowchart Example in User Program Mode........................ 580

Figure 19.9 Flowchart for Flash Memory Emulation in RAM................................................... 581

Figure 19.10 Example of RAM Overlap Operation...................................................................... 582

Figure 19.11 Program/Program-Verify Flowchart ....................................................................... 584

Figure 19.12 Erase/Erase-Verify Flowchart ................................................................................. 586

Figure 19.13 Memory Map in Programmer Mode........................................................................ 588

Section 20 Masked ROM

Figure 20.1 Block Diagram of On-Chip Masked ROM (256 kbytes)........................................ 593

Section 21 Clock Pulse Generator

Figure 21.1 Block Diagram of Clock Pulse Generator............................................................... 595

Figure 21.2 Connection of Crystal Resonator (Example)........................................................... 599

Figure 21.3 Crystal Resonator Equivalent Circuit...................................................................... 599

Figure 21.4 External Clock Input (Examples) ............................................................................ 600

Figure 21.5 External Clock Input Timing................................................................................... 601

Figure 21.6 Connection of Ceramic Resonator........................................................................... 602

Figure 21.7 Connection of Ceramic Resonator........................................................................... 602

Figure 21.8 48-MHz External Clock Input Timing .................................................................... 603

Figure 21.9 Pin Handling when 48-MHz External Clock is Not Used ....................................... 603

Figure 21.10 Example of PLL Circuit .......................................................................................... 604

Figure 21.11 Note on Board Design of Oscillator Circuit ............................................................ 605

Figure 21.12 Example of External Clock Switching Circuit ........................................................ 605

Figure 21.13 Example of External Clock Switchover Timing...................................................... 606

Section 22 Power-Down Modes

Figure 22.1 Mode Transition Diagram ....................................................................................... 609

Figure 22.2 Medium-Speed Mode Transition and Clearance Timing ........................................ 614

Figure 22.3 Software Standby Mode Application Example ....................................................... 618

Figure 22.4 Hardware Standby Mode Timing (Example) .......................................................... 619

Figure 22.5 Timing of Transition to Hardware Standby Mode .................................................. 619

Figure 22.6 Timing of Recovery from Hardware Standby Mode............................................... 620

Section 24 Electrical Characteristics

Figure 24.1 Power Supply Voltage and Operating Ranges ........................................................ 650

Figure 24.2 Output Load Circuit ................................................................................................ 654

Figure 24.3 System Clock Timing.............................................................................................. 655

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Figure 24.4 Oscillation Stabilization Timing.............................................................................. 656

Figure 24.5 Reset Input Timing ..................................................................................................657

Figure 24.6 Interrupt Input Timing............................................................................................. 657

Figure 24.7 Basic Bus Timing (Two-State Access).................................................................... 659

Figure 24.8 Basic Bus Timing (Three-State Access).................................................................. 660

Figure 24.9 Basic Bus Timing (Three-State Access with One Wait State)................................. 661

Figure 24.10 Burst ROM Access Timing (Two-State Access) ................................................... 662

Figure 24.11 External Bus Release Timing.................................................................................663

Figure 24.12 I/O Port Input/Output Timing................................................................................ 666

Figure 24.13 TPU Input/Output Timing ..................................................................................... 666

Figure 24.14 TPU Clock Input Timing ....................................................................................... 666

Figure 24.15 8-bit Timer Output Timing .................................................................................... 667

Figure 24.16 8-bit Timer Clock Input Timing ............................................................................667

Figure 24.17 8-bit Timer Reset Input Timing ............................................................................. 667

Figure 24.18 SCK Clock Input Timing.......................................................................................667

Figure 24.19 SCI Input/Output Timing (Clock Synchronous Mode).......................................... 668

Figure 24.20 A/D Converter External Trigger Input Timing ...................................................... 668

Figure 24.21 Boundary Scan TCK Input Timing......................................................................... 668

Figure 24.22 Boundary Scan TRST Input Timing (At Reset Hold)............................................ 668

Figure 24.23 Boundary Scan Data Transmission Timing ........................................................... 669

Figure 24.24 Data Signal Timing................................................................................................ 670

Figure 24.25 Test Load Circuit...................................................................................................671

Appendix

Figure C.1 TFP-120 Package Dimension .................................................................................. 680

Figure C.2 BP-112 Package Dimension .................................................................................... 681

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Tables

Section 2 CPU

Table 2.1 Instruction Classification ............................................................................................ 35

Table 2.2 Operation Notation...................................................................................................... 36

Table 2.3 Data Transfer Instructions........................................................................................... 37

Table 2.4 Arithmetic Operations Instructions (1) ....................................................................... 38

Table 2.4 Arithmetic Operations Instructions (2) ....................................................................... 39

Table 2.5 Logic Operations Instructions ..................................................................................... 40

Table 2.6 Shift Instructions......................................................................................................... 40

Table 2.7 Bit Manipulation Instructions (1)................................................................................ 41

Table 2.7 Bit Manipulation Instructions (2)................................................................................ 42

Table 2.8 Branch Instructions ..................................................................................................... 43

Table 2.9 System Control Instruction ......................................................................................... 44

Table 2.10 Block Data Transfer Instruction.................................................................................. 45

Table 2.11 Addressing Modes....................................................................................................... 46

Table 2.12 Absolute Address Access Ranges ............................................................................... 48

Table 2.13 Effective Address Calculation (1)............................................................................... 50

Table 2.13 Effective Address Calculation (2)............................................................................... 51

Section 3 MCU Operating Modes

Table 3.1 MCU Operating Mode Selection................................................................................. 55

Table 3.2 Pin Functions in Each Operating Mode ...................................................................... 60

Section 4 Exception Handling

Table 4.1 Exception Types and Priority...................................................................................... 65

Table 4.2 Exception Handling Vector Table............................................................................... 66

Table 4.3 Reset Types................................................................................................................. 67

Table 4.4 Status of CCR and EXR after Trace Exception Handling........................................... 70

Table 4.5 Status of CCR and EXR after Trap Instruction Exception Handling .......................... 71

Section 5 Interrupt Controller

Table 5.1 Pin Configuration........................................................................................................ 77

Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities..................................... 85

Table 5.3 Interrupt Control Modes.............................................................................................. 87

Table 5.4 Interrupt Response Times ........................................................................................... 92

Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses ......................... 92

Table 5.6 Interrupt Source Selection and Clearing Control ........................................................ 95

Section 6 Bus Controller

Table 6.1 Pin Configuration...................................................................................................... 101

Table 6.2 Bus Specifications for Each Area (Basic Bus Interface)........................................... 112

Table 6.3 Data Buses Used and Valid Strobes.......................................................................... 118

Table 6.4 Pin States in Idle Cycle ............................................................................................. 135

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Table 6.5 Pin States in Bus Released State ...............................................................................136

Section 7 DMA Controller

Table7.1 Short Address Mode and Full Address Mode

(For 1 Channel: Example of Channel 0).................................................................... 143

Table 7.2 DMAC Transfer Modes.............................................................................................163

Table 7.3 Register Functions in Sequential Mode.....................................................................164

Table 7.4 Register Functions in Idle Mode ............................................................................... 167

Table 7.5 Register Functions in Repeat Mode ..........................................................................169

Table 7.6 Register Functions in Normal Mode ......................................................................... 172

Table 7.7 Register Functions in Block Transfer Mode..............................................................175

Table 7.8 DMAC Activation Sources........................................................................................180

Table 7.9 DMAC Channel Priority Order .................................................................................187

Table 7.10 Interrupt Source Priority Order ................................................................................. 191

Section 8 Data Transfer Controller (DTC)

Table 8.1 Activation Source and DTCER Clearance ................................................................ 201

Table 8.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCE..................... 204

Table 8.3 Overview of DTC Functions .....................................................................................206

Table 8.4 Register Information in Normal Mode ...................................................................... 207

Table 8.5 Register Information in Repeat Mode ....................................................................... 208

Table 8.6 Register Information in Block Transfer Mode ..........................................................209

Table 8.7 DTC Execution Status............................................................................................... 213

Table 8.8 Number of States Required for Each Execution Status .............................................213

Section 9 I/O Ports

Table 9.1 Port Functions (1)...................................................................................................... 217

Table 9.1 Port Functions (2)...................................................................................................... 218

Table 9.1 Port Functions (3)...................................................................................................... 219

Table 9.1 Port Functions (4)...................................................................................................... 220

Table 9.2 P17 Pin Function.......................................................................................................222

Table 9.3 P16 Pin Function.......................................................................................................222

Table 9.4 P15 Pin Function.......................................................................................................223

Table 9.5 P14 Pin Function.......................................................................................................223

Table 9.6 P13 Pin Function.......................................................................................................223

Table 9.7 P12 Pin Function.......................................................................................................224

Table 9.8 P11 Pin Function.......................................................................................................224

Table 9.9 P10 Pin Function.......................................................................................................224

Table 9.10 P36 Pin Function....................................................................................................... 227

Table 9.11 P35 Pin Function....................................................................................................... 227

Table 9.12 P34 Pin Function....................................................................................................... 227

Table 9.13 P33 Pin Function....................................................................................................... 227

Table 9.14 P32 Pin Function....................................................................................................... 227

Table 9.15 P31 Pin Function....................................................................................................... 228

Rev. 2.0, 10/02, page liv of lviii

Page 55

Table 9.16 P30 Pin Function....................................................................................................... 228

Table 9.17 P74 Pin Function....................................................................................................... 230

Table 9.18 P73 Pin Function....................................................................................................... 230

Table 9.19 P72 Pin Function....................................................................................................... 231

Table 9.20 P71 Pin Function....................................................................................................... 231

Table 9.21 P70 Pin Function....................................................................................................... 231

Table 9.22 PA3 Pin Function...................................................................................................... 235

Table 9.23 PA2 Pin Function...................................................................................................... 236

Table 9.24 PA1 Pin Function...................................................................................................... 236

Table 9.25 PA0 Pin Function...................................................................................................... 236

Table 9.26 Input Pull-Up MOS States (Port A) .......................................................................... 237

Table 9.27 PB7 Pin Function ...................................................................................................... 240

Table 9.28 PB6 Pin Function ...................................................................................................... 240

Table 9.29 PB5 Pin Function ...................................................................................................... 240

Table 9.30 PB4 Pin Function ...................................................................................................... 240

Table 9.31 PB3 Pin Function ...................................................................................................... 241

Table 9.32 PB2 Pin Function ...................................................................................................... 241

Table 9.33 PB1 Pin Function ...................................................................................................... 241

Table 9.34 PB0 Pin Function ...................................................................................................... 241

Table 9.35 Input Pull-Up MOS States (Port B) .......................................................................... 242

Table 9.36 PC7 Pin Function ...................................................................................................... 244

Table 9.37 PC6 Pin Function ...................................................................................................... 245

Table 9.38 PC5 Pin Function ...................................................................................................... 245

Table 9.39 PC4 Pin Function ...................................................................................................... 245

Table 9.40 PC3 Pin Function ...................................................................................................... 245

Table 9.41 PC2 Pin Function ...................................................................................................... 245

Table 9.42 PC1 Pin Function ...................................................................................................... 245

Table 9.43 PC0 Pin Function ...................................................................................................... 246

Table 9.44 Input Pull-Up MOS States (Port C)........................................................................... 246

Table 9.45 PD7 Pin Function...................................................................................................... 249

Table 9.46 PD6 Pin Function...................................................................................................... 249

Table 9.47 PD5 Pin Function...................................................................................................... 249

Table 9.48 PD4 Pin Function...................................................................................................... 249

Table 9.49 PD3 Pin Function...................................................................................................... 249

Table 9.50 PD2 Pin Function...................................................................................................... 249

Table 9.51 PD1 Pin Function...................................................................................................... 250

Table 9.52 PD0 Pin Function...................................................................................................... 250

Table 9.53 Input Pull-Up MOS States (Port D) .......................................................................... 250

Table 9.54 PE7 Pin Function ...................................................................................................... 253

Table 9.55 PE6 Pin Function ...................................................................................................... 253

Table 9.56 PE5 Pin Function ...................................................................................................... 253

Table 9.57 PE4 Pin Function ...................................................................................................... 253

Table 9.58 PE3 Pin Function ...................................................................................................... 254

Rev. 2.0, 10/02, page lv of lviii

Page 56

Table 9.59 PE2 Pin Function.......................................................................................................254

Table 9.60 PE1 Pin Function.......................................................................................................254

Table 9.61 PE0 Pin Function.......................................................................................................254

Table 9.62 Input Pull-Up MOS States (Port E)........................................................................... 255

Table 9.63 PF7 Pin Function....................................................................................................... 257

Table 9.64 PF6 Pin Function....................................................................................................... 257

Table 9.65 PF5 Pin Function....................................................................................................... 257

Table 9.66 PF4 Pin Function....................................................................................................... 258

Table 9.67 PF3 Pin Function....................................................................................................... 258

Table 9.68 PF2 Pin Function....................................................................................................... 258

Table 9.69 PF1 Pin Function....................................................................................................... 258

Table 9.70 PF0 Pin Function....................................................................................................... 259

Table 9.71 PG4 Pin Function ...................................................................................................... 260

Table 9.72 PG3 Pin Function ...................................................................................................... 261

Table 9.73 PG2 Pin Function ...................................................................................................... 261

Table 9.74 PG1 Pin Function ...................................................................................................... 261

Table 9.75 PG0 Pin Function ...................................................................................................... 261

Section 10 16-Bit Timer Pulse Unit (TPU)

Table 10.1 TPU Functions......................................................................................................... 265

Table 10.2 Pin Configuration ....................................................................................................267

Table 10.3 CCLR2 to CCLR0 (channel 0) ................................................................................ 270

Table 10.4 CCLR2 to CCLR0 (channels 1 and 2)..................................................................... 270

Table 10.5 TPSC2 to TPSC0 (channel 0).................................................................................. 271

Table 10.6 TPSC2 to TPSC0 (channel 1).................................................................................. 271

Table 10.7 TPSC2 to TPSC0 (channel 2).................................................................................. 272

Table 10.8 MD3 to MD0 ........................................................................................................... 274

Table 10.9 TIORH_0 (channel 0).............................................................................................. 276

Table 10.10 TIORH_0 (channel 0)..............................................................................................277

Table 10.11 TIORL_0 (channel 0) .............................................................................................. 278

Table 10.12 TIORL_0 (channel 0) .............................................................................................. 279

Table 10.13 TIOR_1 (channel 1)................................................................................................. 280

Table 10.14 TIOR_1 (channel 1)................................................................................................. 281

Table 10.15 TIOR_2 (channel 2)................................................................................................. 282

Table 10.16 TIOR_2 (channel 2)................................................................................................. 283

Table 10.17 Register Combinations in Buffer Operation ............................................................299

Table 10.18 PWM Output Registers and Output Pins.................................................................302

Table 10.19 Phase Counting Mode Clock Input Pins.................................................................. 306

Table 10.20 Up/Down-Count Conditions in Phase Counting Mode 1 ........................................307

Table 10.21 Up/Down-Count Conditions in Phase Counting Mode 2 ........................................308

Table 10.22 Up/Down-Count Conditions in Phase Counting Mode 3 ........................................309

Table 10.23 Up/Down-Count Conditions in Phase Counting Mode 4 ........................................310

Table 10.24 TPU Interrupts......................................................................................................... 311

Rev. 2.0, 10/02, page lvi of lviii

Page 57

Section 11 8-Bit Timers (TMR)

Table 11.1 Pin Configuration...................................................................................................... 329

Table 11.2 Clock Input to TCNT and Count Condition .............................................................. 332

Table 11.3 8-Bit Timer Interrupt Sources ................................................................................... 340

Table 11.4 Timer Output Priorities ............................................................................................. 344

Table 11.5 Switching of Internal Clock and TCNT Operation ................................................... 345

Section 12 Watchdog Timer

Table 12.1 WDT Interrupt Source .............................................................................................. 354

Section 13 Serial Communication Interface

Table 13.1 Pin Configuration...................................................................................................... 361

Table 13.2 Relationships between The N Setting in BRR and Bit Rate B.................................. 375

Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ............................... 376

Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ............................... 377

Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ............................... 378

Table 13.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)............................... 378

Table 13.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)..................... 379

Table 13.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ......................... 380

Table 13.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)......... 380

Table 13.8 Serial Transfer Formats (Asynchronous Mode) ........................................................ 382

Table 13.9 SSR Status Flags and Receive Data Handling .......................................................... 389

Table 13.10 SCI Interrupt Sources................................................................................................ 409

Section 14 Boundary Scan Function

Table 14.1 Pin Configuration...................................................................................................... 419

Table 14.2 Instruction configuration........................................................................................... 420

Table 14.3 IDCODE Register Configuration.............................................................................. 422

Table 14.4 Correspondence between LSI Pins and Boundary Scan Register ............................. 424

Section 15 Universal Serial Bus Interface (USB)

Table 15.1 Pin Configuration...................................................................................................... 436

Table 15.2 EPINFO Data Settings .............................................................................................. 443

Table 15.3 Relationship between the UTSTR0 Setting and Pin Outputs.................................... 478

Table 15.4 Relationship between the UTSTR1 Settings and Pin Inputs ..................................... 480

Table 15.5 SCI Interrupt Sources................................................................................................ 482

Table 15.6 Command Decoding on Firmware ............................................................................ 508

Table 15.7 Register Name Modification List.............................................................................. 517

Table 15.8 Bit Name Modification List ...................................................................................... 518

Table 15.9 EPINFO Data Settings .............................................................................................. 519

Section 16 A/D Converter

Table 16.1 Pin Configuration...................................................................................................... 535

Table 16.2 Analog Input Channels and Corresponding ADDR Registers .................................. 536

Table 16.3 A/D Conversion Time (Single Mode) ....................................................................... 543

Table 16.4 A/D Conversion Time (Scan Mode) ......................................................................... 543

Rev. 2.0, 10/02, page lvii of lviii

Page 58

Table 16.5 A/D Converter Interrupt Source ................................................................................ 544

Table 16.6 Analog Pin Specifications ......................................................................................... 549

Section 17 D/A Converter

Table 17.1 Pin Configuration ......................................................................................................552

Section 19 Flash Memory (F-ZTAT Version)

Table 19.1 Differences between Boot Mode and User Program Mode.......................................560

Table 19.2 Pin Configuration ......................................................................................................564

Table 19.3 Setting On-Board Programming Modes.................................................................... 571

Table 19.4 SCI Boot Mode Operation.........................................................................................574

Table 19.5 System Clock Frequencies for which Automatic Adjustment of

LSI Bit Rate is Possible......................................................................................... 574

Table 19.6 Enumeration Information .......................................................................................... 575

Table 19.7 USB Boot Mode Operation.......................................................................................578

Table 19.8 Flash Memory Operating States ................................................................................589

Table 19.9 Registers Present in F-ZTAT Version but Absent in Masked ROM Version............ 591

Section 21 Clock Pulse Generator

Table 21.1 Damping Resistance Value........................................................................................ 599

Table 21.2 Crystal Resonator Characteristics.............................................................................. 599

Table 21.3 External Clock Input Conditions ...............................................................................600

Table 21.4 External Clock Input Conditions when Duty Adjustment Circuit is not Used .......... 601

Table 21.5 External Clock Input Conditions when Duty Adjustment Circuit is not Used .......... 603

Section 22 Power-Down Modes

Table 22.1 LSI Internal States in Each Mode..............................................................................608

Table 22.2 Low Power Dissipation Mode Transition Conditions ...............................................609

Table 22.3 Oscillation Stabilization Time Settings ..................................................................... 617

Table 22.4 ø Pin State in Each Processing State .........................................................................621

Section 24 Electrical Characteristics

Table 24.1 Absolute Maximum Ratings ....................................................................................649

Table 24.2 DC Characteristics................................................................................................... 651

Table 24.3 Permissible Output Currents.................................................................................... 654

Table 24.4 Clock Timing...........................................................................................................655

Table 24.5 Control Signal Timing .............................................................................................656

Table 24.6 Bus Timing .............................................................................................................. 658

Table 24.7 Timing of On-Chip Supporting Modules.................................................................664

Table 24.8 USB Characteristics (USD+ and USD- pins) when On-Chip USB Transceiver

is Used................................................................................................................... 670

Table 24.9 A/D Conversion Characteristics .............................................................................. 671

Table 24.10 D/A Conversion Characteristics .............................................................................. 672

Table 24.11 Flash Memory Characteristics .................................................................................672

Rev. 2.0, 10/02, page lviii of lviii

Page 59

Section 1 Overview

1.1 Overview

• High-speed H8S/2000 central processing unit with 16-bit architecture  Upwar d -compatible with H8/300 and H8/300H CPUs on an object level  Sixteen 16-bit general registers  65 basic instructions

• Various peripheral functions  DMA controller (DMAC)  Data tran sf er controller (DTC)  16-bit timer-pulse unit (TPU)  8- bit timer (TMR)  Watchdog timer (WDT)  Asynchronous or clocked synchronous serial communication interface (SCI)  Boundary scan  Univ ersal serial bus (USB)  10 - bit A/D converter  8-bit D/A converter  Clock pulse generator

• On-chip memory

ROM Product Code ROM RAM Remarks

F-ZTAT Version

Masked ROM Version

• General I/O ports Modes 4 and 5 Mode 6 Mode 7  I/O pins: 41 41 68  Input-only pins: 15 23 7

• Supports various power-down states

• Compact package

Package (Code) Body Size Pin Pitch Remarks

TQFP-120 TFP-120 14.0 × 14.0 mm 0.4 mm  P-LFBGA-112 BP-112 10.0 × 10.0 mm 0.8 mm 

Rev. 3.0, 10/02, page 1 of 686

Page 60

1.2 Internal Block Diagram

VCC

VSS

DrVCC

DrVSS

TDO

TDI

TCK

TMS

PD7/D15

PD6/D14

PD5/D13

PD4/D12

PD3/D11

PD2/D10

PE7/D7

PE6/D6

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

PD1/D9

PD0/D8

PE0/D0

MD2 MD1 MD0 EXTAL XTAL PLLVCC PLLCAP PLLVSS EXTAL48 XTAL48

NMI FWE* USPND USD+ USD-

VBUS

PF7/ PF6/ PF5/ PF4/ PF3/ / / PF2/ PF1/ PF0/ /

PG4/ PG3/ PG2/ PG1/ / PG0

Port FPort G

PLL for

USB

Boundary

scan

System

generator

clock pulse

USB

generator

clock pulse

Interrupts controller

USB

ROM

RAM

TPU (3 channels)

Port D

H8S/2000 CPU

Port E

Internal address bus

Internal data bus

DMAC

DTC

WDT

TMR (2 channels)

SCI0 (1 channnel, high speed UART)

SCI1, 2 (2 channels)

A/D converter (6 channels)

D/A converter (1 channel)

Bus controller

Peripheral data bus

Peripheral address bus

PA3/A19/SCK2/SUSPND PA2/A18/RxD2 PA1/A17/TxD2

Port APort B

PA0/A16 PB7/A15

PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8

PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3

Port CPort 3

PC2/A2 PC1/A1 PC0/A0

P36 P35/SCK1/ P34/RxD1 P33/TxD1 P32/SCK0/ P31/RxD0 P30/TxD0

AVCC Vref AVSS

Port 1 Port 7

P10/TIOCA0/A20/VM

P11/TIOCB0/A21/VP

P12/TIOCC0/TCLKA/A22/RCV

P13/TIOCD0/TCLKB/A23/VPO

Note: * The FWE pin is only provided in the flash memory version.

Figure 1.1 Internal Block Diagram

Rev. 3.0, 10/02, page 2 of 686

P14/TIOCA1/

P15/TIOCB1/TCLKC/FSE0

P16/TIOCA2/

P17/TIOCB2/TCLKD/

P70/TMRI01/TMCI01/

P71/

P72/TMO0/

P73/TMO1/

P74/

Port 4

P41/AN1

P42/AN2

P43/AN3

P40/AN0

Port 9

P96/AN14/DA0

P97/AN15/DA1

Page 61

1.3 Pin Arrangement

P31/RxD0

P30/TxD0

PF0//PF1/

P32/CSK0/

PF2/

RESERVE

/ /

PF3/

RESERVE

PF4/

PF5/

PF6/

PF7/φ

MD2

EXTAL

VCC

XTAL

VSS

NMI

FWE*

MD1

MD0

EXTAL48

XTAL48

PLLVCC

PLLCAP

PLLVSS

VSS

P33/TxD1

P34/RxD1

P35/SCK1/

RESERVE

P74/ P73/TMO1/ P72/TMO0/

P71/

P70/TMRI01/TMCI01/

PG1/

PG2/ PG3/ PG4/

PE0/D0

RESERVE

PE1/D1

RESERVE

PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 PE7/D7

P36

PG0

TDO

TCK

TMS

TDI

9089888786858483828180797877767574737271706968676665646362

91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120

1234567891011121314151617181920212223242526272829

TFP-120

(Pin Arrangement)

DrVSS

USD-

USD+

DrVCC 56 55

VBUS 54

RESERVE 53

USPND 52

RESERVE 51

AVCC 50

Vref 49

P40/AN0 48

P41/AN1 47

P42/AN2 46

P43/AN3 45

P96/AN14/DA0 44

P97/AN15/DA1 43

AVSS 42

P17/TIOCB2/TCLKD/ 41

P16/TIOCA2/ 40

P15/TIOCB1/TCLKC/FSE0 39

P14/TIOCA1/ 38

P13/TIOCD0/TCLKB/A23/VPO 37

P12/TIOCC0/TCLKA/A22/RCV 36

P11/TIOCB0/A21/VP 35

P10/TIOCA0/A20/VM 34

RESERVE 33

PA3/A19/SCK2/SUSPND 32

PA2/A18/RxD2 31

PA1/A17/TxD2

VSS

PD0/D8

RESERVE

PD1/D9

PD2/D10

PD3/D11

PD4/D12

PD5/D13

PD6/D14

VCC

PC0/A0

PD7/D15

PC1/A1

PC2/A2

PC3/A3

PC4/A4

PC5/A5

PC6/A6

PB0/A8

PB1/A9

PC7/A7

PB2/A10

RESERVE

Note: * The FWE pin is only provided in the flash memory version.

Figure 1.2 Pin Arrangement (TFP-120)

PB5/A13

PB6/A14

PB7/A15

PA0/A16

PB3/A11

PB4/A12

Rev. 3.0, 10/02, page 3 of 686

Page 62

23456789 1110

(Reserve)

PD1/D9

PD4/D12

PD7/D15

VSS

PC3/A3

PE6/D6

PD0/D8

PD3/D11

PD6/D14

PC1/A1

PC4/A4

PE3/D3

PE5/D5

PE7/D7

PD5/D13

PC0/A0

PC2/A2

PE0/D0

PE2/D2

PE4/D4

PD2/D10

VCC

PC5/A5

TMS

TDI

PE1/D1

PG4/

TDO

PG3/

TCK

BP-112

PG1/

PG2/

PG0

P70/ TMRI01/ TMCI01/

P71/

P72/

TMO0/

P73/

TMO1/

P35/

SCK1/

PF3/

MD2

(Top view)

PC6/A6

PB1/A9

PB4/A12

PB7/A15

(Reserve)

Note: * The FWE pin is only provided in the flash memory version.

PC7/A7

PB3/A11

PB6/A14

PA1/

A17/TxD2

PA2/

A18/RxD2

PB0/A8

PB5/A13

PA0/A16

P10/

TIOCA0/

A20/VM

P11/

TIOCB0/

A21/VP

PB2/A10

PA3/ A19/

SCK2/

SUSPND

P12/

TIOCC0/

TCLKA/

A22/RCV

P13/

TIOCD0/

TCLKB/

A23/VPO

P14/

TIOCA1/

P15/

TIOCB1/

TCLKC/

FSE0

P16/TIO

CA2/

AVSS

P17/

TIOCB2/

TCLKD/

P42/AN2

P97/

AN15/DA1

P43/AN3

P96/

AN14/

DA0

USPND

Vref

P40/AN0

P41/AN1

NMI

PLLVCC

DrVCC

VBUS

AVCC

P74/

P36

P32/

SCK0/

PF0/

PF5/

XTAL

MD0

DrVSS

USD+

P34/RxD1

P33/TxD1

P30/TxD0

PF2/

PF6/

EXTAL

XTAL48

PLLVSS

VSS

MD1

USD-

(Reserve)

P31/RxD0

PF1/

PF4/

PF7/

VCC

FWE*

EXTAL48

PLLCAP

(Reserve)

Figure 1.3 Pin Arrangement (BP-112)

Rev. 3.0, 10/02, page 4 of 686

Page 63

1.4 Pin Functions in Each Operating Mode

Pin No. Pin Name TFP-120 BP-112 Mode 4 Mode 5 Mode 6 Mode 7

1 — Reserved Reserved Reserved Reserved NC 2B2D8D8D8PD0D0 3B1D9D9D9PD1D1 4 D4 D10 D10 D10 PD2 D2 5 C2 D11 D11 D11 PD3 D3 6 C1 D12 D12 D12 PD4 D4 7 D3 D13 D13 D13 PD5 D5 8 D2 D14 D14 D14 PD6 D6 9 D1 D15 D15 D15 PD7 D7 10 E4 VCC VCC VCC VCC VCC 11 E3 A0 A0 PC1/A0 PC0 A0 12 E1 VSS VSS VSS VSS VSS 13 E2 A1 A1 PC1/A1 PC1 A1 14 F3 A2 A2 PC2/A2 PC2 A2

PROM Mode

15 F1 A3 A3 PC3/A3 PC3 A3 16 F2 A4 A4 PC4/A4 PC4 A4 17 F4 A5 A5 PC5/A5 PC5 A5 18 G1 A6 A6 PC6/A6 PC6 A6 19 G2 A7 A7 PC7/A7 PC7 A7 20 G3 PB0/A8 PB0/A8 PB0/A8 PB0 A8 21 H1 PB1/A9 PB1/A9 PB1/A9 PB1 A9 22 — RESERVE RESERVE RESERVE RESERVE NC 23 G4 PB2/A10 PB2/A10 PB2/A10 PB2 A10 24 — RESERVE RESERVE RESERVE RESERVE NC 25 H2 PB3/A11 PB3/A11 PB3/A11 PB3 A11 26 J1 PB4/A12 PB4/A12 PB4/A12 PB4 A12 27 H3 PB5/A13 PB5/A13 PB5/A13 PB5 A13 28 J2 PB6/A14 PB6/A14 PB6/A14 PB6 A14 29 K1 PB7/A15 PB7/A15 PB7/A15 PB7 A15 30 J3 PA0/A16 PA0/A16 PA0/A16 PA0 A16 31 K2 PA1/A17/TxD2 PA1/A17/TxD2 PA1/A17/TxD2 PA1/TxD2 A17

Note : * The USB cannot be used in mode 7.

Rev. 3.0, 10/02, page 5 of 686

Page 64

Pin No. Pin Name TFP-120 BP-112 Mode 4 Mode 5 Mode 6 Mode 7

PROM Mode

32 L2 PA2/A18/RxD2 PA2/A18/RxD2 PA2/A18/RxD2 PA2/RxD2 A18 33 H4 PA3/A19/SCK2/

SUSPND

PA3/A19/SCK2/ SUSPND

PA3 /SCK2 NC

34 — RESERVE RESERVE RESERVE RESERVE NC 35 K3 P10/TIOCA0/

A20/VM

36 L3 P11/TIOCB0/

A21/VP

37 J4 P12/TIOCC0/

TCLKA/A22/ RCV

38 K4 P13/TIOCD0/

TCLKB/A23/ VPO

39 L4 P14/TIOCA1/

IRQ0

P10/TIOCA0/ A20/VM

P11/TIOCB0/ A21/VP

P12/TIOCC0/ TCLKA/A22/ RCV

P13/TIOCD0/ TCLKB/A23/ VPO

P14/TIOCA1/

IRQ0

P10/TIOCA0/ A20/VM

P11/TIOCB0/ A21/VP

P12/TIOCC0/ TCLKA/A22/ RCV

P13/TIOCD0/ TCLKB/A23/ VPO

P14/TIOCA1/

IRQ0

P10/TIOCA0 NC

P11/TIOCB0 NC

P12/TIOCC0/

TCLKA

P13/TIOCD0/

TCLKB

P14/TIOCA1/

VSS

IRQ0

40 H5 P15/TIOCB1/

TCLKC/FSE0

41 J5 P16/TIOCA2/

IRQ1

42 L5 P17/TIOCB2/

TCLKD/OE

P15/TIOCB1/ TCLKC/FSE0

P16/TIOCA2/

IRQ1

P17/TIOCB2/ TCLKD/OE

P15/TIOCB1/ TCLKC/FSE0

P16/TIOCA2/

IRQ1

P17/TIOCB2/ TCLKD/OE

P15/TIOCB1/ TCLKC

P16/TIOCA2/

IRQ1

P17/TIOCB2/ TCLKD/OE

VSS

43 K5 AVSS AVSS AVSS AVSS VSS 44 J6 P97/AN15/DA1 P97/AN15/DA1 P97/AN15/DA1 P97/AN15/DA1 NC 45 L6 P96/AN14/DA0 P96/AN14/DA0 P96/AN14/DA0 P96/AN14/DA0 NC 46 K6 P43/AN3 P43/AN3 P43/AN3 P43/AN3 NC 47 H6 P42/AN2 P42/AN2 P42/AN2 P42/AN2 NC 48 L7 P41/AN1 P41/AN1 P41/AN1 P41/AN1 NC 49 K7 P40/AN0 P40/AN0 P40/AN0 P40/AN0 NC 50 J7 Vref Vref Vref Vref VCC 51 L8 AVCC AVCC AVCC AVCC VCC 52 — RESERVE RESERVE RESERVE RESERVE NC 53 H7 USPND USPND USPND — NC 54 — RESERVE RESERVE RESERVE RESERVE NC 55 K8 VBUS VBUS VBUS VSS VSS 56 L9 UBPM UBPM UBPM VSS VSS

Note : * The USB cannot be used in mode 7.

Rev. 3.0, 10/02, page 6 of 686

Page 65

Pin No. Pin Name TFP-120 BP-112 Mode 4 Mode 5 Mode 6 Mode 7

PROM Mode

57 J8 DrVCC DrVCC DrVCC VSS VCC 58 K9 USD+ USD+ USD+ — NC 59 L10 USD- USD- USD- — NC 60 J9 DrVSS DrVSS DrVSS — VSS 61 — VSS VSS VSS VSS VSS 62 K10 PLLVSS PLLVSS PLLVSS — VSS 63 K11 PLLCAP PLLCAP PLLCAP NC NC 64 H8 PLLVCC PLLVCC PLLVCC — VCC 65 J10 XTAL48 XTAL48 XTAL48 — NC 66 J11 EXTAL48 EXTAL48 EXTAL48 — VCC 67 H9 MD0 MD0 MD0 MD0 VSS 68 H10 MD1 MD1 MD1 MD1 VSS 69 H11 FWE FWE FWE FWE FWE 70 G8 NMI NMI NMI NMI VCC 71 G9 STBY STBY STBY STBY VCC 72 G11 RES RES RES RES RES 73 G10 VSS VSS VSS VSS VSS 74 F9 XTAL XTAL XTAL XTAL XTAL 75 F11 VCC VCC VCC VCC VCC 76 F10 EXTAL EXTAL EXTAL EXTAL EXTAL 77 F8 MD2 MD2 MD2 MD2 VSS 78 E11 PF7/φ PF7/φ PF7/φ PF7/φ NC 79 E10 AS AS AS PF6 NC 80 E9 RD RD RD PF5 NC 81 D11 HWR HWR HWR PF4 NC 82 — RESERVE RESERVE RESERVE RESERVE NC 83 E8 PF3/LWR/

ADTRG/IRQ3

PF3/LWR/ ADTRG/IRQ3

PF3/ADTRG/

IRQ3

VCC

84 — RESERVE RESERVE RESERVE RESERVE NC 85 D10 PF2/WAIT PF2/WAIT PF2/WAIT PF2 NC 86 C11 PF1/BACK PF1/BACK PF1/BACK PF1 NC 87 D9 PF0/BREQ/

IRQ2

Note : * The USB cannot be used in mode 7.

PF0/BREQ/ IRQ2

PF0/IRQ2 VCC

Rev. 3.0, 10/02, page 7 of 686

Page 66

Pin No. Pin Name TFP-120 BP-112 Mode 4 Mode 5 Mode 6 Mode 7

PROM Mode

88 C10 P30/TxD0 P30/TxD0 P30/TxD0 P30/TxD0 NC 89 B11 P31/RxD0 P31/RxD0 P31/RxD0 P31/RxD0 NC 90 C9 P32/SCK0/IRQ4 P32/SCK0/IRQ4 P32/SCK0/IRQ4 P32/SCK0/IRQ4 NC 91 B10 P33/TxD1 P33/TxD1 P33/TxD1 P33/TxD1 NC 92 A10 P34/RxD1 P34/RxD1 P34/RxD1 P34/RxD1 NC 93 D8 P35/SCK1/IRQ5 P35/SCK1/IRQ5 P35/SCK1/IRQ5 P35/SCK1/IRQ5 NC 94 B9 P36 P36 P36 P36 NC 95 — RESERVE RESERVE RESERVE RESERVE NC 96 A9 P74/MRES P74/MRES P74/MRES P74/MRES NC 97 C8 P73/TMO1/CS7 P73/TMO1/CS7 P73/TMO1/CS7 P73/TMO1 NC 98 B8 P72/TMO0/CS6 P72/TMO0/CS6 P72/TMO0/CS6 P72/TMO0 NC 99 A8 P71/CS5 P71/CS5 P71/CS5 P71 NC 100 D7 P70/TMRI01/

TMCI01/CS4

P70/TMRI01/ TMCI01/CS4

P70/TMRI01/ TMCI01

101 C7 PG0 PG0 PG0 PG0 NC 102 A7 PG1/CS3/IRQ7 PG1/CS3/IRQ7 PG1/CS3/IRQ7 PG1/IRQ7 NC 103 B7 PG2/CS2 PG2/CS2 PG2/CS2 PG2 NC 104 C6 PG3/CS1 PG3/CS1 PG3/CS1 PG3 NC 105 A6 PG4/CS0 PG4/CS0 PG4/CS0 PG4 NC 106 B6 TDO TDO TDO TDO VCC 107 D6 TCK TCK TCK TCK VCC 108 A5 TMS TMS TMS TMS VCC 109 B5 TRST TRST TRST TRST RES 110 C5 TDI TDI TDI TDI VCC 111 A4 PE0/D0 PE0/D0 PE0/D0 PE0 NC 112 — RESERVE RESERVE RESERVE RESERVE NC 113 D5 PE1/D1 PE1/D1 PE1/D1 PE1 NC 114 — RESERVE RESERVE RESERVE RESERVE NC 115 B4 PE2/D2 PE2/D2 PE2/D2 PE2 NC 116 A3 PE3/D3 PE3/D3 PE3/D3 PE3 NC 117 C4 PE4/D4 PE4/D4 PE4/D4 PE4 VSS 118 B3 PE5/D5 PE5/D5 PE5D5 PE5 OE

Note : * The USB cannot be used in mode 7.

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Pin No. Pin Name TFP-120 BP-112 Mode 4 Mode 5 Mode 6 Mode 7

PROM Mode

119 A2 PE6/D6 PE6/D6 PE6/D6 PE6 WE 120 C3 PE7/D7 PE7/D7 PE7/D7 PE7 CE — A1, A11,

RESERVE RESERVE RESERVE RESERVE NC

L1, L11

Note : * The USB cannot be used in mode 7.

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Page 68

1.5 Pin Functions

Pin No.

Type Symbol TFP-120 BP-112 I/O Function

Power Supply

Clock

VCC 10 E4 Input

75 F11

VSS E1 Input

PLLVCC 64 H8 Input Power supply pin for internal PLL

PLLVSS 62 K10 Input Ground pin for an on-chip PLL

PLLCAP 63 K11 Output External capacitor pin for an on-chip

XTAL 74 F9 Input For connection to a crystal resonator.

EXTAL 76 F10 Input For connection to a crystal resonator.

12 61 73

G10

Power supply pins. Connect all these pins to the system power supply.

Ground pins. Connect all these pins to the system power supply (0 V).

oscillator. Connect this pin to the system power supply.

oscillator.

PLL oscillator.

For examples of crystal resonator connection and externa l clock inpu t, see section 21, Clock Pulse Generator.

(An external clock can be supplied from the EXTAL pin.) For examples of crystal resonator connection and external clock input, see section 21, Clock Pulse Generator.

Operating Mode Control

XTAL48 65 J10 Input EXTAL48 66 J11 Input

φ 78 E11 Output Supplies the system clock to external

MD2 MD1 MD0

77 68 67

F8 H10 H9

Input Set the operating mode. Inputs at

USB operating clock input pins. 48-MHz clock for USB

communications is inp ut. For examples of using an on-chip PLL, EXTAL48 must be fixed low and XTAL48 must be open.

devices.

these pins cannot be modified during operation.

Rev. 3.0, 10/02, page 10 of 686

Page 69

Pin No.

Type Symbol TFP-120 BP-112 I/O Function

System Control

Interrupts

RES 72 G11 Input Reset input pin. When this pin is

driven low, the chip is reset.

STBY 71 G9 Input When this pin is driven low, a

transition is made to hardware standby mode.

MRES 96 A9 Input When this pin is driven low, a

transition is made to manual reset mode.

BREQ 87 D9 Input Used by an external bus master to

issue a bus request to this LSI

BACK 86 C11 Output Indicates that the bus has been

released to an external bus master.

FWE 69 H11 Input Pin for use by flash memory. This pin

is only used in the flash memory version. In the mask ROM version it should be fixed at 0.

NMI 70 G8 Input Nonmaskable interrupt pin. If this pin

is not used, it should be fixed high.

IRQ7 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0

102 93 90 83 87 41 39

A7 D8 C9 E8 D9 J5 L4

Input These pins request a maskable

interrupt.

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Pin No.

Type Symbol TFP-120 BP-112 I/O Function

Address bus A23

A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9

38 37 36 35 33 32 31 30 29 28 27 26 25 23 21

K4 J4 L3 K3 H4 L2 K2 J3 K1 J2 H3 J1 H2 G4 H1

Output These pins output an address.

A8 A7 A6 A5 A4 A3 A2 A1 A0

20 19 18 17 16 15 14 13 11

G3 G2 G1 F4 F2 F1 F3 E2 E3

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Pin No.

Type Symbol TFP-120 BP-112 I/O Function

Data bus D15

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

9 8 7 6 5 4 3 2 120 119 118 117 116 115 113 111

D1 D2 D3 C1 C2 D4 B1 B2 C3 A2 B3 C4 A3 B4 D5 A4

I/O These pins consti tute a bi-dir ectional

data bus.

Bus Control CS7

CS6 CS5 CS4 CS3 CS2 CS1 CS0

AS 79 E10 Output When this pin is low, it indicates that

RD 80 E9 Output When this pin is low, it indicates that

HWR 81 D11 Output A strobe signal that writes to external

97 98 99 100 102 103 104 105

C8 B8 A8 D7 A7 B7 C6 A6

Output Signals for selecting areas 7 to 0.

address output on the address bus is enabled.

the external address space can be read.

space and indicates that the upper half (D15 to D8) of the data bus is enabled.

LWR 83 E8 Output A strobe signal that writes to external

WAIT 85 D10 Input Requests insertion of a wait state in

space and indicates that the lower half (D7 to D0) of the data bu s is enabled.

the bus cycle when accessing external 3-state address space.

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Pin No.

Type Symbol TFP-120 BP-112 I/O Function

16-bit timer pulse unit (TPU)

8-bit timer (TMR)

TCLKA TCLKB TCLKC TCLKD TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1

TIOCA2 TIOCB2

TMO1 TMO0

37 38 40 42 35 36 37 38 39 40

41 42

97 98

J4 K4 H5 L5 K3 L3 J4 K4 L4 H5

J5 L5

C8 B8

Input TPU external clock input pins.

I/O The TGRA_0 to TGRD_0 input

capture input/output compare output/PWM output pins.

I/O The TGRA_1 to TGRB_1 input

capture input/output compare output/PWM output pins.

I/O The TGRA_2 to TGRB_2 input

capture input/output compare output/PWM output pins.

Output Compare match output pins.

Serial Communication interface (SCI)

A/D converter

TMCI01 100 D7 Input Input pins for the external clock input

to the counter. TMRI01 100 D7 Input The counter reset input pins. TxD2 TxD1 TxD0 RxD2 RxD1 RxD0 SCK2 SCK1 SCK0 AN15

AN14 AN3

31 91 88 32 92 89 33 93 90 44

45 46

K2 B10 C10 L2 A10 B11 H4 D8 C9 J6

L6 K6

Output Data output pins

Input Data input pins

I/O Clock input/output pins

Input Analog input pins for the A/D

converter.

AN2 AN1 AN0

47 48 49

ADTRG 83 E8 Input Pin for input of an external trigger to

Rev. 3.0, 10/02, page 14 of 686

H6 L7 K7

start A/D conversion

Page 73

Pin No.

Type Symbol TFP-120 BP-112 I/O Function

D/A converter DA1

DA0

A/D converter

AVCC 51 L8 Input Power supply pin for the A/D and D/A

D/A converter

AVSS 43 K5 Input The ground pin for the A/D and D/A

Vref 50 J7 Input The reference voltage input pin for

Boundary

TMS 108 A5 Input Control signal input pin for the

scan

TCK 107 D6 Input Clock input pin for the boundary scan TD0 106 B6 Output Data output pin for the boundary scan

44 45

J6 L6

Output Analog output pins for the D/A

converter.

converter. When the D/A converter is not used, connect this pin to the system power supply(VCC).

converter. Connect this pin to the system power supply (0 V).

the A/D and D/A converter. When the A/D and D/A converter is not used, this pin should be connected to the system power supply (VCC).

boundary scan

TDI 110 C5 Input Data input pin for the boundary scan TRST 109 B5 Input Reset pin for the TAP controller USD+ 58 K9 I/O USB data input/output pinUSB USD- 59 L10 VBUS 55 K8 Input Connection/di sconnection detecting

Input/output pin for the USB cable

USPND 53 H7 Output USB suspend output

This pin is driven high when a

transition is made to suspend state. VM VP

35 36

K3 L3

Input

Pins to be connected to the

transceiver (PDIUSBP11A)

manufactured by Philips Electronics. RCV

VPO FSE0

SUSPND

37 38 40 42 33

J4 K4 H5 L5 H4

Output

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Pin No.

Type Symbol TFP-120 BP-112 I/O Function

USB UBPM 56 L9 Input Bus power/self power mode setting

Input. When the USB is used in bus power

mode, this input pin must be fixed low.

When the USB is used in self power mode, this input pin must be fixed high.

DrVCC 57 J8  Power supply for the on-chip

transceiver. Connect this pin to the system power supply.

DrVSS 60 J9  Ground pin for the on-chip

transceiver.

I/O port P17

P16 P15 P14 P13 P12 P11 P10 P36 P35 P34 P33 P32 P31 P30 P43

42 41 40 39 38 37 36 35 94 93 92 91 90 89 88 46

L5 J5 H5 L4 K4 J4 L3 K3 B9 D8 A10 B10 C9 B11 C10 K6

I/O 8-bit I/O pins

I/O 7-bit I/O pins

Input 4-bit input pins P42 P41 P40

P74 P73 P72 P71 P70

47 48 49

96 97 98 99 100

Rev. 3.0, 10/02, page 16 of 686

H6 L7 K7

A9 C8 B8 A8 D7

I/O 5-bit I/O pins

Page 75

Pin No.

Type Symbol TFP-120 BP-112 I/O Function

I/O port P97

P96 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7

44 45 33 32 31 30 29 28 27 26 25 23 21 20 19

J6 L6 H4 L2 K2 J3 K1 J2 H3 J1 H2 G4 H1 G3 G2

Input 2-bit input pins

I/O 4-bit I/O pins

I/O 8-bit I/O pins

I/O 8-bit I/O pins PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

18 17 16 15 14 13 11 9 8 7 6 5 4 3 2

G1 F4 F2 F1 F3 E2 E3 D1 D2 D3 C1 C2 D4 B1 B2

I/O 8-bit I/O pins

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Pin No.

Type Symbol TFP-120 BP-112 I/O Function

I/O port PE7

PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF7 PF6 PF5 PF4 PF3 PF2 PF1

120 119 118 117 116 115 113 111 78 79 80 81 83 85 86

C3 A2 B3 C4 A3 B4 D5 A4 E11 E10 E9 D11 E8 D10 C11

I/O 8-bit I/O pins

PF0 PG4 PG3 PG2 PG1 PG0

Reserve RESERVE 1

87 105 104 103 102 101

22 24 34 52 54 82 84 95

D9 A6 C6 B7 A7 C7 A1 A11 L1 L11

I/O 5-bit I/O pins

 Reserved pins

These pins should be open and should not be connected to any device.

112 114

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Section 2 CPU

The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime con trol.

This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.

2.1 Features

• Upward-compatible with H8 /3 00 an d H8/300H CPUs  Can execute H8/300 and H8/300H CPU object programs

• General-register architecture  Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers

• Sixty-five basic instructions  8/1 6/32-bit arithmetic and logic instructions  Multip ly and divide instructions  Power ful bit-manipulation instructions

• Eight addressing modes  Register direct [Rn]  Register indirect [@ERn]  Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]  Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]  Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]  Immediate [#xx:8, #xx:16, or #xx:32]  Program-counter relative [@(d:8,PC) or @(d:16,PC)]  Memory indirect [@@aa:8]

• 16-Mbyte address space  Program: 16 Mbytes  Data: 16 Mbytes

• High-speed operation  All frequently-used instructions execute in one or two states  8/16/32-bit register-register add/subtract: 1 state  8 × 8-bit r e gister-register multiply: 12 states  16 ÷ 8-bit register-register divide: 12 states  16 × 16-bit register-register multiply: 20 states  32 ÷ 16-bit register-register divide: 20 states

CPUS211A_010020020100

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Page 78

• Two CPU operating modes  Normal mode*  Advanced mode

Note : * Normal mode is not available in this LSI.

• Power-down state  Transition to power-down state by SLEEP instruction  CPU clock speed selection

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU

The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.

• Register configuration The MAC register is supported only by the H8S/2600 CPU.

• Basic instru c tions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the

H8S/2600 CPU.

• The number of execution states of the MULXU and MULXS instructions

Execution States

Instruction Mnemonic H8S/2600 H8S/2000

MULXU MULXU.B Rs, Rd 3 12

MULXU.W Rs, ERd 4 20

MULXS MULXS.B Rs, Rd 4 13

MULXS.W Rs, ERd 5 21

In addition, there are differences in address space, CCR and EXR register fu nctions, power-down modes, etc., depending on the model.

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2.1.2 Differences from H8/300 CPU

In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.

• More general registers and control registers  Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been

added.

• Extended address space  Normal mode supports the same 64-kbyte address space as the H8/300 CPU.  Advanced mode supports a maximum 16-Mbyte address sp ace.

• Enhanced addressing  The addressing modes have been enhanced to make effective use of the 16-Mbyte address

space.

• Enhanced instructions  Addressing modes of bit-manipulation instructions have been enhanced.  Sign e d multiply and divide instructions have been added.  Two-bit shift instructions have been added.  In structions for saving and resto ring multiple registers have been ad ded.  A test and set instruction has been added.

• Higher speed  Basic instructions execute twice as fast.

2.1.3 Differences from H8/300H CPU

In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements.

• Additional control register  One 8-bit control registers have been added.

• Enhanced instructions  Addressing modes of bit-manipulation instructions have been enhanced.  Two-bit shift instructions have been added.  In structions for saving and resto ring multiple registers have been ad ded.  A test and set instruction has been added.

• Higher speed  Basic instructions execute twice as fast.

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2.2 CPU Operating Modes

The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins.

2.2.1 Normal Mode

The exception vector table and stack have the same structure as in the H8/300 CPU.

• Address Space

A maximum address space of 64 kbytes can be accessed.

• Extended Registers (En)

The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@–Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected.

• Instruction Set

All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid.

• Exception Vector Table and Memory Indirect Branch Addresses

In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The exception vector table in normal mode is shown in figure 2.1. For details of the exception vector table, see section 4, Exception Handling.

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit (word) operand, providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table.

• Stack Structure

When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling.

Note: Normal mode is not available in this LSI.

Rev. 3.0, 10/02, page 22 of 686

Page 81

H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B

Reset exception vector

(Reserved for system use)

Exception vector table

Exception vector 1

Exception vector 2

Figure 2.1 Exception Vector Ta ble (Normal Mode)

(a) Subroutine Branch (b) Exception Handling

Notes: *1

When EXR is not used, it is not stored on the stack. SP when EXR is not used.

Ignored when returning.

Figure 2.2 Stack Structure in Normal Mode

2.2.2 Advanced Mode

• Address Space

(16 bits)

( )

EXR* Reserved*1* CCR

CCR*

(16 bits)

Linear access is provided to a 16-Mbyte maximum address space.

• Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit

segments of 32-bit registers or address registers.

• Instruction Set All instructions and addressing modes can be used.

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Page 82

• Exception Vector Table and Memory Indirect Branch Addresses

In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.3). For details of the exception vector table, see section 4, Exception Handling.

H'00000000

H'00000003 H'00000004

H'00000007 H'00000008

H'0000000B H'0000000C

H'00000010

Reserved

Reset exception vector

Reserved

(Reserved for system use)

Exception vector table

(Reserved for system use)

Reserved

Exception vector 1

Figure 2.3 Exception Vector Table (Advanced Mode)

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the ex ception vector table.

• Stack Structure

In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling.

Rev. 3.0, 10/02, page 24 of 686

Page 83

Reserved

(24 bits)

(a) Subroutine Branch (b) Exception Handling

(SP )

EXR* Reserved*1* CCR

(24 bits)

Notes: *1

*2 *3

When EXR is not used, it is not stored on the stack. SP when EXR is not used. Ignored when returning.

Figure 2.4 Stack Structure in Advanced Mode

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Page 84

2.3 Address Space

Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.

H'0000

H'FFFF

H'00000000

64 kbytes 16 Mbytes

H'00FFFFFF

H'FFFFFFFF

(b) Advanced Mode(a) Normal Mode *

Note : * Not available in this LSI.

Program area

Data area

Figure 2.5 Memory Map

Rev. 3.0, 10/02, page 26 of 686

Page 85

2.4 Register Configuration

The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and contro l registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR).

General Registers (Rn) and Extended Registers (En)

15 0 7 0 7 0 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP)

Control Registers (CR)

E0 E1 E2 E3 E4 E5 E6 E7

23 0

R0H R1H R2H R3H R4H R5H R6H R7H

R0L R1L R2L R3L R4L R5L R6L R7L

Legend

SP PC EXR T I2 to I0 CCR I UI

:Stack pointer :Program counter :Extended control register :Trace bit :Interrupt mask bits :Condition-code register :Interrupt mask bit :User bit or interrupt mask bit

Note: * Cannot be used as an interrupt mask bit in this LSI.

Figure 2.6 CPU Registers

H U N Z V C

76543210 T I2I1I0

EXR

----

76543210

CCR

IUIHUNZVC

:Half-carry flag :User bit :Negative flag :Zero flag :Overflow flag :Carry flag

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Page 86

2.4.1 General Registers

The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illu strates th e usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letter s ER ( E R0 to ER7).

The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers.

The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers.

The usage of each register can be selected independently.

General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subrou tine calls. Figure 2.8 shows the stack.

• Address registers

• 32-bit registers

ER registers

(ER0 to ER7)

• 16-bit registers • 8-bit registers

E registers (extended registers)

(E0 to E7)

RH registers

(R0H to R7H)

R registers

(R0 to R7)

RL registers

(R0L to R7L)

Figure 2.7 Usage of General Registers

Rev. 3.0, 10/02, page 28 of 686

Page 87

Free area

SP (ER7)

Stack area

Figure 2.8 Stack

2.4.2 Program Counter (PC)

This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is two bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.)

2.4.3 Extended Control Register (EXR)

EXR is an 8-bit register that ma nipulates the LDC, STC, ANDC, ORC, and XORC instru ctions. When these instructions except for the STC instruction is executed, all interrupts including NMI will be masked for three states after execution is completed.

Bit Bit Name Initial Value R/W Description

7 T 0 R/W Trace Bit

When this bit is set to 1, a trace exception is generated each time an instruct ion is execu ted. Whe n this bit is cleared to 0, instructions are execut ed in sequence.

6 to3– 1 – Reserved

These bits are always read as 1.

2 to 0 I2

1 R/W These bits designate the interrupt mask level (0 to 7).

For details, refer to section 5, Interrupt Controller.

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Page 88

2.4.4 Condition-Code Register (CCR)

This 8-bit register contains intern al CPU status information, including an in ter rup t mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.

Operation s can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.

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Bit Bit Name Initial Value R/W Description

7 I 1 R/W Interrupt Mask Bit

Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 by hardware at the start of an exception-handling sequence. For details, refer to section 5, Interrupt Controller.

6 UI undefined R/W User Bit or Interrupt Mask Bit

Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit c a nnot be used as an interrupt mask bit in this LSI.

5 H undefined R/W Half-Carry Flag

When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise.

4 U undefined R/W User Bit

Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions.

3 N undefined R/W Negative Flag

Stores the value of the most significant bit of data as a sign bit.

2 Z undefined R/W Zero Flag

Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.

1 V undefined R/W Overflow Flag

Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times.

0 C undefined R/W Carry Flag

Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:

• Add instructions, to indi cate a carry

Subtract instructions, to indicate a carry

•

Shift and rotate instructions, to indicate a carry

•

They carry flag is also used as a bit accumulator by bit manipulation instructions.

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2.4.5 Initial Register Values

Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the in ter rupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not in itialized.

The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset.

2.5 Data Formats

The H8S/2000 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.

2.5.1 General Register Data Formats

Figure 2.9 shows the data formats in general registers.

Data Type Register Number Data Image

1-bit data

4-bit BCD data

Byte data

RnH

RnL

RnH

RnL

RnH

65432710

7043

Upper Lower

MSB LSB

Don't care

65432710

Don't care

7043

Upper Lower

Don't care

Byte data

RnL

Figure 2.9 General Register Data Formats (1)

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Don't care

MSB LSB

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Data Type Data ImageRegister Number

Word data

15 0

MSB LSB

Longword data

31 16

MSB

Legend

: General register ER

ERn

: General register E

: General register R

: General register RH

RnH

: General register RL

RnL

: Most significant bit

MSB

: Least significant bit

LSB

15 0

MSB LSB

ERn

15 0

En Rn

LSB

Figure 2.9 General Register Data Formats (2)

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2.5.2 Memory Data Formats

Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory , but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instructio n fetches.

When SP (ER7) is used as an address register to access the stack, the operand size should be word size or longword size.

Data Type Address

1-bit data

Byte data

Word data

Longword data Address 2N

Address L

Address 2M Address 2M+1

Address 2N+1 Address 2N+2 Address 2N+3

Data Image

70 76 543210

MSB

LSB

Figure 2.10 Memory Data Formats

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2.6 Instruction Set

The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1.

Table 2.1 Instruction Classification

Function Instructions Size Types

Data transfer

MOV B/W/L 5 POP*1, PUSH*

W/L

LDM, STM L

Arithmetic operations

MOVFPE*

, MOVTPE* ADD, SUB, CMP, NEG B/W/L 19 ADDX, SUBX, DAA, DAS B

INC, DEC B/W/L ADDS, SUBS L MULXU, DIVXU, MULXS, DIVXS B/W EXTU, EXTS W/L

TAS*

B Logic operations AND, OR, XOR, NOT B/W/L 4 Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,

B/W/L 8

ROTXR

Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,

B14

BIAND, BOR, BIOR, BXOR, BIXOR Branch BCC*2, JMP, BSR, JSR, RTS – 5 System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,

–9

NOP Block data transfer EEPMOV – 1

Total: 65

Notes: B:byte size; W:word size; L:longword size.

*1 POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-

SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP.

*2 Bcc is the general name for conditional branch instructions. *3 Cannot be used in this LSI. *4 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

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2.6.1 Table of Instructions Classified by Function

Tables 2.3 to 2.10 summarizes the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below.

Table 2.2 Operation Notation

Symbol Description

Rd General register (destination)* Rs General register (source) * Rn General register* ERn General register (32-bi t register) (EAd) Destination operand (EAs) Source operand EXR Exten ded cont rol regi ster CCR Condition-code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition – Subtraction

× Multiplication ÷ Division ∧ Logical AND ∨ Logical OR ⊕ Logical exclusive OR → Move ∼ NOT (logical complement)

:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Note: *General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to

R7, E0 to E7), and 32-bit registers (ER0 to ER7).

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Table 2.3 Data Transfer Instructions

Instruction Size*

Function

MOV B/W/L (EAs) → Rd, Rs → (EAd)

Moves data between two general registers or between a general register

and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in this LSI. MOVTPE B Cannot be used in this LSI. POP W/L @SP+ → Rn

Pops a general register from the stack. POP.W Rn is identical to MOV.W

@SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn PUSH W/L Rn → @-SP

Pushes a general register onto the stack. PUSH.W Rn is identical to

MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. LDM*

L @SP+ → Rn (register list)

Pops two or more general registers from the stack. STM*

L Rn (register list) → @-SP

Pushes two or more general registers onto the stack. Notes: *1 Size refers to the operand size.

B:Byte W: Word L : Longword

*2 ER7 is used as a stack pointer in STM and LDM instructions. ER7, therefore, should not

be used as a saving (STM) or restoring (LDM) register.

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Table 2.4 Arithmetic Operations Instructions (1)

Instruction Size* Function

ADD SUB

ADDX SUBX

INC DEC

ADDS SUBS DAA DAS

B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd

Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.)

B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd

Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register.

B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd

Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.)

L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

Adds or subtracts the value 1,2, or 4 to or from data in a 32-bit register.

B Rd (decimal adjust) → Rd

Decimal-adjusts an addition or subtraction result in a general register by referring to the OCR to produce 4-bit BCD data.

MULXU B/W Rd × Rs → Rd

Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

MULXS B/W Rd × Rs → Rd

Performs signed multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

DIVXU B/W Rd ÷ Rs → Rd

Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.

Note: *Size refers to the operand size.

B: Byte W: Word L: Longword

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Table 2.4 Arithmetic Operations Instructions (2)

Instruction Size*

Function

DIVXS B/W Rd ÷ Rs → Rd

Performs signed division on data in two general registers: either 16 bits ÷

8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit

quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM

Compares data in a general register with data in another general register

or with immediate data, and sets CCR bits acc ording to the result. NEG B/W/L 0 – Rd → Rd

Takes the two's complement (arithmetic complement) of data in a

general register. EXTU W/L Rd (zero extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16

bits of a 32-bit register to longword size, by padding with zeros on the

left. EXTS W/L Rd (sign extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16

bits of a 32-bit register to longword size, by extending the sign bit.

TAS*

B @ERd – 0, 1 → (<bit 7> of @ERd)

Tests memory contents, and sets the most significant bit (bit 7) to 1. Notes: *1 Size refers to the operand size.

B: Byte W: Word L: Longword

*2 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

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Table 2.5 Logic Operations Instructions

Instruction Size* Function

AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register and another general register or immediate data.

OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register and another general register or immediate data.

XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general register and another general register or immediate data.

NOT B/W/L ∼ Rd → Rd

Takes the one's complement (logical complement) of general register contents.

Note: *Size refers to the operand size.

B: Byte W: Word L: Longword

Table 2.6 Shift Instructions

Instruction Size* Function

SHAL SHAR

SHLL SHLR

ROTL ROTR ROTXL ROTXR

B/W/L Rd (shift) → Rd

Performs an arithmetic shift on general register contents. 1-bit or 2 bit shift is possible.

B/W/L Rd (shift) → Rd

Performs an logical shift on general register contents. 1-bit or 2 bit shift is possible.

B/W/L Rd (rotate) → Rd

Rotates general register contents. 1-bit or 2 bit rotation is possible.

B/W/L Rd (rotate) → Rd

Rotates general register contents through the carry flag. 1-bit or 2 bit rotation is possible.

Note: * Size refers to the operand size.

B: Byte W: Word L: Longword

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Table 2.7 Bit Manipulation Instructions ( 1)

Instruction Size* Function

BSET B 1 → (<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory operand to 1. The bit

number is specified by 3-bit immediate data or the lower three bits of a

general register. BCLR B 0 → (<bit-No.> of <EAd>)

Clears a specified bi t in a general register or memory operand to 0. The

bit number is specified by 3-bit immediate data or the lower three bits of

a general register. BNOT B ∼ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory operand. The bit

number is specified by 3-bit immediate data or the lower three bits of a

general register. BTST B ∼ (<bit-No.> of <EAd>) → Z

Tests a specified bit in a general register or memory operand and sets or

clears the Z flag accordingly. The bit number is spe cif ied by 3-bi t

immediate data or the lower three bits of a general register. BAND B C ∧ (<bit-No.> of <EAd>) → C

ANDs the carry flag with a specified bit in a general regi ster or memory

operand and stores the result in the carry flag. BIAND B C ∧ (<bit-No.> of <EAd>) → C

ANDs the carry flag with the inverse of a specified bit in a general

bit number is specified by 3-bit immediate data. BOR B C ∨ (<bit-No.> of <EAd>) → C

ORs the carry flag with a specified bit in a general register or memory

operand and stores the result in the carry flag. BIOR B C ∨ (∼ <bit-No.> of <EAd>) → C

ORs the carry flag with the inverse of a specified bit in a general register

or memory operand and stores the result in the carry flag. The bit

number is specified by 3-bit immediate data. Note:* Size refers to the operand size.

B: Byte

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Table 2.7 Bit Manipulation Instructions ( 2)

Instruction Size* Function

BXOR B C ⊕ (<bit-No.> of <EAd>) → C

Exclusive-ORs the carry flag wit h a specif ied bit in a genera l regist er or memory operand and stores the result in the carry flag.

BIXOR B C ⊕ ∼ (<bit-No.> of <EAd>) → C

Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.

BLD B (<bit-No.> of <EAd>) → C

Transfers a specified bit in a general register or memory to the carry flag.

BILD B ∼ (<bit-No.> of <EAd>) → C

Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data.

BST B C → (<bit-No.> of <EAd>)

Transfers the carry flag value to a specified bit in a general register or memory operand.

BIST B ∼ C → (<bit-No.>. of <EAd>)

Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3bit immediate data.

Note:* Size refers to the operand size.

B: Byte

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