Hitachi dp86 schematic
NOVEMBER, 1999 Prepared by: ALVIE RODGERS C.E.T.
This training package is geared specifically to the 60SDX88B progressive scan HDTV capable set. The necessary understanding that the 60SDX88B requires a Set-Top-Box to receive SDTV and HDTV signals is important. The 60SDX88B does NOT have a DM-1
module. This module is built into the 61HDX98B which allows this set to receive all
ATSC formats as well as Direct TV, NTSC, SDTV or HDTV.
The 60SDX88B has a built in FLEX converter that translates any input into either 480P for
NTSC or SDTV and/or 1080I for HDTV. It does have Component Inputs.
The Power Supplies are the same for either set.
The Deflection circuit is very similar between the two sets.
The Signal PWB is very similar between the two sets, minus the differences mentioned
above.
Digital Convergence is the same between the two sets.
61HDX98B is a DP-85 chassis with a 16X9 aspect screen.
60SDX88B and the 50SDX89B is a DP-86 chassis with a 3X4 aspect screen.
CONTENTS... 1999 DP-86 HDTV Ready Projection Television Information
DP-86 BLANK PAGE “NOTES”
BLANK PAGE
60SDX88B DP86 CHASSIS TRAINING and INFORMATION
CONTENTS
SECTION PAGE
1): GENERAL BLOCK DIAGRAMS, SECTION:
• Power Supply Block Diagram --------------------------------------------------------------- 01-01
• AV Selector Block Diagram ----------------------------------------------------------------- 01-02
• Signal Processing Block Diagram ---------------------------------------------------------- 01-03
• System Control Block Diagram ------------------------------------------------------------- 01-04
• 2H Video Block Diagram -------------------------------------------------------------------- 01-05
• AV Selector Block Explanation ------------------------------------------------------------- 01-06
• Deflection Circuit Block Diagram ---------------------------------------------------------- 01-07
• CRT Block Diagram -------------------------------------------------------------------------- 01-08
• Audio Output Block Diagram --------------------------------------------------------------- 01-09
• Rear Panel Diagram -------------------------------------------------------------------------- 01-10
• 16X9 Displayed on 4X3 Screen ------------------------------------------------------------- 01-11
2): POWER SUPPLY INFORMATION, SECTION:
• Sub Power Supply SHUT DOWN Block Diagram --------------------------------------- 02-01
• Sub Power Supply SHUT DOWN Circuit Diagram -------------------------------------- 02-02
• Sub Power Supply Visual Trouble Shooting LED's Diagram -------------------------- 02-03
• Sub Power Supply Distribution Diagram -------------------------------------------------- 02-04
• Deflection and High Voltage Power Supply SHUT DOWN Block Diagram --------- 02-05
• Deflection and High Voltage Power Supply SHUT DOWN Circuit Diagram -------- 02-06
• Deflection Power Supply Visual Trouble Shooting LED's Diagram ------------------ 02-07
• Deflection Power Supply Distribution Diagram ------------------------------------------ 02-08
3): HORIZONTAL DRIVE, SECTION:
• Horizontal Drive Circuit Diagram --------------------------------------------------------- 03-01
4): VIDEO SIGNAL INFORMATION:
• Video Signal Main and Terminal Circuit Diagram -------------------------------------- 04-01
• ABL Circuit Diagram ------------------------------------------------------------------------- 04-02
• Horizontal and Vertical SWEEP LOSS DETECTION Circuit ------------------------ 04-03
5): AUDIO CIRCUIT INFORMATION:
• Audio Signal Main and Terminal Board Circuit Diagram ----------------------------- 05-01
• Audio SURROUND Board Circuit Diagram ---------------------------------------------- 05-02
• Front Left & Right Graphic EQ Circuit Diagram -------------------------------------- 05-03
• Center Graphic EQ Circuit Diagram ------------------------------------------------------ 05-04
• Audio and Video MUTE Circuit Diagram ------------------------------------------------ 05-05
• Audio MUTE Surround Board Circuit Diagram ----------------------------------------- 05-06
• Audio MUTE Audio Output Board Circuit Diagram ------------------------------------ 05-07
6): DIGITAL CONVERGENCE CIRCUIT INFORMATION:
• Digital Convergence INTER-CONNECTION Diagram -------------------------------- 06-01
• Digital Convergence OVERLAY DIMENSIONS Information ------------------------ 06-02
• Digital Convergence REMOTE CONTROL Button Identification ------------------- 06-03
CONTENTS PAGE (A-1)
60SDX88B DP86 CHASSIS TRAINING and INFORMATION
CONTENTS
SECTION PAGE
7): MICROPROCESSOR
• Microprocessor Port Block Diagram ..........................................................................07-01
• Microprocessor Data Communications Block Diagram .............................................07-02
8): PWB INFORMATION
• Signal PWB ...................................................................................................................08-01
• Deflection PWB ............................................................................................................08-02
• Control PWB ................................................................................................................08-03
• CRT PWB .....................................................................................................................08-04
• SUB POWER PWB ......................................................................................................08-05
9): MISCELLANEOUS INFORMATION
• Flex Converter Information and Diagram ....................................................................09-01
• 60SDX88B Component and Parts Identification ......................................................09-02
• Overlay Part Numbers Diagram ..................................................................................09-04
• 53SBX89B Component Identification ........................................................................09-05
CONTENTS PAGE (A-2)
BLOCK DIAGRAM EXPLANATION POWER SUPPLY BLOCK
The 61HDX98B utilizes two switching power supplies.
DP-85's stand by switching mode operation is different
from AP-7X and 8X chassis's. Switching frequency of
AP-7X and 8X chassis is dropped to 20kHz during
stand by mode. But the DP-85's power supply is not
dropped during stand by mode. DP-85's is operated
about 100kHz.
Normally Power Supply switching is operated as following.
T901: 25- 56 kHz (Normal)
100-200 kHz (Stand by)
TP91 30- 53 kHz (normal)
POWER SUPPLY UTILIZED FOR THE DIGITAL AND SIGNAL CIRCUITS:
(Sub Power Supply PWB)
This supplies power primarily to the Digital circuits, i.
e. DM-1 module. This supply runs anytime the set is
plugged into an AC outlet.
The voltages produced are;
• +33V,
• Power for the Satellite dish which is switched be-
tween 13V and 19V dependant upon the channel
being received.
• Stand By 12V also called A12V
• TV9V
• TV5V
• 3.3V
• -5V
POWER SUPPLY UTILIZED FOR THE DEFLECTION, AUDIO and DIGITAL CONVERGENCE CIRCUITS: (Deflection PWB)
This supply only operates when the set is turned ON.
When the ON command is received from the DM-1
module, relay S-901 energizes and delivers AC to the
main bridge rectifier D903 located on the Sub Power
Supply PWB.
This supplies power primarily to the Deflection circuit
for the collector of the High Voltage generation circuit
and the collector of the Deflection Output transistor.
Also, the Convergence output amps and the Audio
output amps derive their voltages from here as well.
The voltages produced are;
• +130V used for Deflection and High Voltage cir-
cuits.
• 220V used for the collectors of the R, G, B drivers
on the CRT PWB and the Velocity Modulation
circuits.
• 6.3V to drive the CRT Heaters.
• +28V for the Convergence, Velocity modulation
and Audio Out circuit.
• +13V for Vertical.
• -13V for Vertical and also converted down to
the –5V for the Digital Convergence Unit.
The TV9V supply generated from the Power Supply
for Digital listed above, is regulated down to +5V for
the Digital Convergence Unit and the A12V for the
Power Supply for Digital is used as a switched On/Off
for the Deflection Vcc by the Rainforest IC.
Page 01-01
DP86 POWER SUPPLY BLOCK DIAGRAM
Fuse
Line
Filter
Relay
Line
Filter
R
POWER SUB
P.W.B.
STAND BY
35V
I901
Sub
Switching
Regulator
EE42
24.5V
R/F 28V
C21V
+33VS Reg
A12V Sw. Reg.
9V Sw. Reg.
TV9V
5V Sw. Reg.
TV5V
28V
21V
To Signal Block
POWER DEFLECTION
SWITCHED
IP01
Main
Switching
Regulator
EE49
P.W.B.
(130V) Reg
220V
6.3V
+28V
-28V
+13V Reg.
-13V Sw. Reg.
-5V Reg.
Def. +B V1&V2
CRT &
Vm Out
Heater
Convergence
Velocity Mod.
Convergence
Vertical
Vertical (M13)
DCU
Block
To Deflection
AC108-
PAGE 01-02
132V/
60Hz.
AC Inlet Type
+5V Reg.TV9V
DCU
HVcc12VA12V
BLOCK DIAGRAM EXPLANATION FRONT END
The 61HDX98B utilizes a non-repairable Front End
Assembly called the DM-1 Module. This module contains the main System control center, NTSC Front
End, Direct TV Receiver and ATSC Tuner. The block
diagram indicates the internal blocks contained within
the Front End Assembly, hear after called the DM-1.
Starting counterclockwise from the upper left.
SATELLITE:
This represents the Direct TV satellite dish connection
to the back of the set.
SATELLITE TUNER/IF:
This is the internal IRD, (Integrated Receiver and Decoder). This receives the satellite signal from the LNB
(Low Noise Block) located on the Dish. This block
converts the signal to a usable signal for decoding.
SATELLITE CARD and SATELLITE LINK
BLOCK:
To receive Direct TV signals, the customer is required
to insert an active Security Card into the back of the
set. This care contains a programmable chip that contains the consumer’s information and the channels that
the consumer is allowed to receive. Also, this card is
used when billing information is retrieved by Direct
TV.
LINK/MIX:
This block passes the particular signal that the customer has decided to view on screen. Either the Direct
TV signal or the ATSC tuner.
TERRESTRIAL:
This indicates the outside antenna the consumer has
erected to receive NTSC signals as well as ATSC signals.
CABLE:
This is the input from the consumer’s cable signal.
HD/NTSC TUNER/IF SPLITTER:
This block receives the Terrestrial signal and dependant upon which source the consumer has decided to
view, processes the signal through the appropriate
tuner.
• HD: Receives the Terrestrial Signal and routes it
to the ATSC tuner. This tuner is capable of receiving all 18 ATSC formats.
• NTSC: Receives the Terrestrial Signal and route
it to the NTSC Tuner.
• The NTSC signal is routed out of this block on the
line labeled Composite Video to the Signal Selector IC which selects the appropriate signal according to the consumer’s choice. Either Tuner,
AVX1, 2 or 3 and/or S-In 1,2 or 3.
• The NTSC audio IF signal is routed to the MTS
STEREO DECODER.
• SPLITTER:
• The splitter routes the NTSC signal out to the RF
Out PinP Tuner path to the PinP Tuner.
MTS STEREO DECODER:
Decodes the NTSC Audio IF signal an decodes it into
Left Total and Right Total. This signal is routed to the
Dolby® Pro-Logic decoder.
HDTV LINK:
This block routs the ATSC signal received by the
ATSC tuner to the Link Mix.
NTSC YUV A/D:
This block receives the NTSC luminance and chroma
signals and converters them to a digital signal to be
utilized by the MPEG VIDEO decoder.
FROM MAIN MICRO:
This is communication in and out for the SubMicroprocessor. Information such as the Selector IC
selection, power on/off commands, etc.., are routed
from the ARM/Transport or Main Microprocessor section.
SD-A/V:
This is the output of the AC-3 digital audio to be used
by an off board AC-3 decoder.
MODEM:
Direct TV polls the Direct TV receiver section through
the customer’s phone lines and determines such things
as Pay for View authorization, customer’s information, Card authorization and billing information.
ARM/TRANSPORT:
The Arm/Transport block receives all signals from Direct TV, ATSC. It also receives the Infrared remote control signals, Front panel Key data, and Slave Microprocessor information. This is the Main Microprocessor section of the DM-1 module. Dynamic RAM and ROM information is processed from Soft ward load into ROM
and determines the state of the Television. Information
from ATSC and/or Direct TV is routed to the MPEG
VIDEO DECODER.
Page 01-03
BLOCK DIAGRAM EXPLANATION FRONT END
MPEG VIDEO DECODER, NTSC UPCONVERSION, OSD:
What ever signal is requested by the consumer as the
source for viewing is processed through this block and is
output to the YUV D/As.
YUV/DAs:
This block takes the digital signals provided to it and
converts them to an analog signal which is usable by the
signal processing circuits.
All signals are routed out through the line labeled 2.14
YUV/YIQ, (NTSC Signal up converted to 480P or 2.14
HYPBPR which is the HDTV output as 1080I.
MPEG/AC-3 AUDIO DECODER:
This block processes the audio component from the
ARM/TRANSPORT or the block A/Ds AUDIO, which
is the NTSC audio processed by the Pro Logic decoding
circuit, labeled as 5.1, (Front Left, Front Right, Center,
Rear Left and Rear Right + Sub Woofer audio also called
LFE. Then this block processes the signal and outputs all
audio to the Audio D/As.
AUDIO D/As:
This block is the Digital to Analog converter which converts the digital audio signal sent to it by the ARM/
TRANSPORT block and converts it to a usable analog
signal to be processed by the audio output section.
The audio labeling is comprised of the following:
L/R = Audio Front Left and Right
LS/RS = Rear or Surround audio Left and Right
C/LFE = C for Center and LFE for Sub Woofer, also
called Low Frequency Effects.
Page 01-04
A/V SELECTOR BLOCK DP85 CHASSIS
TERMINAL P.W.B.
Antenna
A
Out to
Converter
Antenna
B
VT+33V
Main
Tuner U002
Lock
Clock
Data
Enable
+5V +9V
Comp. Video (Main) R/L (Main)
+5V +9V
Tuner U003
VT+33V
C/V
Det.
RF
Antenna
Switch Box
Video 4 V4, S4, L/R4
PinP Video and MonoAudio
Selected L/R
(NTSC Main Audio)
Lock/Clock
Data/Enable
Video
PinP
Mono
C Video
C/V Det
PinP
9V
AUDIO/VIDEO
SELECTOR
TA8851BN
Video D YC
To 3DYC
I2C
Ant
From Micro
PinP Video
to PinP Unit
YUV
2 Line
Y/C
for PinP
PinP L/R Out
To Audio Out PWB
PinP V
PinP YC
Video One In
Video Two In
V1 S1 L/R1
V2 S2 L/R2
Video Three In
V3 S3 L/R3
YUV Det
C/V
Det.
YUV
Y
CR/PR
CB/PB
YUV In
480I/480P/1080I
PAGE 01-05
BLOCK DIAGRAM EXPLANATION A/V SELECTOR
C. VIDEO (MAIN) and R/L (AUDIO MAIN):
NTSC Video and NTSC Audio is routed from the
DM-1 Block diagram. They are shown in the Block
Diagram as one line, but they are separate signals.
Anytime a signal is routed from the DM-1 or going to
the DM-1 module, they must be sent through a DM-1
I/F block. This block reduces the noise by a noise cancellation process. This process uses the output of a
comparator and routes the output back to the negative
input to subtract the noise. It also level shifts the signal
to make it useable by the circuit to which it is routed.
DM-1 I/F BA4558:
This is the noise cancellation and level shift block.
AUDIO/VIDEO SELECTOR TA8851BN:
This is the selector IC. Dependant upon the customer’s
viewing preference, the DM-1 will communicate via
I2C bus communications and select the NTSC signal
which is sent to the demodulator. The demodulator
prepares the NTSC signal for the DM-1 module.
This IC selects the following inputs;
Main tuner
Video One, Two or Three
S-In One, Two or Three
PinP Video and Audio outputs. This can be any of the
input provided above except the PinP has it’s own
tuner.
Note: PinP isn’t available when the customer has selected Direct TV or ATSC as it’s source. This is because, as will be shown later, the PinP Video is super
exposed upon the NTSC video only.
Any video source selected for the Main picture will be
routed to the 3D Y/C module.
Note: There are NO Component inputs on this set.
Page 01-06
DP86 CHASSIS SYSTEM CONTROL & SIGNAL PROCESSING BLOCK
Clock/
Data/
Enable
PinP
YC
I2C +5V +9V +3.3V
3D Y/C Unit
and
PinP Unit
HC3152
VIDEO
YC
YUV
HV
6dB Amp
YUV
Clock/Data/
Enable
+9V
+5V
HC140538CP
HV
+5V
2H Sync
Selector
FC
UNIT
HC5125
Flex
Converter
2H YUV
H V
HV Blk
Clamp
YUV YIQ
+5V
YUV
Y
YUV
BA7657F
YUV Selector
Sync
Sep
V Sync
Sep.
PinP Y/C from Selector
IC
SIGNAL P.W.B.
HV
Sync
YUV Switch
PinP
Sync Det.
PinP V
To Microprocessor
Main
Sync Det.
Main Video/S-YC
from Selector IC
PAGE 01-07
BLOCK DIAGRAM EXPLANATION
SYSTEM CONTROL AND SIGNAL PROCESSING
MAIN VIDEO FROM SELECTOR IC:
At the bottom left hand side is shown the Main Video
from Selector label. This is the NTSC video from the
selector IC. This is routed to two blocks.
3D Y/C:
The 3D Y/C separates luminance from the chroma. It
also add the 3D effect, (if the 3D Y/C is turned on
within the menu). Noise is canceled and the two separate components are output to the Video/Chroma Demodulator.
VIDEO/CHROMA DEMODULATOR:
This IC decodes the signal down to it’s Luminance and
Chroma. components and outputs it as 1HYIQ.
DM-1 I/F:
Noise cancellation and level shifting preparing the signal for the DM-1 module.
1HYIQ:
1HY = Standard NTSC format luminance. (Also
known as 480I).
I and Q = Standard NTSC format, demodulated
chroma components.
SYNC DET.:
Separates the Sync signal from the composite video signal.
SYNC DET.:
This block outputs composite sync to the PinP unit which
is used for timing for display. This is specifically related
to the Demodulator, D/As and Read/Write clock. The
Read/Write clock also is controlled by the frequency of
the Subcarrier also called fsc.
The Composite sync is also sent to the DM-1 on the line
labeled as 1H Composite Sync. The DM-1 uses this signal for OSD positioning, auto channel detection and AFC
loop activation.
TV uCOM MICROPROCESSOR:
This is the slave Microprocessor or Sub-Microprocessor.
This IC is in constant communications with the DM-1
module. The slave uP. Receives or outputs the following
signals;
HBLK: = Input; this is the Horizontal Blanking signal.
Used for Service OSD signal creation timing.
S.WIDE: = Output; when the customer watches regular
NTSC 4X3 aspect source, they have a choice of viewing
the signal in one of 4 ways.
Normal: This will display a standard 4X3 picture
with black panels on each side of the picture.
Fill: This will expand the picture to fill the screen.
The top and bottom will be cropped.
Full: This will expand the picture side ways and fill
the screen. However the picture will be non-linear.
Smooth Wide: This will keep the center of the picture linear and stretch the outside edges to fill the
screen.
With the four choices above, the DM-1 module controls
the signal for 3 of them; Normal, Fill and Full. However,
during Smooth Wide, the deflection circuit is switched to
perform the stretching of the sides. The slave Microprocessor outputs S.Wide during this time.
CUT OFF: = Output; labeled as V. Stop, during the Ser-
vice adjustments for Cut Off, (Screen Background controls), the vertical must be collapsed. This output causes
the B+ to the vertical output IC front end to be grounded
and grounds the vertical trigger pulse called V. Saw.
D. SIZE: = Output; labeled as Digicon Size, during
Smooth Wide mode, the Digital Convergence Unit, hear
after called DCU, must know that the set is in the distorted deflection mode. This signal tells the DCU just
that.
MAGIC SW: = Input; when the customer presses the
Magic Focus button on the control panel, the DCU notifies the slave micro. That it is busy performing Magic
Focus. The slave micro. Notifies the DM-1 module and
the DM-1 module ignores infrared pulses from the remote control.
CLOSED CAP. DATA: = Input; This input receives the
composite sync signal and decodes the Closed Caption
Data. (Data Slice line 21) and the communicates with the
DM-1 Module. The DM-1 Module actually introduces
the Closed Caption Characters into the Video stream.
F. PANEL: = Output, Dependant upon the customer’s
menu selection, will determine the IRE level of the side
panels when 4X3 Normal mode is used. By raising the
side panel IRE levels, the 4X3 picture won’t burn in the
CRT’s.
MAIN SYNC DET: = Input; this is used for detecting the
Closed Caption Data. This information is routed to the
DM-1 module for OSD generation. NOTE: the submicro. Doesn’t produce OSD characters for Closed Caption.
PinP SYNC DET: = Input; PinP tuner sync is routed to
the sub-micro. And is used during PinP tuner channel
Page 01-08
BLOCK DIAGRAM EXPLANATION
SYSTEM CONTROL AND SIGNAL PROCESSING
selection to activate AFC.
MAIN SYNC DET. = Input; This input is used for Service OSD positioning and Auto Programming channel
detection.
PinP SYNC DET. = Input; This input is used for judgement of the Slave Microprocessor to determine the AFC
Loop activity of the PinP Tuner.
MUTE (Audio): = Output; during channel change, external video selection with no input, power up or power
off, and loss of Vertical Blanking, the audio and video
are muted.
V.MUTE (Video): = Output; during child lock, channel
change, or power on/off, the video is muted.
POWER: = Output; when the front power button or the
remote power button is pressed, the DM-1 module notifies the sub-micro. And the sub-micro. Outputs a power
on/off command to the relay driver Q-007. Outputs high
for ON and low for OFF.
OSD & OSD BLK: = Output, this is the on screen characters for the Service Menu only. OSD Blk is OSD
blanking. This cleans us the video where the OSD is to
be inserted.
HV BLK: = Input; this inputs are utilized by the Microprocessor for Service OSD positioning.
HV BLK PH: = Output; during Service Adjustment and
in the NTSC normal mode. This picture doesn’t fill the
screen. The areas on the side of the picture are called
Side Panels. This can be adjusted. The HV BLK PH,
controls the timing of the side panel OSD outputs.
SIDE PANEL APL FROM 2H VIDEO PWB: = Input;
the Microprocessor receives a pulse created within the
2H video PWB. This pulse represents the timing pulse
for the Side Panel OSD production.
Blocks continued;
OSD MIX: Only the Service menu OSD is output from
the Slave Microprocessor. The Digital convergence unit
puts out OSD characters as well. This characters product
the Service Grid and other text during Digital Convergence adjustments and/or Magic Focus. The two OSD
sources are received by the OSD Mix. This is comprised
of a quad Or Gate and outputs the signal to be superimposed upon the video signal path from the DM-1 Module.
PinP VIDEO FROM SELECTOR IC: The video from
the PinP tuner is routed to the PinP unit and the Sub Microprocessor for Closed Caption decoding.
Page 01-09
DP86 CHASSIS SYSTEM CONTROL BLOCK
IR From
Control Panel
IR
I2C
YUV Switch
DAC
M62392
MTS
F. MONO
ANT
UV/IQ Sel
YUV Sel
SYNC On/Off
CUT OFF
31/33
To Deflection (DCU)
TV uCOM
Microprocessor
IR In
Dimmer
Key In
D. Size
Main Tuner Enable
PinP Tuner Enable
Sync Det
P.Blk.
Mute (Audio)
V.Mute (Video)
FH Det
FV Det
Power On/Off
OSD & OSD Blk
I2C
I2C
Cut Off
D. Size
31.57/33.75
To Deflection
Busy
Digital OSD
OSD RGB Ys
OSD
Select
IR
RGB Ys
OSD
Main Sync Det
PinP Sync Det
MEMORY
Main Video from Selector IC
CCD Video
Main
SIGNAL P.W.B.
HV BLK
YM
Busy
PAGE 01-10
BLOCK DIAGRAM EXPLANATION 2H VIDEO
The 2H Video PWB is similar to the Rainforest circuits used in the past. The YUV/YIQ
(480P) and/or the Y-PR/PB (1080I) is routed
through another DM-1 Interface IC for noise
cancellation and level shifting and into the
Rainforest chip, IX01. Here the signal is prepared for the CRT’s. Pedestal level detection,
Chroma preparation, OSD RGB from either
the DCU or the Slave Microprocessor is input
here.
Remember that the OSD for Customer usage
such as the Channel numbers, clock, Main
Menu, etc.. is generated by the DM-1 Module.
Also, ABL controls the brightness and
Contrast; as well as the color level at this
chip.
The Velocity modulation control signal is
produced from the Rainforest IC. This signal
is a representative of the Peak White components of luminance and drives the Velocity
Modulation coils on each CRT.
Page 01-11
2H PWB BLOCK DP86 CHASSIS
2H VIDEO P.W.B.
OSD RGBYSI2C YM ABL
YUV/YIQ/
Y PB PR
+9V
Clamp
HV Blk
RGB PROCESSOR
TA1276AN
Clamp
H/V Blk.
YUV RGB
YUV
YIQ
YPBPR
RGB
VM
PAGE 01-12
BLOCK DIAGRAM EXPLANATION DEFLECTION BLOCK
The 61HDX98B deflection circuit differs from conventional Hitachi product. It utilizes in a sense, two
horizontal output circuits. One for Deflection and on
for High Voltage. The notations around the Block diagram will be described in a counter clock wise fashion
as best a possible.
CUT OFF:
Cut of collapses the Vertical circuit during I2C Bus
alignments, during CRT Set Up.
I2C:
Communication from the Sub Microprocessor I001
during sweep variations due to Standard/NTSC 480P
mode and 1080I High Definition mode.
ABL:
ABL voltage is generated by monitoring the current
through the flyback transformer. This voltage will
fluctuate down when the scene is bright and up when
the scene is dark. The ABL voltage will manipulate
the screen brightness and contrast to prevent blooming
under these conditions.
HV SYNC:
The composite sync is routed into the Sync processor
which determines the sweep condition for the signal
being provided.
H and V BLK:
Horizontal and Vertical Blanking is developed within
the Deflection circuit. The Horizontal Blanking pulse
operates around 13V P/P and is produced by taking a
sample pulse from the Deflection transformer T752.
The Vertical Blanking pulse is generated from the
Vertical output IC, I601 pin 7. This pulse normally
operates at 23V P/P.
IR:
The Infrared Pulses coming from the remote control
are routed through the Deflection PWB to the Digital
Convergence Unit. During DCAM (Digital Convergence Adjustment Mode), the Remote Control provides manipulation pulses for the DCU.
DIG RGB BUSY:
This indicates Digital RGB and BUSY.
Digital RGB represents the on screen characters produced by the DCU for generating the Digital Convergence adjustment grid and text produced during certain conditions such as Magic Focus, Sensor Initialization, Data Storage, etc…
Busy notifies the sub Microprocessor I901 which in
turn notifies the DM-1 module that the DCU has entered the DCAM. During this time, the DM-1 module
ignores the remote control commands.
MAGIC SW:
When the customer presses the Magic Focus button on
the front of the set, it produces a command for the
DCU to begin the Magic Focus process.
D SIZE:
Digital Size is a control signal for raster enlargement
when MAGIC FOCUS is operated. Raster enlargement is required for the MAGIC FOCUS PATTERN
to hit the photo sensors.
This signal is output from DCU and input to the Sub
Microprocessor I901. The Sub Microprocessor controls the I702 on the DEF.SUB PWB) for enlarging
raster size.
In case of AP-85, this control signal is called "A.
SIZE". It's the same function between DIG.SIZE and
A.SIZE.
S WIDE:
Smooth Wide is a condition entered through the Menu
by the customer while watching an NTSC 4X3 aspect
video source and the customer wants to fill the screen.
TO CONVERGENCE YOKES:
The DCU provides compensation signal for deflection
abnormalities to the convergence output IC. The Convergence output IC in turn, amplify the signals and
rout them to the convergence yokes.
+26V, 26VP and RETRACE PULSE:
The positive 26V and the negative 26V is routed to the
Deflection transformer I752. They enter the transformer as a pure DC voltage. A 15V P/P horizontal
pulse is added to the DC voltage and leaves as +26VP
and –26VP. From here these voltages are routed to the
Convergence output section and they are rectified.
They become +33V and -33V respectively. This process prevents the need for another power supply.
+B 130V:
The Deflection transformer receives the 130V V1 DC
source.
DF OUT:
Generated from the I702 on the Sub Deflection PWB
and the Horizontal Blanking pulses, a Dynamic Focus
waveform is created. This is a parabolic waveform that
Page 01-13
BLOCK DIAGRAM EXPLANATION DEFLECTION BLOCK
is superimposed upon the static focus voltage to compensate for beam shape abnormalities which occur on
the outside edges of the screen because the beam has
to travel further to those locations.
HV PARABOLA:
Described above.
SCREEN 700V: 700V Supplied to the screen grids on
the CRT’s.
FOCUS 9KV:
Focus voltage supplied to the CRT’s.
32Kv HV:
32,000 volts DC supplied to the CRT’s anodes.
TO DEFLECTION YOKES:
Horizontal and Vertical deflection wave forms driving
the deflection yokes.
INTERNAL BLOCKS DESCRIPTION
HV CONTROL:
The uPc1344C IC generates the horizontal drive signal
utilized by the High Voltage circuit. The HV control
IC receives it’s locking pulse from the Deflection circuit. A feed back voltage is sampled from the High
Voltage Regulation Detector circuit and compared
with a reference voltage to maintain an accurate 32KV
on the CRT’s.
VERTICAL OUTPUT:
The vertical output utilized in the 61HDX98B operates
differently from previous chassis. This circuit utilizes
a +13V and a –13V to generate the waveform to drive
the vertical deflection yokes. A pump up circuit is utilized to product the retrace pulse for the vertical deflection yoke. It’s at this time when a higher pulse is
needed because the beam has to travel from the bottom
of the screen to the top very rapidly. The vertical output IC receives it’s trigger pulse from the ramp generator.
SYNC PROCESSOR:
The Sync Processor located in I702 on the Sub Deflection PWB, detects the horizontal sync rate for the displayed signal, either 480P or 1080I.
VERTICAL RAMP GENERATOR:
I702 on the Sub Deflection PWB generates the Vertical Saw signal. This signal is controlled by several
factors. The Sync Processor detection and I2C data
communication.
DIST CONTROL:
Distortion control is another signal produce by I702
and sent to the Side Pin cushion circuit. These compensation parabolic wave forms are combined with the
horizontal circuit to compensate for Side pincushion
errors.
H-SIZE SIDE-PIN CONTROL:
This circuit generates the Side Pincushion Distortion
compensation pulse which is impressed onto a coil
located in the output side of the Deflection Output section and compensates for Pin Cushion distortion.
HORZ. DRIVE and HORZ. OUT:
This circuit comprises the Drive and Output for the
Deflection output circuit.
S-CORRECT (SMOOTH MODE):
During Smooth mode, the deflection circuit is manipulated so that the outside 1/3 of the picture is stretched
to fill the screen. The center 2/3 of the picture is left
undistorted. When an S Wide signal is received, a capacitor is switched off on the output side of the Deflection output circuit.
PHOTO SENSOR:
There are 8 sensors located on the internal outside
edges of the cabinet. These Photo Cells receive the
light patterns being generated during MAGIC FOCUS
or SENSOR INITIALIZATION and deliver this voltage to the Sensor Distribution circuit.
SENSOR DISTRIBUTION:
This represents the amplifiers that receive the Photo
receivers (Photo Cells) inputs during Magic Focus operation.
DIGITAL CONV. UNIT:
This is the Digital Convergence Unit. This is a nonrepairable unit. It contains the distortion compensation
wave form generation circuits, RAM, ROM and D/A’s
for the convergence circuit.
SERVICE SWITCH:
When the set needs a convergence alignment, the Ser-
Page 01-14
Loading...