Hitachi dp3x schematic

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Page 1

June 2005

(ver n) Training Materials Prepared by: ALVIE RODGERS C.E.T.

HITACHI

PROJECTION

TELEVISION

http://www.hitachiserviceusa.com

2003

MODEL RELEASE

DIGITAL HD READY PTV

Model No Chassis

46W500 DP33W 2 51S700 DP36 57S700 DP36 65S700 DP36 51S500 DP37 3 57S500 DP37 3 65S500 DP37 3 57T500 DP37C 65T500 DP37C 57X500 DP37D 65X500 DP37D

Includes built in ATSC/QUAM tuner

Includes built in DVD Player

Includes built in Photo Card Reader

1,3 1,3 1,3

CONTENTS... 2003 DP-3X Chassis Projection Television Information

Materials Prepared by… Alvie Rodgers C.E.T. (Chamblee, GA.)

Page 2

DP-3X BLANK PAGE “NOTES”

BLANK PAGE

Page 3

June 2005

SECTION (1) POWER SUPPLY DIAGRAMS:

•

SECTION (2) MICROPROCESSOR INFORMATION:

•

SECTION (3) VIDEO CIRCUIT INFORMATION:

•

(ver n)

TOPICS PAGE

(Visual Trouble Shooting) Stand By Power S upply Circuit Diagram Explained -------

LEDs

(Visual Trouble Sh ooting) Stand By Po wer Supply Ci rcuit Diagram --------------------

LEDs

(Visual Trouble Shooting) Deflection Power Supply Circuit Diagram Explained -----

LEDs

(Visual Trouble Shooting) Defl ection Power Supply Circuit Diagram -------------------

LEDs Power Supply Shut Down Power Supply Shut Down Protect (Deflection) Hi Volt Shut Down Prot_CPT and PROT_SW Shut Down SW +115V Hi Voltage Regulation SW +115V Hi Voltage Regulation

Microprocessor Microprocessor

Audio Video Mute Audio Video Mute

Microprocessor Microprocessor

Video NTSC Video NTSC Component Video Component Video Rainforest IC Pulse

Circuit Diagram Explanation

ABL

Circuit Diagram

ABL Component Sync

Component Sync ATSC (Digital Tuner)

Input Circuit Diagram

DVI

•

Audio Video Mute

•

Audio Video Mute

DP-3X TABLE OF CONTENTS

Circuit Diagram Expl ained -------------------------------------------Circuit Diagram ---------------------------------------------------------

Circuit Diagram ----------------------------------------Circuit Diagram Expl ained ---------------------------------Circuit Diagram -----------------------------------------------

DATA COMMUNICATION DATA COMMUNICATION

Circuit Diagram Explanation Circuit Diagram

NTSC Sync Input NTSC Sync Input

Circuit Diagram Explained Circuit Diagram

and

NTSC Continued

and

NTSC Continued

Explanation Explained

---------------------------------------------------------------------------------- 03-09

Circuit Diagram E xplanation ----------------------------------------------------Circuit Diagram ---------------------------------------------------------------------

Block Diagram

---------------------------------------------------------------------------- 03-13

Circuit Diagram Explanation (See Microprocessor Section) Circuit Diagram (See Microprocessor Section)

----------------------------------------------------------------- 02-08

Circuit Diagram Explained Circuit Diagram

----------------------------------------------------------- 03-01

Circuit Diagram

------------------------------------------------------------------- 03-08

DP-36 and DP-38 Only

Materials prepared by

Alvie Rodgers C.E.T.

01-01 01-02 01-03 01-04 01-05 01-10

Circuit Di agram and Explanation -------------------

Explanation

Circuit Diagram

------------------------------------------------- 02-06

Circuit Diagram

------------------------------------------------------ 03-03

Circuit Di agram Explanation ----------------------Circuit Diagram

-------------------------------------------------------- 03-07

------------------------------------- 02-01

------------------------------------ 02-05

--------------------------------- 02-09

----------------------------- 02-10

---------------------------------------

-------------------------------------- 03-12

--------

-----------------------

01-11 01-12 01-13 01-14

03-04 03-06

03-10 03-11

02-06 02-07

Continued on Next Page

Table of Contents Page 1 of 3

Page 4

June 2005

(ver n)

DP-3X TABLE OF CONTENTS

TOPICS PAGE

Materials prepared by

Alvie Rodgers C.E.T.

SECTION (4) AUDIO CIRCUIT INFORMATION:

Audio

•

SECTION (5) DEFLECTION CIRCUIT:

•

SECTION (6) DIGITAL CONVERGENCE CIRCUIT INFORMATION:

•

SECTION (7) ADJUSTMENT INFORMATION: Only information that differs for the DP-2X (previous chassis) are included.

•

Main Terminal Circuit Diagram Explanation

Audio

Main Terminal Circuit Diagram

Main / Sub Audio Main / Sub Audio

Horizontal Drive Horizontal Drive IH01 Horizontal Drive IC Sweep Loss Sweep Loss Vertical Output Vertical Output Pincushion Circuit

Pincushion Circuit

Digital Convergence Interco nn ect Digital Convergence Interco nn ect Remote CLU5728TSI Remote CLU5727TSI Remote CLU5725TSI 46" Overlay 51" Overlay 57" Overlay

65" Overlay

DCU Crosshatch Phase Settings --------------------------------------------------------------------------------- 07-01 Off-Set for Red and Blue Raster Position Vertical Size Horizontal Size DCU Character Set-Up DCU Pattern (Sensor Position) Set-Up Read from ROM Notes -------------------------------------------------------------------------------------------- 07-07 Remote CLU5728TSI Remote CLU5727TSI Remote CLU5725TSI Adjusting Digital Convergence Magic Focus Magnet Locations --------------------------------------------------------------------------------------------------- 07-13

Overlay

•

Selection Circuit Diagram Explanation Selection Circuit Diagram

Circuit Diagram Explanation Circuit Diagram

Voltages and Waveforms (Also, Not Running Info.) Detection Circuit Diagram Explanation Detection Circuit Diagram

Circuit Diagram Explanation Circuit Diagram

Diagram Diagram

Dimensions Dimensions Dimensions

Dimensions

Adjustment

Error Codes

Dimensions (See Digital Convergence Section)

--------------------------------------------------------------------------------------- 05-09

--------------------------------------------------------------------------------------- 05-10

(Digital Convergence Mode Functions) DP-37 (Digital Convergence Mode Functions) DP-33W (Digital Convergence Mode Functions) DP-37C and DP-37D

------------------------------------------------------------------------------------------- 06-09

------------------------------------------------------------------------------------------- 06-10

------------------------------------------------------------------------------------------- 06-11

------------------------------------------------------------------------------------------- 06-12

------------------------------------------------------------------------------------------- 07-03

--------------------------------------------------------------------------------------- 07-04 DCU Data Confirmation

and

(Digital Convergence Mode Functions) DP-37 (Digital Convergence Mode Functions) DP-33W (Digital Convergence Mode Functions) DP-37C and DP-37D

------------------------------------------------------------------------------------------ 07-12

--------------------------------------------------------------------------- 04-02

-------------------------------------------------------------------------------- 05-03

--------------------------------------------------------------------------- 05-06

---------------------------------------------------------------------------------- 05-08

Circuit Diagram Explanation Circuit Diagram

Adjustment

Using an External Sign al

----------------------------------------------------------- 04-01

--------------------------------------------------- 04-03

------------------------------------------------------------------- 04-04

---------------------------------------------------------------- 05-01

------------------------- 05-04

----------------------------------------------------------- 05-05

------------------------------------------------------------------ 05-07

------------------------------------------- 06-01

---------------------------------------------------------- 06-05

------------------------------------- 06-06

---------------------------------- 06-07

------------------- 06-08

Adjustment

------------------------------------------------------ 07-02

Adjustment

---------------------------------------------------------- 07-06

--------------------------------------------------- 07-11

--------------------------------------- 07-05

------------------------------------- 07-08

---------------------------------- 07-09

------------------- 07-10

--------------------------------------- 06-09 ~06-12

Continued on Next Page

Table of Contents Page 2 of 3

Page 5

June 2005

Use Contents on the Left Hand Side to Navigate to Topics as this section can change often. Or Go to the page after the Section 10 Things You Should Know Section Divider for an Index.

SECTION (8) MISCELLANEOUS IN FOR MATI O N:

•

SECTION (9) DP-33W DVD TROUBLESHOOTING:

•

DVD PLAYER TROUBLESHOOTING PICTURES:

•

SECTION (10) THINGS YOUR SHOULD KNOW: ----------------------------------- 10-01

(ver n)

TOPICS PAGE

Signal PWB Deflection PWB Power Supply PWB CRT PWBs Front Control PWBs Rear Panel Rear Panel Rear Panel Rear Panel Rear Panel

No DVD Player Picture ------------------------------------------------------------------------------ 09-01 No DVD Player Analog Audio ---------------------------------------------------------------------- 09-02 No DVD Player Digital Audio ---------------------------------------------------------------------- 09-03 DVD Player Power Supply Check ----------------------------------------------------------------- 09-04 DVD Player Control Check ------------------------------------------------------------------------- 09-05 DVD Player Audio / Video Check ------------------------------------------------------------------ 09-06 DVD Player Interface Block Diagram ------------------------------------------------------------ 09-07 DVD Player Video Signal Diagram ---------------------------------------------------------------- 09-08 DP-33W Microprocessor Data Communication Signal Diagram --------------------------- 09-09 DVD Player Audio Signal Path Signal Diagram ------------------------------------------------ 09-10

DVD Player Front View and Plastic Cover ------------------------------------------------------ 09-11 DVD Player Control Panel Removal and Plastic Cover Removal --------------------------- 09-12 DVD Player Removal and Dropped Down But Still Connected ----------------------------- 09-13 DVD Player Removed and Top View ------------------------------------------------------------- 09-14 DVD Player Top Screws Removal and Ribbon Cables Identified --------------------------- 09-15 Separation DVD Player From Power Supply PWB -------------------------------------------- 09-16 DVD Player Separated From Power Supply PWB --------------------------------------------- 09-17 Power Supply PWB Troubleshooting Layout --------------------------------------------------- 09-18

DP-3X TABLE OF CONTENTS

Drawing

DP-36 (Terminal Input) Drawing (S700 Models) DP-37 (Terminal Input) Drawing (S500 Models) DP-37C (Terminal Input) Drawing (T500 Models) DP-37D (Terminal Input) Drawing (X500 Models) DP-33W (Terminal Input) Drawing (W750 Models)

--------------------------------------------------------------------------------- 08-01

Drawing

---------------------------------------------------------------------------- 08-02

Drawing

---------------------------------------------------------------------------------- 08-04

Drawing

----------------------------------------------------------------------- 08-03

---------------------------------------------------------------------- 08-05

------------------------------------ 08-06

----------------------------------- 08-07

--------------------------------- 08-08

-------------------------------- 08-09

------------------------------- 08-10

Materials prepared by

Alvie Rodgers C.E.T.

Table of Contents Page 3 of 3

Page 6

DP-3X BLANK PAGE “NOTES”

BLANK PAGE

Page 7

POWER SUPPLY

INFORMATION

DP-3X

CHASSIS INFORMATION

SECTION 1

Page 8

DP-3X BLANK PAGE “NOTES”

BLANK PAGE

Page 9

DP-3X LED (Visual Trouble Detection) CIRCUIT EXPLANATION

STAND BY POWER SUPPLY

This explains the LED used for Visual Trouble Shooting Circuit Diagram explanation:

(See DP-3X LED (Visual Trouble Detection) Diodes for Stand By Power Supply Diagram for details)

1 GREEN

In the DP-3X chassis, there is 1 Green LED in the Stand By power supply. Use this LED to determine if the set is experiencing a problem.

The LEDs can be used in the following ways.

OFF:

• If the LED is off, then the power supply that is being monitored is unavailable. (Excluding the possibility

that the LED itself is malfunctioning).

• If the LED turns on but then quickly goes off, then the power supply that is being monitored can be sus-

pected.

ON:

• If the LED is on, then the power supply that is being monitored is working normal. (There is the possibility

that the power supply being monitored may in fact be present but low. If after making visual inspection and all seems OK, but there’s still a problem, be sure to check the accuracy of the power supply in question.

GREEN LED D913.

D913 (Stand By +5V)

• Monitors the

• This is a new IC in the DP-3X chassis. It is a self contained DC-DC converter that provides the Stand

By +5V which keeps the necessary circuits alive when the set is turned off. Such as the Microprocessor, etc…..

Stand By +5V

output from

U901

pin 1.

PAGE 01-01

Page 10

DP-3X CHASSIS

L.E.D. (Visual Troubleshooting) for the Stand By Power Supply

(1 Green L.E.D. for visual trouble sensing observation)

U901

Stand By

DC-DC

Converter

L924

C919

C918

GREEN

L.E.D.

C922

D913

PPS5

4 Gnd

Gnd

D913 illuminates when the Stand By +5V is available.

SBY + 5V

PAGE 01-02

Page 11

DP-3X LED (Visual Trouble Detection) CIRCUIT EXPLANATION

This explains the LEDs used in t he Def lect ion Power Supply used for Visual Trouble Shooting Circuit Diagram explanation:

(See DP-3X LED (Visual Troubleshooting) for the Deflection Power Supply Diagram for details)

5 LEDS, 4 GREEN AND 1 RED

In the DP-3X chassis, there are 5 total LEDs that can be used for Visual Trouble shooting. 4 Green and 1 Red. Use these LEDs to determine if the set is experiencing a problem. The LEDs can be used in the following ways.

OFF:

If the LED is off, then the power supply that is being monitored is unavailable. (Excluding the possibility that the LED itself is malfunctioning). NOTE: If condition because of it’s current flow explained below. If the LED turns on but then quickly goes off before the others, then the power supply that is being monitored can be suspected.

ON:

If the LED is on, then the power supply that is being monitored is working normal. (There is the possibility that the power supply being monitored may in fact be present but low. If after making visual inspection and all seems OK, but there’s still a problem, be sure to check the accuracy of the power supply in question.

RED LED D912

is used to monitor the Start Up and Run voltage for the Driver IC

D912

lowing voltages.

• Audio SW +30V

• SW +10V

• +220V

• SW+28V

• SW -28V

• SW +115V

The LED

GREEN LEDs D956, D955, D954 and D932.

D956 (Audio +30V)

D955 (SW +5.5V)

D954 (SW +28V)

D932 (SW +115V)

D912

• Monitors the

D922

• Monitors the SW +28V output from

• Note: Th is LED requires the SW –28V power supply to be functioning to operated. If the LED opens, or

the negative SW –28V is missing, this LED will not illuminate. If the SW –28V is missing, the set will shut down.

• Monitors the

• This power supply is used for Deflection and High Voltage generation.

is attached to pin 4 of

Audio +30V

SW +5.5V

cathode.

SW +115V

generated by the SW +5.5V regulator

. If the voltage is missing, the LED will not light.

I901

output from

pin 18 and rectifier

T901

pin 15 and rectifier

T901

pin 11 and rectifier

T901

LED opens, then the set will be in shut down

D932

. This IC is used to generate the fol-

I901

cathode.

D919

I905

D922

D925

pin 1 from

cathode.

pin 15 and rectifier

T901

PAGE 01-03

Page 12

DP-3X CHASSIS

L.E.D. (Visual Troubleshooting) for the Main Power Supply

(5 Total L.E.D. for visual trouble sensing observation, 4 Green and 1 Red)

T901

28V

-28V

E901

E904

E905

D922

C932

C933

C940

D923

C939

L918

L920

D919

C924 C925

1.77A

C934

C935

C941

GREEN

L.E.D.

R931

I905

SW+5.5V

Reg

5 8

R964

D954

R965

L909

C926

D956

L910

1.59A

L914

R932

R933

GREEN L.E.D.

D952 D953

R934

C936

GREEN

L.E.D.

IAA1

Ft. Audio

Out

L919

See Shut

Down Circuit

L915

D955

Right Audio

Left Audio

2.28A

1.00A

PPS5

3 Gnd

4 Gnd

5 Gnd

7 Gnd

PPD5

SW + 5.5V

SW+ 28V

+115V D925

T901

C942

C943

Osc B+

From Relay

S901

C911

RED L.E.D.

Hot Ground from

pin 9 of T901

Q905

C949

D912

R944 0.39 Ohm

Start Up

R907R906

D911

R918

E907

+115V

Over

Current

R946

D932

Run

16.3V

D907

I901

Driver/Output IC

R914

D910

L923

R952

R953

GREEN L.E.D.

D908

Q901

115V Regulator

0.85A

R913

I904

Gnd

From Pin 8 T901

7.5P/P

Regulator Photocoupler

I906

SW + 115V

C946

R940

R941

R942

D927

PAGE 01-04

Page 13

DP-3X POWER SUPPLY SHUT DOWN EXPLANATION

GENERIC SHUT DOWN C IRCUITS EXPLAINED:

The following circuits are commonly used in Hitachi product and relate to the drawing on page 01-10:

SW +115V EXCESSIVE CURRENT DETECTION

(See Figure 1)

One very common circuit used in many Hitachi television products is the B+ circuit. In this circuit is a low ohm resistor series with the SW +115V. The value of this resistor is

0.39 ohm

voltage drop across the resistor increases. If the voltage drop is sufficient to reduce the voltage on the base of Shutdown signal that is directed to the appropriate circuit indicated on the drawing on page 01-10 as point

NEGATIVE VOLTAGE LOSS DETECTION

(See Figure 2)

The purpose of the Negative Voltage Loss detection circuit is to compare the negative voltage with its’ counter part positive voltage. If at any time, the negative voltage drops or disappears, the circuit will produce a Shutdown signal. In Figure 2, there are two resistors of equal value, (15K). One to the positive voltage SW +28V and one to the negative voltage SW –28V. At their tie point, (neutral point), the voltage is effectually zero (0) volts. If however, the negative voltage is lost, the neutral point will go positive. This in turn will cause the zener diode and on to the appropriate circuit indicated on the drawing on page 01-10 as point Note: The LED nated by the current draw from +28V to the –28V supply.

VOLTAGE TOO HIGH DETECTION

(See Figure 3) Another circuit used is the

circuit. In the example shown in Figure 3, the

tion

zener diode

R952

the voltage at the divider center point will rise as well and trigger or fire the zener diode which produces a Shutdown sig na l through ate circuit indicated on the drawing on page 01-10 as point

. When the current demand increases, the

, the transistor will conduct, producing a

Q905

(A)

to fire, cre ating a Shutdown Signal through

D952

D954

D931

and

(A)

. If the voltage source rises to o high,

R953

Excessive Current Sensing

R944

(A)

used for visual trouble shooting is illumi-

Voltage Too High Detec-

is connecte d to a voltage divider

and on to the appropri-

D930

SW+115V

D953

C949

Voltage Loss

R964

15K

D931

D930

Detector

SW +28V

R952

R953

R944

0.39

Current Sensor

Q905

Shut-Down Signal

Figure 1

Shut-Down Signal

D954

Figure 2

High Detector

Figure 3

R946

R947

D953 D952

R965

15K

SW -28V

SW +115V

Voltage Too

Shut-Down Signal

Base

Bias

(Continued on page 6)

PAGE 01-05

Page 14

DP-3X POWER SUPPLY SHUT DOWN EXPLANATION

VOLTAGE LOSS or SHORT DETECTION

(See Figure 4) One circuit used is the

Voltage Loss Detection

cuit. This is a very simple circuit that detects a loss of a particular power supply and supplies a PullDown path for the base of a PNP transistor. This circuit consist of a diode connected by its cathode to a positive B+ power supply. Under normal conditions, the diode is reversed biases, which

cir-

Voltage

Loss

Detector

Any Positive

B+ Supply

B+

keeps the base of Q1 pulled up, forcing it OFF. However, if there is a short or excessive load on the B+ line that’s being monitored, the diode in effect will have a L OW on its cat hode, turning it ON. This

Figure 4

Shut-Down Signal

will allow a current path for the base bias of Q1, which will turn it ON and generates a Shutdown Signal.

B+ GENERATION FOR THE MAIN POWER SUPPLY DRIVER IC I901:

Vcc for the Driver IC is first generated by the AC input. This voltage is called Start Up Voltage.

23.3V

. However, it will begin operation at routed through the main fuse radiation for radiating back into the AC power line. After passing AC is routed through the relay 150V DC voltage to be supplied to the power supply switching transformer However, one leg of the AC is routed to

D911

Zener tor of When the power supply begins to operate by turning on and off the internal Switch MOS FET, the Raw 150V DC routed through out of pin (2) through four low ohm resistors ( FET turns on, it causes the transformer to saturate building up the magnet field. When the internal Switch MOS FET turns off, the magnet field collapses and the EMF is coupled over to the secondary windings, as well as the drive windings. The drive windings at pin (8) produce a run voltage pulse which is rectified by and now becomes run voltage (

HOT GROUND SIDE SHUT DOWN SENSING CIRCUITS. (Specific to I901).

In addition, there are 4 Hot Ground side Shutdown inputs that are specifically detected by the main power driver IC These sensors circuits protect

LATCHED SHUT DOWN MONITORS:

1. (OVP)

2. (TSD)

3. (Trigger) Over Load Protection monitors the difference between the Hot Ground and Floating Ground.

RECOVERING SHUT DOWN INPUT:

4. (OCP)

and made available to pin (4) of

I901

is turned On and it begins to operate.

T901

, in on pin 3 (Drain) and out on pin 2 which is the Source. The Sou r ce of the internal Switch MOS FET is routed

Pin 4

is monitored for Over Voltage Protection at pin 4 of

I901

itself is monitored for Excessive Heat. This block is labeled TSD. (Thermal Sensing Device).

Pin 1

monitors the low ohm resistors, condition caused by monitoring the current through the internal Switch MOS FET, the voltage will rise and pin 1 has an internal Over Voltage detection op-amp. If this voltage rises enough to trigger this op-amp, the IC will stop producing a drive signal.

F901

(a 10 Amp fuse), then through the Line filter

S901

23.3V

I901

from excessive current, temperature or over voltage.

12V

on pin (4) of

and AC arrives at the main full wave bridge rectifier

R906

I901

) for

(AC must be removed to recover).

(Driver IC will recover on it’s own when trouble is removed.)

R907

and

I901

as start up voltage. When this volt age reaches 13Vd c, the internal Regu la-

R908, R909, R910 and R911

pin 4.

R908, R909, R910

I901

. When the s et is tu rned on by

L901

(both a 3.9K ohm resistor), filtered by

D907

I901

and

I901

normal pin 4 voltage is

S901

, AC is applied. AC is

L901

to prevent any internal high frequency

filter it passes another filter

D901

T901

pins (1 and 2).

) to hot ground. When the internal Switch MOS

, filtered by

R911

C911

. If these resistors have an excessive curren t

L903

. The HOT leg of

where it is converted to Raw

C911

, clamped by a 36V

then routed clamped by

D911

I901

(Continued on page 7)

PAGE 01-06

Page 15

DP-3X POWER SUPPLY SHUT DOWN EXPLANATION

The next explanation discusses the Cold Ground side shut down circuit operation.

This explains the Pow er Supply Shut Down Circuit Diagram:

See DP-3X Power Supply Shut Down Diagram for details Use this explanation and Diagram in conjunction with the following diagrams; DP-3X Deflection Protect Power Supply Shut Down Circuit Diagram and DP-3X PROT_CPT and PROT_SW Shut Down Circuit Diagram.

The Power supply is centered around the Switching Transformer This power supply creates voltages that are Switched on when the Set is turned on.

1. Audio SW +30V 2. SW +10V

3. +220V 4. SW+28V

5. SW -28V 6. SW +115V

Other supplies are generated from these 6 main voltages.

Q904 Relay Inhibit Activation. (SHUT DOWN) called COMMON ACTION CIRCUIT. All Shut Down events will cause the main power relay to turn off. This action will stop all secondary power suppli es. The Low Voltage power supply (S tand-By) continues to operate.

If any of the 23 shut down circuits activate, the base of High from prevents

SOME SHUTDOWN CIRCUITS ARE DEFEATED IN STANDBY MODE. (Set Off).

When the set is turned off or in Stand By, 12 of the shut down inputs are not active.

These shut down circuits are d efeated because the SW (Switched) power supplies are turned off in standby. So to prevent faults triggering of the shutdown circuit, the sensing circuits are turned off also..

Q906

voltage to operated. Emitter voltage is supplied from the to function. When the set is turned off these switched voltages disappear, so

COLD GROUND SIDE SHUT DOWN INPUTS EXPLAINED

GENERAL INFORMATION

All of the Power Supply Shutdown circuitry can be broken down into the following categories;

PPS4

connector pin 7 called

Q904

from turning off is the shut down signal disappears after shutdown.

Shorted

•

monitored by Shorted

•

Shorted

•

Shorted

•

Shorted

•

Prot_SW

•

1. SW +2.2V 2. SW +3.3V

3. SW +5V 4. SW +9V

5. SW +9.3V 6. Blue CRT VM 220V excessive current sensing circuit. Shorted

•

supplies the high for shutdown if any of the shut down circuit attached to its base become low.

Voltage Missing Detection or Short Detection or Negative Voltage Loss Detection

•

Voltage Too High Detection

•

Excessive Current Detection

•

SW+35V

SW+10V SW+5.5V 220V SW+6.3V

(6 shut down inputs) This voltage is monitored by

SW+28V

(from voltage divider

D938

(from pin 16 of

(from pin 1 of

(from pin 10 of

(from pin 1 of

(from pin 15 of

Power_1

T901

I905

T901

) This voltage is monitored by

I906

T901

(See previous pages for generic circuit details)

Q904

and the main power supply will STOP.

R940

). This voltage is monitored by

) This voltage is monitored by

SW +6.3V

T901

and the driver IC,

will go High. This turns on

R941

and

off the SW+115V from pin 11 of

D944

SW +10V

and

I901.

Q903

and removes the Power On

Q903

operates as a “latch”. This

T901

D939

D940

D941

Q906

D942

and

D943

line. This voltage must be active for

can no longer operate.

Q906

). This voltage is

requires emitter

Q906

(Continued on page 8)

PAGE 01-07

Page 16

DP-3X POWER SUPPLY SHUT DOWN EXPLANATION

COLD GROUND SIDE SHUT DOWN SENSING CIRCUITS.

Looking at the base of

SHUT DOWN CIRCUITS:

There are a total of 23 individual Shutdown inputs to the Relay Inhibit transistor will be described later. However, there are some that are routed to the Power Supply from external circuits not shown on the Power Supply Shut Down circuit diagram.

There are a total of 3 individual Shutdown inputs from the Deflection PWB via

•

ing diode

Vertical Output I601 Excessive Current Detection

-5V Loss Detection

Excessive High Voltage Detection

3. There is 1 Shutdown input from the

•

QE08 VM Protect,

Power PWB via sive current on the Red CRT PWB. (See PROT_CPT & PROT_SW Shut Down Circuit Diagram).

There are 6 individual Shutdown input from the

•

All of the Cold Ground side Shutdown detection circuits can be categorized by the previously described shut down circuits which were discussed in the Generic Shut Down Circuits Explanation section.

In the following explanation, the Shutdown circuits will be grouped. This will assist the Service Technician with trouble shooting the Chassis, by understanding these circuits and having the associated circuit routs, the technician can then

and Conquer”

Voltage Loss (or Short) Detection

signal to a (Hi) then throu gh

On the Signal PWB 2 of 3 PROT-SW

Prot_CPT & Prot_SW Shut Down Circuit Diagram)

Shorted SW+2.2V (

•

Shorted SW+3.3V (

•

Shorted SW+5V (

•

Shorted SW+9V monitored by

•

Shorted SW+9.3V monitored by

•

Q904

the shut down events are triggered by the following.

D951

. (See Deflection Protect Power Supply Shut Down Circuit Diagram).

Protect_CPT

on the Red CRT PWB. From the Red CRT PWB to the Green CRT PWB via

Green CRT PWB to Signal PWB via

PPS4

connector pin 6 called

of these inputs is from

EGB1

via pin 2 called From PWB via CRT PWB.

of these inputs are monitoring for a shorted B+ line. These circuits are on the Signal PWB 2 of 3. The y moni-

tor the following;

All routed through

connector pin 8 called

Gain.Cont

Q554

collector to the

PPS4

connector pin 5. This signal would be low if the +220V draws excessive current on the Blue

1. SW +2.2V from

2. SW +3.3V from

3. SW +9V monitored by

4. SW +9.3V monitored by

5. SW +5V from (See PROT_CPT & PROT_SW Shut Down Circuit Diagram).

D933

I404 I403

I402

QEA8

on th the Blue CRT PWB. From the Blue CRT PWB to the Green CRT PWB

. From the

PPS4

I404

pin 4.

I403

pin 3 monitored by

D404.

D403.

I402

pin 3 monitored by

All short detections signals active (Lo). Routed to the base of Q906 which inverts the

to the base of

PPS4

pin 5 to

pin 4) monitored by pin 3) monitored by

pin 3) monitored by

D404

D403

Protect_CPT

Protect_SW

Gain.Cont

PSC

connector pin 2 to the base of

connector pin

Q904,

Common Action Circuit.

D944

R420 D402

D401

(AC must be removed to recover).

Q904

. Many of these are discrete circuits and

Protect_Def

circuit routed through steering diode

PSC

connector pin 3 called

. This signal would be high if the +220V draws exces-

circuit monitored by

. From the Green CRT PWB to Signal PWB via

now called

D402.

D401.

on Power PWB. Labeled

Protect_SW

VM Protect

D944.

Q554

which inverts this High to a Low. . From the Signal PWB to Power

PROT-SW

routed through steer-

D959

. This input is from

ERG1

connector pin 7 called

, from Signal PWB to

PSC

on the Schematic. (See

connector

“Divide

(Continued on page 9)

PAGE 01-08

Page 17

DP-3X POWER SUPPLY SHUT DOWN EXPLANATION

On the Power PWB

SW –7V Voltage Loss Detectio n

•

lost, the positive

SW –28V Voltage Loss Detection

•

lost, the positive

In the Deflection Circuit

–5V Voltage Loss Detection

•

DK90.

bias connector pin 6 to

Voltage Too High Detect ion

Action Circuit. (See DP-3X Power Supply Shut-Down Circuit Diagram for details)

On the Power PWB.

SW +115V Voltage Too High Detection

•

Audio Ground

•

tored by

SW +10V Voltage Too High Detection

•

SW +5.5V Voltage Too High Detection

•

From, the Deflection circuit output called Protect_Def.

DH14 High Voltage Too High Sensing Circuit.

•

ing the pulse from the flyback This high will be routed to pin 6 of ate a high that will be routed through the

Circuit Diagram for details)

At the same time, the zener diode

•

Horizontal Drive for High Voltage and this IC will shut off, turning off High Voltage drive pulses.

Excessive Current Detection

On the Power PWB.

SW +115V Excessive Current Detection

•

tion/High Voltage Circuit draws too much current, voltage of routed to relay.

In the Deflection Circuit on the Power/Deflection PWB.

Q604 Vertical Circuit Ex cessive Current Se nsing Circuit.

•

tical Output IC. If the IC draws too much current, voltage of routed through erate a high that will be routed through the Down Circuit Diagram for details)

On the CRT PWB PROT_CPT.

On the RED CRT PWB +220V Excessive Current Detection

•

current, the base voltage of

ERG1

pin 7,

On the BLUE CRT PWB VM+220V Excessive Current Detection

•

too much current, the base voltage of through

lector goes low. This low is routed to the PPS4

base of Q906 low turning it on causing shut down.

EGB1

+6.3V

will forward bias

+28V

will forward bias

Any abnormality seen in the deflection circuit will generate a high that will be routed through the

D951.

(See DP-3X Deflection Protect Shut-Down Circuit Diagram for details)

All voltage too high detections circuits are active (Hi) and routed to the base of

If the Audio Output IC

D960

and routed through

(See DP-3X Power Supply Shut-Down Circuit Diagram for details)

Q905

to fall turning on this transistor. When this happens, it’s collector will go high. This high will be

D928

causing it to fire. This high will be routed through

Q604

to fall turning on this transistor. When this happens, it’s collector will go high. This high will be

D608

and to pin 6 of

(See PROT_CPT & PROT_SW Shut Down Circuit Diagram).

PSC

pin 8,

pin 3,

PSC

PPS4

pin 2, to the base of

Monitored by

D949

Monitored by

D952

Monitored by

IAA1

D961.

Monitored by

TH01

pin 5. If the voltage at the cathode of

PPD4

DH14

PPD4

QE08

will fall turning it on. The collector will go high. This high will go through

pin 6 to

D959

QEA8

D949

and routed through

and it will fire causing shut down.

D952

and routed through

and it will fire causing shut down.

DK90

. In this circuit, if the

D931

and routed through

has an internal short, the Audio ground will go positive. This is Moni-

D957

and routed through

D947

and routed through

This circuit monitors the

Protect_Def

connector pin 6 to

will fire and this high will be routed to pin 7 of

Monitored by

Protect_Def

PPD4

will fall turning it on. The collector will go high. This high will go

Q554

. Any abnormality seen in the deflection circuit will gener-

D951.

Q905

R927

will develop a larger voltage drop. This will cause the base

R629

will develop a larger voltage drop. This will cause the base

. Any abnormality seen in the deflection circuit will gen-

connector pin 6 to

on the Signal PWB. This h igh turns on

pin 5 to the cathode of

D928

and

D930

This circuit monitors the

Monitored by

D950

. In this circuit, if the

D953

. In this circuit, if the

–5V

is lost, the positive

D930

D958

D948

High Voltage

DH15

goes too high, this zener will fire.

(See DP-3X Deflection Protect Shut-Down

and routed through

and to the base of

D951.

(See DP-3X Deflection Protect Shu t-

RE35

Monitored by

D944

causing D945 to fire and pull the

line generated by rectify-

D930.

Q904

+28V

line going to

220V

. If the

REF1

. If the

Q554B and it’s col -

SW –7V

SW –28V

+5V

will forward

Q904,

Common

IH01

. This is the

If the Deflec-

shutting off the

I601

draws too much

VM220V

PPD4

draws

Ver-

PAGE 01-09

Page 18

DP-3X MAIN POWER SUPPLY SHUT DOWN DIAGRAM

D938R958

SW +6.3VSW +10V

D939R959

SW +35V

SW +10V

D934

SBY +5V

R957

S901

Q902

Q906

SHORT

DETECTION

D936D935

R954 C951

Active Lo

R956 C952

D918

R929

D933

D940R960

SW +5.5V

D942R961

D941

+220V

D943R962

SW +6.3V

D944D945

Prot_SW

D946R963

PPS4

SW +28V

D959

Protect_CPT

Power On/Off

onoff

Power_1

T901

D917

Relay

Driver

D925

C943

C921

Relay Inhibit

C949

R948

Q904

C950

R927

R944

R951

C947

C948

R947

Q905

R946

D928

D929

Q903

R949

E907

R950

SW+115

L923

R952

R953

D931

Point

PPD5

D932

D961 D960

D958 D957

D948 D947

D951

D950 D949

D953 D952

Audio Gnd

SW +10V

SW +5.5V

Protect_Def

R937

+6.3V

R939

SW -7V

R965

SW -28V

D954

R964

SW +28V

D930

PAGE 01-10

Page 19

DP-3X DEFLECTION PROTECT POWER SUPPLY SHUTDOWN DIAGRAM

Any fluctuations in High Voltage will also be reflected by the 50P output P/P. By monitoring the 50P (50 Pulse) rises in High Voltage will be sensed. If High Voltage climbs too high, DH15 will fire and trigger a shut down event. DH14 will fire and stop High Voltage Horz. Drive

Flyback RH32 allows ABL fluctuations to manipulate the Trigger Point of Shut Down as screen brightness varies. ABL is inverse proportionate to brightness. This prevents false Shut Down triggering.

ABL

Active

Normal

PPD4

RH32

TH01

5OP

High Voltage

Sensing Circuit

RH23

LH06

DH13

PROTECT _DEF

See Power Supply Shut Down Circuit Diagram for continuation.

Vertical Output Circuit

I601

R629

C604

0.68 Ohm

Q604

R630

C610

Excessive Vertical Current Det.

R631

D608

28V

R632

29.01V

RH24

RH25

Hi Volt

H. Drive

IH01

OVP

H. Drive

DH15

Excessive Hi

Voltage Det.

DK90 Monitors the -5V and +5V lines going to the DCU. If the -5V line is loss, the +5V line provides the Shut Down Hi.

CH17

Stops H. Drive

CH10 RH09

RK98

DH14

RH26

+5V

DK90

CK90

RK97

-5V Loss Det.

-5V

If the Vertical Output IC has a problem, R629

will sense the current rise. The voltage drop will

be reflected at the base of Q604 turning it on

and producing a Shut Down high.

PAGE 01-11

Page 20

DP-3X PROT_CPT and PROT_SW SHUT DOWN DIAGRAM

PROT_CPT SHUT DOWN DIAGRAM

+220V

VM 220V

PDC1

CE10

W8A1

REF2

QEA8

RE35

2.2 Ohm

QE08

RE29

REF1

15 Ohm

REE9

RED CRT PWB

RGB Drives VM Circuit

RE31

PROT_SW SHUT DOWN DIAGRAM

BLUE CRT PWB

VM Circuit

REF5

CEC1

RE34

PROT

REF6

CONT

GAIN

RED CRT

PWB

ERG1

BLUE

CRT

PWB

EGB1

PROT

GAIN

CONT

GREEN

CRT

PWB

PSC

GREEN

CRT

PWB

PSC

PROT

GAIN

CONT

SIGNAL

PWB

PSC

SIGNAL

PWB

PSC

SIGNAL

CPT

PROT

SIGNAL

GAIN

CONT

PWB

PPS4

Active

PROT

CPT

PWB

PPS4

Active

5 5

PROT

POWER

PWB

PPS4

POWER

PWB

PPS4

D421~D424

SW +5.5V

SW +9V

SW +9.3V

SW +2.2V Reg

I404

SW +3.3V Reg

I403

SW +5V Reg

I402

SIGNAL PWB 2 of 3

SW +2.2V

SW +3.3V

SW +5V

D402

D401

D404

D403

C592

R5T4

RL50

Q554

R420

PAGE 01-12

Page 21

DP-3X SW +115V POWER SUPPLY REGULATION EXPLANATION

Hi-Voltage Power Supply Circuit Diagram explanation:

(See Power Supply SW+115V Regulation Circuit Diagram for details)

THIS POWER SUPPLY RU NS ONLY WHEN THE SET IS TURNED ON:

TURNING ON THE SW +115V POWER SUPPLY:

When the Set is turned on, the Microprocessor Power On command is ro uted through the base of collector will go low. This will supply a ground path for the power on Relay energized, AC is supplied to the Bridge rectifier

develops raw 150V which is routed through

D901

the primary coil inside FET. The Ground return path for the primary voltage is out pin 2 of Switch MOS FET and then through four 0.22 ohm resistors

See SW+115V Regulation Circuit Diagram for details.

SW +115 REGULATION

SW +115V pulse is generated from pin 11 of routed thro ugh the Excessive Current sensing circui t The primary route for the to the Deflection circuit and High Voltage generation circuit. However, the regulation route is through variable resistor whose resistance is dependant upon the resistor manipulates the current flow from pin 2 to pin 3 ground. This will cause the voltage at pin 2 of manipulated. Internally, the LED is illuminated by degrees dependant upon the The internal receiver receives this light and acts as a variable resistor from pin 4 to pin 3 which is the regulation control signal. This action causes pin 1 of quency of the drive pulse delivered to the Gate of the internal SMOSFET (Switch Metal Oxide Semiconductor Field Effect Transistor) to manipulate the frequency of the pulse generated on the primary of drain of the internal SMOSFET is monitored by four low ohm resistors mentioned above. If this current exceeds a specific value, the voltage developed by these low ohm resistors is routed through is the Over Current Protection circuit as well as the Regulation Control pin. This pin will inhibit the drive signal to the gate of the SMOSFET. As soon as the excessive current situation is eliminated, the IC will recover and continue func ti o ni n g.

B+ GENERATION FOR THE POWER SUPPLY DR IVER IC:

Vcc for the Driver IC is first generated by the AC input. This voltage is called Start Up Voltage.

DC to operate normal. However, it will begin operation at

23.3V

When AC is applied to the main full wave bridge rectifier to be supplied to the power supply switching transformer However, one leg of the AC is routed to a half wave filter consisting of tor), filtered by When this voltage reaches 12Vdc, the internal Regulator of When the power supply begins to operate by turning on and off the internal Switch MOS FET, the Raw 150V DC routed through MOS FET is routed out of pin (2) through four low ohm resi stors to hot gro und. When the internal Switch MOS FET turns on, it causes the transformer to saturate building up the magnet field. When the internal Switch MOS FET turns off, the magnet field collapses and the EMF is coupled over to the secondary windings, as well as the drive windings. The drive windings at pin (8) produce a run voltage pulse which is rectified by

then clamped by

C911

The RED LED

provided the Shut Down sensor

Q902

and out pins 5 and 6 to pin 3 of

T901

SW +115V

I901

, clamped by a 36V Zener

C911

, in on pin 1 (Drain) and out on pin 2 which is the Source. The Source of the internal Switch

T901

and now becomes run voltage (

D911

can be used to determine if the B+ to pin 4 of

D912

Q027

is through

E906

to manipulate the internal oscillator within

Outputs a Power On/Off 1 high command via pin 59. This

I001

and

Q028

Q904

D901

F903

. This pulse is rectified by

T901

E907, L923

to pin 1 of

D911

to the

isn’t activated. When the base of

to Pins 1 and 2 of

R908, R909, R910

and

R944

I904

SW +115V

D901

T901

and made available to pin 4 of

I901

connector pin 7. This High will be passed to

PPS4

S901

. This voltage is routed through

T901

which is the Drain of the internal Switch MOS

I901

which is the Source of the internal

I901

and

D925

Q905

to pin 9 and 10 of

. Internally, the regulator transistor works as a

voltage fluctuations. The internal variable

12V DC

where it is converted to Raw 150V DC voltage

pin 1 and 2.

R906

is turned On and begins operation.

) for

23.3V

I901

PPD5

SW +115V

. This in turn causes the fre-

I901

on pin 4 of

and

R907

pin 4.

is present.

goes high, it’s

Q902

turning it on. When the relay is

R911

, filtered by

and output as

voltage fluctuations .

T901

back into pin 1 which

R912

I901

(both a 3.9K ohm resis-

as start up voltage.

I901

and then

C943

SW +115V

I903

. The current

requires

I901

, filtered by

D907

to be

PAGE 01-13

Page 22

DP-3X CHASSIS POWER SUPPLY SW +115V REGULATION

T901

7.5P/P

1 of 3

C911 R918

AC for D902

Supplied from

Relay S901

From Bridge D902

150V

F903

From Relay S901

D911

D912

RED L.E.D.

167V

T901

High Voltage Power Supply

R913

R906

23.3V

I901

Driver/

Output IC

3 2

R907

OCP

Start Up

Osc B+

R912

R908 R909 R910 R911

0.22

Ohm

11.6V

E906

0.5K

Run

D907

R914

C914

D908

Q901

R916

D910

B+ 115V

D927

23.3V

13.6V

R919

C946

I903

Regulator

Photocoupler

Hot Ground from

pin 9 of T901

I904

1 2

SW + 115V

R940

R941

12.1V

R942

11.2V

R943

D926

C944

T901

3 of 3

C942

D925

C943

2 of 3

C949

Q905

X-Ray Protect

R944

0.39 Ohm

D928

D929

D930

R946

R942

D931

E907

R952

R953

L923

Deflection

B+ 115V

D932

PPD5

0.86A

Cold Ground from

pin 12 of T901

C905

SW +115V

PAGE 01-14

Page 23

MICROPROCESSOR

INFORMATION

DP-3X

CHASSIS INFORMATION

SECTION 2

Page 24

DP-3X BLANK PAGE “NOTES”

BLANK PAGE

Page 25

DP-3X MICROPROCESSOR DATA COMMUNICATIONS CIRCUIT EXPLANATION

Microprocessor Data Communications circuit diagram. (See DP-3X Microprocessor Data Communications Circuit Diagram for Details)

The Microprocessor must keep in communication with the Chassis to maintain control over the individual circuits. Some of the circuits must return information as well so the Microprocessor will know how to respond to different request. The Microprocessor uses two types of communication for control, I lines . The I

C communication scheme only requires 2 lines for control. These lines are called SDA and SCL. Serial Data and Serial Clock respectively. Also, due to the fact that this Microprocessor operates at 3.3Vdc, it requires a Level Shift IC to bring the DC level of the control lines up to make it compatible with the connected components. The Level Shift IC also brings the DC levels down as outside circuits communicate with the microprocessor. The Microprocessor communicates with the following ICs:

ON THE SIGNAL PWB:

•

UD2003 Digital Module

•

U301 Main Tuner

•

U302 PinP Tuner

•

I003 EEPROM

•

U401 Flex Converter

•

I010 Level Shift

•

I501 Rainforest

•

IA01 Audio Control

(ATSC Tuner DP-36 and DP-38 Chassis Only)

ON THE TERMINAL PWB:

•

IY01 3D Y/C

•

IV01 A/V Selector

•

IV11 Digital to Analog Converter DAC

•

IV03 Y Pr/Pb Selector

•

IY04 Main Video Chroma Y Pr/Pb Selector

•

IY03 Sub Video Chroma Y Pr/Pb Selector

The following explanation will deal with the communication paths used between the Microprocessor and the respected ICs.

ON THE SIGNAL PWB:

UD2003 Digital Tuner (ATSC Tuner)

DP-36 and DP-38 Chassis Only

The Microprocessor controls the Digital Tuner via communication lines. They are listed below;

•

DM RTS DM CTS DM TXD

(Digital Module Receive Transmission) from pin 9 of (Digital Module Serial Clock) bi-directional pin 20 of

(Digital Module Transmission Data) bi-directional pin 35 of

tor.

•

DM RXD Power 2

of the

(Digital Module Receive Data) bi-directional pin 36 of

(Turns on Digital Module separate from the main Power On line) from pin 58 of

connector. The Table below shows the relationship between Power_1 and Power_2.

PMS1

C Bus and the Serial Data, Clock and Load

connector to pin 27 of the

PMS1

pin 7 of the

I001

to pin 5 of the

I001

pin 6 of the

I001

PMS1

connector.

PMS1

I001

connec-

connector.

to pin

I001

MODE Power _1 Power _2

Stand By Lo Lo

Timer Lo Hi

TV On Hi Hi

When the Timer is set for an unattended Recording, the Set turns on the Tuner and allows the "Video Out (Monitor out) to become active so that a recording can be made without turning on the entire set.

(Continued on page 2)

PAGE 02-01

Page 26

DP-3X MICROPROCESSOR DATA COMMUNICATIONS CIRCUIT EXPLANATION

U301 Main Tuner (with MTS outputs).

The Microprocessor controls the Main Tuner by SDA2 (Data) and SCL2 (Clock) I SCL2 and SDA2 lines for the Main Tuner are output from the Microprocessor at pins (

C communication lines.

31 SDA2 and 28 SCL2

) respectively. These lines go directly to the Main Tuner, SDA2 at pin (5) and SCL2 at pin (4). These lines control band switching, programmable divider set-up information, pulse swallow tuning selection, etc...

U302 PinP Tuner (monaural only).

The Microprocessor controls the Sub Tuner by SDA2 (Data) and SCL2 (Clock) I SCL2 and SDA2 lines for the Main Tuner are output from the Microprocessor at pins (

C communication lines.

31 SDA2 and 28 SCL2

I003 EEPROM

The EEPROM is ROM for many different functions of the Microprocessor. Channel Scan or Memory List, Customer set ups for Video, Audio, Surround etc… are memorized as well. Also, some of the Microprocessors internal sub routines have variables that are stored in the EEPROM, such as the window for Closed Caption detection. Data and Clock lines are pin (29) of the Microprocessor to pin (6) of the

from pin (30) of the Microprocessor to pin (5) of the

SDA1

EEPROM

. Data travels in both directions on the Data line.

EEPROM

and

SCL1

from

Note: In this chassis, if the EEPROM is removed or defective, the Microprocessor will LOCK the picture. No functions other that the front Power Button will work. LOCK will appear on the screen, but the customer’s menu can not be accessed.

U401 Flex Converter FC04

The projection television is capable of displaying NTSC as well as ATSC (SDTV) and HD (High Definition). The Flex Converter is responsible for receiving any video input and converting it to 33.75 Khz output (2.14H). This output is controlled by sync and by the customer’s menu and how it is set up. The set up can be 4X3 with grey side panels, Smooth Wide, Fill or Full and even 4X3 with Black Side panels. 16X9 for SDTV. This set will automatically bypasses the Flex Converter completely and inputs the 1080i signal directly to the Rainforest IC I501. This happens when a true 1080i signal or Antenna C is selected. The Flex Converter can take any NTSC, SIn, Component, NTSC or any of the 18 formats of ATSC except 1080i which doesn’t route through the Flex converter. Control for the Flex Converter is Clock, Data and Enable lines. The be routed through the Level Shift IC

to be brought up to 5V.

I007

Clock, Data and Enable

lines must

• The Clock line for the Flex Converter is output from the Microprocessor at pin (

at pins (

I007

2 Clock

• The Data line for the Flex Converter is output from the Microprocessor at pin (

at pins (

I007

4 Data

) and is output at pins (18) then through the

) and is output at pins (16) then through the

connector pin 10

PFC1

connector pin 11

PFC1

52 Data

• The Enable line for the Flex Converter is output from the Microprocessor at pin (

input to

I007

at pins (

6 Enable

) and is output at pins (14) then through the

PFC1

53 Clock

54 FCENABLE

connector pin 12.

). Clock is input to

). Data is input to

). Enable is

Data from the Flex Converter is also sent back to the Microprocessor. Data from the Flex is sent out of the connector pin 11 to pin 5 of sor

I001

, level shifted down to 3.3V and output at pin 15 into pin 51 of the Microproces-

I007

PFC1

I007 Level Shift

The Microprocessor operates at 3.3Vdc. Most of the Circuits controlled by the Microprocessor operate at 5Vdc. The Level Shift IC steps up the DC voltage to accommodate.

• Pin 18 outputs a Clock signal, used by the Flex Converter

• Pin 14 outputs an Enable signal, used by the Flex Converter

• Pin 16 outputs a Data signal, used by the Flex Converter.

• Pin 15 outputs 3.3V Data, sent from the Flex Converter

(Continued on page 3)

PAGE 02-02

Page 27

DP-3X MICROPROCESSOR DATA COMMUNICATIONS CIRCUIT EXPLANATION

I501 Rainforest (Video/Chroma Processor)

The Video Processing IC (Rainforest) is responsible for controlling video/chroma processing before the signal is made available to the CRTs. Some of the emphasis circuits are controlled by the customer’s menu. As well as some of them being controlled by AI, (Artificial Intelligence). Communication from the Microprocessor and 30) respectively.

IA01 BBE Audio Control (Surround)

This chassis utilizes BBE Surround. Communication from the Microprocessor via pins (

) respectively.

ON THE TERMINAL PWB:

(Through the connector PST2)

IY01 3D Y/C

(IC mounted directly on the Terminal PWB). The 3D Y/C IC is a Luminance/Chrominance separator, as well as a 3D adder. Separation takes place digitally. Using advanced separation technology, this circuit separates using multiple lines and doesn’t produce dot pattern interference or dot crawl. The 3D effect is a process of adding additional emphasis signals to the Luminance and Chrominance. These signals relate specifically to transitions. Transitions are the point where the signal goes from dark to light or vice versa. The 3D adds a little more black before the transition goes to white and a little more white just before it gets to white. It also adds a little more white just before it goes dark and a little more dark just before it arrives. This gives the impression that the signal pops out of the screen or a 3D effect. The Microprocessor communicates with the 3D Y/C IC via I from the Microprocessor are pins (

pins (47 and 46) respectively.

IY01

40 SDA3

The Microprocessor also is able to turn on and off circuits within the 3D Y/C circuit determined by customer menu set-up.

IV01 A/V Selector

The A/V Selector IC is responsible for selecting the input source for the Main Picture as well as the source for the PinP or Sub picture. Communication from the Microprocessor via pins ( connector pins (13 and 12) respectively then to

IV11 DAC (Digital to Analog Converter)

This IC works controlling different switches via the DAC0, DAC1 and DAC2 control lines.

•

pin 7 controls the V. Sync selector

DAC0

DVI 1/2 via pin 9.

IV06

pin 6 controls the Y selector

DAC1

Media Card via pin 10.

•

pin 5 controls the V. Sync selector

DAC2

Sync selector

for the DVI 1/2/Media Card via pin 11.

IV06

Communication from the Microprocessor via pins ( to

pins (14 and 15) respectively.

IV11

IV03 Main/PinP Y Pr/Pb Selector

Any input that is in the Y Pr/Pb or Y Cr/Cb state, will have be selected by this IC. Both for the Main Picture and the PinP (Sub) picture. The Main/PinP Y Pr/Pb Selector IC selects the appropriate input between Components 1 or 2, DVI 1 or 2, ATSC Tuner and/or DVD Player, if provided. Communication from the Microprocessor via pins (

) to connector

SCL2

pins (15 and 14) to

PST2

I001

and

via pins (

31 SDA2

and

28 SCL2

C bus data and clock. The communications ports

39 SCL3

IV01

IV07

IV03

) to connector

pins (34 and 33) respectively.

for DVI 1/2 input via pin 9 and H Sync selector

IV07

for DVI 1/2 input via pin 10 and Y selector

for DVI 1/2/Media Card input via pin 11 and V.

IV07

31 SDA2

and

28 SCL2

pins (26 and 27) respectively.

28 SCL2

) to the Rainforest IC pins (28

) to the Audio Control IC pins (13 and

pins (17 and 16) to the 3D Y/C

PST2

30 SDA1

and

) to connector

29 SCL1

PST2

31 SDA2

) to the

for the

IV06

pins (15 and 14)

and

PST2

(Continued on page 4)

PAGE 02-03

Page 28

DP-3X MICROPROCESSOR DATA COMMUNICATIONS CIRCUIT EXPLANATION

IY04 Main Video Chroma Y Pr/Pb Switch IC

This IC is responsible for selecting the Main picture source. It will be either Composite NTSC Y and C or component Y Pr/Pb or Y Cr/Cb dependant upon the customer’s selection.

• This IC processes the NTSC Luminance (Y) and Chroma (C) from the 3D Y/C circuit for the main picture if

this is the selection. It receives the Y (pin 4) and C (pin 19) and prepares it for the Flex Converter by outputting it as Y (pin 24) Cr (pin 22) / Cb (pin 23) NTSC Only 480i component to the Flex Converter .

• This IC selects the Y (pin 30) Pr or Cr (pin 28) / Pb or Cb (pin 29) if this is the selection by the customer and

outputs it as Y (pin 24) Pr or Cr (pin 22) / Pb or Cb (pin 23) to the Flex Converter. If the output is 1080i, it’s

routed directly to the Rainforest IC I501. Communication from the Microprocessor via pins ( then to

Note: Y Pr/Pb indicates either 31.5Khz or 33.75Khz and Y Cr/Cb indicates 15.734KHz

IY03 Sub Video Chroma Y Pr/Pb Switch IC

This IC is responsible for selecting the PinP (Sub) picture source. It will be either Composite NTSC Y and C or component Y Pr/Pb or Y Cr/Cb dependant upon the customer’s selection.

• This IC processes the NTSC Luminance (Y) and Chroma (C) from the 3D Y/C circuit for the main picture if

this is the selection. It receives the Y (pin 4) and C (pin 19) and prepares it for the Flex Converter by output-

ting it as Y (pin 24) Cr (pin 22) / Cb (pin 23) NTSC Only 480i component to the Flex Converter .

• This IC selects the Y (pin 30) Pr or Cr (pin 28) / Pb or Cb (pin 29) if this is the selection by the customer and

outputs it as Y (pin 24) Pr or Cr (pin 22) / Pb or Cb (pin 23) to the Flex Converter. If the output is 1080i, it’s

routed directly to the Rainforest IC I501. Communication from the Microprocessor via pins ( then to

Note: Y Pr/Pb indicates either 31.5Khz or 33.75Khz and Y Cr/Cb indicates 15.734KHz

pins (13 and 14) respectively.

IY04

pins (13 and 14) respectively.

IY03

31 SDA2

and

28 SCL2

) to connector

pins (15 and 14)

PST2

pins (15 and 14)

PST2

PAGE 02-04

Page 29

SDA3

SCL3

DP-3X Chassis Microprocessor Data Communications

PST2

SDA3

SCL3

IY01

3D-Y/C

Terminal PWB

IOO1

Micro

PAGE 02-05

Data / Key Out 2

Clock / Key Out 1

SDA1

SCL1

SDA2

SCL2

DM RTS

DM CTS

DM TXD

DM RXD

POWER 2

FCData

FCEnable

Audio Control

Rainforest

Sweep Cont.

PMS1

20 7

35 6

36 5

52 4

IA01

I501

DM RTS

DM CTS

DM TXD

DM RXD

POWER 2

I010

Level Shift

UD2003

Digital Module

ATSC Tuner

146

SDA2

SCL2

SDA1

SCL1

SDA2

SCL2

SDA1

SCL1

PFC1

FCData

FC Enable

FC Clock

SDA1

SCL1

SDA2

SCL2

3413

U401

SDA1

IV01

A/V Select

SCL1

SDA1

IOO3

EEPROM

SCL1

SDA2

SCL2

SDA2

FC04

FLEX

PinP

U301

Tuner

Main

U302

Tuner

PinP

Main/PinP

IV11 DAC

14 15

IV03

Y Pr/Pb

SELECTOR

26 27

IY04 Main

Video/Chroma

Y Pr/Pb SW

13 14

SIGNAL PWB

MODE Power _1 Power _2

Stand B y Lo Lo

Timer Lo Hi

TV On Hi Hi

When the Timer is set for an unattended

Recording, the Set turns on the Tuner and

allows the "Video Out (Monitor out) to

become active so that a recording can be

made without turning on the entire set.

IY03 Sub

Video/Chroma

Y Pr/Pb SW

13 14

Page 30

DP-3X AUDIO VIDEO MUTE CIRCUIT EXPLANATION

(See DP-3X Series Chassis Audio Video Mute Circuit Diagram for details)

There are times in which the main picture and audio must be muted. This can be because of changing channels where the noise between stations is unacceptable, same thing for Auto Programming channels. When the deflection circuit malfunctions, etc… All this is done primarily to prevent damage to the CRTs or to external amplifiers or speakers connected to the projection television.

MICROPROCESSOR OUTPUT:

The Microprocessor high is routed to the Video and Audio Mute circuit.

VIDEO MUTE PATH.

The High fr om pin 49 is routed to VATION here forward, please use the below explanation when Mute Activation is mentioned.

• MUTE ACTIVATION:

1. When

2. Another route for the high from

3. Another route for the high from

SPOT:

Another circuit attached to the Mute Activation circuit ( deflection PWB when either Horizontal or Vertical deflection is lost. This is to prevent a horizontal or vertical line from being burnt into the CRTs. See Horizontal and Vertical Sweep Loss Detection circuit and explanation and circuit diagram for details. This high is input from

. See the Mute Activation circuit explained previously.

Q529

H Blk Loss Det:

Another circuit attached to the Mute Activation circuit ( If the Horizontal Blanking signal is loss to the Signal PWB, plied with H. Blanking on it’s base. By the activity of the pulse charging it’s emitter are held high keeping it turned off. If H. Blk is lost, then blocked by

to the base of

D508

AUDIO MUTE PATH:

See the Mute Activation circuit explained previously as to how When Mute Activation is turned on, the following circuits are activated.

CRT MUTE PATH:

The high from to the following diodes, PWB. When the diodes are supplied with a low on their cathodes, they remove the base voltage fro the RGB drivers,

Q853, Q803

Q529

to the HVcc 9.3V line through routed to the following circuits. Through This pin is also the same pin that FC H Blk and FC V Blk is input. Generally this input is a positive going pulse that blanks the video during the peak pulses which represent retrace. However, when the DC component is forced high by the action of RGB.

the Terminal PWB. This turns on Monitor Out on the Terminal PWB.

and outputs the high from it’s emitter to mute the Audio described later.

and it holds the emitter of

D509

Q527

outputs V. Mute from pin

I001

to the base of

D507

turn on, the collector pulls the base of

and

R5A5

is through

Q528

QV08

is through

Q528

Q525

. See the Mute Activation circuit explained previously.

Q529

Labeled as V MUTE 2: (Emitter of Q527 Mute Activation Circuit)

Shown going to the CRT PWB. Labeled a s V MUTE 1:

is routed to

on the Green CRT PWB,

D853

and

Q8A3

pin 11. This high go es to

PSC

on the Green, Red and Blue CRT PWBs. This shuts off each CRT Drive.

See next page for continuation of Audio Mute Circuit explanation.

when changing channels, Auto Programming, etc… This

. The following actions will be labeled MUTE ACTI-

Q529

low and turns it on. It’s collector is connected

Q528

. When

D510

R564, D503

turning on, t his pin goes high and mutes the output of

Q528

D406

and

high. This action turns on

which grounds out the Audio Outputs from the

QV09

R5A1

base) is

Q529

pin (4), through

PPD3

base) is

Q529

Q525

on the Red CRT PWB

D803

turns on, it’s collector goes high. This is

Q528

, and

. This high continues to the

to the base of

will detect the loss. Normally,

Q527

Q856

and into the Rainforest IC

R561

Q527

This signal is generated from the

SPOT.

pin (4),

PPS3

H Blk Loss Det.

and

C546

will discharge through

C546

is turned on.

base. This turns on and supplies a ground

C545

and supplies a high through

Q525

pin 39.

I501

connector on

PST1

. This transistor turns On

to the base of

D511

is sup-

Q526

, the base of

on the Blue CRT

D8A3

R599. C545

Q525

and

PAGE 02-06

Page 31

DP-3X AUDIO VIDEO MUTE CIRCUIT EXPLANATION

FRONT AUDIO OUT H A RD MUTE PATH:

• The high from

base of dio Out. (Note: This is not the same thing as the Mute selected fro m the customer’s re mote. This is controlled by the Front Audio Control IC 1/2 Mute = 50% and Full Mute = 0%.

OUT TO HI-FI MUTE PATH:

and then to the cathodes of they grounds the Right and Left audio for the Out to Hi-Fi audio output jacks.

FRONT AUDIO OUT MUTE:

V MUTE 1:

High is sent to the following 4 circuits:

1. To the Front Audio Out Hard Mute circuit routed through

2. The high is also route d through they ground the audio going into the Audio Output IC of the

CRT Mute:

Out to Hi-Fi Mute Path:

and then to the cathodes of turns on, they ground the audio going into the audio for Out to Hi-Fi audio output jacks.

A MUTE PATH: (Microprocessor Pin 71)

A MUTE:

This High is sent to the following 3 circuits:

Front Audio signal mute:

and to the base of the Audio Output IC of

Main Tuner U301 Mute:

Tuner

Out to Hi-Fi Mute Path:

and then to the cathodes of turns on, they ground the audio going into the audio for Out to Hi-Fi audio output jacks.

REC MUTE PATH: (Microprocessor Pin 70) Record Mute signal path.

connector on the Terminal PWB. Here it is routed to

PST1

. When this line goes high, the Audio Left and Right is muted coming from the monitor o utputs. The DP-

QV09

36 utilizes a Digital Tuner (ATSC). The ATSC tuner also outputs NTSC video and Audio which is routed to the Monitor outputs for VCR recordings. When the ATSC tuner (Antenna C) changes channels, the aud io is muted briefly to avoid the unnecessary noise during switching. Note too that the DP-36 does not utilize D406 like all the other chassis.

FRONT SPEAKER OFF: (IA01 Pin 17)

Front Speaker Off signal.

1. It goes to sistor turns on, it supplies a Lo to pin 11 of

2. It goes through audio going into the Audio Output IC connector to pin 4 of

QAA2.

The high from the Microprocessor pin 49 to

connector to pin 4 of

PPS4

See CRT Mute Path explanation above.

Also, the high from the Microprocessor pin 71 to

. Left audio in pin 3 of the

IAA1

. This high mutes the Audio and Video outputs from the Tuner.

U301

DA07

is routed to

Q527

When this transistor turns on, it supplies a Lo to pin 11 of

The high from the Mute Activation circuit is also routed to the anode of

and

DA51

QA01,

IAA1

This pin is only used in the DP-36 chassis. It is routed through

to the

to the base of

DA05

IAA1

DA52

Labeled as V MUTE 1 (Microprocessor Pin 49)

DA03

The high from the Level shifter

DA51

The high from the Level shifter

and

QA02.

at the

The high from the Level shifter

DA51

The high from the Audio Control IC

connector pin 4. The high co nt inues to the ba se of

PPS4

. Left audio in pin 3 of the

the through the

DA06

internally and functions in three states, No Mute = 100%,

IA01

to the base of

. Left audio in pin 3 of the

IAA1

and

DA52

When these transistor turns on, they ground the audio going into

connector. Right audio in pin 2 of the

PPS4

connector to pin 2 of

PPS4

and

DA52

QA01,

IAA1

QA51,

I010

QA01,

to the base of

DV02

and hard mutes the Audio Out.

IAA1

and

QA02.

at the

PPS4

connector pin 4. The high continues to the

PPS4

and

QA54.

(in pin 3 at 3.3V and out pin 17 at 5V). This

DA06

and

at the

IAA1

I007

QA51,

(in pin 7 at 3.3V and out pin 13 at 5V).

I007

QA51,

and

DV03

IA01

When these transistor turns on, they ground the

connector. Right audio in pin 2 of the

connector to pin 2 of

When these transistor turns on,

. (Described above)

QA02.

pin 13 is routed to the anode of

IAA1

pin 13 is routed to pin 25 of the Main

pin 13 is routed to the anode of

When these transistor turns on,

PPS4

and

QA54.

pin 13 is routed to the anode of

and

QA54.

and then to the bases of

pin 17 goes to 2 circuits:

and hard mutes the Au-

IAA1

DA54

connector. Right audio in pin 2

connector to pin 2 of

When these transistor

connector to pin 4

PPS4

When these transistor

to pin 38 of the

D405

QV08

QAA2.

When this tran-

IAA1

DA53

DA04

DA53

PPS4

and

PAGE 02-07

Page 32

NOTE:

V MUTE 1 becomes V MUTE 2 on Signal PWB 2 & 3 Then V MUTE 1 again on CRT PWB

Turns on Q856

which removes base drive for R, G and B drivers.

Simply grounds out Audio

coming from the Monitor

Outputs.

Rec Mute To QV08, 09

Terminal PWB

V MUTE 1

CRT PWB

PSC

PST1

DP-3X Series Chassis AUDIO and VIDEO MUTE Circuit

FC H Blk

Q523

HVcc 9.3V

R597

C546

D516

D405

R5K6

DP-36 Only

D406

All Chassis But the DP-36

D507

D508

V MUTE

C545

R564

D503

Q525

R555

D509

R598

Q526

R599

Q522

R561

565

R5AD

D511

PPS3

FC V Blk

FBP In

PPD3

Power PWB

I501

Rainforest

H Blk

Deflection

PWB

Spot

JA01

Out To

Micro Processor

CA54

CA51

Hi-Fi

I001

Rec Mute

V MUTE

PAGE 02-08

A MUTE

MAIN TUNER

CA55

CA52

QA51

RA55

QA54

RA66

49 71 7

U301

A MUTE

DA51

DA52

I010

Level

Shift

DA54

V MUTE 1

17 13

A MUTE

Right

Left

DA53

HVcc 9.3V

R5A5

Q527

V MUTE 2

SPK OFF

17 23

IA01

Ft. Audio Control

DA05 DA04 DA03

D510

R5A1

CA06

QA01

CA19

RA10

DA06

RA11

Q528

DA07

R5A3

PPS4

QA02

C547

Q529

2 3

RAA7

RAA8 Right

Left

R5A4

R5A7

R546

QAA2

CAC4

RAA2 RAA1

"SPOT"

Horizontal Sweep Loss Det.

Vertical Sweep Loss Det.

(From Deflection PWB)

See Sweep Loss Detection

Circuit Diagram for details

RAA4

CAC5

CAA4

CAA2

Mute = Lo

Mute

IAA1

R In R Out

L In L Out

FRONT L & R

Audio Output

Page 33

DP-3X MICROPROCESSOR NTSC SYNC INPUT CIRCUIT EXPLANATION

NTSC SYNC CIRCUIT DIAGRAM. (See NTSC Sync Circuit Diagram for Details)

The Microprocessor tion, Customer’s Menu, Service Menu, etc….. The Chassis feeds back this information in the form of Blanking pulses and Sync from the Video. The following describes the types of feedback sync signals. The following describes the pins on the Microprocessor.

(62) H BLK (Horizontal Blanking):

• H Blk is input to the Microprocessor at Pin 62. H Blk is generated from the Deflection Transformer pulse off pin 7 of Then out the gets level shifted and inverted and into pin 62 of the Microprocessor.

(64) V BLK (Vertical Blanking):

• V Blk is input to the Microprocessor at Pin 64. V Blk is generated from the Vertical Output IC

. Then routed out the

to the Signal PWB. From here it is sent to the base of into pin 64 of the Microprocessor.

(93) MAIN AFC (Automatic Frequency Control):

• Main AFC is input to the Microprocessor at Pin 93. Main AFC is generated from the Main Tuner pin 16. Then routed to

The Microprocessor uses this input signal to align or adjust the precise Oscillator and Programmable divider settings within the Main Tuner for proper Reception.

(92) SUB AFC (Automatic Frequency Control for PinP Tuner):

• Sub AFC is input to the Microprocessor at Pin 92. Sub AFC is generated from the Sub Tuner

. Then routed to

The Microprocessor uses this input signal to align or adjust the precise Oscillator and Programmable divider settings within the PinP Tuner for proper Reception.

(100) MAIN CCD IN:

• The Microprocessor receives Main Sync information and strips the Closed Caption Data from line 21. This composite sync signal is supplied to the Microprocessor from stripping V Chip Data.

• When an NTSC component input is supplied to Input 2, this is called 480i. This must also be monitored for Closed Caption data and for V. Chip Data. If Input 2 is selected and it is 480i (NTSC), then the Microprocessor outputs a Main CCD Select signal from pin 73 to

• NOTE: Component inputs other than 480i (NTSC) are not able to display Closed Caption Data.

(97) Sub CCD IN:

• The Microprocessor receives Sub Sync information and strips the V Chip Data. This composite sync signal is supplied to the Microprocessor from

• When an NTSC component input is supplied to Input 2, this is called 480i. This must also be monitored for V. Chip Data. If Input 2 is selected as PinP source and it is 480i (NTSC), then the Microprocessor outputs a Sub CCD Select signal from pin 74 to

(23) M/S Sync Det (Main / Sub Sync Detection):

• The composite sync signal from either Main or PinP (Sub) is supplied to the Microprocessor from pin 4. The Microprocessor uses the Sync signal to activate the AFC loop, and for Auto Programming. When the channels are changed for the PinP Tuner, the Microprocessor outputs a short control signal from pin 25 (SD Sel) to this IC outputs the Main composite sync signal input on pin 3.

must have Sync inputs from the Chassis to Lock it’s generation of OSD, Closed Cap-

I001

, wave shaped by

T701

connector pin 8 to the Signal PWB. From here it is sent to the base of

PPS3

connector pin

PPD3

and

Q041

and

Q035

I008

pin 9.

Q036

I009

. Then routed out the

Q706

to the Power Supply. Then out the

where it gets level shifted and inverted and

Q026

. Then into pin 93 of the Microprocessor.

Q042

. Then into pin 92 of the Microprocessor.

I008

pin 15.

I008

pin 10 to select 480i input at pin 1.

I008

then outputs the Sub composite sync signal input on pin 5. Normally

connector pin 8 to the Power Supply.

PPD3

Q025

connector pin

PPS3

pin 14. It uses this same input for

I008

pin 11 to select 480i input at pin 13.

where it

I601

U301

U302

I008

PAGE 02-09

Page 34

V4 8

PAGE 02-10

DP-3X SERIES CHASSIS MICROPROCESSOR NTSC SYNC INPUT CIRCUIT DIAGRAM

PST1

U301

Main Tuner

U302

Sub Tuner

UD2002

Digital Module

Front Control PWB

Aux 5 Video V3V

Aux 5 S-Y V3Y

Aux 5 S-C V3C

S-5 Det.

Aux 3 Video

Aux 3 S-Y

Aux 3 S-C

S-3 Det.

Aux 4 Video

Aux 4 S-Y

Aux 4 S-C

S-4 Det.

Input 2

Input 1

PFT

Composite 2

480i Only

DM Y

DM C

S-4

S-3

S-2

IV01

2811

Selector IC

Composite

QV02QV01

Main Y

/Video

Sub Y

/Video

480i

Input 2

V5 In

Terminal PWB

QV18

Q012QV13

Q014

39 2

Q016

Y In (480i)

PiP Video and Sub Video are the same.

Main

Sub

480i

Sub

480i

Main

For 480i

Y Component

Only for CCD

& V Chip

NTSC Only

IX02

Separation Circuit Diagram

See Component Sync

Q025

Q026

Q041

Q035

Q042

Q036

SIGNAL PWB 1 of 2

I008

Lo Hi

I001

Main CCD Sel

Sub CCD Sel

SD Sel

Main CCD In

Sub CCD In

M/S Sync

HBlk

VBlk

Main AFC

Sub AFC

Micro

Processor

Q010

SW +9V

Det

Q005

Q009

Q007

Q006

Q003

Q008

Q004

Main CCD Infor CCD & V Chip

100

Sub CCD In for V. Chip Data

M/S Sync Det. (Main/Sub) Used for AFC during Channel tuning and Auto Programming

Page 35

VIDEO

INFORMATION

DP-3X

CHASSIS INFORMATION

SECTION 3

Page 36

DP-3X BLANK PAGE “NOTES”

BLANK PAGE

Page 37

DP-3X CHASSIS VIDEO SIGNAL PATH NTSC EXPLANATION

(See Video Signal Path-NTSC Diagram for details)

It’s important to note that this Chassis horizontal deflection operates at 33.75Khz at all times. Even though this is more than twice as fast as NTSC, the set will still display NTSC video with no problem. This is accomplished by the Flex Converter. The Flex Converter will manipulate any input, be it NTSC, Component 480i, 480P, 720P to the appropriate Horizontal Frequency rate of 33.75Khz. This makes this chassis very versatile in it’s application. Note: 1080i is already 540 in the native state. In this case, true 1080i does not need to be routed through the Flex Converter. It’s routed directly into the Rainforest IC.

The following will discuss the signal flow as show in the above listed Circuit Diagram.

TUNER INPUTS:

These sets utilizes two tuners, (DP-36 and DP-38 also have an ATSC Digital Tuner UD2002) one for the Main picture U301 and one for the PinP (Sub) picture U302. U301 is an intergraded tuner with RF front end, IF decoding, Audio Decoding to Lt/ Rt. The tuner communicates with th e Microprocessor via I2C bus. (See Microprocessor Data Communications Circuit Diagram for details). The PinP tuner U302 is also an intergraded tuner, however the Audio output is mono only. Both tuners output their respected composite video via pin 18.

•

U301 Main Tuner Output pin 18 to PST1 connector pin 50, to the Selector IC IV01 pin 63.

•

U302 PinP (Sub) Tuner Output pin 18 to PST1 connector pin 45, to the Selector IC IV01 pin 60.

(DP-36 and DP-38 ONLY):

•

UD2002

◊

LUMINANCE: The ATSC (QAM) Tuner (Digital Tuner) Outputs DM Y from pin 7 to the PST1 connector pin 31, to the Selector IC IV01 pin 3.

◊

CHROMINANCE: The ATSC (QAM) Tuner (Digital Tuner) Outputs DM C from pin 5 to the PST1 connector pin 32, to the Selector IC IV01 pin 5.

These inputs are used while viewing an SDTV or HDTV source, so that there will be an output from the Monitor Video Jack. NOTE: The DP-36-38 have a Digital Tuner (ATSC-8VSB and Cable QAM Tuner) is in the Digital Module. This Digital Module is also the input/output access for IEEE1394. (See the ATSC Block Diagram which is coming up after the Component, OSD and NTSC Diagra m ). Even though this explanation is related to NTSC, the ATSC tuner is involved because of the Video Output called (Monitor Out) jack. When ATSC or QAM is viewed, the monitor out must have video output for recording purposes. This is accomplished by the ATSC (Digital Tuner) having a Y/C output sent to the NTSC circuit for this purpose.

AUXILIARY INPUT: This chassis utilizes 5 separate inputs plus a newly added input called DVI. The following will break down those input routes to the Selector IC IV01. (Some models will also have a built in DVD player for 6th input). (1) INPUT 1: This input is only for Component Inputs Y Pr/Pb (31.5Khz to 33.75Khz ATSC) and will not accept Compos-

ite on the Y input. Input one’s Y line is input directly into IV04 pin 9 (Y Pr/Pb Selector), not for NTSC.

(2) INPUT 2: This input will accept Component Inputs Y Pr/ Pb (31.5Khz to 33.75Khz ATSC) or Y Cr/Cb (15,735Hz.

NTSC). It will also accept Composite Video input as long as there is no Pr plug inserted. Input 2 is routed into the Selector IC IV01 pin 30.

(3) INPUT 3: This is NTSC composite input only. It also has an accompanying S-Input. Remember that the S-Input takes

priority over composite input, when S-Input is active. Input 3 is routed into the Selector IC IV01 pin 15. The S-Input inputs are pin 17 for Y (Luminance) and pin 19 for C (Chroma). When an S-Jack is inserted into the plug, an i nternal mechanical switch is activated which produces a lo w to the Selector IC IV01 pin 21 and the Selector IC notifies the Microprocessor that and S-Jack i s installed.

(4) INPUT 4: This is NTSC composite input only. It also has an accompanying S-Input. Remember that the S-Input takes

priority over composite input, when S-Input is active. Input 4 is routed into the Selector IC IV01 pin 8. The S-Input inputs are pin 10 for Y (Luminance) and pin 12 for C (Chroma). When an S-Jack is inserted into the plug, an internal me- chanical switch is activated which produces a low to the Selector IC IV01 pin 14 and the Selector IC no tifies the Microprocessor that and S-Jack is i nstalled.

(5) INPUT 5: On the Front Control Panel. This is NTSC composite input only. It also has an accompanying S-Inpu t . Re-

member that the S-Input takes priority over composite input, when S-Input is active. Video Input 5 is routed through the PFT connector pin 2, into the Sele ctor IC IV01 pin 22. The S-Input inputs are routed through the PFT connector pin 7 for Y and pin 9 for C, into the Selector IC IV01 pin 24 for Y (Luminance) and pin 26 for C (Chroma). When an S-Jack is inserted into the plug, an internal mechanical switch is activated which produces a low through the PFT connector pin 11, into the Selector IC IV01 pin 28 and the Selector IC not ifies the Microprocessor that and S-Jack is installed.

(Continued on page 03-02)

PAGE 03-01

Page 38

DP-3X CHASSIS VIDEO SIGNAL PATH NTSC EXPLANATION

(Continued from page 03-01)

MONITOR OUT FROM IV01: Composite video is output pin 41. S-Out Y pin 39, S-Out C pin 37.

COMPOSITE VIDEO PATH:

When a composite input is selected, it must be broken down into it respective parts, Y and C. This is accomplished for the Main video by the 3D Y/C and for the PinP (Sub) picture by the 2-Line Comb filter. MAIN: The Main composite output is routed out of the Selector IC IV01 pin 44 to QV14. Then through the video low pass filter comprised of QY01, QY02, and QY04. It arrives at the 3D Y/C chip IY01 pin 93. Here the composite video is separated into Y/C 3D enhanced, and output on the following pins, Y from pin 89 and C from pin 86. NOTE: Sync for the Microprocessor is routed out pin 44 of IV01 to QV13.

Y COMPONENT FROM THE 3D Y/C (For Composite In). The Y component is then routed through a low pas filter comprised of QY09, LPF XY01, QY10, and QY12 into the Main Video/Chroma Processor IC IY04. Note too that the Y component is also routed into the PinP (Sub) Video/Chroma Processor IC IY03 pin 2. This is for when the customer presses the Swap button when the PinP Sub window is on.

C COMPONENT FROM THE 3D Y/C : (For Composite In). The C component is then routed through a low pas filter comprised of QY13, LPF XY02, QY14, and QY15. Then the chroma must be routed through the TILT circuit. This circuit compensates for the phase relationship of flesh tones between composite and component. This circuit is comprised of QY16 and QY17. Not shown is the switch that enables this phase rotation circuit. The output control is from the selector IC IY04 pin 8 to QY19. From QY17 the Chroma component is routed into pin 16 of the Main Video/Chroma Processor IC IY04. Note too that the Chroma component is also routed into the PinP (Sub) Video/ Chroma Processor IC IY03 pin 16. This is for when the customer presses the Swap button when the PinP Sub window is on.

S-INPUT 3, 4 and/or 5:

When the S-Input is selected, it is already separated into Y and C components. In this case, Y is routed directly into the Main Video Chroma Processor IY04. It is output from the Selector IC IV01 pin 44, through QV14 and into the Main Video Chroma Processor IY04 pin 4. The Chroma component is output from the Selector IC IV01 pin 47, through QV16, QV17, and into the Main Video Chroma Processor IY04 pin 19. The responsibility of IY04 is to now convert the Y/C components of the Main picture into a usable format for the Flex Converter. The Flex Converter FC4 utilizes component inputs Y Pr/Pb or Y Cr/Cb. IY04 outputs only NTSC, so it’s outputs are Y Cr/Cb. Y from pin 24, Cr from pin 22, and Cb from pin 23. Y is then routed through QY29 to the connector PST2 pin 40. Cr is then routed through QY30 to the connector PST1 pin 37. Cb is then routed through QY28 to the connector PST1 pin 38. (See the Component Video Signal Path for continuation).

PinP (Sub) Video Path:

The PinP (Sub) composite video is output from the Selector IC IV01 pin 53, through QV23, QV24, and into the 2-Line Comb Filter IV02 pin 4. It is separated into it’s individual Y/C components. The Y (Luminance) component of the PinP (Sub) picture is then output pin 15, through QV25, low pass filter XV01, through QV26, QV28 and back into the Selector IC IV01 pin 49. The C (Chroma) component of the PinP (Sub) picture is then output pin 13, through QV29, low pass filter XV02, through QV30, QV32 and back into the Selector IC IV01 pin 51.

From here, the Selector IC IV01 dependant upon the customer’s selection, will choose between the separated Y/C from composite or the separated inputs S-In and outputs the Y from pin 56 through QV19, QV20 into the PinP (Sub) Video/Chroma Processor IY03 pin 4. The C component from pin 58 through QV21, QV22 into the PinP (Sub) Video/Chroma Processor IY03 pin 19. IY03 FUNCTION: The responsibility of IY03 is to now convert the separated Y/C components of the PinP (Sub) picture into a usable format for the Flex Converter. The Flex Converter FC4 utilizes component inputs Y Pr/Pb or Y Cr/Cb. IY03 outputs only NTSC, so it’s output are Y Cr/Cb. Y from pin 24, Cr from pin 22, and Cb from pin 23. Y is then routed through QY22 to the connector PST2 pin 29. Cr is then routed through QY24 to the connector PST2 pin 26. Cb is then routed through QY23 to the connector PST2 pin 27.

(See the Component Video Signal Path for continuation).

NOTE: The DVI input signal flow is shown in the Component Video Signal Path Circuit Diagram. NOTE: Models using the DVD Player is also shown in the Component Video Signal Path Circuit Diagram.

PAGE 03-02

Page 39

SIGNAL PWB

U301

Main Tuner

U302

Sub Tuner

UD2002

Digital Module

Front Control PWB

See Component Signal Path for Component 1 Y Pr/Pb and 480i Y Cr/Cb

Component 1 Y

Aux 5 Video V3V

Aux 5 S-Y V3Y

Aux 5 S-C V3C

S-5 Det.

Y Pr/Pb Select

Aux 2 Video

No Pr Plug = Composite

Aux 3 Video

Aux 3 S-Y

Aux 3 S-C

S-3 Det.

Aux 4 Video

Aux 4 S-Y

Aux 4 S-C

S-4 Det.

PAGE 03-03

Monitor Out Video

MON

OUT

Must be S-In for S-Out

Monitor Out S-Y

Monitor Out S-C

IV04

PST1

PFT

DP-3X CHASSIS VIDEO SIGNAL PATH - NTSC

SEE DVI and DVD SIGNAL PATH DIAGRAM for DVI and DVD FLOW

QV24

QV25QV26QV28

QV29QV30QV32

QV20

DM Y

DM C

2811

V Out 1

S-4

Y In 1

C In 1

Y Out 1

SUB OUT

C Out 1

QV18

QV23

XV01 23

XV02

QV19

QV21 QV22

See Micro.

Sync Path

IV01

A/V Select

QV13

See Micro.

QY17

QY16

Sync Path

3DV

QY01

VIDEO LPF

S-1

S-3

S-2

V Out 3

Y Out 3

C Out 3

MAIN

OUT

V/Y

Out 2

MON

OUT

QV14

QV17

QV16

Chroma Tilt

Correction

TERMINAL PWB

Y2 In

C2 In

Y1 In

C1 In

QY29

Main Y

QY04QY02

Y LPFY AMP

XY01QY10QY12

C LPFC AMP

XY02QY14QY15

V In

Y Out

C Out

QY28

QY30

IV02

2Line Y/C

Separator

IY03 Sub

Sub Cr Out

Sub Cb Out

Sub Y Out

16 C1

QY09

QY13

TERMINAL PWB

For PinP Only

Sub Video/Chroma

Processor

QY24

QY23

QY22

IY04

Video/Chroma

Processor

V In

Y Out AYO

C Out ACO

Main Cr Out

Main Cb Out

Main Y Out

PST2

-6db

MAIN

IY01

3D Y/C

Separator

Component, OSD for continuation.

See the Video Signal Path-NTSC,

Page 40

DP-3X CHASSIS COMPONENT EXPLANATION

See the DP-3X Chassis Component Video Signal Path for details. Also see Video Signal Path (NTSC) Circuit Diagram for details about NTSC

It’s important to note that this Chassis horizontal deflection operates at 33.75Khz at all times. Even though this is more than twice as fast as NTSC, the set will still display NTSC video with no problem. This is accomplished by the Flex Converter. The Flex Converter will manipulate any input, be it NTSC, Component 480i, 480P, 720P to the appropriate Horizontal Frequency rate of 33.75Khz. This makes this chassis very versatile in it’s application. 1080i is already 540 so it’s routed directly into the Rainforest IC I501.

The following will discuss the Component signal path and the continuation of the NTSC signal path. This chassis utilizes 6 separate inputs which also include 2 DVI inputs plus a New Photo Media card reader. The following will break down those input routes to the Y Pr/Pb Selector IC IV03. DVD Player (not shown)

(1) COMPONENT INPUT 1: This input is only for Component Inputs Y Pr/Pb (31.5Khz to 33.75Khz ATSC)

and Y Cr/Cb (15,735Hz 480i NTSC) but will not accept Composite on the Y input.

• The Y line is input directly into the Y Pr/Pb Selector IV04 pin 9.

• The Pr/Cr line is input directly into the Y Pr/Pb Selector IV04 pin 1.

• The Pb/Cb line is input directly into the Y Pr/Pb Selector IX02 pin 14.

(2) COMPONENT INPUT 2: This input will accept Component Inputs Y Pr/ Pb (31.5Khz to 33.75Khz

ATSC) or Y Cr/Cb (15,735Hz. 480i NTSC). This will accept Composite Video on the Y input as long as there is no Pr plug inserted.

• The Y line is input directly into the Y Pr/Pb Selector IV07 pin 9.

• The Cr/Pr line is input directly into the Y Pr/Pb Selector IV07 pin 1.

• The Cv/Pb line is input directly into the Y Pr/Pb Selector IV07 pin 14.

• Input 2 Composite Video is routed into the Selector IC IV01 pin 30.

(3) DVI 1 INPUT (Digital Video Interface): This input will accept Component Inputs Y Pr/ Pv (31.5Khz to

33.75Khz ATSC) only. (See DVI Signal Path for further details).

• The G line is input from the PET connector pin 14 into the Y Pr/Pb Selector IV04 pin 8.

• The R line is input from the PET connector pin 12 into the Y Pr/Pb Selector IV04 pin 16.

• The B line is input from the PET connector pin 16 into the Y Pr/Pb Selector IV04 pin 11.

(4) DVI 2 INPUT (Digital Video Interface): This input will accept Component Inputs Y Pr/ Pv (31.5Khz to

33.75Khz ATSC) only. (See DVI Signal Path for further details). (Only in the DP37D Chassis).

• The G line is input from the PET connector pin 5 into the Y Pr/Pb Selector IV05 pin 8.

• The R line is input from the PET connector pin 3 into the Y Pr/Pb Selector IV05 pin 16.

• The B line is input from the PET connector pin 7 into the Y Pr/Pb Selector IV05 pin 11.

(5) DIGITAL TUNER (ATSC) UD2002 INPUT: These inputs are provided from the Digital Tuner (ATSC).

The ATSC Tuner outputs DM-Y, DM-Pb and DM-Pr. (Only in the DP36 Chassis).

•

DM-HY (Luminance) from PMS2 pin 11, through PST1 pin 31 to Y Pr/Pb Selector IV0 pin 15.

•

DM-Pb (Blue Chroma) from PMS2 pin 9, through PST1 pin 25 to Y Pr/Pb Selector IV03 pin 17.

•

DM-Pr (Red Chroma) from PMS2 pin 7, through PST1 pin 26 to Y Pr/Pb Selector IV03 pin 19.

NOTE: When receiving a SDTV or HDTV signal, the Digital Module also outputs Composite Video/ Chroma for Monitor Output. (See NTSC Signal Path for specifics).

(6) PHOTO MEDIA CARD READER: DP-37/C/D. (Access on the front). Note: DP-36 Photo Card reader is

fed directly into the Digital Module.

•

Y (Luminance) from Card Reader, through PTB in 6 to Y Pr/Pb Selector IV03 pin 53.

•

Pb (Blue Chroma) from Card Reader, through PTB in 2 to Y Pr/Pb Selector IV03 pin 55.

•

Pr (Red Chroma) from Card Reader, through PTB in 4 to Y Pr/Pb Selector IV03 pin 57.

Picture File names must be 8 characters only, 4 characters Alpha and 4 characters numeric. MAIN COMPONENT VIDEO PATH from IV03:

The following describes Main Component outputs from the Y Pr/Pb Selector IV03.

•

Y pin 44, to QV33, to Main Video/Chroma Y Pr/Pb Switch IY04 pin 30 and 6.

•

Pr pin 40, to QV35, to Main Video/Chroma Y Pr/Pb Switch IY04 pin 28.

•

Pb pin 42, to QV34, to Main Video/Chroma Y Pr/Pb Switch IY04 pin 29.

(Continued on page 5)

PAGE 03-04

Page 41

DP-3X CHASSIS COMPONENT EXPLANATION

FROM MAIN COMPONENT VIDEO PATH from IY04:

The following describes Main Component outputs from the Video Chroma Y Pr/Pb Switch IY04.

•

Y pin 24, to QY28, to PST2 connector pin 40, at this point the signal splits;

•

To Q401 to U401 Flex Converter pin 3.

•

To Q505 to I501 RGP Processor (Rainforest) pin 63.

•

Pr pin 22, to QY30, to PST2 connector pin 37, at this point the signal splits;

•

To Q403 to U401 Flex Converter pin 5.

•

To Q507 to I501 RGP Processor (Rainforest) pin 60.

•

Pb pin 23, to QY29, to PST2 connector pin 38, at this point the signal splits;

•

To Q402 to U401 Flex Converter pin 4.

•

To Q506 to I501 RGP Processor (Rainforest) pin 61.

Note: The reason the signal splits here is because if the signal is 1080i (540) it is sent directly into the Rainforest IC because it needs no conversion since it’s the same frequency as the deflection circuit.

SUB COMPONENT VIDEO PATH from IV03:

The following describes PinP Component outputs from the Y Pr/Pb Selector IV03.

•

Y pin 50, to QV36, to Main Video/Chroma Y Pr/Pb S witch IY03 pin 30 and 6.

•

Pr pin 46, to QV38, to Main Video/Chroma Y Pr/Pb Switch IY03 pin 28.

•

Pb pin 48, to QV37, to Main Video/Chroma Y Pr/Pb Switch IY03 pin 29.

SUB (PinP COMPONENT VIDEO PATH from IY03:

The following describes PinP Component outputs from the Video Chroma Y Pr/Pb Switch IY03.

•

Y pin 24, to QY22, to PST2 connector pin 29, to U401 Flex Converter pin 17.

•

Pr pin 22, to QY24, to PST2 connector pin 26, to U401 Flex Converter p i n 19.

•

Pb pin 23, to QY23, to PST2 connector pin 27, to U401 Flex Converter pin 18.

MAIN SIGNAL FROM FLEX CONVERTER U401:

The Flex Converter outputs only one horizontal frequency and that is 33.75Khz (540P) which relates specifically to 1080i deflection rate. So in other words, all inputs NTSC, 480i, 480P, 720P, 1080P are upconverted to the higher deflection rate. 1080i is routed directly to the Rainforest IC I501 and has no need for Flex Converter manipul at i o n.

This can be a trouble shooting tool if the Flex Converter is suspected as having problems.

Simply input a true 1080i signal and the set automatically bypasses the Flex Converter. The PinP is added inside the Flex Converter if selected.

•

Y pin 16, to Q510, and into the Rainforest IC pin 68 of I501. Pr pin 20, to Q508, and into the Rainforest IC pin 66 of I501.

•

Pb pin 18, to Q509, and into the Rainforest IC pin 67 of I501.

•

RAINFOREST IC I501 OUTPUTS:

This IC processes the input signal source, adjust brightness, contrast, color, tint, etc… and adds OSD information and outputs the Main Picture as R, G and B.

Green is output pin 13 to Q541, 42, 43 and 44 to the PSC connector pin 7 then to the Green CRT.

•

Red is output pin 12 to Q537, 38, 39 and 40 to the PSC connector pin 5 then to the Red CRT.

•

Actually this signal first arrives at the Green CRT then it’s routed to the Red CRT. Blue is output pin 14 to Q545, 46, 47 and 48 to the PSC connector pin 9 then to the Blue CRT.

•

Actually this signal first arrives at the Green CRT then it’s routed to the Blue CRT.

OSD:

(See Digital Convergence Interface Circuit Diagram Explanation for details).

PAGE 03-05

Page 42

DP-3X Chassis Component Video Signal Path

See

DVI Input

Signal Diagram

1 0F 2

PET

DVI1 R

DVI1 G

DVI1 B

14 16

See

DVI Input

Signal Diagram

2 0F 2

DP-37D

DVI2 G

Only

DVI2 R

DVI2 B

PET

3 5

PAGE 03-06

DP-36 Only

PST1

From ATSC

Digital

Tuner

UD2002

In1A In3A In2A

In1B

In2B

In3B

OUT 1 OUT 2 OUT 3

COMP 1 (Cr/Pr)

COMP 1 (Cb/Pb)

COMP 1 (Y)

IV04 Selector

Y/Pb/Pr DVI 1

IV05 Selector

Y/Pb/Pr DVI 2

COMP 2 (Cb/Pb)

COMP 2 (Y)

OUT 1

In1A

OUT 2

In3A

OUT 3

In2A

In1B

COMP 2 (Cr/Pr)

In2B

In3B

23 25 26

3 5 6

Control

3 5 6

Control

IV03 Selector

DM HY

DM PB

17 19

DM PR

DVI 1 Det

Y/Pb/Pr

INPUT 1

Main Pr-Out 2

DP-37, 37C, 37D Only

PHOTO G PHOTO B PHOTO R

NTSC Y In

S-In Y In

53 55 57

PBT

From

PHOTO

MEDIA

Photo Card Reader on DP-36

is fed via USB into the Digital Module

QV35

IY04

MAIN

Video/Chroma

Y Pr/Pb Switch

Cr/Pr R In

DP-33W Only

PAT

Player

5 7

Power PWB

From

DVD

I501

RGB

Processor

1080I Flex Bypass

PST2

QV34

LOut 1

Lo = Y Pr/Pb Hi = DVI 1

DVI 2 Det

Main Pb-Out 2

Main Y-Out 2

42 44

QV33

NTSC Y In

S-In Y In

Cb/Pb B In

Main Cr/Pr Out

D-Sync 1/Y3/ G In

Main Cb/Pb Out

D-Sync 2 In

Main Y Out

Video/Chroma

IY03 SUB

22 23

QY30

QY29

QY28

Y Pr/Pb Switch

QV38

Y PB PR

I N P

SUB Pb-Out 1

U T

SUB Y-Out 1

SUB Pr-Out 1

QV37

QV36

Cr/Pr R In

Sub CrPr Out

Cb/Pb B In

Sub Cb/Pb Out

D-Sync 2 In

D-Sync 1/Y3/ G In

Sub Y Out

22 23 24

QY24

QY23

QY22

RAINFOREST IC

Q507

Q506

Q505

Pr1In Y1InPb1In

PFC1

Q403

Q402

Q401

MAIN

19 18 17

To CPT

PWBs

Pr 2 In

Pb 2 In

Y 2 In

676668

Pr Out

Pb Out

R Out

G Out

B Out

U401

FC4

UNIT

Y Out

PFC2

PSC

Q537~40

Q541~44

Q545~48

Q508

Q509

Q510

SUB

LOut2

Lo = Y Pr/Pb Hi = DVI 2

TERMINAL PWB

FLEX CONVERTER

SIGNAL PWB

Page 43

SCP IN Pin 49

Black Peak

DP-3X RAINFOREST IC INFORMATION (I501)

Pin 49 = SCP. Black Peak: 2.2V ~ 2.8V: This input is utilized for establishing the Black Peak stop level

4.2 ~ 9V CLAMP

2.2 ~ 2.8V

used in Black Peak expansion circuit. Here the Black Peak is expanded towards Black to increase the contrast ratio. CLAMP: 4.2V ~ 9V: Received from the Flex Converter via connector PFC2 Pin 8. The clamp pulse is utilized for DC restoration and blanking timing.

FBP IN Pin 39

Max 9V

H-AFC 5.3V

BLK 2.3V

YM/P-MUTE/BLK Pin 79

7 ~ 9V Blanking

2.7 ~ 4V P Mute

1.2 ~ 1.8V Half Tone

0 ~ 0.5V Internal

YS3 Pin 2

Pin 39 = FBP. Combination of the following. BLK: 2.3V H-AFC: This input is received from the Horizontal Blanking (H. Blk)

signal generated in the Deflection circuit by Q706. This signal is used as a sample pulse in the Horizontal AFC circuit, which synchronizes the Horizontal Drive signal with the incoming Video sync signal input at pin 16. In Through Mode, pin 8. H-AFC Fly back pulse: 5.3V ~ 9.0V Max: This input is received from the Flex Converter and is a combination of Horizontal and Vertical blanking signals. H Blk from the Flex Converter PFC2 Pin 7 through Q523 V Blk from the Flex Converter PFC2 Pin 6 through Q522 Used within the Rainforest for DC restoration, Pedestal level detection and Clamping signals, such as Burst Gate Pulse. Also, from the Mute circuit of Q528 throug D503 to force RGB mute.

Pin 79 = YM/P-MUTE/BLK. Combination of the following. INTERNAL: 0.0V ~ 0.5V Used internal within the Rainforest IC. HALFTONE: 1.2V ~ 1.8V: This input is received from the Microprocessor

and is used to establish the Transparency effect of OSD. This also mutes the video in exact timing with On Screen Display pulses (OSD). Half Tone from the Microprocessor Pin 22 through Q415.

P MUTE: 2.7V ~ 4V: Not Used. BLANKING: 7V ~ 9V: Not Used.

1.5 ~ 9V Analog RGB SVM Mute

0 ~ 0.5V Internal

YS1 Pin 80 / YS2 Pin 1

2.9 ~ 9V OSD SVM Mute 1

1.1 ~ 1.7V SVM Mute

0 ~ 0.9V Internal

Pin 2 = YS3. Combination of the following. INTERNAL: 0.0V ~ 0.5V Used internal within the Rainforest IC. ANALOG RGB: 1.5V ~ 9V: This input is received from the Digital

Convergence Unit anytime the DCU is outputting graphics. During the time this pulse is above 1.5V, the Velocity Modulation drive signal is muted, so VM is turned off.

Pin 80 & 1 = YS2/3. Combination of the following. INTERNAL: 0.0V ~ 0.5V Used internal within the Rainforest IC. SVM MUTE: 1.1V ~ 7V: Halftone This input is received from the

Microprocessor Pin 22. During the time this pulse is between 1.1~1.7V, the Velocity Modulation drive signal is muted, so VM is turned off. OSD SVM: 2.9V ~ 9V: OSD Blk, received from the Microprocessor Pin

21. This mutes the video signal in sequence with the location and timing of the OSD Characters.

PAGE 03-07

Page 44

DP-3X ABL CIRCUIT EXPLANATION

(See ABL Circuit Diagram for details)

The ABL volta ge is gener ated fro m the Flybac k transfor mer

RH27

and

. They receive their pull up voltage from the

RH28

ated in the Power Supply.

ABL VOLTAGE OPERAT ION

The ABL voltage is determined by the current draw through the Flyback transformer. As the picture brightness becomes brighter or increases, the demand for replacement of the High Voltage being consumed is greater. In this case, the Flyback will work harder and the current through the Flyback increases. This in turn will decrease the ABL voltage. The ABL voltage is inversely proportionate to screen brightness. Also connected to the ABL voltage line i s

. This zener diode acts as a clamp for the ABL voltage. If the

DH16

ABL voltage tries to increase above 10V due to a dark scene which decreases the current demand on the flyback, the ABL voltage will rise to the point that

dumps the excess voltage into the 10V line.

DH16

ACCL TRANSISTOR OPERATION

The ABL voltage is routed through t h e

connector pin 3 to the Power Supply PWB, then to

PPD3

pin 3 on the Signal PWB. Then the ABL voltage is ro uted through t he acceleration circuit base of supplied to the cathode of

. Under normal conditions, this transistor is nearly saturated.

Q511

, which is connected to pi n 78 of the Rainforest IC,

D502

decrease due to an excessive bright circumstance, the base of age which in turn drops the cathode voltage of forest IC,

. Internall y, this reduc es the con trast and b rightness voltage which is bein g controlle d by the

I501

. This in turn will pull voltage away from pin 78 of the Rain-

D502

bus data communication from the Microprocessor arriving at pins 29 and 30 of the Rainforest IC and reduces the overall brightness, preventing blooming as well as reducing the Color saturation level to prevent color smear.

BLACK PANEL SWITCH QH05

This chassis has the ability to change the Side Panels when watching a NT SC 4X3 image. When a 4X3 images is displayed on a 16X9 set, the sides do not reach the edges. To avoid excessive ageing at the 4X3 display area, the side panels IRE levels are raised. However, sometimes the customer may want to turn the side gray panels off. Through the Video Advanced feature s Menu the customer can do this. When the Si de panels are turned off, the overall average ABL level for the image is reduced. To compensate, Microprocessor

. This high is routed through the

. This adds Resistor

tells the Rainforest IC

I001

to the ABL pull up circuit and the ABL level drops slightly to compensate for the

RH38

I501

connector pin 9,

PPS3

via I

C communication to output a high from the DAC2 line pin

PPD3

side panel loss of brightness.

ABL pin (3). The ABL pull-up resistors are

TH01 SW +115V

which is the B+ line for Deflection cre-

PPS3

and

R528

determines the voltage being

Q511

. During an ABL voltage

I501

will go down, this will drop the emitter volt-

Q511

Black Panel Switch is turned on. The

QH05

connector pin 9 the base of

QH05

connector

to the

D501

turning it

Black Side Panels

Turned on by the

customer

Gray Side Panels

Black Side Panels

ABL SWITCH QH04:

This switch adjust the ABL voltage when the Color Temperature is changed to high by the customer, 10,500K. During High Color temperature, the overall average brightness is slightly higher, ABL pull up resistors. This slightly lowers the overall range of ABL during High Color Temperature.

When color temperature is high, SW

•

All other color temperatures, SW

•

manipulates the trigger point of shut down dependant upon the ABL level avoiding false triggering.

RH32

QH04

is ON.

is OFF

QH04

switches in

RH36

to the

PAGE 03-08

Page 45

DP-3X Chassis A.B.L. Circuit Diagram

ABL

PAGE 03-09

D501

+115V

ABL Switch

Black Panel

Power Supply

PWB

ABL

R529R528

C511

PPD5

PPD3PPS3

Q511

R530

C512

Black Panel

ABL Switch

ABL switches QH04~05 slightly reduce the overall operational point of ABL due to the loss of overall brightness levels.

Off High Color Temperature On all other Temperatures

RH37

RH41

RH39

RH42

On Black Side Panels On Off Gray Side Panels On

As Brightness goes Up, ABL Voltage

goes Down. (Inverse Proportional)

QH04

QH05

R532

RH36

ABL Switch

RH38

Black Panel

R531

180K

47K

HVcc +9.3V

D502

C513

Sw +10V

Clamp

R533

ABL

C514

Deflection PWB

27K

RH27

Collector of High Voltage

QH03

used in 4X3 models.

DH16 RD30EB4

CH18

To QH01

Output Transistor

only

RH28

[

Current Path

RH27 & RH28

39K

RH31

ABL Pull-Up

Resistors

]

6.8K

I501

Rainforest

SDA2

SCL2

DAC2

B+

CH14

RH32

180K

RH24

43K

29 30

TH01

50P

CH21

1080i

Y In

R572

R571

FBT

Gnd

ABL

LH01

RH21

RH25

DH15

HZ22-2L

31 28

ABL Switch

LH06

RH23

To Anodes

To Focus

18K

Micro

I001

SDA2 SCL2

DH13

DH14

XRay Protect

Signal

PWB

CH17

Stops

H. Drive

IH01

OVP

RH26

RH09 CH10

Page 46

DP-3X COMPONENT SYNC CIRCUIT DIAGRAM EXPLANATION

(See Main/Component Sync Separation Signal Path for details)

IY04 Main/Chroma Y Pr/Pb Switch: Any Component’s Y signal arrives at pin 6 for the Main Picture. The Y component for NTSC is input at pin 4.

IY03 Sub/Chroma Y Pr/Pb Switch: Any Component’s Y signal arrives at pin 6 for the Sub Picture. The Y component for NTSC is input at pin 4.

Main Y Output from IY04:

The Main signal, either component or composite, is sync separated inside IY04 and output. The following describes it’s associated output path.

(ALL CHASSIS)

H sync pin 17 to QY31 to the PST2 connector pin 35, to pin 8 of the PFC1 on the Flex Converter.

(ALL CHASSIS BUT DP- 37)

V sync pin 15 to QY32 to the PST2 connector pin 34, to pin 7 of the PFC1 on the Flex Converter. (All chassis but DP-37)

(DP-37 CHASSIS ONLY)

This chassis has a Photo Card reader, the V Sync is output from pin 15 but is routed to pin 13 of IV07. The V Sync from the Photo Card Reader (Media Bridge) is input from the PBT connector pin 10 and arrives at IV07 pin 13. Which ever signal source is selected, the V Sync (MVD Out) is sent out pin 14 to the base of QY32 to the PST2 connector as described above.

Sub Y Output from IY03:

The Sub signal, either component or composite, is sync separated inside IY03 and output. The following describes it’s associated output path.

• H sync pin 17 to QY25 to the PST2 connector pin 31, to pin 15 of the PFC1 on the Flex

Converter.

• V sync pin 15 to QY26 to the PST2 connector pin 32, to pin 14 of the PFC1 on the Flex

Converter.

SYNC FROM THE FLEX CONVERTER U401 TO THE RAINFOREST IC I501

• H sync pin 35 to pin 12 of the Sync Selector I502, H sync for a true 1080i signal is input to

pin 13 of the Sync Selector I502 and output from pin 14 to the Rainforest IC pin 50. Note: 1080i bypasses the Flex converter. If 1080i is detected, the Rainforest IC I501 outputs a high from the DAC 1 pin 34 to pin 11 of I502 sync selector to select Y sync prior to the Flex Converter.

• V sync pin 34 to pin 52, of the Rainforest IC I501. Since Sync is the same for 1080i

(60Hz) there is no need to route through a sync selector like the H. Sync.

PAGE 03-10

Page 47

DP-3X MAIN/COMPONENT SYNC CIRCUIT DIAGRAM

NTSC Y In

S-In Y In

Cr/Pr R In

Cb/Pb B In

D-Sync 2 In Y In

D-Sync 1/Y3/ G In

Bridge Media

V Sync

Pin 10 PBT

D-Sync 2 In Y In

NTSC Y In

S-In Y In

Cr/Pr R In

Cb/Pb B In

IY04

MAIN

Video/Chroma

Y Pr/Pb Switch

Main H Out

Main V Out

MVD

1313 14

IV07

Video/Chroma

Y Pr/Pb Switch

28 29

17 15

MVD Out

IY03

SUB

Sub H Out

Sub V Out

QY31

Note: IV07 in DP-37 Chassis for Photo Card Reader

17 15

QY32

QY25 QY26

PST2

31 32

Main H In

Main V In

Sub H In

Sub V In

FC4 UNIT

PFC1

8 7

15 14

U401

Main H

Out

Main V

Out

PFC2

HD Out

VD Out

I502

13 12

HVcc 9.3V

I501

50 HD In14

DAC 1

VD In

PAGE 03-11

D-Sync 1/Y3/ G In

FLEX CONVERTER

Page 48

Block Diagram of UD2002

ATSC / QAM / IEEE1394 Interface Module

ATSC CATV RF IN

Front-End Board

IF circuit

Main Board

Digital

Tuner

64MB

SDRAM

AGC

HL Decoder

Demux

NTSC

Encoder

TS in

Glue Logic 2/2

AGC

Demodulator

TC90A55TB

MPG

Decoder

AC-3

Decoder

TS out

BCM3510 VSB/QAM

DAC

Down

Mix

CPU

bus

Y/C, V

Glue

Logic 1/2

DAC

RAM for

256QAM

L,R

64MB

SDRAM

YSD-038 Graphics

Graphics

NTSC

Encoder

Peripherals

DAC

Memory Card

Board

Memory Card I/F

Optical

Sub

CPU

SH4 Main CPU

64MB

SDRAM

Memory

Card

I/F

SPD

I/F

IEEE 1394

I/F

IEEE1394

Physical

IEEE1394 Board

IEEE1394

Link

RAM

SCI

Modem

Board

Modem

I/F

L,R Y/C

Analog

Audio

NTSC Video

PTV Signal Board

Analog

Power

Supply

CPU

bus

Y/Pb/Pr

Y Pr/Pb SCI

Video

SCI

16MB

FLASH

Digital

Power

Supply

PAGE 03-12

Page 49

RX2-

RX2+

GND2/4

RX4+

RX4-

SCL

SDA

VSYNC

RX1-

RX1+

GND1/3

RX3+

RX3-

GND

HTPIUG

RX0-

RX0+

GND0/5

RX5+

RX5-

GNDC

TXC+

TXC-

PAGE 03-13

PDJ1

DVI CONN

DJ04

DJ05

1 2

DJ01

1 2

DJ02

1 2

DJ16DJ14

DJ07

DJ08

DJ03

B+

1 2

B+

QJ05

Mode

DP-3X CHASSIS DVI SIGNAL PATH

10 12 16 21 25

28 33 35 43 45 50

IOR

IOG

IOB

Vcc

SCDT

AVcc AVcc

DVcc

Reset

IJ04

NDC7002N

4 6

DVIDET

4 539

SDA

DJ06

DJ09

DJ12

IJ05

NDC7002N

IJ03

SiI907BCQ52

RX2-

RX2+

B+

RX1-

RX1+

RXO-

RXO+

RXC+

RXC-

DJ10

HSync VSync

DACVccR

DACVccG

DACVccB

DACVcc

SCL

DVIH DVIV

DVIR

DVIG

DVIB

IJ02

All of these pins are ground

QJ03

QJ02

QJ01

QJ04

LJ15

IJ01

8 3

LJ17

DJ15

PET

DVIH DVIV

DVIR DVIG

DVIB

DVIDET

GND GND

GND

GND GND

SW+5V

SW+5.5

NC NC NC NC

NC NC

Page 50

DP-3X BLANK PAGE “NOTES”

BLANK PAGE

Page 51

AUDIO

INFORMATION

DP-3X

CHASSIS INFORMATION

SECTION 4

Page 52

DP-3X BLANK PAGE “NOTES”

BLANK PAGE

Page 53

DP-3X AUDIO (Main-Terminal) CIRCUIT DIAGRAM EXPLANATION

(See Audio (Main-Terminal) Signal Path Diagram for details)

IV01 AUDIO VIDEO SELECTOR IC:

The main Audio path is delivered to the Audio/Video Selector IC

(Left) and 64 (Right): This is the Audio input from the Main Tuner

decoding circuit that outputs Lt (Left Total) from pin 26 and Rt (Right Total) from pin 27. The Left continues through the

connector pin 48 and the Right continues to pin 47. They arrive at

PST2

(DM-Left) and 4 (DM-Right): This is the Audio input from the ATSC Tuner

Audio decoding circuit that outputs Lt (Left Total) from pin 13 and Rt (Right Total) from pin 14. The Left continues through the Digital Module (ATSC Tuner) is only available on the DP-36 chassis.

(Left) and 61 (Right): This is the Audio input from Auxiliary 1 input. This audio is associated with component input 1

and with DVI 1 input.

(Left) and 31 (Right): This is the Audio input from Auxiliary 2 input. This audio is associated with component input 2

which also accepts composite video on the Y jack without a Cr plug and with DVI 2 input..

(Left) and 18 (Right): This is the Audio input from Auxiliary 3 input, composite or S-In only.

(Left) and 11 (Right): This is the Audio input from Auxiliary 4 input, composite or S-In only.

(Left) and 25 (Right): This is the Audio input from the front Auxiliary 5 input, composite or S-In only. These inputs

are delivered through the

SOME MODELS WITH DVD PLAYER:

If the set has a built in DVD Player, it will have input 5 or the DVD Player. Front Audio input L pin 12 and R Pin 2. DVD Audio L pin 13 and R pin 1. It outputs selected audio L from pin 14 and R from pin 15 to

MONITOR OUTPUTS:

(Left) and 40 (Right): This is the Monitor Audio Outputs.

LEFT and RIGHT OUTPUTS:

(Left) and 45 (Right): This is the Left Total and Right Total output which represent the Audio associated with the

Main picture. The Lt and Rt represent the fact that the Audio has any Dolby ® encoding still embedded.

The outputs are then routed through the and 12 respectively. television to operate in TV as Center Mode. The Center audio is routed to pins 1 and 13. The control switching signal is provided by the Microprocessor to receive inputs from the main L and R and a high on these pins will place the IC into the Center mode. The audio from

IA01 AUDIO CONTROL IC:

The NJW1160 is a sound processor includes the both BBE sound enhancement and SRS 3D Stereo. It includes all of the functions processing audio signal for TV, such as tone control, balance, volume, mute, and AGC functions. It also performs sound enhancement and surround. The sound enhancement regenerates high definitive and nearly real sound, and SRS 3D Stereo regenerates 3D surround sound with two speakers. All of the internal status and variables are controlled by I

The Audio is output from pin 8 (L) and pins 2 (L) and 4 (R) and out pin The Secondary route from

(See the Audio Video Mute circuit in the Microprocessor section for details on the Mute transistors operation and control).

connector pin 28 and the Right continues to pin 29. They arrive at

PST2

connector pins 4 and 5 respectively.

PFT

. This IC is responsible for selecting either the Front Audio from

IV08

pin 23 and R pin 25.

IV01 L

connector pins 23 (Left) and

PST2

is responsible for selecting the audio input from the Center Jack when the customer has set the

IA51

pin 18 through the inverter

I001

leaves pin 15 Left and 14 Right and into the Audio Control IC

IA51

C BUS interface.

(R) to two different circuits. Primary route is to the Audio Output IC

(L) and 7 (R) to the speaker plug

is to the Out to Hi-Fi jacks. L

IA04

QA54

to the following pins;

IV01

. The integrated Tuner has an Internal Audio

U301

pins 62 and 64 respectively.

IV01

UD2003

(Right) to the Center Select IC

to pin 10 and 11. A low on these pins with switch

QA58

pin 5 and R pin 1.

PSP L

and

QA55, R QA53

. The Digital Tuner has an Internal

pins 2 and 4 respectively. The

IV01

IA01

and

QA52

IA51

IAA1

pins 2

PAGE 04-01

Page 54

SIGNAL PWB

DP-36, DP-38

DP-38D Only

UD2003

ATSC Tuner

PMS2

U301

Main Tuner

See Main / Sub Audio Select Circuit Diagram

Aux 1 Left

Aux 1 Right

Aux 2 Left

Aux 2 Right

Aux 3 Left

Aux 3 Right

17 18

DM R

DM L

TV Main R

TV Main L

PTV L

PTV R

PST1

QV03 QV04

29 2813

47 4826

DP-3X Chassis Audio (Main-Terminal) Signal Path

Q406 Q405

Digital Tuner Audio

Right Out

Tuner Audio

IV01

A/V Select

Left

Input 1 Right

Left Input 2 Right

31 16

Left Input 4 Right

Left Out

43 45

PST2

23 24

SEL OUT

I001

Micro

1 2

12 13

IA51

Lo Lo

Center = L

Not In DP-33W

10 15

11 14

TV as

SCL2

SDA2

Left Right

SIGNAL PWB

1R In

QA58

18 Center Sel

L In

SCL2

SDA2

IA01

NJW1160

Audio Control

L Out

R Out

Not In DP-33W

FRONT SPEAKER OFF

BBEout R

Tone R In

BBEout L

Tone L In

QA53

QA52

QA55

JA01

Center In

HiFi Out

Left

Right

Front Control

DP-33W Only

PAGE 04-02

DVD L

DVD R

Aux 4 Left

Aux 4 Right

IV08

PFT1

4 5

PAT

MON

Some Models

Hi DVD, Lo V5

Monitor Out Left

Monitor Out Right

TERMINAL PWB

14 15 11

Left Input 3 Right

Left Input 5 or DVD Right

1725

Monitor Out

Left Output 3

Right

See AV Mute

Circuit Diagram

See AV Mute

Circuit Diagram

SIGNAL PWB

QA01

QA02

See AV Mute Circuit Diagram

PPS4

IAA1

Front Audio Out

TA8258H

QA56

FR (WO) Out

FL (WO) Out

QA54

CAE3

FR (TW) Out

CAE4

FL (TW) Out

POWER PWB

QA51

PSP

1 3

5 7

Page 55

DP-3X MAIN / SUB AUDIO SELECT CIRCUIT DIAGRAM EXPLANATION

(See Main/Sub Audio Select Circuit Diagram for details)

responsibility is to route either the Main Tuner’s Audio or the Sub Tuner’s Audio to the Selector IC,

I301

This is possible while in the Split Screen mode for PinP. By pressing the Swap button in this mode, the audio is switched between Main and PinP Audio.

The following describes the Left and Right audio path to

Main Tuner U301 (Left Total, Right Total):

From pin Through To

I301

Sub Tuner 302 (PinP Tuner):

From pin To

Q050

Through To

I301

I301 Main/Sub Selector IC.

The Audio inputs are selected by the control lines at pins 10 and 11. These pins are controlled by the output from the Microprocessor

outputs the selected audio on the following pins, 15 for Right and 14 for Left. Through the

I302

pin 47 Right and

(See Audio (Main/Terminal) Signal Path Circuit Diagram for details related to the continuation of the Audio signal flow)

Right and pin 26 Left.

Right,

C099

pin 1 Right, pin 13 Left.

mono audio.

C086

pin 2 Right, pin 12 Left.

I001

• Pins 10 and

48 Left

Left.

C098

pin 72 through inverter

11 High 11 Low

to the A/V Selector IC

Q033

= Main Tuner.

= Sub (PinP) Tuner.

IV01

Selector IC, pin 47 Right and pin 48 Left

IV01

64 Right

and pin 62 Left.

PST2

connector

IV01

PAGE 04-03

Page 56

DP-3X MAIN / SUB AUDIO SELECT CIRCUIT DIAGRAM

I301

U301

Main Tuner

U302

Sub Tuner

TV Main R

TV Main L

Mono

Q050

I001

MICRO

C099

C098

C086

HVcc 9.3V

PST2

TV R

A/V Select

TV L

Pins 10 and 11 High = Main Tuner. Pins 10 and 11 Low = Sub (PinP) Tuner.

IV01

PAGE 04-04

TVAUDSEL

Q033

Page 57

DEFLECTION

INFORMATION

DP-3X

CHASSIS INFORMATION

SECTION 5

Page 58

DP-3X BLANK PAGE “NOTES”

BLANK PAGE

Page 59

DP-3X HORIZONTAL DRIVE CIRCUIT EXPLANATION

HORIZONTAL DRIVE CIRCUIT DIAGRAM DESCRIPTION:

(Use the Horizontal Drive Circuit Diagram for details)

CIRCUIT DESCRIPTION

When B+ arrives at the Rainforest IC routed through the connector switches the ground return for pin (8) of the Driver transformer (

. Then through

R730

develop. As this signal collapses, it creates a pulse on the output pin of ( flection Horizontal output transistor Transformer

Q777 TRANSISTOR PRODUCES THE FOLLOWING OUTPUT PULSES;

1. The This is a parabolic waveform that is superimposed upon the static focus voltage to compensate for beam shape abnormalities which occur on the outside edges of the screen because the beam has to travel further to those locations.

2. Horizontal Deflection Yokes drive signals.

Horizontal Deflection Yokes.

T701 TRANSFORMER PRODUCES THE FOLLOWING OUTPUT PULSES;

•

Deflection H. Pulse from pin (7):

HORIZONTAL BLANKING (H. BLK) GENERATED FROM PIN (7):

The Horizontal Pulse is also routed to the Horizontal Blanking generation transistor ates the 13V P/P called

• To the signal. It is compared to the reference signal coming in at pin (50) Horizontal Sync. If there are any differences between these two signals, the output Drive signal from pin (37) is corrected.

NOTE

Sync now becomes the H Sync before the Flex Converter. Output from sync selector

(See the Main/Component Sync Circuit Diagram for details).

• The H Blk signal is also routed to the Microprocessor which uses this signal for OSD positioning and for Station Detection during Auto programming within the coincidence detector, also as a detection signal to activate the AFC Loop.

• The PinP unit uses this signal for switching purposes. Like the read/write clock, positioning, etc…

• Through the

• Through

is lost.

H Blk for HORIZONTAL DRIVE FOR THE HIGH VOLTAGE CIRCUIT:

• The Horizontal Blanking signal This IC uses this signal as a Tickle Pulse signal to lock the high voltage H. Drive signal from The high voltage H. Drive signal is output pin 1 and routed to the driver transistors, Voltage Horizontal Output Transistor

. Deflection SW +115 is sent through pin (9) and output pin (10) to the collector of the Horizontal Out-

TH01

put Transistor

A sample of the High Voltage is output from the Flyback transformer (9) of the High Voltage Driver IC

T701

Dynamic Focus OUT Circuit to QF01

PPD3, PPS3

: When a 1080i signal is input through component inputs, the Reference signal for Horizontal

PDG

CN01

QH01

pin (45), horizontal drive is output from pin (37). The drive signal is

I501

PPS3, PPD3

and supplied to pin (5) as primary voltage. The switching of

D715

. This signal goes to the following circuits;

H Blk

connector pin 8 to pin (39) of

connector pin

to the Sweep Loss Circuit (

IH01

pin 6 to the Horizontal Driver Transistor

T702

. This transistor provides primary switching pulses for the Deflection

Q777

: A Dynamic Focus waveform, (Horz. Parabola) is created.

The collector of

This pulse is used by;

to the Convergence circuit for correction waveform generation.

) to shut off the drive to the CRTs if Horizontal deflection

QN01

from

H Blk

. This voltage is compared to the reference voltage available at pin (12).

Q706

. This transistor switches the primary of the Flyback transformer

QH01

I501

is also sent to the High Voltage Driver IC

FBP In.

SW+28

T702

Q777

Here this signal is used as a comparison

TH01

. This transistor

Q709

volts is routed through

allows EMF to

Q709

) at pin (4) to the base of the De-

provides the drive signal for all

. This transistor gener-

Q706

I502

. Then to the High

QH02

pin (12). This voltage is sent to pin

(Continued on page 2)

, pin (

IH01

R748

14)

pin (3).

pin 1.

and

PAGE 05-01

Page 60

DP-3X HORIZONTAL DRIVE CIRCUIT EXPLANATION

If there is a difference between the two voltages, an error voltage is generated and output from pin (10) and input again at pin (11) where it manipulates the PWM (Pulse With Modulation) signal producing the Horizontal Drive signal output from pin (1).

It’s important to notice that the High Voltage circuit can not function without the Horizontal Deflection circuit providing a drive signal. The Sweep Loss circuit will since the loss of H. Blanking and output a high that’s routed through the internal op-amp that creates the sawtooth comparator signal. Thus stopping H. Drive. Pin 14 high will saturate the internal generator that produces the sine wave for the sawtooth op-amp. See Figure 1 below.

DN10

to pin 3 and

to pin 14. If these voltages go high, pin 3 will defeat the H. Drive by saturating

DN09

Gen

DC Ref.

DC Feed Back

DC Ref.

GENERAL INFORMATION:

The DP-3X deflection circuit differs from analog Hitachi projection televisions. It utilizes in a sense, two horizontal output circuits. One for Deflection and one for High Voltage. This allows for better deflection stabilization and is not influenced by fluctuations of the High Voltage circuit which may cause unacceptable breathing and side pulling of the deflection.

Fig 1

10 11

PAGE 05-02

Page 61

DP-3X SERIES CHASSIS HORIZONTAL DRIVE CIRCUIT

PPD3

R735

D709

PDG

PAGE 05-03

CN01

Deflection PWB

Power

Supply

PWB

PPS3

Signal PWB

To Convergence Circuit

H.Blk.

RH07

Fron Sweep Loss

Det Circuit QN02

Stops H. Drive

To H. Sweep Loss Det. Circuit QN01

H.Blk.

H Drive

Q709

SW +28V

Q706

SW +10V

To Micro. for OSD, Auto Prog, SD, AFC,

I501

FBP In

H Out

Rainforest IC

See Voltage and Waveform

RN16

RN15 DN09

DN10

VCC

HVCO

HD In

Y2 In

H Freq Sw

R748

R730

D715

Chart on next page.

SW +9.3V

H Sync

1080i for Through Mode

NTSC/PAL-Q551 28K-Q552

C725

DH04

PPD4

DH01

RH02RH01

CN01

Ref. V.

Osc.

X501

T702

SW + 15V

I503

SW +10V

Q777

Side Pin Modulator

IH01

Gen

Drive

Com1

OVP

r r

Q701

FB In

PMR

PMG

PMB

T701

SW +115V

QH02

DH05

RH26

H. Def. Yoke R

H. Def. Yoke G

H. Def. Yoke B

To Dynamic Focus QF01

Def.

H Pulse

PPD5

Horizontal

Output

QH01

HV Sample

RH22

DH14 DH13

TH01

High Voltage

50P

Page 62

DP-3X IH01 HIGH VOLTAGE DRIVER IC WAVEFORM AND VOLTAGES

IH01 NORMAL OPERATION:

Pin 1 = 6.80V with Color Bar, Varies with Brightness levels.

11 12 13 14

Pin 2 = 11.72V Pin 3 = 0.59V Pin 4 = 2.47V Pin 5 = 1.60V Pin 6 = 10.58V Pin 7 = 0.0V Pin 8 = 0.0V

REF

UVLOGENAGCUVP OVP POUT

Pin 9 = 4.90V Pin 10 = 0.03V

8 7 6 5 4 3 2 1

Pin 11 = 0.03V Pin 12 = 4.90V Pin 13 = 0.05V Pin 14 = 2.02V

Pin 1 12V P/P 33.75Khz

Pin 15 = 4.96V Pin 16 = 0.0V

Pin 3 4.5V P/P 33.75Khz

Gnd

IH01 NOT RUNNING:

Pin 1 = 12.28V Pin 2 = 11.86V Pin 3 = 3.96V Pin 4 = 3.5V Pin 5 = 1.089V Pin 6 = 0.021V Pin 7 = 0.0V Pin 8 = 0.0V Pin 9 = 0.019V Pin 10 = 0.038V Pin 11 = 0.038V Pin 12 = 4.90V Pin 13 = 0.05V Pin 14 = 4.59V Pin 15 = 4.96V Pin 16 = 0.0V

Pin 4 3V P/P 33.75Khz

NOT RUNNING EXPLANATION:

This situation can happen and possibly lead the Service Technician off on the wrong path. Take a quick look at the voltages for pin 3 and 14. This is the key. These two pins tie back to the Horz. and Vert. Sweep Loss Detection Circuit.

(See page 05-05 for the Sweep Loss Detection Circuit Diagram).

If the Sweep Loss circuit is activated, it outputs a high from QN02. This high is used to shut off the CRT to prevent CRT burn, However, the Collector of QN02 is also routed to these two pins through diodes DN09 to pin 14 and DN10 to pin 3. When QN02 goes high, it drives pin 3 and 14 high which turns off the internal oscillator of IH01 via pin 3. This action stops Horizontal Drive to the High Voltage circuit. This action causes pin 1 to saturate and it goes High. Note that pin 14 is tied to an internal op-amp (-) leg. This cause the output to stop. So no Horizontal Drive is allowed to pass to the output amp. connected to pin 1.

PAGE 05-04

Page 63

DP-3X SWEEP LOSS DETECTION CIRCUIT EXPLANATION

(See Sweep Loss Detection Circuit for details)

The key component in the Sweep Loss Detection circuit is pull up resistor +10V to be applied to two different circuits, the Spot circuit and the High Voltage Drive circuit. Either

turning on, will turn

QN04

. When the base becomes 0.6V below the e mitter, it will be turned on, causing the SW

RN18

on.

QN02

. This transistor is normally biased off by the

QN02

QN03

SPOT ACTIVATION CIRCUIT

When will then pass through be directed to the Signal PWB where it will pass through

Q527

A control (ena ble) circui t for SPOT is route d fro m pin 5 of when accessing certain adjustments parameters in the service mode; i.e. turning off vertical drive for making CRT drive or cut-off adjustments. When Vertical Drive is defeated, the Vertical Sweep loss circuit would activate. Cut Off is produced from the Microprocessor from activating and shutting off the CRTs.

is turned on, the SW +10V will be applied to the anode of

QN02

. It will then be clamped by

DN11

. This is done to prevent CRT burns. (See Audio Video Mute Circuit for details)

I001

, and arrive at pin 4 of

DN12

and activate the Video Mute circuitry

D511

PPS3, PPD3

pin 47 and routed to

, forward biasing it. This voltage

DN11

called “

CUT OFF

QN06

PPD3, PPS3

to “inhibit” the Spot line

. It will then

Q529 -

”. This will activate

HIGH VOLTAGE DRIVE CIRCUIT

When Voltage Drive IC used to pro duce High Vo ltage via pecially during sweep loss. This high is also routed through

is turned on, the SW +10 V will also be routed through

QN02

at pin 14. When this occurs, the IC will stop generating the drive signal from pin 1 that is

IH01

, the High Voltage Driver. Again, this is done to pr event CRT burn, es-

QH02

RN16, DN10

to pin 3 of

and

RN15

which also kills the internal drive.

IH01

DN09

and applied to the High

CONCERNING QN02

There are several factors that can cause

to activate; loss of vertical or horizontal blanking.

QN02

Loss of Vertical Blanking (V Blk)

The Vertical pulse at the base of ficiently enough to prevent the base of

When the 24 Vp/p positive vertical blanking pulse is missi ng from off, which will cause the collector to pull up high because cause tor and through ply. This increase of current flow through Circuit” above will occur.

to turn on because it’s base pulls up high, creating an increase of current flow from emitter to collec-

QN04

RN09. RN08

, (which is located across the emitter base j unction of

QN05

switches

from going high to turn it on and activate

QN04

RN08

on and off at the vertical rate. This discharges

ON05

CN04

charges up through

CN03

will bias on

and the events described in “Spot Activation

QN02

to the base of

QN02

CN03

, it will be turned

QN05

. This in turn will

RN11

), to the SW +10V sup-

suf-

Loss of Horizontal Blanking (H Blk)

The Horizontal pulse at the base of sufficiently enough to prevent the base of

When the 11.6 Vp/p positive horizontal blanking pulse is missing from turned off, which will cause the collector to go high through in turn will cause increase of current flow from emitter to collector, through flow thro ugh

RN08

to turn on because it’s base is pulled up high when

QN03

will bias on

QN02

switches

QN01

from going high to turn it on and activate

QN03

and the events described in “Spot Activation Circuit” above will occur.

on and off at the horizontal rate. This discharges

ON01

QN02

to the base of

CN01

DN03, RN02

, and up thro ugh

RN10

as the SW +10V charges

fires. When

DN02

. This increase of current

RN08

QN01

QN03

CN02

turns on, an

CN02

, it will be

. This

PAGE 05-05

Page 64

DP-3X SWEEP LOSS DETECTION CIRCUIT

SW+10V

DN13

Vertical Blanking

From Pin 11 I601

V. Blk.

CN04

24V P/P

Horizontal Blanking

From Q706 Emitter

H. Blk.

CN01 RN04

RN13

RN14

RN03CN02

RN12

QN05

QN01

RN05

DN08

RN02

DN03

DN02

RN11

CN03

DN01

RN01

RN10

QN03

RN09

QN04

DN06 DN07

QN02

RN06

RN15

DN09

CN06

RN18

High Voltage

Driver IC

IH01

Stops

Drive

11.6V P/P

SPOT

To Q529

Signal

3of 3

See A/V

MUTE Circuit

CUT OFF

From I001

Micro Pin 47

PPS3

PPD3

Prevents CRT Burn

DN12

RN17

When Vertical Drive is turned Off during adjustment, I 2C.

DN11

Spot Inhibit

QN06

RN19

H. Blk

DN10

RN16

DN04

Stops High Voltage Drive Signals From being produced when Sweep Loss is detected.

RH07

Stops

Osc

PAGE 05-06

Drive

QH02

Page 65

DP-3X VERTICAL OUTPUT CIRCUIT EXPLANATION

(See the Vertical Output Circuit for details)

I601 B+:

The Vertical Output IC output for the

, filtered by

D922

PWB and is routed through the Vertical B+ Excessive Current Sensor

TRIGGER PULSE:

The Trigger pulse is routed from the Rainforest IC nector pin 10, to the Power Supply PWB Trigger Input on During Trace, the internal Ramp Generator circuit using charging. As it charges, the Pump Up circuit is also charging from the internal switch of output stage push pull pair inside pull pair inside This is only needed for a short duration of time, (retrace) so the Charge Pump circuit eliminates the need for a 50V power supply.

(V BLK) VERTICAL BLANKING PULSE GENERATION:

When the Charge Pump discharges and produces the 50V p/p pulse for Vertical drive during retrace, this pulse at pin 11 is also routed as the Vertical Blanking pulse. It’s amplitude is around 21V p/p and is sent to the following circuits;

VERTICAL OUTPUT PULSE:

The Vertical Output pulse is then routed to the Vertical Yokes generating a linear sawtooth current which moves the beam. (Trace = from top to bottom, Retrace = from bottom to top). This linear current is generated by the charge time constant of the vertical yokes charging

VERTICAL YOKE CHARGE PULSE:

The pulse generated on the positive side of cuit of

R621

and focus. The pulse generated on the positive side of this signal is for vertical linearity compensation. The DC component of this signal and the DC component provided by the Vertical size pot into pin 4 are routed back to the Ramp generator circuit described above. The DC component determines the charge time associated with the ramp generator or in other words, the Vertical height.

D SIZE SWITCH:

When Magic Focus is activated by either the Magic Focus button or customer’s menu or during service when the sensors are initialized,

connector. When

PDS

to ground. This increases the Vertical size to allow positive contact of the light pattern hitting the sensors.

SW+28V

C933, L918, C934

I601

I601.

I601

• Vertical Sweep Loss detection circuit

• Convergence circuit for vertical correction waveform generation

• To the

and

PPD3, PPS3

processor uses this signal to time it’s OSD.

C608

requires

I601

pulse is from pin 15 of

pin 3.

When the Trigger pulse arrives (Retrace Time), the internal switch toggles over to the

already have +28V input from pin 10. So the output pulse from pin 1 is now near 50V p/p.

to the side pincushion circuit and to the dynamic focus circuit for corrections to deflection

receives the

Q603

turns on, it bypasses

Q603

SW+28V

and output from the

, and the +28V charged capacitor

I601

connector pin 12 to be sent to various circuits on the signal PWB. The Micro-

to operated. This voltage is supplied from the Power Supply. The

. This power supply is protected by

T901

connector pin 1 and 2. It arrives at the Deflection

PPD5

R629, Q604

I501

connector pin 10 to the Deflection PWB. It is then sent to the

PPS3

through the low ohm resistors

C607

is also routed through the parabolic wave form generation cir-

C607

is also routed back to

C607

command from the Digital Convergence Unit,

D Size

and lowers the resistance from

R611

on the Signal PWB. It is output to the

connected to pin 7 as the time constant begins

C603

SW+28V

C605

I601

to pin 10 of

discharges. The output stage push

pin 8 and 9. The AC component of

, through pin 11 to an

C605

R619, R620

R607

, rectified by

E904

I601

UKDG

(Vertical Size Pot)

con-

PPS3

pin 15 of

PAGE 05-07

Page 66

To Conv.

Circuit

PPD3

PPS3

DP-3X CHASSIS VERTICAL OUTPUT CIRCUIT DIAGRAM

To Micro. for OSD Positioning

I501

Main Y Direct

Protect_Def

PPS3

R632

Power

Supply PWB

28V

R626

PMB

2 1

V+

V-

V. Def. Yoke B

V.Blk.

PAGE 05-08

Power Supply

C611

R602

To Vertical Sweep Loss Detection Circuit

Q601

R634

R603

R611

R635

R612

D Size

PWB

D602

C612

C601

Q603

V.Blk.

V Drive

Signal PWB

D601

C603

Q602

R607 V Size

C602

VP Out

I601

Gnd

Trigger Input

Ramp Gen

R608

VCC

HVCO

VD1 In

V OUT

Output

Stage Vs

Flyback

Gen

Inverting

Input

Buffer

Out

V OUT

Hight

Adj

55 21

HVcc 9.3 V

1 2

V.Blk.

R609

R618

Osc.

V. Sync In

From Flex Converter

C605

Charge

Pump

R604

R613

R614

D612

D603

D608

R631

R699

R605

D604 D607

R637 R636

Q604

R630

C604

D610 D611

R617

R606

C606

R619

1.2 ohm

C610

L601

R622

R616

D605

R629

0.68

L602

C609

R620

1.2 ohm

R621

C607 2200/25

R627

R628

R625

PDD1

PMG

V+

V-

PMR

V+

V-

D606

V. Saw Out

C608

V. Inf.

V. Def. Yoke G

V. Def. YokeR

To Side Pin Cushion Circuit

To Dynamic Focus Circuit

Page 67

DP-3X SIDE PINCUSHION CIRCUIT EXPLANATION

(See the Side Pincushion Circuit Diagram for details)

Due to the nature of deflection, the sides of the picture has a tendencies to pull in similar to an hour glass. The Side pincushion circuit is responsible for manipulating deflection to compensate. This is accomplished by super imposing a vertical parabolic waveform on the DC voltage utilized for Horizontal Size.

VERTICAL YOKE CHARGE PULSE:

The pulse generated on the positive side of

, and

R621

SIDE PIN WAVE FORM GENERATION IC:

Then through to this input circuit is the Horizontal Size circuit comprised of variable resistor pin 5 to the feedback circuit from the Side Pin Cushion output circuit for stability.

The output of the DC offset voltage with Vertical parabolic wave form attached is then routed out pin 7 to the base of This transistor drives the base of the Side Pin Cushion modulator transistor nected to the Deflection SW +115V. The DC offset voltage and Vertical parabolic side pin cushion compensation wave form is now super imposed on the SW +115V which is sent to the Deflection Transformer Horizontal Linearity circuit

D SIZE SWITCH:

When Magic Focus is activated by either the Magic Focus button or the customer’s menu or during service when the sensors are initialized, 15 of to ground. This increases the Horizontal size to allow positive contact of the light pattern hitting the sensors.

Q703

PDG

to the side pincushion circuit.

C608

R742, C702, R709

which adjust the DC level at pin

R711

. This transistor has its emitter off set above ground by

connector. When

to pin 6 of

C715, L703, R729

receives the

Q710

turns on, it bypasses

Q710

(See Vertical Output Circuit for details)

is routed through the parabolic wave form generation circuit of

C607

. This is the negative leg of the internal op-amp. Also attached

I701

R710, R711, R713

. The positive leg of the op-amp is connected through

D713, R747

Q701

and

D Size

to the Horizontal Yoke returns.

R756

command from the Digital Convergence Unit,

and lowers the resistance from the emitter of

R714

and clamped by

back to the

. The collector of

SW +9V

D714.

and

Q701

T701

UKDG

The

R704

is con-

and the

Q701

PAGE 05-09

Page 68

DP-3X SIDE PINCUSHION CIRCUIT DIAGRAM

SW +115V

Q701

R701

R702

R703

R714

PAGE 05-10

R706

D701

R707

Q703

R704

D713

Q710

R715

C701

R708

8.96V

R747

Sensor Initialize = Hi Magic Focus = Hi

D SIZE

SW +9V

8 6 57

I701

1 3 42

C722 R721

4.39V 5.17V 5.14V

Deflection Horizontal Driver

Q777

R709

R710

R712

H Size

Adj

R713

6 1

SW+11V

R711

D714

T701

C702

7 8

V Parabolic

R742

To Q705 H. Blk Generator

R756

C715 L703 R729

To H. Deflection Yokes

To H. Linearity off H. Yoke Returns

L704, L705

Page 69

DIGITAL

CONVERGENCE

INFORMATION

DP-3X

CHASSIS INFORMATION

SECTION 6

Page 70

DP-3X BLANK PAGE “NOTES”

BLANK PAGE

Page 71

DP-3X DIGITAL CONVERGENCE INTERFACE CIRCUIT EXPLANATION

See Digital Convergence Interconnection Circuit Diagram for details.

The Digital Convergence circuit is responsible for maintaining proper convergence of all three colors being produced by the CRTs. Many different abnormalities can be quickly corrected by running Magic Focus. The Digital convergence Interconnect Diagram depicts how the Digital Convergence Circuit is interfaced with the rest of the Projection’s circuits. The main components and/or circuits are;

• THE DIGITAL CONVERGENCE UNIT (called DCU)

• CONVERGENCE OUTPUT TO STKs

• CONVERGENCE YOKES

• MAGIC FOCUS SENSORS AND INTERFACE

• MAGIC FOCUS activation by Magic Focus Switch on Front Control Panel or customer’s Menu.

• MICROPROCESSOR

• RAINFOREST IC (Video Processor).

• SERVICE ONLY SWITCH

• INFRARED REMOTE RECEIVER

• ON SCREEN DISPLAY PATH

THE DIGITAL CONVERGENCE UNIT (DCU) (8 Sensor array).

The DCU is the heart of the Digital convergence circuit. Held within are all the necessary components for generating the necessary waveforms for correction, and associated memories for the adjustment data and Magic Focus Data.

Sensors (X8)

To Video Circuits

Via O.S.D.

Displays CrossHatch

256 Adjusted

Points

Per/Color

117 Points Per/Color

Addressable

Technician

Also available; 35 Adjustment Points 9 Adjustment Points

Remote Control

Infra-Red Decoder

One Chip CPU

8 bit

128 Kbit

EEPROM

(2Kbit)

117 Points Per/Color

Adjust through observation

Stored during Initialize

Stored Light Sensor Data

Data Comparator

between stored data

and light sensor data

SLOW

EEPROM

2K Bit

Error Data

Digital Cross

Hatch Gen.

Serial/Parallel

Gate Array 4000 gates

Technician's Eye

Serial-Parallel

Converter

S-RAM

(256Kbit)

FAST

D/A Conv.

Static Centering

Timing

Controller

Converter

Timing

Controler

SCREEN

A/D

Sensor PWB

D/A

Calculation of other 139 points per/color

INTERPOLATION

Back Up

1st S/H

2nd S/H

X6 X6 X6X6X1

Light

LPF

DIGITAL CONVERGENCE CIRCUIT

CRT

CLAMP

CY CLAMP

MIRROR

AC Applied, Copy from EEPROM, then caculations will be made. Time, approx. 20 sec.

Figure 1

The Block above shows the relationship of the DCU to the rest of the set. Note that the light being produced by the CRTs is what is used by the sensors for Magic Focus. This allows the DCU to make adjustments regardless of circuit or mechanical changes or magnet influence, by actually using the light on the screen to make judgments.

EEPROM AND SRAM SHOWN IN FIGURE 1: (8 Sensor Array). Each color can be adjusted in any one of 117 different locations. The internal workings of the DCU can actually make 256 adjustment points per color. These adjustment points are actual digital data stored in memory. This

(Continued on page 2)

PAGE 06-01

Page 72

DP-3X DIGITAL CONVERGENCE INTERFACE CIRCUIT EXPLANATION

data represents a specific correction signal for that specific location. When the Service Technician makes any adjustment, the new information must be stored in memory, EEPROM. The EEPROM only stores the 117 different adjustment points data, the SRAM interpolates to come up the additional 139 adjustment points for a total of 256 per color. The EEPROM data is slow in relationship to the actual deflection raster change. The SRAM is a very fast memory. So, during the first application of AC power, the EEPROM data is read and the SRAM makes the interpolation and as long as power remains, interpolation no longer has to be made. This can be seen during an adjustment. If the Interpolation key is pressed on the remote control, what is happening is that the SRAM must make those additional calculations beyond the 117 made by the Servicer and this is all placed into memory.

INFRARED REMOTE CONTROL INPUT SHOWN IN FIGURE 1:

As can be seen in Figure 1, the Infrared Remote control signals actually manipulate the internal data when the Service Only Switch is pressed on the Deflection PWB. This process prevents the Microprocessor from responding to Remote commands, via a Busy line output from the DCU.

INTERNAL CONTROLLER, D/A CONVERTERS SHOWN IN FIGURE 1:

The internal controller, takes the stored data and converts it to a complicated Convergence correction waveform for each color. The Data is converted through the D/A converter, 1st and 2nd sample and hold, the Low Pass Filter that smoothes out the parasitic harmonic pulses from the digital circuit and the output Clamp that fixes the DC offset level. The DC offset voltage is adjusted by several things.

•

Raster Centering

and Vertical direction. This Offset voltage will move the entire raster Up or Down, Left or Right.

When a complete Digital Convergence procedure has been performed and the adjustment information stored in memory by pressing the

If Sensor Initialization is not performed, the set will not allow Magic Focus to operate. If the Magic Focus button is pressed, the screen will display an adjustment grid instead.

This is done by pressing the begins a preprogrammed generation of different light patterns. Magic Focus memory memorizes the characteristics of the light pattern produced by the digital convergence module. If a convergence touchup is required in the future, the customer simply presses the menu and the set begins another preprogrammed production of different light patterns. This automated process duplicates the same light pattern it memorized from the initialization process, re-aligns the set to the memorized convergence condition. Note that this process is using “Light” as it’s source. This is a better process than using waveforms or voltages as it is adjusting using the actual light pattern as see by the customer.

“MAGIC

This process is a joint effort between the digital convergence module and 8 Photo-sensors, physically located on the corners and center of the cabinet, just behind the screen. The physical placement of the sensors assures that they will not produce a shadow on the screen that can be seen by the customer. Magic Focus is activated by pressing the Magic Focus button inside the front control panel door or by the Customer’s Menu. An on-screen graphic display pattern will be displayed to confirm that the automatic convergence mode (Magic Focus) has begun. The digital convergence module produces different patterns for each CRT, and the sensors on the side of the cabinet pick up the transmitted light and generate a DC voltage. This voltage is sent to the DCU and converted to digital data and compared with the memorized sensor initialization data. Distinct patterns will be generated in each primary color. As the process continues, the digital module manipulates the convergence correction waveforms that it is producing to force the convergence back into the original memorized configuration. When all cycles have been completed, the set will return to the original signal and the convergence will be corrected. In most cases, activating the Magic Focus will allow the set to correct itself, without further adjustments.

FOCUS”

. The Raster Centering adjustment actually moves the DC offset voltage for Horizontal

PIP Mode

SENSORS SHOWN ON FIGURE 1:

button twice (2), it is mandatory

PIP-MODE

button on the remote one (1) time, then pressing the

Magic Focus

button on the front panel or activates it from the customer’s

to run Sensor Initialization.

SURF

button. This

(Continued on page 3)

PAGE 06-02

Page 73

DP-3X DIGITAL CONVERGENCE INTERFACE CIRCUIT EXPLANATION

EXPLANATION OF THE DIGITAL CONVERGENCE INTERCONNECT DIAGRAM:

INFRARED RECEIVER:

During normal operations, the IR receiver directs it signal to the Main Microprocessor where it interprets the incoming signal and performs a predefined set of operations. However, when the Service Only Switch is pressed, the Main Microprocessor ignores remote control commands. Now the DCU receives theses commands and interprets them accordingly. The Microprocessor is notified at pin 42 when the DCU begins its operation by the BUSY line. As long as the BUSY line is active, the Main Microprocessor ignores the IR signal.

ON SCREEN DISPLAY PATH:

MICROPROCESSOR SOURCE FOR OSD:

The On Screen Display signal path is shown with the normal OSD information such as Channel Numbers, Volume Graphic Bar, Main Menu, Service Menu, etc… sent from the Main Microprocessor pins 34, 33 and 32 to the Rainforest pendant upon there actual horizontal time for display.

DCU (Digital Convergence Unit P/N CS00731) SOURCE FOR OSD:

The DCU has to produce graphics as well. When the Service Only switch is pressed, the Main Microprocessor knows the DCU is Busy as described before. Now the On Screen Display path is from the DCU pins 22, 21 and

to the Rainforest

The output for the DCU OSD characters is output through the

and 22 Dig Blue

) to the

Blue

(

Q519 Dig Red, Q520 Dig Green and Q521 Dig Blue

Red, 25 Dig Green and 24 Dig Blue

is saturated and the output is generated to the CRTs. Any combination for these inputs generates either the primary color Red, Green or Blue or the complementary color Red and Green which creates Yellow, Red and Blue which creates Magenta or Green and Blue which creates Cyan.

OUTPUT STKs IK05 and IK04:

These are output amplifiers that take the correction waveforms generated by the DCU and amplify them to be used by the Convergence Yoke assemblies for each color. RV is Red Vertical Convergence correction. Adjust the location either up or down for Red. RH is Red Horizontal Convergence correction. Adjust the location either left or right for Red. GV is Green Vertical Convergence correction. Adjust the location either up or down for Red. GH is Green Horizontal Convergence correction. Adjust the location either left or right for Red. BV is Blue Vertical Convergence correction. Adjust the location either up or down for Red. BH is Blue Horizontal Convergence correction. Adjust the location either left or right for Red.

CONVERGENCE YOKES:

Each CRT has a Deflection Yoke and a Convergence Yoke assembly. The Deflection manipulates the beam in accordance to the waveforms produced within the Horizontal and Vertical Deflection circuits. The Convergence Yoke assembly manipulates the Beam in accordance with the correction waveforms produced by the DCU.

MAGIC FOCUS SENSORS AND INTERFACE: (8 Sensor Array).

Each of the eight photo cells, called solar batteries in the service manual, have their own amps which develop the DC potential produced by the photo cells. Each amp is routed through the connector on the DCU where the DCU converts this DC voltage to Digital signals. These digital signals are used only when the Magic Focus Button is pressed and Magic Focus runs or during Initialization of the sensors.

pins 21, 19 and 18. These are positive going pulses, about 5 V p/p and about 3uS in length de-

I501

pins 24, 25 and 26.

I501

). These are routed through their buffers (

PPD1, PPS1

connector pins (

). When a character pulse arrives at any of these pins, the internal color amp

connector pins (

PDG

QK06 Dig Red, QK07 Dig Green and QK08 Dig

1 Dig Red, 4 Dig Green and 8 Dig Blue

). Then it arrives at the Rainforest

connector and arrives at the

PDS1

20 Dig Red, 21 Dig Green

). Then through their buffers,

at pins (

I501

26 Dig

PDS

(Continued on page 4)

PAGE 06-03

Page 74

DP-3X DIGITAL CONVERGENCE INTERFACE CIRCUIT EXPLANATION

MICROPROCESSOR:

The Microprocessor is only involved in the Digital Convergence circuit related to disabling IR (Infrared Remote Control Signals). When the DCU is put into the Digital Convergence Adjustment Mode (DCAM) or Magic Focus, the Microprocessor ignores IR pulses. This is accomplished by the signal is routed from the DCU out the nector pin 2 to the Microprocessor

I001

connector pin 19, to the

PDG

PDD1

pin 42 telling the Microprocessor that the DCU is busy.

RAINFOREST IC (Video Processor).

The Rainforest

is only involved with the Digital Convergence circuit related to OSD and Velocity Modula-

I501

tion inhibit during Digital convergence OSD operation in which it inhibits the Luminance from the main video. This is accomplished by pin 2 of

I501

DCU YS

from pin 19 of the

connector to

PDG

SERVICE ONLY SWITCH:

The Service Only Switch is located just in front of the DCU on the Deflection PWB. If the front speaker grills are removed and the front access panel is opened, the switch will be on the far left hand side. When this button is pressed with the TV ON, the DCU enters the Digital Convergence Adjustment Mode. If the button is pressed and held down with the TV OFF and the power button is pressed, the Digital Convergence RAM is cleared. This turns off any influence from the DCU related to beam deflection. Magnetic centering is performed in the mode as well as the ability to enter the 3X3, (9 adjustment points) mode.

: The Digital Convergence Adjustment Mode DCAM can be entered by the Remote Control. Magic

NOTE

Focus must be able to run. Press Magic Focus button on front panel, while its running, press the Magic Focus button in and hold. Stop will be displayed. Press the

button on the remote while STOP is dis-

INFO

played.

MAGIC FOCUS SWITCH:

• Located on the Front Control panel is the Magic Focus switch. When Magic Focus is activated by the customer pressing this switch, the DCU enters the “MAGIC

FOCUS”

• When the Customer presses the Magic Focus Switch, the low is sent to the Microprocessor Microprocessor pin 44 then communicates with (Magic Sw). This low is routed through the

PPS1, PPD1

pin 8 (Level Shift) and it outputs a low on pin 12

I010

connector pin 5 to the DCU connector

This starts the Magic Focus function.

• Also the Magic Focus can be started from the Customer’s Menu by this same process.

CONVERGENCE MUTE:

is the convergence mute IC. When the +28V line collapses when power is turned off, it’s possible that the

IK02

output STKs could be damaged. To prevent this, put a Mute signal to pin 21 of connector

on the Digital Convergence Unit.

PDS

monitors the +28V line. If it falls too low, pin 3 will out-

IK02

CUSTOMER’S MANUAL DIGITAL CONVERGENCE ADJUST:

This year, the Digital convergence can be adjusted by the customer. This is accessed from the Video Menu and selecting Magic Focus. Under the Magic Focus menu, select Manual. (See Figure). They have access to the 117 adjustment points for Red and Blue. (Green is fixed as reference). However, if after adjusting using this process, the customer can no longer use Magic Focus. To regain Magic Focus operation, return to the Customer’s Menu-Video-Magic Focus and select AUTO. Magic Focus will become functional however, manual adjustment data is lost.

signal from the DCU. The

BUSY

connector pin 2, then the

QK09

PPD1 PPS1

PPS1

pin 2 to

Q518

adjustment mode described earlier.

pin 45. The

I001

PDS

Video

Magic Focus

Aligns the Red, Green, and Blue colors to correct for Magnet Influences.

Adjustment Mode

Auto Manual

If you want to adjust now

Move Sel Select

START

BUSY

con-

pin 1.

PAGE 06-04

Page 75

DP-3X CHASSIS "DIGITAL CONVERGENCE" INTERCONNECTION CIRCUIT DIAGRAM

MAG SW In

I010

3.3V-5V

MAG SW Out

BUSY

Magic Focus

SM09

Ft. Control

DP-33W/DP-36/DP-37/DP-37C/DP-37D/DP-38

PWB

PFS

QM05

QM01

IR Out

HMO2

IR Receiver

PAGE 06-05

IR Out

HMO3

IR Receiver

EFI

2 1

QM07

QM06

IR In

MAG SW

Stby +5V

Signal

PWB

DP-37C/DP-37D/DP-38

S0 ~S7

8 Total

Sensors

5011

LED

I001

Magic Sw In

Digicon Adj

Magic Sw Out

Digicon Busy In

Power

Supply

PWB

Sensor

PWB

GND

OSD B

OSD G

OSD R

Main

PPD1PPS1

PDS1

+5V

OSD B

OSD G

OSD R

BUSY

DK55

Dig R

IR-In

Dig G

Dig B

MAG SW

+5V Digital

QK09

QK07

From QK01

From IK01

Dig OSD B

Dig OSD G

Dig OSD R

Service Only

DCU YS

BUSY

QK06

QK08

Signal PWB 3 of 3

SK01

PDG

Sw Adj

Dig Adj

Dig R

IR-In

Dig G

Dig B

H Blk

D Size

V Blk

-5V

+5V

MAG SW

PDS

Gnd

Digital Convergence

Adjustment Mode

Convergence

"Mounted on

Q517

Q516

Q518

UKDG

CS00731

"DCAM"

Digital

Unit

"DCU"

Deflection

PWB"

Q515

Rainforest

Q521

Q520

PDS

Q519

N/C

Deflection

PWB

RK21

Mute

RK22

I501

OSD B

OSD G

OSD R

Dig OSD B

Dig OSD G

Dig OSD R

2 YS3

DK04

DK86

Normal "Lo"

IK02

DK53

FK01

Mute

RK66

RK67

+28P

10+28P

15 16

-28P

15 16

Mute

DK85

14 13

RK24

Q545 Q548

Q546

Q542Q541 Q544

Q538Q537 Q540

IK05

DK05

IK04

FK02

4817 12

6 7

RK23

+28V

CYV+

CYV-

CYH+

CYH-

CYH+

CYH-

CYV-

CYV+

CYV-

CYH+

CYH-

PSC

To CRTs

To Blue Convergence Yokes

PCB

PCG

To Green Convergence Yokes To Red Convergence Yokes

PCR

Page 76

DP-37 REMOTE CONTROL CLU-5728TSI (P/N HL01828)

Must be in VCR Mode

DP-37 51S500, 57S500, 65S500

POWER

CURSOR UP

CURSOR LEFT

RASTER PHASE

BLUE (13X9)

REMOVE

COLOR

SOURCE WIZARD

DVD

SLEEP

ANT

VOL CH

1 2 3

4 5 6

7 8 9

PHOTO

C.C.

SELECT

CBLVCR

TAPE

EXIT

ASPECT

STB

AMP

CURSOR DOWN

CURSOR RIGHT

RED (7 X 5)

INFO

GREEN (3 X 3)

VIRTUAL HD

CROSSHATCH VIDEO

CORRECTION BUTTONS

CALCULATE

INITIALIZE

PIP MODE +

SURF

WRITE TO

ROM

PRESS (2X)

MUTE

VID 1

VID 2

PIP FREEZE

PIP-MODE

REC

LAST CH

VID 3

SURF

PIP ACCESS

SWAP

HITACHI

CLU-5728TSI

VID 5

VID 4

CENTERING RASTER POSITION

DAY/NIGHT

READ OLD ROM DATA PRESS (2X)

PAGE 06-06

Page 77

DP-33W REMOTE CONTROL CLU-5727TSI (P/N HL01825)

Must be in VCR Mode

46W500

POWER

CURSOR UP

CURSOR LEFT

RASTER PHASE

BLUE (13X9)

REMOVE

COLOR

SOURCE WIZARD

DVD

SLEEP

10+

ANT

VOL CH

1 2 3

4 5 6

7 8 9

VIRTUAL HD

DVD

SELECT

CBLVCR

PVR

EXIT

ASPECT

STB

AMP

INFO

C.C.

SUB TITLE

CURSOR DOWN

CURSOR RIGHT

RED (7 X 5)

GREEN (3 X 3)

CROSSHATCH VIDEO

CORRECTION BUTTONS

CALCULATE

INITIALIZE

PIP MODE +

SURF

WRITE TO

ROM

PRESS (2X)

VID 1

PiP

MODE

REC

MUTE

VID 2

LAST CH

VID 3

DISC MENUNAVI ADVANCED

SURF FRZ

SWAP

HITACHI

CLU-5727TSI

VID 4

ZOOM

DAY/NIGHT

VID 5

CENTERING RASTER POSITION

READ OLD ROM DATA PRESS (2X)

PAGE 06-07

Page 78

DP-37 REMOTE CONTROL CLU-5725TSI (P/N HL01825)

Must be in VCR Mode

DP-37C 57T500, 65T500 and DP-37D 57X500, 65X500

POWER

CURSOR UP

CURSOR LEFT

RASTER PHASE

BLUE (13X9)

REMOVE

COLOR

SOURCE WIZARD

DVD

SLEEP

ANT

VOL CH

1 2 3

4 5 6

7 8 9

AV NET

C.C.

SELECT

CBLVCR

PVR

EXIT

ASPECT

STB

AMP

CURSOR DOWN

CURSOR RIGHT

RED (7 X 5)

INFO

GREEN (3 X 3)

VIRTUAL HD

CROSSHATCH VIDEO

CORRECTION BUTTONS

CALCULATE

INITIALIZE

PIP MODE +

SURF

WRITE TO

ROM

PRESS (2X)

MUTE

VID 1

VID 2

PIP FREEZE

PIP-MODE

REC

LAST CH

VID 3

SURF

PIP ACCESS

SWAP

HITACHI

CLU-5725TSI

VID 5

VID 4

CENTERING RASTER POSITION

DAY/NIGHT

READ OLD ROM DATA PRESS (2X)

PAGE 06-08

Page 79

27.5

37.0

74.0

NOTE: Aspect may not be correct but dimensions are correct.

DIGITAL CONVERGENCE OVERLAY DIMENSIONS

46W500 DP-33W Chassis

OVERLAY DIMENSIONS NORMAL MODE

1018

18.2

81.8

81.8 81.8 81.8 81.8 81.8 81.8 81.8 81.8

H. SIZE

18.2

74.0

37.0

27.5

V. SIZE

Centering Offset

RED OFFSET = 20mm BLUE OFFSET = 35mm

573

PART NUMBER H312275

VERTICAL SIZE = 505mm HORIZONTAL SIZE = 930mm

PAGE 06-09

Page 80

30.5

41.0

82.0

NOTE: Aspect may not be correct but dimensions are correct.

DIGITAL CONVERGENCE OVERLAY DIMENSIONS

51S500 DP-37 Chassis

OVERLAY DIMENSIONS NORMAL MODE

1129

19.7

90.8

90.8 90.8 90.8 90.8 90.8 90.8 90.8 90.8

H. SIZE

19.7

82.0

41.0

30.5

V. SIZE

Centering Offset

RED OFFSET = 20mm BLUE OFFSET = 25mm

635

PART NUMBER H312272

VERTICAL SIZE = 560mm HORIZONTAL SIZE = 1020mm

PAGE 06-10

Page 81

34.1

45.8

91.7

NOTE: Aspect may not be correct but dimensions are correct.

DIGITAL CONVERGENCE OVERLAY DIMENSIONS

57S500 DP-37 / 57T500 DP-37C / 57X500 DP-37D CHASSIS

OVERLAY DIMENSIONS NORMAL MODE

1262

22.0

101.5

101.5 101.5 101.5 101.5 101.5 101.5 101.5 101.5

H. SIZE

22.0

91.7

45.8

34.1

V. SIZE

Centering Offset

RED OFFSET = 20mm BLUE OFFSET = 25mm

710

PART NUMBER H312273

VERTICAL SIZE = 625mm HORIZONTAL SIZE = 1140mm

PAGE 06-11

Page 82

38.6

52.1

104.6

NOTE: Aspect may not be correct but dimensions are correct.

65S500 DP-37 / 65T500 DP-37C / 65X500 DP-37D CHASSIS

OVERLAY DIMENSIONS NORMAL MODE

1439

25.3

115.7

115.7 115.7 115.7 115.7 115.7 115.7 115.7 115.7

H. SIZE

19.7

104.6

52.1

38.6

V. SIZE

Centering Offset

RED OFFSET = 20mm BLUE OFFSET = 25mm

809

PART NUMBER H312274

VERTICAL SIZE = 710mm HORIZONTAL SIZE = 1300mm

PAGE 06-12

Page 83

ADJUSTMENT

INFORMATION

DP-3X

CHASSIS INFORMATION

SECTION 7

Page 84

DP-3X BLANK PAGE “NOTES”

BLANK PAGE

Page 85

DP-3X CHASSIS DCU CROSSHATCH PHASE ADJUSTMENT

Adjustment Preparation:

•

Cut Off adjustment should be finished.

•

Video Control: Brightness 90%, Contrast Max.

Adjustment Procedure: NORMAL MODE

1) Receive any NTSC signal.

2) Screen Format is Normal

3) Press the SERVICE ONLY switch on the Deflection / Convergence PWB to enter DCAM.

4) Press the PHOTO key on the Remote, Green Cross hatch appears.

5) Then press the EXIT key. (This is the Phase

adjustment mode).

6) Adjust data value using the keys indicated in the chart, until the data matches the values indicated in the chart.

Exiting Adjustment Mode:

7) Press PHOTO key on

remote control.

8) Press PIP MODE key

TWICE to store the information.

9) When Green dots are

displayed, press the MUTE key twice to return to DCAM grid.

*DCA stands for (Digital Convergence Adjustment)

PHASE MODE Display Format NORMAL

ADJUST USING

4 and 6 keys on Remote

2 and 5 keys on Remote

Cursor Left and Right on Remote

Cursor Up and Down on Remote

Address

Data Value

PH-H E2

PH-V 07

CR-H 35

CR-V 14

PAGE 07-01

Page 86

DP-3X VERTICAL SIZE ADJUSTMENT

VERTICAL SIZE:

1) Receive an NTSC signal.

2) With Power Off, press the Service Only switch on the Convergence PWB. While holding the Service Only Switch down, press the Power On button and Release. DCU Grid will appear without convergence correction. NOTE: After entering DCAM, with each press of the Service Only Switch, the picture will toggle between Video mode and DCU Grid.

3) Select GREEN (A/CH) and press the MENU button to remove Red and Blue.

4) Adjust using R607

(Vertical Size Adj. VR) to match sizes in the Table Below.

VERTICAL SIZE

NOTE: Centering magnet may be moved to facilitate. Distance is important, not centering.

NOTE: Do not use the Hash marks on the Overlay as they may be incorrect and/or the Vertical Size may change to improve performance.

DP37

Screen Size

46 inch - -

51 inch - -

57 inch 625 mm

65 inch 710 mm

- -

560 mm

625 mm

710 mm

DP37C/D/P

llll

DP36

- -

560 mm

625 mm

710 mm

Top and

Bottom Lines

DP33W

505

- -

PAGE 07-02

Page 87

DP-3X HORIZONTAL SIZE ADJUSTMENT

HORIZONTAL SIZE: (Display Mode NORMAL)

•

Install the correct Overlay.

•

Input an NTSC Signal.

•

Digital Convergence RAM should be cleared. With Power Off, press the Service Only switch on the Convergence PWB. While holding the Service Only Switch down, press the Power On button and Release. DCU Grid will appear without convergence correction.

NOTE: After entering DCAM, with each press of the Service Only Switch, the picture will toggle between Video mode and DCU Grid.

•

Project only the Green raster by selecting Green Adjustment mode and pressing the MENU button on remote.

ADJUSTMENT

1. Adjust using R711

(Horz. Size Adj. VR) Ad-

HORIZONTAL SIZE

just Horizontal Size until the size matches the chart below.

2) Press “Power Off” to exit

DCAM. (Digital Convergence Adjustment Mode.)

NOTE: Do not use the Hash marks on the Overlay as they may be incorrect and/or the Vertical Size may change to improve performance.

Outside Left and Right

hand lines

llll

DP37

Screen Size

46 inch - -

51 inch - -

57 inch 1140 mm

65 inch 1300 mm

- -

1020 mm

1140 mm

1300 mm

DP37C/D/P

DP36

- -

1005 mm

1120 mm

1280 mm

DP33W

930

- -

PAGE 07-03

Page 88

DP-3X CHASSIS RED AND BLUE RASTER OFFSET ADJUSTMENT

INFORMATION:

Raster Offset is necessary to conserve Memory allocation. It is very important to remember that the Red is offset Left of Center and Blue is offset Right of center. Please use the following information to accurately offset Red and Blue from center. Also see Overlay Dimensions for further details.

Preparation for adjustment:

• With Power Off, press the Service Only switch on the Convergence PWB. While holding the Service Only Switch down, press the Power On button and Release. DCU Grid will appear without convergence correction. NOTE: After entering DCAM, with each press of the Service Only Switch, the picture will toggle between Video mode and DCU Grid.

• Video Control should be set at Factory Preset condition.

• Static Focus adjustment should be finished.

Adjustment Procedure

1. Turn the centering magnets of Red, Green and Blue and adjust so that the center point of the cross-hatch

pattern satisfies the diagram and Offset Value Table below. (DCU data is cleared). Remember Green is Centered. Red is to the left of Green and Blue is to the right of Green as indicated below.

• All Vertical positions are geometric center of screen.

• Parameters are +/- 2mm.

Offset Value Table

SCREEN SIZE Red Offset Blue Offset

46 inch

51 inch

57 inch

65 inch

Geometric Vertical Center

Red Offset

20mm 35mm

20mm 25mm

Red Blue

Blue Offset

Green

Geometric Horizontal

PAGE 07-04

Page 89

DP-3X CHASSIS MAGIC FOCUS “CHARACTER SET UP”

NOTE: This instruction should be applied when a new DCU is being replaced.

Adjustment Preparation:

1. Receive NTSC RF or Video Signal.

2. With Power Off, Press and HOLD the

SERVICE ONLY

button on the Convergence/ Focus PWB, then press the Power On/Off and release. When picture appears, release Service Only switch. (DCU grid is displayed without convergence correction data.

Adjustment Procedure:

1. Press the

FREEZE

key on R/ C. (One additional line appears near the top and bottom.

2. Press the

SURF

key, the ADJ. PARAMETER mode is displayed as following.

ADJ.PARAMETER

ADJ. DISP. : 0F DEMO.WAIT : 1F INT. START. : 13 V. SQUEEZE : 10

NOTE:

Press the Cursor Left and Right Button to change the ADJ. DISP. data to match Table 1 on the right.

DATA VALUES CONFIRMATION:

3. Use the Cursor Up and Down keys to scroll through the ADJ. PARAMETER table. Confirm Data values in accordance with

TABLE

make data value changes, Press the Cursor Left and Right keys.

1 to the right. To

4. Press the (

MODE

PIP MODE

in DP-33W) key 2 times to write the changed data into EEPROM.

•

First press, ADJ PARAMETER ROM WRITE ? Is displayed for alarm.

•

2nd press writes data into EEPROM. Green dots appear after completion of operation.

5. Press the

MUTE

times exit back to DCAM.

6. Press the

Switch

Service Only

to exit from DCAM.

7. Power set off.

button 3

TABLE 1 DP-37

Parameter Normal

ADJ. DISP 0F

DEMO WAIT 1F

INT. START 13

V. SQUEEZE 10

INT STEP 1 02

INT STEP 2 06

INT BAR 2D

INT DELAY 01

MGF STEP 1 10

MGF STEP 2 06

MGF BAR 1B

MGF DELAY 01

SEL. STAT. 00

LINE WID 7F

ADD LINE 09

SENSOR CK 00

PORT 0 07

PORT 1 06

PORT 2 05

PORT 3 04

PORT 4 03

PORT 5 02

PORT 6 01

PORT 7 00

AD LEVEL 03

CENT. BAL 00

E. DISPLAY 00

ADJ. TIMS 60

ADJ. LEVEL 05

ADJ. NOISE 0A

OVER LF-H 01

OVER LF-V 00

OVER RI-H 00

OVER RI-V 00

PHASE MOT 60

H. BLK RV 00

H. BLK GV 03

H. BLK BV 00

H. BLK H 20

PON DELAY 0F

IR-CODE 00

INITIAL 50 9E

MGF 50 96

CENTER 50 FE

STAT 50 FE

DYNA 50 9F

PAGE 07-05

Page 90

DP-3X CHASSIS MAGIC FOCUS “PATTERN SET UP”

NOTE: This instruction should be applied when a new DCU is being replaced. This instruction shows how to set up the pattern position for Magic Focus. Each model has a specific set up pattern position.

Adjustment Preparation:

•

Receive NTSC RF or Video Signal.

•

With Power Off, Press and HOLD the

SWITCH

SERVICE ONLY

the Deflection / Convergence PWB, then press the Power On/Off at the same time, until picture appears, then release both. (Picture may be displayed without convergence correction data. Press the Service Only button to bring up Internal Crosshatch.)

Adjustment Procedure:

1. Press the

FREEZE

key on R/C. (One additional line appears near the top and bottom.

2. Press the

PHOTO AV Net DVD

•

The PATTERN mode is dis-

key on DP-37 or

key on DP-37C / D

key on DP-33W

played as follows.

0 1 2

RH : 0A RV : 03

7 3

6 5 4

3. Use the 6 Key to rotate Arrow. Arrow rotates clockwise with each press on the 6 Key.

4. Use the following Keys to switch color of patterns.

•

INFO : GREEN

•

0 : RED

•

ANT : BLUE

5. Press the Thumb Stick Left and Right buttons to change the Pattern Position Data in horizontal Direction. Press the Thumb Stick Up and Down buttons to change the Pattern Position Data in Vertical Direction.

6. Set the Data Values as shown in the Table below.

7. Press the

PIP MODE (MODE

on DP-33W) key 2 times to write the changed data into EEPROM.

•

First press, ADJ PARAMETER ? ROM WRITE ? Is displayed for alarm.

•

2nd press writes data into EEPROM. Green dots appear after completion of operation.

8. Press the

MUTE

button 3 times

exit Pattern Mode.

9. Press the

SWITCH

SERVICE ONLY

to exit DCAM.

10.Power set off.

NORMAL MODE: 46 INCH SETS

NORMAL MODE: 51 and 57 INCH SETS

NORMAL MODE: 65 INCH SETS

PAGE 07-06

Page 91

DP-3X CHASSIS READ FROM ROM NOTES

BEFORE MAKING ANY DIGITAL CONVERGENCE ADJUSTMENTS

Heat Run the set for at least 20 minutes. Do not run Magic Focus before the 20 minutes have passed.

MAKE A DETERMINATION:

1) There are many situations where the digital convergence looks as thought it may need a convergence adjustment.

2) Be sure that it really does before beginning.

3) READ FROM OLD ROM DATA:

4) In any Hitachi Digital convergence set, the Old ROM data can be re-read to place the unit into the last saved condition. This could be beneficial before an attempt to make a rather lengthily adjustment.

5) Enter the DCAM.

•

Press the Service Only switch on the Deflection PWB.

6) To Read the Old ROM Data, press the SWAP button twice.

•

First press: (Read from ROM?) will appear on screen.

•

Second press: Screen goes black, then reappears with green dots.

•

Press the MUTE button to return to Digital convergence grid.

EXAMPLE:

Sometimes the Magic Focus will not run correctly and will return an error code.

Sometimes after Magic Focus is run but the convergence appears off after completion.

OTHER IMPORTANT INFO:

Many times after a complete adjustment, when initializing the Magic Focus sensors, an error code will appear, overflow, Error 4, etc… When this happens, most of the time it is because some critical adjustments were overlooked or skipped. The below adjustments are very critical to the complete alignment process and CAN NOT be overlooked.

•

Vertical Size Adjustment

•

Horizontal Size Adjustment

•

Red and Blue Offset Adjustment

•

DCU Character Adjustment and data confirmation check

•

DCU Sensor Position Adjustment.

All of the above adjustment can vary dependant upon the Chassis used. Be sure to check the Service Manual for specifics related to values.

•

In I2C Bus adjustment: H. POSI Adjustment

PAGE 07-07

Page 92

DP-37 REMOTE CONTROL CLU-5728TSI (P/N HL01828)

Must be in VCR Mode

51S500, 57S500, 65S500

POWER

CURSOR UP

CURSOR LEFT

RASTER PHASE

BLUE (13X9)

REMOVE

COLOR

SOURCE WIZARD

DVD

SLEEP

ANT

VOL CH

1 2 3

4 5 6

7 8 9

PHOTO

C.C.

SELECT

CBLVCR

TAPE

EXIT

ASPECT

STB

AMP

CURSOR DOWN

CURSOR RIGHT

RED (7 X 5)

INFO

GREEN (3 X 3)

VIRTUAL HD

CROSSHATCH VIDEO

CORRECTION BUTTONS

CALCULATE

INITIALIZE

PIP MODE +

SURF

WRITE TO

ROM

PRESS (2X)

MUTE

VID 1

VID 2

PIP FREEZE

PIP-MODE

REC

LAST CH

VID 3

SURF

PIP ACCESS

SWAP

HITACHI

CLU-5728TSI

VID 5

VID 4

CENTERING RASTER POSITION

DAY/NIGHT

READ OLD ROM DATA PRESS (2X)

PAGE 07-08

Page 93

DP-33W REMOTE CONTROL CLU-5727TSI (P/N HL01825)

Must be in VCR Mode

46W500

POWER

CURSOR UP

CURSOR LEFT

RASTER PHASE

BLUE (13X9)

REMOVE

COLOR

SOURCE WIZARD

DVD

SLEEP

10+

ANT

VOL CH

1 2 3

4 5 6

7 8 9

VIRTUAL HD

DVD

SELECT

CBLVCR

PVR

EXIT

ASPECT

STB

AMP

INFO

C.C.

SUB TITLE

CURSOR DOWN

CURSOR RIGHT

RED (7 X 5)

GREEN (3 X 3)

CROSSHATCH VIDEO

CORRECTION BUTTONS

CALCULATE

INITIALIZE

PIP MODE +

SURF

WRITE TO

ROM

PRESS (2X)

VID 1

PiP

MODE

REC

MUTE

VID 2

LAST CH

VID 3

DISC MENUNAVI ADVANCED

SURF FRZ

SWAP

HITACHI

CLU-5727TSI

VID 4

ZOOM

DAY/NIGHT

VID 5

CENTERING RASTER POSITION

READ OLD ROM DATA PRESS (2X)

PAGE 07-09

Page 94

DP-37 REMOTE CONTROL CLU-5725TSI (P/N HL01825)

Must be in VCR Mode

DP-37C 57T500, 65T500 and DP-37D 57X500, 65X500

POWER

CURSOR UP

CURSOR LEFT

RASTER PHASE

BLUE (13X9)

REMOVE

COLOR

SOURCE WIZARD

DVD

SLEEP

ANT

VOL CH

1 2 3

4 5 6

7 8 9

AV NET

C.C.

SELECT

CBLVCR

PVR

EXIT

ASPECT

STB

AMP

CURSOR DOWN

CURSOR RIGHT

RED (7 X 5)

INFO

GREEN (3 X 3)

VIRTUAL HD

CROSSHATCH VIDEO

CORRECTION BUTTONS

CALCULATE

INITIALIZE

PIP MODE +

SURF

WRITE TO

ROM

PRESS (2X)

MUTE

VID 1

VID 2

PIP FREEZE

PIP-MODE

REC

LAST CH

VID 3

SURF

PIP ACCESS

SWAP

HITACHI

CLU-5725TSI

VID 5

VID 4

CENTERING RASTER POSITION

DAY/NIGHT

READ OLD ROM DATA PRESS (2X)

PAGE 07-10

Page 95

CONVERGENCE USING OUTSIDE SIGNAL SOURCE

By superimposing the digital cross hatch on the main picture or the adjustment point on the main picture, adjustments can be made that are more specific to errors seen while observing the main picture instead of only the cross hatch pattern.

Marker (Adjustment Point)

Press the "Service Only" switch on the Deflection PWB to bring up the normal Convergence Cross Ha tch pattern. (Figure 1).

Marker

Press the "Menu" button on the remote control. Only display color selected for adjustment. (Note Green always appears), in this case, Red is selected, so Red and Green (yellow) lines appears. (Figure 2).

Press the "Menu" button again and the Crosshatch appears on the main picture. (Figure 3).

Press the "Menu" button again, Marker plus Box marker appears on the main picture. (Figure 4).

Press the "Menu" button again, only Box marker appears on the main picture. (Figure 5).

Marker

Only Box Marker

By pressing the "Menu" button, this cycle will repeat.

PAGE 07-11

Page 96

MAGIC FOCUS ERROR CODES FOR THE DP-3X CHASSIS

CONVERGENCE ERRORS:

If an error message or code appears while performing MAGIC FOCUS or initialize ( Digital Convergence Adjustment Mode, follow this confirmation and repair method.

1) Turn on Power and receive any signal.

2) Press the Service Only Switch on the Deflection / Convergence Output PWB.

3) Press

4) Error code will be displayed in bottom right corner of screen.

5) If there is no error, and

SWAP

and then the

INITIAL OK

buttons on the remote control.

SURF

will appear on screen.

PIP MODE

and

SURF

ERROR!!

Error Code

6) Follow repair table for errors.

Error

Code

1 VF Error Replace DCU

2 *2

3*2 A/D Level Same as Error Code 2

4 Over Flow 1. Check the placement

Error

Display

Code

Connect 1 1. Darken Outside Light

2. Placing of Sensor

3. Is pattern hitting sensor?

4. Check connection and solder bridge of sensor

5. Replace Sensor.

6. Replace Sensor PWB.

7. Sensor Connector check.

8. Replace DCU.

9. Adjustment check (H/V size, centering).

2. Adjustment check (H/V size, centering).

3. Conv. Amp. Gain check*1 (check resistor values only)

Countermeasure

CONNECT 1!

No. 1 3

ERROR!!.

Application

Initialize Magic

Focus

X X

—

X X

Error Message

Sensor Position

SENSOR POSITION

1 0

7 3

5 4

5 Convergence Same as Error Code 4

7 Operation Same as Error Code 4

9 Connect 2 Same as Error Code 2

10 Noise Input strong field. Strong signal. Check the wiring of

connector between sensor and DCU

11 Sync Input strong field. Strong signal. Check the wiring of

connector between sensor and DCU

*1 = RK 42, 46, 50, 54, 58, 62 check these resistors. *2 = Sensor Position

X X

— X

X X

PAGE 07-12

Page 97

FRONT

DP-3X MAGNETS

Adjustment Points

RED

CRT

GREEN

CRT

BLUE

CRT

7 8 9

1 3

(1) Centering magnet RED (2) Centering magnet GREEN (3) Centering magnet BLUE (4) Beam Form Magnets (5) Beam Alignment magnets (6) Focus Block Assembly

Red, Green & Blue Focus Controls Also: Screen Controls for Red, Green & Blue

(7) RED Yoke (8) GREEN Yoke (9) BLUE Yoke

PAGE 07-13

Page 98

DP-3X BLANK PAGE “NOTES”

BLANK PAGE

Page 99

MISCELLANEOUS

INFORMATION

DP-3X

CHASSIS INFORMATION

SECTION 8

Page 100

DP-3X BLANK PAGE “NOTES”

BLANK PAGE

Hitachi dp3x schematic

Specifications and Main Features

Frequently Asked Questions

User Manual

VERTICAL SIZE

HORIZONTAL SIZE