10/10/06 CONFIDENTIAL INFORMATION-DO NOT COPY 4
October 10, 2006 11:23 am
SupraHD-760-DTS-GEN-v1.0-Preliminary Release
Figure 3: SupraHD-760 Detailed Block Diagram
ZR39760
SADR[13:0], SBS[1:0]_n
SDQM[3:0]
SRAS_n, SCAS_n , SWE_n
SCLK, SCLK_ n, SCKE
SDQS[3:0],
SDATA[15 :0]
SVREF
Memor y
Interface Unit
(MIF)
16
4
3
3
4
16
Embedded
Processi ng Unit
(EPC)
MI PS 4Kec
I Cache
D Cache
MMU
EJTAG
Ctl r .
JTAG
Ctl r .
Counters /
Timer s
6
Transpor t
Processi ng Unit
(TRP)
Xport I /F
Xport Demux
Video Captur e
Uni t
HDMI
NTSC/ PAL
Decoder
8
Audio
Processi ng Unit
(APU)
Di spl ay
Processor
(DPC)
Graphic s
MPEG2 Decode
Uni t
(VDEC)
uControl ler
(MCU)
Sequencer
(MCE)
Flex Bus Unit
(FBU)
MIF BUS (64b)
I2 C Ctlr . 1
I2 C Ctlr . 2
I2 C Ctlr . 3
GPI O
2
2
2
4
IRR
1
I2 C0C, I 2C0D
I2 C1C, I 2C1D
I2 C2C, I 2C2D
GPIO[3:0]
IRR
UART0
2
UART0_TX, UART0_RX
BVCI
Modifi ed
Guest Bus
5
GADR[4:0]
GDAT[7:0]
6
GCS_n[5:0]
1
GWS_ACK
5
GDI R, GOE_n , GI OWR_n , GIORD_n , GWE_n
4
GIRQ[3:0]
CLKI N,
CLKOUT
BVCI/AVCI BUS (64b)
RESET_ n
Video I /F
2
9
13
HDMI_SCL , HDMI_SDA,
HDMI_CEC, HDMI_HPD, HDMI _REXT,
HDMI_D0P, HDMI_D0N, HDMI_D1P,
HDMI_ D1N, HDMI _D2P, HDMID2N,
HDMI_CLKP, HDMI_CLKN
TDO, TDI
TCK, TMS
TRST_N, TAPSEL
10
PVCI BUS (64b)
Link Li st
CLKGEN
DVCXO
PLL
2
BLT
UART1
2
UART1_TX, UART1_RX
ACLK
BCLK, LRCLK
ADATAO[ 2:0 ]
ADATAI [2 :0]
IEC958
PIXOUT[23:0],PCLK, DEN, OSDP,
AFHSI , AFVSI
HDMI
PHY
VFE_YI N, VFE_CI N,
VFE_CVBS, VFE_REFP, VFE_REFN,
VFE_VCM, VFE_I BEXT, VFE_BG
Unique 128- bit
ID
LVDS Output
1
9
LVDS_C_P, LVDS_C_N,
LVDS_D[7:0]_P, LVDS_D[7:0]_N
LVDS_REXT
L/R
Audio
DACs
4
ADATAO[ 2:0 ]
ADATAI [2 ]
Shared
with the
I2S
signal s
AGC
4
IF_AGC, AGC_SENSE, RF_AGC,
PWM_OUT
Demod
7
IFE_AI MP, I FE_VREFP, IFE_VREFN,
IFE_AINN, IFE_RBIAS, IFE_VCM, IFE_VINBIAS
Smart
Antenna
3
SADATA, GPIOx, GPIO,
8
4
TSO_CLK, TSO_FRAME,
TSO_VALID, TSO_DATA
4
TSI_CLK, TSI_FRAME,
TSI_VALID, TSI _DATA
SPI
5SPI_CLK, SPI_SI , SPI _SO,
SPI_HOLD, SPI_WEN