GSI GS88436B-133, GS88418B-200I, GS88418B-200, GS88418B-180I, GS88418B-180 Datasheet

Rev: 1.05 10/2001 1/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

512K x 18, 256K x 36

8Mb S/DCD Sync Burst SRAMs

200 MHz–133 MHz

3.3 V V

DD

3.3 V and 2.5 V I/O

119-Bump BGA
Commercial Temp
Industrial Temp

Features

• FT pin for user-configurable flow through or pipelined
operation

• Single/Dual Cycle Deselect Selectable

• ZQ mode pin for user-selectable high/low output drive strength

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock Control, registered, address, data, and control

• Internal self-timed write cycle

• Automatic power-down for portable applications

• 119-bump BGA package

Functional Description

Applications

The GS88418/36B is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1, in x18 version, E1 and
E2 in x36 version), address burst control inputs (ADSP,
ADSC, ADV), and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive-edge-triggered
clock input (CK). Output enable (G) and power-down control
(ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order

(LBO) input. The Burst function need not be used. New
addresses can be loaded on every cycle with no degradation of
chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by
the user via the FT mode bump (Bump 5R). Holding the FT
mode pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising­edge-triggered Data Output Register.

SCD and DCD Pipelined Reads

The GS88436B is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the
SCD mode input on Bump 4L.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ
low) for multi-drop bus applications and normal drive strength
(ZQ floating or high) point-to-point applications. See the
Output Driver Characteristics chart for details.

Sleep Mode

Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS884B operates on a 3.3 V power supply and all inputs/
outputs are 3.3 V- and 2.5 V-compatible. Separate output
power (V

DDQ

) pins are used to decouple output noise from the

internal circuit.

-200 -180 -166 -150 -133 Unit

Pipeline

3-1-1-1

tCycle

tKQ
IDD

5.0

3.0

450

5. 5

3.2

410

6.0

3.5

380

6.7

3.8

350

7.5

4.0

340

ns
ns

mA

Flow

Through

2-1-1-1

t

KQ

tCycle

I

DD

7.5
10

270

8

10

270

8.5
10

250

9.0
10

240

9.5
10

220

ns
ns

mA

Rev: 1.05 10/2001 2/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

GS88436 Pad Out

119-Bump BGA—Top View

1 2 3 4 5 6 7

A

V

DDQ

A6 A7 ADSP A8 A9 V

DDQ

B

NC E2 A4 ADSC A15 A17 NC

C

NC A5 A3 V

DD

A14 A16 NC

D

DQC4 DQPC9 V

SS

ZQ V

SS

DQPB9 DQB4

E

DQC3 DQC8 V

SS

E1 V

SS

DQB8 DQB3

F

V

DDQ

DQC7 V

SS

G V

SS

DQB7 V

DDQ

G

DQC2 DQC6 BC ADV BB DQB6 DQB2

H

DQC1 DQC5 V

SS

GW V

SS

DQB5 DQB1

J

V

DDQ

V

DD

NC V

DD

NC V

DD

V

DDQ

K

DQD1 DQD5 V

SS

CK V

SS

DQA5 DQA1

L

DQD2 DQD6 BD SCD BA DQA6 DQA2

M

V

DDQ

DQD7 V

SS

BW V

SS

DQA7 V

DDQ

N

DQD3 DQD8 V

SS

A1 V

SS

DQA8 DQA3

P

DQD4 DQPD9 V

SS

A0 V

SS

DQPA9 DQA4

R

NC A2 LBO V

DD

FT A13 NC

T

NC NC A10 A11 A12 NC ZZ

U

V

DDQ

NC NC NC NC NC V

DDQ

Rev: 1.05 10/2001 3/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

GS88418 Pad Out

119-Bump BGA—Top View

1 2 3 4 5 6 7

A

V

DDQ

A6 A7 ADSP A8 A9 V

DDQ

B

NC NC A4 ADSC A15 A17 NC

C

NC A5 A3 V

DD

A14 A16 NC

D

DQB1 NC V

SS

ZQ V

SS

DQA9 NC

E

NC DQB2 V

SS

E1 V

SS

NC DQA8

F

V

DDQ

NC V

SS

G V

SS

DQA7 V

DDQ

G

NC DQB3 BB ADV NC NC DQA6

H

DQB4 NC V

SS

GW V

SS

DQA5 NC

J

V

DDQ

V

DD

NC V

DD

NC V

DD

V

DDQ

K

NC DQB5 V

SS

CK V

SS

NC DQA4

L

DQB6 NC NC SCD BA DQA3 NC

M

V

DDQ

DQB7 V

SS

BW V

SS

NC V

DDQ

N

DQB8 NC V

SS

A1 V

SS

DQA2 NC

P

NC DQB9 V

SS

A0 V

SS

NC DQA1

R

NC A2 LBO V

DD

FT A13 NC

T

NC A10 A11 NC A12 A18 ZZ

U

V

DDQ

NC NC NC NC NC V

DDQ

Rev: 1.05 10/2001 4/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

BPR2000.002.14

GS88418/36 BGA Pin Description

Pin Location Symbol Type Description

P4, N4 A0, A1 I Address field LSBs and Address Counter Preset Inputs

A2, A3, A5, A6, B3, B5, C2, C3, C5,

C6, G4, R2, R6, T3, T5

An I Address Inputs

T4 An I Address Inputs (x36 Version)
T2, T6 NC — No Connect (x36 Version)
T2, T6 An I Address Inputs (x18 Version)

K7, L7, N7, P7, K6, L6, M6, N6, P6
H7, G7, E7, D7, H6, G6, F6, E6, D6
H1, G1, E1, D1, H2, G2, F2, E2, D2

K1, L1, N1, P1, K2, L2, M2, N2, P2

DQA1–DQPA9
DQB1–DQPB9
DQC1–DQPC9
DQD1–DQPD9

I/O Data Input and Output pins (x36 Version)

L5, G5, G3, L3 BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low ( x36 Version)

P7, N6, L6, K7, H6, G7, F6, E7, D6

D1, E2, G2, H1, K2, L1, M2, N1, P2

DQA1–DQA9
DQB1–DQB9

I/O Data Input and Output pins (x18 Version)

L5, G3 BA, BB I Byte Write Enable for DQA, DQB Data I/Os; active low ( x18 Version)

P6, N7, M6, L7, K6, H7, G6, E6, D7,

D2, E1, F2, G1, H2, K1, L2, N2, P1,

G5, L3, T4

NC — No Connect (x18 Version)

K4 CK I Clock Input Signal; active high

E4 E1 I Chip Enable; active low

B2 E2 I Chip Enable; active high

F4 G I Output Enable; active low

T7 ZZ I Sleep Mode control; active high

R5 FT I Flow Through or Pipeline mode; active low

R3 LBO I Linear Burst Order mode; active low

L4 SCD I Single Cycle Deselect/Dual Cycle Deselect Mode Control

D4 ZQ I

FLXDrive Output Impedance Control

(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

B1, C1, R1, T1, L4, B7, C7, U6, R7,

J3,J5, U2, U3, U4, U5

NC — No Connect

J2, C4, J4, R4, J6

V

DD

I Core power supply

D3, E3, F3, H3, K3, M3, N3, P3, D5,

E5, F5, H5, K5, M5, N5, P5

V

SS

I I/O and Core Ground

A1, F1, J1, M1, U1, A7, F7, J7, M7,

U7

V

DDQ

I Output driver power supply

Rev: 1.05 10/2001 5/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

GS88418/36 Block Diagram

A1

A0

A0

A1

D0
D1

Q1

Q0

Counter

Load

D Q

D Q

Register

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

DQ

Register

DQ

Register

A0–An

LBO
ADV

CK
ADSC

ADSP
GW

BW
BA

BB

BC

BD

E1

G

ZZ

Power Down

Control

Memory

Array

18

18

4

A

Q D

DQx0–DQx9

Note: Only x18 version shown for simplicity.

DCD=0

SCD=1

FT

Rev: 1.05 10/2001 6/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

Note:
There are pull-up devices on the LBO, ZQ, SCD, and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and
the chip will operate in the default states as specified in the above table.

Enable / Disable Parity I/O Pins

This SRAM allows the user to configure the device to operate in Parity I/O active (x18 or x36) or in Parity I/O inactive (x16 or
x32) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Tying PE high
deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits
generated and read into the ByteSafe parity circuits.

Burst Counter Sequences

BPR 1999.05.18

Mode Pin Functions

Mode Name Pin Name State Function

Burst Order Control LBO

L Linear Burst

H or NC Interleaved Burst

Output Register Control FT

L Flow Through

H or NC Pipeline

Power Down Control ZZ

L or NC Active

H

Standby, IDD = I

SB

Single/Dual Cycle Deselect Control SCD

L Dual Cycle Deselect

H or NC Single Cycle Deselect

FLXDrive Output Impedance Control ZQ

L High Drive (Low Impedance)

H Low Drive (High Impedance)

Linear Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

I

nterleaved Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01
4th address 11 00 01 10

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01

4th address 11 10 01 00

Rev: 1.05 10/2001 7/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

Byte Write Truth Table

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “C” and “D” are only available on the x36 version.

Function GW BW BA BB BC BD Notes

Read H H X X X X 1

Read H L H H H H 1
Write byte a H L L H H H 2, 3
Write byte b H L H L H H 2, 3
Write byte c H L H H L H 2, 3, 4
Write byte d H L H H H L 2, 3, 4

Write all bytes H L L L L L 2, 3, 4
Write all bytes L X X X X X

Rev: 1.05 10/2001 8/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

Synchronous Truth Table

Operation

Address

Used

State

Diagram

Key

5

E1

E2

2

(x36only)

ADSP ADSC ADV

W

3

DQ

4

Deselect Cycle, Power Down None X H X X L X X High-Z

Deselect Cycle, Power Down None X L F L X X X High-Z

Deselect Cycle, Power Down None X L F H L X X High-Z

Read Cycle, Begin Burst External R L T L X X X Q

Read Cycle, Begin Burst External R L T H L X F Q
Write Cycle, Begin Burst External W L T H L X T D

Read Cycle, Continue Burst Next CR X X H H L F Q

Read Cycle, Continue Burst Next CR H X X H L F Q

Write Cycle, Continue Burst Next CW X X H H L T D

Write Cycle, Continue Burst Next CW H X X H L T D
Read Cycle, Suspend Burst Current X X H H H F Q
Read Cycle, Suspend Burst Current H X X H H F Q
Write Cycle, Suspend Burst Current X X H H H T D
Write Cycle, Suspend Burst Current H X X H H T D

Notes:

1. X = Don’t Care, H = High, L = Low.

2. For x36 Version, E = T (True) if E2 = 1; E = F (False) if E2 = 0.

3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.

4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).

5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.

6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.