GSI GS88436B-133, GS88418B-200I, GS88418B-200, GS88418B-180I, GS88418B-180 Datasheet

Rev: 1.05 10/2001 1/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

512K x 18, 256K x 36

8Mb S/DCD Sync Burst SRAMs

200 MHz–133 MHz

3.3 V V

DD

3.3 V and 2.5 V I/O

119-Bump BGA
Commercial Temp
Industrial Temp

Features

• FT pin for user-configurable flow through or pipelined
operation

• Single/Dual Cycle Deselect Selectable

• ZQ mode pin for user-selectable high/low output drive strength

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock Control, registered, address, data, and control

• Internal self-timed write cycle

• Automatic power-down for portable applications

• 119-bump BGA package

Functional Description

Applications

The GS88418/36B is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1, in x18 version, E1 and
E2 in x36 version), address burst control inputs (ADSP,
ADSC, ADV), and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive-edge-triggered
clock input (CK). Output enable (G) and power-down control
(ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order

(LBO) input. The Burst function need not be used. New
addresses can be loaded on every cycle with no degradation of
chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by
the user via the FT mode bump (Bump 5R). Holding the FT
mode pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising­edge-triggered Data Output Register.

SCD and DCD Pipelined Reads

The GS88436B is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the
SCD mode input on Bump 4L.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ
low) for multi-drop bus applications and normal drive strength
(ZQ floating or high) point-to-point applications. See the
Output Driver Characteristics chart for details.

Sleep Mode

Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS884B operates on a 3.3 V power supply and all inputs/
outputs are 3.3 V- and 2.5 V-compatible. Separate output
power (V

DDQ

) pins are used to decouple output noise from the

internal circuit.

-200 -180 -166 -150 -133 Unit

Pipeline

3-1-1-1

tCycle

tKQ
IDD

5.0

3.0

450

5. 5

3.2

410

6.0

3.5

380

6.7

3.8

350

7.5

4.0

340

ns
ns

mA

Flow

Through

2-1-1-1

t

KQ

tCycle

I

DD

7.5
10

270

8

10

270

8.5
10

250

9.0
10

240

9.5
10

220

ns
ns

mA

Rev: 1.05 10/2001 2/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

GS88436 Pad Out

119-Bump BGA—Top View

1 2 3 4 5 6 7

A

V

DDQ

A6 A7 ADSP A8 A9 V

DDQ

B

NC E2 A4 ADSC A15 A17 NC

C

NC A5 A3 V

DD

A14 A16 NC

D

DQC4 DQPC9 V

SS

ZQ V

SS

DQPB9 DQB4

E

DQC3 DQC8 V

SS

E1 V

SS

DQB8 DQB3

F

V

DDQ

DQC7 V

SS

G V

SS

DQB7 V

DDQ

G

DQC2 DQC6 BC ADV BB DQB6 DQB2

H

DQC1 DQC5 V

SS

GW V

SS

DQB5 DQB1

J

V

DDQ

V

DD

NC V

DD

NC V

DD

V

DDQ

K

DQD1 DQD5 V

SS

CK V

SS

DQA5 DQA1

L

DQD2 DQD6 BD SCD BA DQA6 DQA2

M

V

DDQ

DQD7 V

SS

BW V

SS

DQA7 V

DDQ

N

DQD3 DQD8 V

SS

A1 V

SS

DQA8 DQA3

P

DQD4 DQPD9 V

SS

A0 V

SS

DQPA9 DQA4

R

NC A2 LBO V

DD

FT A13 NC

T

NC NC A10 A11 A12 NC ZZ

U

V

DDQ

NC NC NC NC NC V

DDQ

Rev: 1.05 10/2001 3/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

GS88418 Pad Out

119-Bump BGA—Top View

1 2 3 4 5 6 7

A

V

DDQ

A6 A7 ADSP A8 A9 V

DDQ

B

NC NC A4 ADSC A15 A17 NC

C

NC A5 A3 V

DD

A14 A16 NC

D

DQB1 NC V

SS

ZQ V

SS

DQA9 NC

E

NC DQB2 V

SS

E1 V

SS

NC DQA8

F

V

DDQ

NC V

SS

G V

SS

DQA7 V

DDQ

G

NC DQB3 BB ADV NC NC DQA6

H

DQB4 NC V

SS

GW V

SS

DQA5 NC

J

V

DDQ

V

DD

NC V

DD

NC V

DD

V

DDQ

K

NC DQB5 V

SS

CK V

SS

NC DQA4

L

DQB6 NC NC SCD BA DQA3 NC

M

V

DDQ

DQB7 V

SS

BW V

SS

NC V

DDQ

N

DQB8 NC V

SS

A1 V

SS

DQA2 NC

P

NC DQB9 V

SS

A0 V

SS

NC DQA1

R

NC A2 LBO V

DD

FT A13 NC

T

NC A10 A11 NC A12 A18 ZZ

U

V

DDQ

NC NC NC NC NC V

DDQ

Rev: 1.05 10/2001 4/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

BPR2000.002.14

GS88418/36 BGA Pin Description

Pin Location Symbol Type Description

P4, N4 A0, A1 I Address field LSBs and Address Counter Preset Inputs

A2, A3, A5, A6, B3, B5, C2, C3, C5,

C6, G4, R2, R6, T3, T5

An I Address Inputs

T4 An I Address Inputs (x36 Version)
T2, T6 NC — No Connect (x36 Version)
T2, T6 An I Address Inputs (x18 Version)

K7, L7, N7, P7, K6, L6, M6, N6, P6
H7, G7, E7, D7, H6, G6, F6, E6, D6
H1, G1, E1, D1, H2, G2, F2, E2, D2

K1, L1, N1, P1, K2, L2, M2, N2, P2

DQA1–DQPA9
DQB1–DQPB9
DQC1–DQPC9
DQD1–DQPD9

I/O Data Input and Output pins (x36 Version)

L5, G5, G3, L3 BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low ( x36 Version)

P7, N6, L6, K7, H6, G7, F6, E7, D6

D1, E2, G2, H1, K2, L1, M2, N1, P2

DQA1–DQA9
DQB1–DQB9

I/O Data Input and Output pins (x18 Version)

L5, G3 BA, BB I Byte Write Enable for DQA, DQB Data I/Os; active low ( x18 Version)

P6, N7, M6, L7, K6, H7, G6, E6, D7,

D2, E1, F2, G1, H2, K1, L2, N2, P1,

G5, L3, T4

NC — No Connect (x18 Version)

K4 CK I Clock Input Signal; active high

E4 E1 I Chip Enable; active low

B2 E2 I Chip Enable; active high

F4 G I Output Enable; active low

T7 ZZ I Sleep Mode control; active high

R5 FT I Flow Through or Pipeline mode; active low

R3 LBO I Linear Burst Order mode; active low

L4 SCD I Single Cycle Deselect/Dual Cycle Deselect Mode Control

D4 ZQ I

FLXDrive Output Impedance Control

(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

B1, C1, R1, T1, L4, B7, C7, U6, R7,

J3,J5, U2, U3, U4, U5

NC — No Connect

J2, C4, J4, R4, J6

V

DD

I Core power supply

D3, E3, F3, H3, K3, M3, N3, P3, D5,

E5, F5, H5, K5, M5, N5, P5

V

SS

I I/O and Core Ground

A1, F1, J1, M1, U1, A7, F7, J7, M7,

U7

V

DDQ

I Output driver power supply

Rev: 1.05 10/2001 5/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

GS88418/36 Block Diagram

A1

A0

A0

A1

D0
D1

Q1

Q0

Counter

Load

D Q

D Q

Register

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

DQ

Register

DQ

Register

A0–An

LBO
ADV

CK
ADSC

ADSP
GW

BW
BA

BB

BC

BD

E1

G

ZZ

Power Down

Control

Memory

Array

18

18

4

A

Q D

DQx0–DQx9

Note: Only x18 version shown for simplicity.

DCD=0

SCD=1

FT

Rev: 1.05 10/2001 6/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

Note:
There are pull-up devices on the LBO, ZQ, SCD, and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and
the chip will operate in the default states as specified in the above table.

Enable / Disable Parity I/O Pins

This SRAM allows the user to configure the device to operate in Parity I/O active (x18 or x36) or in Parity I/O inactive (x16 or
x32) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Tying PE high
deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits
generated and read into the ByteSafe parity circuits.

Burst Counter Sequences

BPR 1999.05.18

Mode Pin Functions

Mode Name Pin Name State Function

Burst Order Control LBO

L Linear Burst

H or NC Interleaved Burst

Output Register Control FT

L Flow Through

H or NC Pipeline

Power Down Control ZZ

L or NC Active

H

Standby, IDD = I

SB

Single/Dual Cycle Deselect Control SCD

L Dual Cycle Deselect

H or NC Single Cycle Deselect

FLXDrive Output Impedance Control ZQ

L High Drive (Low Impedance)

H Low Drive (High Impedance)

Linear Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

I

nterleaved Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01
4th address 11 00 01 10

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01

4th address 11 10 01 00

Rev: 1.05 10/2001 7/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

Byte Write Truth Table

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “C” and “D” are only available on the x36 version.

Function GW BW BA BB BC BD Notes

Read H H X X X X 1

Read H L H H H H 1
Write byte a H L L H H H 2, 3
Write byte b H L H L H H 2, 3
Write byte c H L H H L H 2, 3, 4
Write byte d H L H H H L 2, 3, 4

Write all bytes H L L L L L 2, 3, 4
Write all bytes L X X X X X

Rev: 1.05 10/2001 8/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

Synchronous Truth Table

Operation

Address

Used

State

Diagram

Key

5

E1

E2

2

(x36only)

ADSP ADSC ADV

W

3

DQ

4

Deselect Cycle, Power Down None X H X X L X X High-Z

Deselect Cycle, Power Down None X L F L X X X High-Z

Deselect Cycle, Power Down None X L F H L X X High-Z

Read Cycle, Begin Burst External R L T L X X X Q

Read Cycle, Begin Burst External R L T H L X F Q
Write Cycle, Begin Burst External W L T H L X T D

Read Cycle, Continue Burst Next CR X X H H L F Q

Read Cycle, Continue Burst Next CR H X X H L F Q

Write Cycle, Continue Burst Next CW X X H H L T D

Write Cycle, Continue Burst Next CW H X X H L T D
Read Cycle, Suspend Burst Current X X H H H F Q
Read Cycle, Suspend Burst Current H X X H H F Q
Write Cycle, Suspend Burst Current X X H H H T D
Write Cycle, Suspend Burst Current H X X H H T D

Notes:

1. X = Don’t Care, H = High, L = Low.

2. For x36 Version, E = T (True) if E2 = 1; E = F (False) if E2 = 0.

3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.

4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).

5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.

6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

Rev: 1.05 10/2001 9/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

First Write

First Read

Burst Write

Burst Read

Deselect

R

W

CRCW

X

X

W R

R

W R

XX

X

Simple Synchronous OperationSimple Burst Synchronous Operation

CR

R

CW CR

CR

Simplified State Diagram

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

2. The upper portion of the diagram assumes active use of only the Enable (E1 and E2) and Write (BA, BB, BC, BD, BW, and GW) control
inputs, and that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.

Rev: 1.05 10/2001 10/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

First Write

First Read

Burst Write

Burst Read

Deselect

R

W

CRCW

X

X

W R

R

W

R

X

X

X

CR

R

CW CR

CR

W

CW

W

CW

Simplified State Diagram with G

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.

Rev: 1.05 10/2001 11/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended
period of time, may affect reliability of this component.

Notes:

1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V ≤ V

DDQ

≤ 2.375 V

(i.e., 2.5 V I/O) and 3.6 V ≤ V

DDQ

≤ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case.

2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.

3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.

4. Input Under/overshoot voltage must be –2 V > Vi < V

DD

+2 V with a pulse width not to exceed 20% tKC.

Absolute Maximum Ratings

(All voltages reference to VSS)

Symbol Description Value Unit

V

DD

Voltage on VDD Pins

–0.5 to 4.6 V

V

DDQ

Voltage in V

DDQ

Pins –0.5 to V

DD

V

V

CK

Voltage on Clock Input Pin –0.5 to 6 V

V

I/O

Voltage on I/O Pins

–0.5 to V

DDQ

+0.5 (≤ 4.6 V max.)

V

V

IN

Voltage on Other Input Pins

–0.5 to V

DD

+0.5 (≤ 4.6 V max.)

V

I

IN

Input Current on Any Pin +/–20 mA

I

OUT

Output Current on Any I/O Pin +/–20 mA

P

D

Package Power Dissipation 1.5 W

T

STG

Storage Temperature –55 to 125

o

C

T

BIAS

Temperature Under Bias –55 to 125

o

C

Recommended Operating Conditions

Parameter Symbol Min. Typ. Max. Unit Notes

Supply Voltage

V

DD

3.135 3.3 3.6 V

I/O Supply Voltage

V

DDQ

2.375 2.5

V

DD

V 1

Input High Voltage

V

IH

1.7 —

V

DD

+0.3

V 2

Input Low Voltage

V

IL

–0.3 — 0.8 V 2

Ambient Temperature (Commercial Range Versions)

T

A

0 25 70 °C 3

Ambient Temperature (Industrial Range Versions)

T

A

–40 25 85 °C 3

Rev: 1.05 10/2001 12/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

Note: These parameters are sample tested.

Notes:

1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient.
Temperature air flow, board density, and PCB thermal resistance.

2. SCMI G-38-87

3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1

Capacitance

(TA = 25oC, f = 1 MHZ, V

DD

= 3.3 V)

Parameter Symbol Test conditions Typ. Max. Unit

Input Capacitance

C

IN

V

IN

= 0 V

4 5 pF

Input/Output Capacitance

C

I/O

V

OUT

= 0 V

6 7 pF

Package Thermal Characteristics

Rating Layer Board Symbol Max Unit Notes

Junction to Ambient (at 200 lfm) single

R

ΘJA

40 °C/W 1,2

Junction to Ambient (at 200 lfm) four

R

ΘJA

24 °C/W 1,2

Junction to Case (TOP) —

R

ΘJC

9 °C/W 3

20% tKC

VSS – 2.0 V

50%

V

SS

V

IH

Undershoot Measurement and Timing Overshoot Measurement and Timing

20% tKC

VDD + 2.0 V

50%

V

DD

V

IL

Rev: 1.05 10/2001 13/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.

3. Output Load 2 for tLZ, tHZ, t

OLZ

and t

OHZ

4. Device is deselected as defined by the Truth Table.

AC Test Conditions

Parameter Conditions

Input high level 2.3 V

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level 1.25 V

Output reference level 1.25 V

Output load Fig. 1& 2

DC Electrical Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage Current

(except mode pins)

I

IL

V

IN

= 0 to V

DD

–1 uA 1 uA

ZZ Input Current

I

INZZ

V

DD ≥ VIN ≥ VIH

0 V ≤ V

IN

≤ V

IH

–1 uA
–1 uA

1 uA

300 uA

Mode Pin Input Current

I

INM

V

DD ≥ VIN ≥ VIL

0 V ≤ V

IN

≤ V

IL

–300 uA

–1 uA

1 uA
1 uA

Output Leakage Current

I

OL

Output Disable,

V

OUT

= 0 to V

DD

–1 uA 1 uA

Output High Voltage

V

OH

I

OH

= –4 mA, V

DDQ

= 2.375 V

1.7 V —

Output High Voltage

V

OH

I

OH

= –4 mA, V

DDQ

= 3.135 V

2.4 V —

Output Low Voltage

V

OL

I

OL

= 4 mA

— 0.4 V

DQ

VT = 1.25 V

50Ω

30pF

*

DQ

2.5 V

Output Load 1

Output Load 2

225Ω

225Ω

5pF

*

* Distributed Test Jig Capacitance

Rev: 1.05 10/2001 14/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

Operating Currents

Parameter Test Conditions Symbol

-200 -180 -166 -150 -133
Unit

0

to

70°C

-40
to

85°C

0

to

70°C

-40
to

85°C

0

to

70°C

-40
to

85°C

0

to

70°C

-40
to

85°C

0

to

70°C

-40
to

85°C

Operating

Current

Device Selected;

All other inputs

≥VIH or ≤ V

IL

Output open

I

DD

Pipeline

450 470 410 430 380 400 350 370 340 360 mA

I

DD

Flow Through

270 290 270 290 250 270 240 250 220 240 mA

Standby

Current

ZZ ≥ V

DD

– 0.2 V

I

SB

Pipeline

40 60 40 60 40 60 40 60 40 60 mA

I

SB

Flow Through

40 60 40 60 40 60 40 60 40 60 mA

Deselect

Current

Device Deselected;

All other inputs

≥ VIH or ≤ V

IL

I

DD

Pipeline

120 140 110 130 100 120 100 120 90 110 mA

I

DD

Flow Through

90 110 80 100 80 100 70 90 70 90 mA

Rev: 1.05 10/2001 15/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

AC Electrical Characteristics

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.

Parameter Symbol

-200 -180 -166 -150 -133
Unit

Min Max Min Max Min Max Min Max Min Max

Pipeline

Clock Cycle Time tKC 5.0 — 5.5 — 6.0 — 6.7 — 7.5 — ns

Clock to Output Valid tKQ — 3.0 — 3.2 — 3.5 — 3.8 — 4.0 ns

Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

Clock to Output in Low-Z

tLZ

1

1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

Flow

Through

Clock Cycle Time tKC 10.0 — 10.0 — 10.0 — 10.0 — 10.0 — ns

Clock to Output Valid tKQ — 7.5 — 8.0 — 8.5 — 9.0 — 9.5 ns

Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns

Clock to Output in Low-Z

tLZ

1

3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns

Clock HIGH Time tKH 1.3 — 1.3 — 1.3 — 1.3 — 1.3 — ns

Clock LOW Time tKL 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

Clock to Output in High-Z

tHZ

1

1.5 3.0 1.5 3.2 1.5 3.5 1.5 3.8 1.5 4.0 ns

G to Output Valid tOE — 3.2 — 3.2 — 3.5 — 3.8 — 4.0 ns

G to output in Low-Z

tOLZ

1

0 — 0 — 0 — 0 — 0 — ns

G to output in High-Z

tOHZ

1

— 3.0 — 3.2 — 3.5 — 3.8 — 4.0 ns

Setup time tS 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns

ZZ setup time

tZZS

2

5 — 5 — 5 — 5 — 5 — ns

ZZ hold time

tZZH

2

1 — 1 — 1 — 1 — 1 — ns

ZZ recovery tZZR 20 — 20 — 20 — 20 — 20 — ns

Rev: 1.05 10/2001 16/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

CK

ADSP

ADSC

ADV

GW

BW

WR2 WR3

WR1

WR1

WR2 WR3

tKC

Single Write

Burst Write

tKL

tKH

tS

tH

tS

tH

tS

tH

tS

tH

tS tH

tS

tH

tS

tH

Write specified byte for 2A and all bytes for 2B, 2C& 2D

ADV must be inactive for ADSP Write

ADSC initiated write

ADSP is blocked by E inactive

A0–An

BA–BD

DQA–DQD

Write

Deselected

WR1 WR2 WR3

Write Cycle Timing

E1

tS

tH

E2 only sampled with ADSP or ADSC

E1 masks ADSP

Deselected with E2

G

tS

tH

D2A D2B

D2C D2D D3A

D1A

Hi-Z

tS

tH

E2*

* Only in 88436B

Rev: 1.05 10/2001 17/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

Q1A

Q3A

Q2D

Q2cQ2B

Q2A

tKQ

tLZ

tOE

tOHZ

tOLZ

tKQX

tHZ

tKQX

CK

ADSP

ADSC

BW

G

GW

ADV

Burst Read

RD2 RD3

tKL

tS

tH

tH

tS

tH

tS

tH

ADSC initiated read

Suspend Burst

Single Read

ADSP is blocked by E inactive

A0–An

BA–BD

tKH

tKC

tS

tH

tS

tS

tH

DQA–DQD

RD1

Hi-Z

Suspend Burst

Flow Through Read Cycle Timing

tH

tH

E1 masks ADSP

Deselected with E2

E1

tS

tS

E2*

E2 only sampled with ADSP or ADSC

Rev: 1.05 10/2001 18/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

Flow Through Read-Write Cycle Timing

CK

ADSP

ADV

GW

BW

G

Q1A D1A

Q2A

Q2B Q2c

Q2D

Single Read

Burst Read

tOE

tOHZ

tS

tH

tS

tH

tH

tS

tH

tS tH

tKH

DQA–DQD

BA–BD

tKL

tKC

tS

Single Write

ADSP is blocked by E inactive

tKQ

tS

tH

Hi-Z

Q2A

Burst wrap around to it’s initial state

WR1

RD1

WR1

RD2

tS

tH

A0–An

ADSC

tS tH

ADSC initiated read

E1

tS

E1 masks ADSP

tH

tS

tH

E2 only sampled with ADSP and ADSC

E2*

* Only in 88436B

Rev: 1.05 10/2001 19/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

Pipelined SCD Read Cycle Timing

Q1A

Q3A

Q2D

Q2c

Q2B

Q2A

tKQ

tLZ

tOE

tOHZ

tOLZ

tKQX

tHZ

tKQX

CK

ADSP

ADSC

BW

G

GW

ADV

Burst Read

RD2

RD3

tKL

tS

tH

tH

tS

tH

tS

tH

ADSC initiated read

Suspend Burst

Single Read

ADSP is blocked by E inactive

A0–An

BWA–BWD

tKH

tKC

tS

tH

tS

tS

tH

DQA–DQD

RD1

Hi-Z

tH

tH

E1 masks ADSP

E2 only sampled with ADSP or ADSC

Deselected with E2

E1

tS

tS

E2*

* Only in 88436B

Rev: 1.05 10/2001 20/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

Pipelined DCD Read-Write Cycle Timing

CK

ADSP

ADV

GW

BW

G

WR1

Q1A

D1a Q2A

Q2B Q2c

Q2D

Single Read

Burst Read

tOE tOHZ

tS

tH

tS tH

tH

tS

tH

tS

tH

tKH

DQA–DQD

tKL

tKC

tS

Single Write

ADSP is blocked by E1 inactive

tKQ

tS

tH

Hi-Z

BA–BD

RD1

WR1

RD2

tS

tH

A0–An

ADSC

tS

tH

ADSC initiated read

E1

tS

E1 masks ADSP

tH

tS

tH

E2 only sampled with ADSP and ADSC

E2*

* Only in 88436B

Rev: 1.05 10/2001 21/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

Application Tips

Single and Dual Cycle Deselect

SCD devices force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on
dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address
boundary crossings), but greater care must be exercised to avoid excessive bus contention.

CK

ADSP

ADSC

tH

tKH

tKL

tKC

tS

ZZ

tZZR

tZZH

tZZS

~

~

~

~

~

~

~

~

~

~

~

~

Snooze

Sleep Mode Timing Diagram

Rev: 1.05 10/2001 22/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

FLXDrive Output Driver Characteristics

-140.0

-120.0

-100.0

-80.0

-60.0

-40.0

-20.0

0.0

20.0

40.0

60.0

80.0

100.0

120.0

-0.5 0 0.5 1 1.5 2 2.5 3 3.5 4
V Out (Pull Down)

VDDQ - V Out (Pull Up)

I Out (mA)

3.6V PD HD 3.3V PD HD 3.1V PD HD 3.6V PD LD 3.3V PD LD 3.1V PD LD

3.1V PU LD 3.3V PU LD 3.6V PU LD 3.1V PU HD 3.3V PU HD 3.6V PU HD

Pull Up Drivers

Pull Down Drivers

VDD

VOut

I Out

VSS

Rev: 1.05 10/2001 23/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

Package Dimensions—119-Pin BGA

N

P

A

B

Pin 1
Corner

K

E

F

C T

A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U

G

S

D

1234567

Package Dimensions—119-Pin BGA

Unit: mm

Symbol Description Min. Nom. Max

A Width 13.8 14.0 14.2
B Length 21.8 22.0 22.2
C Package Height (including ball) - 2.40
D Ball Size 0.60 0.75 0.90
E Ball Height 0.50 0.60 0.70
F Package Height (excluding balls) 1.46 1.70

G Width between Balls 1.27

K Package Height above board 0.80 0.90 1.00
N Cut-out Package Width 12.00
P Foot Length 19.50
R Width of package between balls 7.62
S Length of package between balls 20.32
T Variance of Ball Height 0.15

Bottom View

R

Top View

Side View

Rev: 1.05 10/2001 24/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

Ordering Information for GSI Synchronous Burst RAMs

Org

Part Number

1

Type Package

Speed

2

(MHz/ns)

T

A

3

Status

512K x 18 GS88418B-200 S/DCD Pipeline/Flow Through BGA 200/7.5 C
512K x 18 GS88418B-180 S/DCD Pipeline/Flow Through BGA 180/8 C
512K x 18 GS88418B-166 S/DCD Pipeline/Flow Through BGA 166/8.5 C
512K x 18 GS88418B-150 S/DCD Pipeline/Flow Through BGA 150/9 C
512K x 18 GS88418B-133 S/DCD Pipeline/Flow Through BGA 133/9.5 C
256K x 36 GS88436B-200 S/DCD Pipeline/Flow Through BGA 200/7.5 C
256K x 36 GS88436B-180 S/DCD Pipeline/Flow Through BGA 180/8 C
256K x 36 GS88436B-166 S/DCD Pipeline/Flow Through BGA 166/8.5 C
256K x 36 GS88436B-150 S/DCD Pipeline/Flow Through BGA 150/9 C
256K x 36 GS88436B-133 S/DCD Pipeline/Flow Through BGA 133/9.5 C
512K x 18 GS88418B-200I S/DCD Pipeline/Flow Through BGA 200/7.5 I Not Available
512K x 18 GS88418B-180I S/DCD Pipeline/Flow Through BGA 180/8 I
512K x 18 GS88418B-166I S/DCD Pipeline/Flow Through BGA 166/8.5 I
512K x 18 GS88418B-150I S/DCD Pipeline/Flow Through BGA 150/9 I
512K x 18 GS88418B-133I S/DCD Pipeline/Flow Through BGA 133/9.5 I
512K x 36 GS88418B-200I S/DCD Pipeline/Flow Through BGA 200/7.5 I Not Available
512K x 36 GS88418B-180I S/DCD Pipeline/Flow Through BGA 180/8 I
256K x 36 GS88436B-166I S/DCD Pipeline/Flow Through BGA 166/8.5 I
256K x 36 GS88436B-150I S/DCD Pipeline/Flow Through BGA 150/9 I
256K x 36 GS88436B-133I S/DCD Pipeline/Flow Through BGA 133/9.5 I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88418BT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.

3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.05 10/2001 25/25 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88418/36B-200/180/166/150/133

Revision History

DS/DateRev. Code: Old;

New

Types of Changes
Format or Content

Page;Revisions;Reason

GS8841836B Rev 1.00 First Release

•

88418_r1; 88418_r1_01 Content

• Updated BGA pinout to meet JEDEC standards

88418_r1_01; 88418_r1_02 Format

• Updated format to comply with Technical Publications
standards

88418_r1_02; 88418_r1_03 Content

• Updated Capitance table—removed Input row and changed
Output row to I/O

88418_r1_03; 88418_r1_04 Content

• Updated speed bin table on page 1 (Added 150 MHz and 133
MHz)

• Updated pinouts on pages 2 & 3 (U2–U5 should all be NC)

• Removed PE, DP, and QE from Pin Description table on page
4; added R7, J3, J5, U2, U3, U4, U5 to NC row

• Added 150 MHz and 133 MHz to Operating Currents table on
page 14

• Added 150 MHz and 133 MHz to Electrical Characteristics
table on page 15

• Deleted BSR table on page 22

88418_r1_04; 88418_r1_05 Content

• Added references to 150 MHz and 133 MHz speed bins to

headers and ordering information table