BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
P381: G72/G3-64, 32 BIT DDR2 MEMORY, VGA +S DTV
P381: G72/G3-64, 64 BIT DDR2 MEMORY, VGA +S DTV
P381: G72/G3-64, 32 BIT DDR2 MEMORY, DVI+SDT V
P381: G72/G3-64, 64 BIT DDR2 MEMORY, DVI+SDT V
P381: G72/G3-64, 64 BIT DDR2 MEMORY, VGA+DVI+S DTV
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR O THERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARR ANTIES INCLU DING, WITHOU T LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ABDFH
5
Title
Size Document NumberRev
Custom
EGC
Date:Sheetof
P381 : G72
GV-NX73TC512DL-RH
Friday, January 06, 2006
GIGABYTE
1.0
114
PEX-Interface
PLACE NEAR FINGERS
3V3
C23
C21
.1UF
10V
10%
X5R
0402
COMMON
C22
.01UF
25V
10%
X7R
0402
COMMON
1UF
1
10V
10%
X5R
0603
COMMON
GND
Net Name
PEX_TSTCLK
IN
PEX_TSTCLK*
IN
2
3
4
5
PEX_TX0*
IN
PEX_TX1
IN
PEX_TX1*
IN
PEX_TX2
IN
PEX_TX2*
IN
PEX_TX3
IN
PEX_TX3*
IN
PEX_TX4
IN
PEX_TX4*
IN
PEX_TX5
IN
PEX_TX5*
IN
PEX_TX6
IN
PEX_TX6*
IN
PEX_TX7
IN
PEX_TX7*
IN
PEX_TX8
IN
PEX_TX8*
IN
PEX_TX9
IN
PEX_TX9*
IN
PEX_TX10
IN
PEX_TX10*
IN
PEX_TX11
IN
PEX_TX11*
IN
PEX_TX12
IN
PEX_TX12*
IN
PEX_TX13
IN
PEX_TX13*
IN
PEX_TX14
IN
PEX_TX14*
IN
PEX_TX15
IN
PEX_TX15*
IN
PEX_TXX0
IN
PEX_TXX0*
IN
PEX_TXX1
IN
PEX_TXX1*
IN
PEX_TXX2
IN
PEX_TXX2*
IN
PEX_TXX3
IN
PEX_TXX3*
IN
PEX_TXX4
IN
PEX_TXX4*
IN
PEX_TXX5
IN
PEX_TXX5*
IN
PEX_TXX6
IN
PEX_TXX6*
IN
PEX_TXX7
IN
PEX_TXX7*
IN
PEX_TXX8
IN
PEX_TXX8*
IN
PEX_TXX9
IN
PEX_TXX9*
IN
PEX_TXX10
IN
PEX_TXX10*
IN
PEX_TXX11
IN
PEX_TXX11*
IN
PEX_TXX12
IN
PEX_TXX12*
IN
PEX_TXX13
IN
PEX_TXX13*
IN
PEX_TXX14
IN
PEX_TXX14*
IN
PEX_TXX15
IN
PEX_TXX15*
IN
PEX_RX0
IN
PEX_RX0*
IN
PEX_RX1
IN
PEX_RX1*
IN
PEX_RX2
IN
PEX_RX2*
IN
PEX_RX3
IN
PEX_RX3*
IN
PEX_RX4
IN
PEX_RX4*
IN
PEX_RX5
IN
PEX_RX5*
IN
PEX_RX6
IN
PEX_RX6*
IN
PEX_RX7
IN
PEX_RX7*
IN
PEX_RX8
IN
PEX_RX8*
IN
PEX_RX9
IN
PEX_RX9*
IN
PEX_RX10
IN
PEX_RX10*
IN
PEX_RX11
IN
PEX_RX11*
IN
PEX_RX12
IN
PEX_RX12*
IN
PEX_RX13
IN
PEX_RX13*
IN
PEX_RX14
IN
PEX_RX14*
IN
PEX_RX15
IN
PEX_RX15*
IN
PEX_REFCLK
IN
PEX_REFCLK*
IN
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR O THERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARR ANTIES INCLU DING, WITHOU T LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR O THERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARR ANTIES INCLU DING, WITHOU T LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
PLACE ALL DISCRETE COMPONENTS AS NEAR AS POSSIBLE TO MEMORY
1
3,3,4,4,5,5
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR O THERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARR ANTIES INCLU DING, WITHOU T LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR O THERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARR ANTIES INCLU DING, WITHOU T LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ABDFH
U5C
BGA84
COMMON
1/2
K7
RAS
L7
CAS
K3
WE
L8
CS
M8
A<0>
M3
A<1>
M7
A<2>
N2
A<3>
N8
A<4>
N3
A<5>
N7
A<6>
P2
A<7>
P8
A<8>
P3
A<9>
M2
A<10>
P7
A<11>
R2
A<12>
R8
NC/A<13>
R3
NC/A<14>
R7
NC/A<15>
L2
BA<0>
L3
BA<1>
L1
NC/BA<2>
K2
CKE
J8
CLK
K8
CLK
K9
ODT
A2
NC
E2
NC
4
FBADQM4
5
FBADQM5
6
FBADQM6
7
FBADQM7
4
FBADQS4
5
FBADQS5
6
FBADQS6
7
FBADQS7
4
FBADQSN4
5
FBADQSN5
6
FBADQSN6
7
FBADQSN7
FBVDDQ
A1
VDD
E1
VDD
J9
VDD
M9
VDD
R1
VDD
A9
VDDQ
C1
VDDQ
C3
VDDQ
C7
VDDQ
C9
VDDQ
E9
VDDQ
G1
VDDQ
G3
VDDQ
G7
VDDQ
G9
VDDQ
J1
VDDL
A3
VSS
E3
VSS
J3
VSS
GND
N1
VSS
P9
VSS
A7
VSSQ
B2
VSSQ
B8
VSSQ
D2
VSSQ
D8
VSSQ
E7
VSSQ
F2
VSSQ
F8
VSSQ
H2
VSSQ
H8
VSSQ
J7
VSSL
VREF_A
J2
Vref
GND
32
FBAD32
33
FBAD33
34
FBAD34
35
FBAD35
36
FBAD36
37
FBAD37
38
FBAD38
39
FBAD39
FBADQM4
FBADQS4
FBADQSN4
40
FBAD40
41
FBAD41
42
FBAD42
43
FBAD43
44
FBAD44
45
FBAD45
46
FBAD46
47
FBAD47
FBADQM5
FBADQS5
FBADQSN5
SUBPARTITION BITS ---->
USED ONLY FOR 1GB DEVICES ---->
3,5,5,5
3,5,5,5
FBVDDQ
R31
1K
1%
0402
COMMON
C51
R32
.047UF
1K
16V
1%
0402
10%
COMMON
X7R
0402
COMMON
GND
U5A
BGA84
COMMON
2/2
D9
DQ<0>
D7
DQ<1>
C8
DQ<2>
B9
DQ<3>
B1
DQ<4>
C2
DQ<5>
D3
DQ<6>
D1
DQ<7>
B3
DQM
B7
DQS
A8
DQS
U502C
BGA84
COMMON
2/2
C8
DQ<0>
D1
DQ<1>
B9
DQ<2>
B1
DQ<3>
D7
DQ<4>
D9
DQ<5>
D3
DQ<6>
C2
DQ<7>
B3
DQM
B7
DQS
A8
DQS
Place the d ifferentia l termination resistor at t he end of the transmission line.
13
4
5
6
IN
IN
FBVDDQ
FBACLK1
3,5,5,5
IN
15
25
9
8
1
3
21
23
19
20
17
16
14
SNN_FBA4_NC_R8
SNN_FBA4_NC_R3
SNN_FBA4_NC_R7
10
18
7
11
SNN_FBA4_NC_A2
SNN_FBA4_NC_E2
R507
120/X
5%
0402
DNP
R504 100
1%
R506
120/X
5%
0402
DNP
GNDGND
HGFEDCBA
NET
FBACLK1
3,5,5,5
IN
FBACLK1*
3,5,5,5
IN
4
3,4,4,5
U502A
BGA84
COMMON
1/2
K7
RAS
L7
CAS
K3
WE
L8
CS
M8
A<0>
M3
A<1>
M7
A<2>
N2
A<3>
N8
A<4>
N3
A<5>
N7
A<6>
P2
A<7>
P8
A<8>
P3
A<9>
M2
A<10>
P7
A<11>
R2
A<12>
R8
NC/A<13>
R3
NC/A<14>
R7
NC/A<15>
L2
BA<0>
L3
BA<1>
L1
NC/BA<2>
K2
CKE
J8
CLK
K8
CLK
K9
ODT
A2
NC
E2
NC
FBVDDQ
A1
VDD
E1
VDD
J9
VDD
M9
VDD
R1
VDD
A9
VDDQ
C1
VDDQ
C3
VDDQ
C7
VDDQ
C9
VDDQ
E9
VDDQ
G1
VDDQ
G3
VDDQ
G7
VDDQ
G9
VDDQ
J1
VDDL
A3
VSS
E3
VSS
J3
VSS
GND
N1
VSS
P9
VSS
A7
VSSQ
B2
VSSQ
B8
VSSQ
D2
VSSQ
D8
VSSQ
E7
VSSQ
F2
VSSQ
F8
VSSQ
H2
VSSQ
H8
VSSQ
J7
VSSL
J2
Vref
C54
.047UF
16V
10%
X7R
0402
COMMON
GND
FBADQS[7..0]
IN
FBADQSN[7..0]
3,4,4,5
IN
FBVDDQ
GND
FBVDDQ
GND
FBADQS4
FBADQSN4
4
FBADQS5
5
FBADQSN5
5
FBADQS6
6
FBADQSN6
6
7
FBADQS7
7
FBADQSN7
C516
.1UF
10V
10%
X5R
0402
COMMON
C511
.1UF
10V
10%
X5R
0402
COMMON
FBACLK11100DIFF
FBADQS4100DIFF1
FBADQS4100DIFF1
FBADQS5100DIFF1
FBADQS5100DIFF1
FBADQS6100DIFF1
FBADQS6100DIFF1
FBADQS7100DIFF1
C43
.1UF
10V
10%
X5R
0402
COMMON
C517
.1UF
10V
10%
X5R
0402
COMMON
NV_IMPEDANCEDIFFPAIR
100DIFF1FBADQS7
C49
1UF
6.3V
10%
X5R
0402
COMMON
1100DIFFFBACLK1
C59
4.7UF
6.3V
10%
X5R
0603
COMMON
NV_CRITICAL_NET
1
2
3
U502B
BGA84
COMMON
48
FBAD48
49
FBAD49
50
FBAD50
51
FBAD51
52
FBAD52
53
FBAD53
54
FBAD54
55
FBAD55
FBADQM6FBADQM[7..0]
FBADQS6
FBADQSN6
56
FBAD56
57
FBAD57
58
FBAD58
59
FBAD59
60
FBAD60
61
FBAD61
62
FBAD62
63
FBAD63
FBADQM7
FBADQS7
FBADQSN7
R502
120/X
5%
0402
DNP
FBACLK1*
COMMON0603
R501
120/X
5%
0402
DNP
2/2
G8
DQ<0>
F9
DQ<1>
G2
DQ<2>
F1
DQ<3>
H7
DQ<4>
H9
DQ<5>
H1
DQ<6>
H3
DQ<7>
F3
DQM
F7
DQS
E8
DQS
U5B
BGA84
COMMON
2/2
F1
DQ<0>
H7
DQ<1>
H9
DQ<2>
H3
DQ<3>
H1
DQ<4>
G2
DQ<5>
G8
DQ<6>
F9
DQ<7>
F3
DQM
F7
DQS
E8
DQS
Place near signal transition area
FBVDDQ
3,5,5,5
IN
FBVDDQ
C39
C45
.01UF
.01UF
25V
25V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
GND
EGC
FBVDDQ
C53
C510
.1UF
10V
10%
X5R
0402
COMMON
GND
FBVDDQ
C42
.1UF
10V
10%
X5R
0402
COMMON
GND
FBVDDQ
FBVDDQ
C38
C36
.01UF
.01UF
25V
25V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
GND
C48
.1UF
1UF
10V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C509
.1UF
10V
10%
X5R
0402
COMMON
Title
Size Document NumberRev
Custom
Date:Sheetof
Memory Bit 32..63
GV-NX73TC512DL-RH
Friday, January 06, 2006
GIGABYTE
C504
4.7UF
6.3V
10%
X5R
0603
COMMON
514
4
5
1.0
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