BASE LEVEL GENERIC SCHEMATIC ONLY, COMMON & NO_STUFF ASSEMBLY NOTES AND BOM NOT FINAL
P381: G72/G3-64, 32 BIT DDR2 MEMORY, VGA+SDTV
P381: G72/G3-64, 64 BIT DDR2 MEMORY, VGA+SDTV
P381: G72/G3-64, 32 BIT DDR2 MEMORY, DVI+SDTV
P381: G72/G3-64, 64 BIT DDR2 MEMORY, DVI+SDTV
P381: G72/G3-64, 64 BIT DDR2 MEMORY, VGA+DVI+SDTV
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
<UNDEFINED>
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ABDFH
5
GIGABYTE
GIGABYTE
Title
Title
Title
Size Document NumberRev
Size Document NumberRev
Size Document NumberRev
Custom
Custom
Custom
Date:Sheet
Date:Sheet
EGC
Date:Sheet
P381 : G72
P381 : G72
P381 : G72
GV-NX73L128T-RH-LE
GV-NX73L128T-RH-LE
GV-NX73L128T-RH-LE
Thursday, August 03, 2006
Thursday, August 03, 2006
Thursday, August 03, 2006
GIGABYTE
1.0
1.0
1.0
of
115
of
115
of
115
PEX-Interface
PLACE NEAR FINGERS
3V3
C21
C21
C22
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C22
.01UF
.01UF
25V
25V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
C23
C23
1UF
1UF
10V
1
10V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
GND
Net Name
PEX_TSTCLK
IN
PEX_TSTCLK*
IN
PEX_TX0
IN
2
3
4
5
PEX_TX0*
IN
PEX_TX1
IN
PEX_TX1*
IN
PEX_TX2
IN
PEX_TX2*
IN
PEX_TX3
IN
PEX_TX3*
IN
PEX_TX4
IN
PEX_TX4*
IN
PEX_TX5
IN
PEX_TX5*
IN
PEX_TX6
IN
PEX_TX6*
IN
PEX_TX7
IN
PEX_TX7*
IN
PEX_TX8
IN
PEX_TX8*
IN
PEX_TX9
IN
PEX_TX9*
IN
PEX_TX10
IN
PEX_TX10*
IN
PEX_TX11
IN
PEX_TX11*
IN
PEX_TX12
IN
PEX_TX12*
IN
PEX_TX13
IN
PEX_TX13*
IN
PEX_TX14
IN
PEX_TX14*
IN
PEX_TX15
IN
PEX_TX15*
IN
PEX_TXX0
IN
PEX_TXX0*
IN
PEX_TXX1
IN
PEX_TXX1*
IN
PEX_TXX2
IN
PEX_TXX2*
IN
PEX_TXX3
IN
PEX_TXX3*
IN
PEX_TXX4
IN
PEX_TXX4*
IN
PEX_TXX5
IN
PEX_TXX5*
IN
PEX_TXX6
IN
PEX_TXX6*
IN
PEX_TXX7
IN
PEX_TXX7*
IN
PEX_TXX8
IN
PEX_TXX8*
IN
PEX_TXX9
IN
IN
PEX_TXX10
IN
PEX_TXX10*
IN
PEX_TXX11
IN
PEX_TXX11*
IN
PEX_TXX12
IN
PEX_TXX12*
IN
PEX_TXX13
IN
PEX_TXX13*
IN
PEX_TXX14
IN
PEX_TXX14*
IN
PEX_TXX15
IN
PEX_TXX15*
IN
PEX_RX0
IN
PEX_RX0*
IN
PEX_RX1
IN
PEX_RX1*
IN
PEX_RX2
IN
PEX_RX2*
IN
PEX_RX3
IN
PEX_RX3*
IN
PEX_RX4
IN
PEX_RX4*
IN
PEX_RX5
IN
PEX_RX5*
IN
PEX_RX6
IN
PEX_RX6*
IN
PEX_RX7
IN
PEX_RX7*
IN
PEX_RX8
IN
PEX_RX8*
IN
PEX_RX9
IN
PEX_RX9*
IN
PEX_RX10
IN
PEX_RX10*
IN
PEX_RX11
IN
PEX_RX11*
IN
PEX_RX12
IN
PEX_RX12*
IN
PEX_RX13
IN
PEX_RX13*
IN
PEX_RX14
IN
PEX_RX14*
IN
PEX_RX15
IN
PEX_RX15*
IN
PEX_REFCLK
IN
PEX_REFCLK*
IN
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
PLACE ALL DISCRETE COMPONENTS AS NEAR AS POSSIBLE TO MEMORY
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
PLACE ALL DISCRETE COMPONENTS AS NEAR AS POSSIBLE TO MEMORY
FBACMD[25..0]
1
IN
FBACMD15FBACMD15
15
FBACMD25FBACMD25
25
FBACMD9FBACMD9
9
FBACMD8FBACMD8
8
FBACMD1FBACMD1
1
FBACMD3FBACMD3
3
FBACMD13FBACMD13
13
FBACMD4FBACMD4
4
FBACMD5FBACMD5
SUBPARTITION BITS ---->
2
USED ONLY FOR 1GB DEVICES ---->
3
5
FBACMD6FBACMD6
6
FBACLK1FBACLK1
IN
FBACLK1*FBACLK1*
IN
FBACMD21FBACMD21
21
FBACMD23FBACMD23
23
FBACMD19FBACMD19
19
FBACMD20FBACMD20
20
FBACMD17FBACMD17
17
FBACMD16FBACMD16
16
FBACMD14FBACMD14
14
SNN_FBA3_NC_R8
SNN_FBA3_NC_R3
SNN_FBA3_NC_R7
FBACMD10FBACMD10
10
FBACMD18FBACMD18
18
FBACMD7FBACMD7
7
FBACMD11FBACMD11
11
FBACMD12FBACMD12
IN
SNN_FBA3_NC_A2
SNN_FBA3_NC_E2
FBAD[63..0]
BI
FBADQM[7..0]
IN
FBADQS[7..0]
IN
4
FBADQSN[7..0]
IN
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
ABDFH
U5C
U5C
BGA84
BGA84
COMMON
COMMON
1/2
1/2
K7
RAS
L7
CAS
K3
WE
L8
CS
M8
A<0>
M3
A<1>
M7
A<2>
N2
A<3>
N8
A<4>
N3
A<5>
N7
A<6>
P2
A<7>
P8
A<8>
P3
A<9>
M2
A<10>
P7
A<11>
R2
A<12>
R8
NC/A<13>
R3
NC/A<14>
R7
NC/A<15>
L2
BA<0>
L3
BA<1>
L1
NC/BA<2>
K2
CKE
J8
CLK
K8
CLK
K9
ODT
A2
NC
E2
NC
FBADQM4
4
FBADQM5
5
FBADQM6
6
FBADQM7
7
FBADQS4
4
FBADQS5
5
FBADQS6
6
FBADQS7
7
FBADQSN4
4
FBADQSN5
5
FBADQSN6
6
FBADQSN7
7
FBVDDQ
A1
VDD
E1
VDD
J9
VDD
M9
VDD
R1
VDD
A9
VDDQ
C1
VDDQ
C3
VDDQ
C7
VDDQ
C9
VDDQ
E9
VDDQ
G1
VDDQ
G3
VDDQ
G7
VDDQ
G9
VDDQ
J1
VDDL
A3
VSS
E3
VSS
J3
VSS
GND
N1
VSS
P9
VSS
A7
VSSQ
B2
VSSQ
B8
VSSQ
D2
VSSQ
D8
VSSQ
E7
VSSQ
F2
VSSQ
F8
VSSQ
H2
VSSQ
H8
VSSQ
J7
VSSL
VREF_A
J2
Vref
GND
FBAD32
32
FBAD33
33
FBAD34
34
FBAD35
35
FBAD36
36
FBAD37
37
FBAD38
38
FBAD39
39
FBADQM4
FBADQS4
FBADQSN4
FBAD40
40
FBAD41
41
FBAD42
42
FBAD43
43
FBAD44
44
FBAD45
45
FBAD46
46
FBAD47
47
FBADQM5
FBADQS5
FBADQSN5
FBVDDQ
C51
C51
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
R31
R31
1K
1K
1%
1%
0402
0402
COMMON
COMMON
GND
SUBPARTITION BITS ---->
R32
R32
1K
1K
1%
1%
0402
0402
COMMON
COMMON
D9
D7
C8
B9
B1
C2
D3
D1
B3
B7
A8
C8
D1
B9
B1
D7
D9
D3
C2
B3
B7
A8
U5A
U5A
BGA84
BGA84
COMMON
COMMON
U502C
U502C
BGA84
BGA84
COMMON
COMMON
USED ONLY FOR 1GB DEVICES ---->
2/2
2/2
DQ<0>
DQ<1>
DQ<2>
DQ<3>
DQ<4>
DQ<5>
DQ<6>
DQ<7>
DQM
DQS
DQS
2/2
2/2
DQ<0>
DQ<1>
DQ<2>
DQ<3>
DQ<4>
DQ<5>
DQ<6>
DQ<7>
DQM
DQS
DQS
Place the differential termination resistor at the end of the transmission line.
13
4
5
6
IN
IN
FBVDDQ
FBACLK1
IN
15
25
9
8
1
3
21
23
19
20
17
16
14
SNN_FBA4_NC_R8
SNN_FBA4_NC_R3
SNN_FBA4_NC_R7
10
18
7
11
SNN_FBA4_NC_A2
SNN_FBA4_NC_E2
R507
R507
120/X
120/X
5%
5%
0402
0402
DNP
DNP
R504 100
R504 100
1%
1%
R506
R506
120/X
120/X
5%
5%
0402
0402
DNP
DNP
GNDGND
HGFEDCBA
DIFFPAIR
NET
FBACLK1
IN
IN
FBADQSN[7..0]
IN
U502A
U502A
BGA84
BGA84
COMMON
COMMON
1/2
1/2
K7
RAS
L7
CAS
K3
WE
L8
CS
M8
A<0>
M3
A<1>
M7
A<2>
N2
A<3>
N8
A<4>
N3
A<5>
N7
A<6>
P2
A<7>
P8
A<8>
P3
A<9>
M2
A<10>
P7
A<11>
R2
A<12>
R8
NC/A<13>
R3
NC/A<14>
R7
NC/A<15>
L2
BA<0>
L3
BA<1>
L1
NC/BA<2>
K2
CKE
J8
CLK
K8
CLK
K9
ODT
A2
NC
E2
NC
FBVDDQ
A1
VDD
E1
VDD
J9
VDD
M9
VDD
R1
VDD
A9
VDDQ
C1
VDDQ
C3
VDDQ
C7
VDDQ
C9
VDDQ
E9
VDDQ
G1
VDDQ
G3
VDDQ
G7
VDDQ
G9
VDDQ
J1
VDDL
A3
VSS
E3
VSS
J3
VSS
GND
N1
VSS
P9
VSS
A7
VSSQ
B2
VSSQ
B8
VSSQ
D2
VSSQ
D8
VSSQ
E7
VSSQ
F2
VSSQ
F8
VSSQ
H2
VSSQ
H8
VSSQ
J7
VSSL
J2
Vref
C54
C54
.047UF
.047UF
16V
16V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
FBVDDQ
GND
FBVDDQ
GND
FBADQSN4
4
FBADQS5
5
FBADQSN5
5
FBADQS6
6
FBADQSN6
6
FBADQS7
7
FBADQSN7
7
C516
C516
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C511
C511
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
FBACLK1*
IN
FBADQS4
4
FBADQS[7..0]
FBACLK11100DIFF
FBADQS4100DIFF1
FBADQS4100DIFF1
FBADQS5100DIFF1
FBADQS5100DIFF1
FBADQS6100DIFF1
FBADQS6100DIFF1
FBADQS7100DIFF1
C43
C43
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
C517
C517
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
NV_IMPEDANCE
100DIFF1FBADQS7
C49
C49
1UF
1UF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
1100DIFFFBACLK1
C59
C59
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
NV_CRITICAL_NET
1
2
3
U502B
U502B
BGA84
BGA84
COMMON
COMMON
2/2
FBAD48
48
FBAD49
49
FBAD50
50
FBAD51
51
FBAD52
52
FBAD53
53
FBAD54
54
FBAD55
55
FBADQM6
FBADQS6
FBADQSN6
FBAD56
56
FBAD57
57
FBAD58
58
FBAD59
59
FBAD60
60
FBAD61
61
FBAD62
62
FBAD63
63
FBADQM7
FBADQS7
FBADQSN7
R502
R502
120/X
120/X
5%
5%
0402
0402
DNP
DNP
FBACLK1*
COMMON0603
COMMON0603
R501
R501
120/X
120/X
5%
5%
0402
0402
DNP
DNP
2/2
G8
DQ<0>
F9
DQ<1>
G2
DQ<2>
F1
DQ<3>
H7
DQ<4>
H9
DQ<5>
H1
DQ<6>
H3
DQ<7>
F3
DQM
F7
DQS
E8
DQS
U5B
U5B
BGA84
BGA84
COMMON
COMMON
2/2
2/2
F1
DQ<0>
H7
DQ<1>
H9
DQ<2>
H3
DQ<3>
H1
DQ<4>
G2
DQ<5>
G8
DQ<6>
F9
DQ<7>
F3
DQM
F7
DQS
E8
DQS
Place near signal transition area
IN
FBVDDQ
C39
C39
.01UF
.01UF
25V
25V
10%
10%
X7R
X7R
0402
0402
COMMON
COMMON
GND
EGC
FBVDDQ
FBVDDQ
C48
C510
C510
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
GND
FBVDDQ
C42
C42
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
GND
FBVDDQ
C38
C38
C36
C36
.01UF
.01UF
.01UF
.01UF
25V
25V
25V
25V
10%
10%
10%
10%
X7R
X7R
X7R
X7R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
GND
GND
C48
C53
C53
1UF
1UF
.1UF
.1UF
6.3V
6.3V
10V
10V
10%
10%
10%
10%
X5R
X5R
X5R
X5R
0402
0402
0402
0402
COMMON
COMMON
COMMON
COMMON
C509
C509
.1UF
.1UF
10V
10V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
GIGABYTE
GIGABYTE
Title
Title
Title
Size Document NumberRev
Size Document NumberRev
Size Document NumberRev
Custom
Custom
Custom
Date:Sheet
Date:Sheet
Date:Sheet
Memory Bit 32..63
Memory Bit 32..63
Memory Bit 32..63
GV-NX73L128T-RH-LE
GV-NX73L128T-RH-LE
GV-NX73L128T-RH-LE
Thursday, August 03, 2006
Thursday, August 03, 2006
Thursday, August 03, 2006
GIGABYTE
C504
C504
4.7UF
4.7UF
6.3V
6.3V
10%
10%
X5R
X5R
0603
0603
COMMON
COMMON
of
515
of
515
of
515
4
5
1.0
1.0
1.0
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