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MiCOM P543i
Technical Manual
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GE MiCOM P40 Agile, MiCOM P543i, MiCOM P545i Technical Manual

GE Energy Connections Grid Solutions
MiCOM P40 Agile
P543i/P545i
Technical Manual Single Breaker Current Differential (with Distance)
Hardware Version: M Software Version: 85 Publication Reference: P54x1i-TM-EN-1
Contents
Chapter 1 Introduction 1
1 Chapter Overview 3 2 Foreword 4
2.1 Target Audience 4
2.2 Typographical Conventions 4
2.3 Nomenclature 5
2.4 Compliance 5
3 Product Scope 6
3.1 Product Versions 6
3.1.1 Ordering Options 7
4 Features and Functions 8
4.1 Current Differential Protection Functions 8
4.2 Distance Protection Functions 8
4.3 Protection Functions 8
4.4 Control Functions 9
4.5 Measurement Functions 10
4.6 Communication Functions 10
5 Logic Diagrams 11 6 Functional Overview 13
Chapter 2 Safety Information 15
1 Chapter Overview 17 2 Health and Safety 18 3 Symbols 19 4 Installation, Commissioning and Servicing 20
4.1 Lifting Hazards 20
4.2 Electrical Hazards 20
4.3 UL/CSA/CUL Requirements 21
4.4 Fusing Requirements 21
4.5 Equipment Connections 22
4.6 Protection Class 1 Equipment Requirements 22
4.7 Pre-energisation Checklist 23
4.8 Peripheral Circuitry 23
4.9 Upgrading/Servicing 24
5 Decommissioning and Disposal 25 6 Regulatory Compliance 26
6.1 EMC Compliance: 2014/30/EU 26
6.2 LVD Compliance: 2014/35/EU 26
6.3 R&TTE Compliance: 2014/53/EU 26
6.4 UL/CUL Compliance 26
6.5 ATEX Compliance: 2014/34/EU 26
Chapter 3 Hardware Design 29
1 Chapter Overview 31 2 Hardware Architecture 32
2.1 Coprocessor Hardware Architecture 32
3 Mechanical Implementation 34
3.1 Housing Variants 34
3.2 List of Boards 35
4 Front Panel 37
4.1 Front Panel 37
Contents P543i/P545i
4.1.1 Front Panel Compartments 37
4.1.2 Keypad 38
4.1.3 Front Serial Port (SK1) 38
4.1.4 Front Parallel Port (SK2) 39
4.1.5 Fixed Function LEDs 39
4.1.6 Function Keys 39
4.1.7 Programable LEDs 40
5 Rear Panel 41 6 Boards and Modules 43
6.1 PCBs 43
6.2 Subassemblies 43
6.3 Main Processor Board 44
6.4 Power Supply Board 45
6.4.1 Watchdog 47
6.4.2 Rear Serial Port 48
6.5 Input Module - 1 Transformer Board 49
6.5.1 Input Module Circuit Description 50
6.5.2 Transformer Board 51
6.5.3 Input Board 52
6.6 Standard Output Relay Board 53
6.7 IRIG-B Board 54
6.8 Fibre Optic Board 55
6.9 Rear Communication Board 56
6.10 Ethernet Board 56
6.11 Redundant Ethernet Board 58
6.12 Coprocessor Board 60
6.12.1 Current Differential Inputs 60
6.12.2 Coprocessor board with 1PPS input 60
Chapter 4 Software Design 63
1 Chapter Overview 65 2 Sofware Design Overview 66 3 System Level Software 67
3.1 Real Time Operating System 67
3.2 System Services Software 67
3.3 Self-Diagnostic Software 67
3.4 Startup Self-Testing 67
3.4.1 System Boot 67
3.4.2 System Level Software Initialisation 68
3.4.3 Platform Software Initialisation and Monitoring 68
3.5 Continuous Self-Testing 68
4 Platform Software 70
4.1 Record Logging 70
4.2 Settings Database 70
4.3 Interfaces 70
5 Protection and Control Functions 71
5.1 Acquisition of Samples 71
5.2 Frequency Tracking 71
5.3 Direct Use of Sample Values 71
5.4 System Level Software Initialisation 71
5.5 Distance Protection 72
5.6 Fourier Signal Processing 72
5.7 Programmable Scheme Logic 73
5.8 Event Recording 74
5.9 Disturbance Recorder 74
5.10 Fault Locator 74
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5.11 Function Key Interface 74
Chapter 5 Configuration 75
1 Chapter Overview 77 2 Settings Application Software 78 3 Using the HMI Panel 79
3.1 Navigating the HMI Panel 80
3.2 Getting Started 80
3.3 Default Display 81
3.4 Default Display Navigation 82
3.5 Password Entry 83
3.6 Processing Alarms and Records 83
3.7 Menu Structure 84
3.8 Changing the Settings 85
3.9 Direct Access (The Hotkey menu) 86
3.9.1 Setting Group Selection Using Hotkeys 86
3.9.2 Control Inputs 86
3.9.3 Circuit Breaker Control 87
3.10 Function Keys 87
4 Line Parameters 89
4.1 Tripping Mode 89
4.1.1 CB Trip Conversion Logic Diagram 89
4.2 Residual Compensation 90
4.3 Mutual Compensation 90
5 Date and Time Configuration 92
5.1 Using an SNTP Signal 92
5.2 Using an IRIG-B Signal 92
5.3 Using an IEEE 1588 PTP Signal 92
5.4 Without a Timing Source Signal 93
5.5 Time Zone Compensation 93
5.6 Daylight Saving Time Compensation 94
6 Settings Group Selection 95
Chapter 6 Current Differential Protection 97
1 Chapter Overview 99 2 Current Differential Protection Principle 100
2.1 Numerical Current Differential Protection 100
3 Synchronisation of Current Signals 102
3.1 Time Alignment using Ping-Pong Technique 102
3.2 GPS Synchronisation 103
4 Phase Current Differential Protection 105
4.1 Phase Current Differential Tripping Criteria 106
4.2 Phase Current Differential Protection Logic 107
5 Neutral Current Differential Protection 108 6 Three-Terminal Schemes 109
6.1 Three-Terminal Scheme Reconfiguration on Energisation 110
7 Transient Bias 111 8 Capacitive Charging Current Compensation 112 9 CT Compensation 113 10 Feeders with In-Zone Transformers 114
10.1 CT Phase Correction 114
10.2 Zero Sequence Filtering 115
10.3 Magnetising Inrush Restraint 116
10.3.1 Second Harmonic Restraint 117
10.4 Overfluxing Restraint 119
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10.4.1 Fifth Harmonic Blocking 119
10.5 Logic for Feeders with In-Zone Transformers 120
10.6 Second Harmonic Blocking Logic 121
10.7 Fifth Harmonic Blocking Logic 122
11 Current Differential Intertripping 123 12 Stub Bus Differential Protection 124 13 Application Notes 125
13.1 Setting Up the Phase Differential Characteristic 125
13.2 Sensitivity Under Heavy Loads 126
13.3 Permissive Intertripping 127
13.4 CT Ratio Correction Setting Guidelines 127
13.5 Feeders with Small Tapped Loads 128
13.6 Setting a Two-Terminal Phase Current Differential Element 128
13.7 Setting a Three-Terminal Phase Current Differential Element 129
Chapter 7 Distance Protection 133
1 Chapter Overview 135 2 Introduction 136
2.1 Distance Protection Principle 136
2.2 Performance Influencing Factors 136
2.3 Impedance Calculation 137
2.4 Implementation with Comparators 137
2.5 Polarization of Distance Characteristics 137
3 Distance Measuring Zones Operating Principles 138
3.1 Mho Characteristics 139
3.1.1 Directional Mho Characteristic for Phase Faults 139
3.1.2 Offset Mho Characteristic for Phase Faults 139
3.1.3 Directional Self-Polarized Mho Characteristic for Earth Faults 140
3.1.4 Offset Mho Characteristic for Earth Faults 142
3.1.5 Memory Polarization of Mho Characteristics 144
3.1.6 Dynamic Mho Expansion and Contraction 144
3.1.7 Cross Polarization of Mho Characteristics 147
3.1.8 Implementation of Mho Polarization 148
3.2 Quadrilateral Characteristic 149
3.2.1 Directional Quadrilaterals 150
3.2.2 Earth Fault Quadrilateral Characteristics 154
3.3 Quadrilateral Characteristic for Phase Faults 162
3.3.1 Phase Fault Impedance Reach Line 163
3.3.2 Phase Fault Reverse Impedance Reach Line 163
3.3.3 Phase Fault Resistive Reach Line 164
3.3.4 Phase Fault Reverse Resistive Reach Line 166
3.3.5 Phase Fault Quadrilateral Characteristic Summary 166
4 Phase and Earth Fault Distance Protection Implementation 168
4.1 Phase Fault Characteristics 168
4.2 Earth Fault Characteristics 168
4.3 Distance Protection Tripping Decision 168
4.4 Distance Protection Phase Selection 169
4.4.1 Faulted Phase Selection 169
4.5 Biased Neutral Current Detector 170
4.6 Distance Element Zone Settings 171
4.6.1 Directionalizing the Distance Elements 171
4.6.2 Advanced Distance Zone Settings 172
4.6.3 Distance Zone Sensitivities 172
4.7 Capacitor VT Applications 173
4.7.1 CVTs with Passive Suppression of Ferroresonance 173
4.7.2 CVTs with Active Suppression of Ferroresonance 173
4.8 Load Blinding 174
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4.9 Cross Country Fault Protection 175
5 Delta Directional Element 176
5.1 Delta Directional Principle and Setup 176
5.2 Delta Directional Decision 177
6 Distance Isolated and Compensated Systems 179
6.1 Peterson Coil Earthed Systems 179
6.2 Earth Fault Distance Protection for Isolated and Compensated Systems 182
6.2.1 Single-phase to Earth Faults on Isolated or Compensated Systems 183
6.2.2 Cross-Country Faults on Isolated or Compensated Systems 183
6.3 Implementation of Distance Protection for Isolated and Compensated Networks 184
6.3.1 Network Earthing System Setting 184
6.3.2 First Earth FaultDetection 184
6.3.3 Fault Detection Logic 186
6.3.4 Phase Preferential Logic 187
7 Application Notes 193
7.1 Setting Mode Choice 193
7.2 Operating Characteristic Selection 193
7.2.1 Phase Characteristic 193
7.2.2 Earth Fault Characteristic 194
7.3 Zone Reach Setting Guidelines 194
7.3.1 Quadrilateral Resistive Reaches 195
7.4 Earth Fault Resistive Reaches and Tilting 195
7.4.1 Dynamic Tilting 196
7.4.2 Fixed Tilting 197
7.5 Phase Fault Zone Settings 197
7.6 Directional Element for Distance Protection 198
7.7 Filtering Setup 198
7.7.1 Distance Digital Filter 198
7.7.2 Setting up CVTs 198
7.8 Load Blinding Setup 199
7.9 Polarizing Setup 199
7.10 Delta Directional Element Setting Guidelines 200
7.10.1 Delta Thresholds 200
7.11 Distance Protection Worked Example 201
7.11.1 Line Impedance Calculation 202
7.11.2 Residual Compensation for Earth Fault Elements 202
7.11.3 Zone 1 Phase and Ground Reach Settings 202
7.11.4 Zone 2 Phase and Ground Reach Settings 203
7.11.5 Zone 3 Phase and Ground Reach Settings 203
7.11.6 Zone 3 Reverse Reach Settings 203
7.11.7 Zone 4 Reverse Reach Settings 203
7.11.8 Load Avoidance 204
7.11.9 Quadrilateral Resistive Reach Settings 204
7.12 Teed Feeder Applications 206
Chapter 8 Carrier Aided Schemes 207
1 Chapter Overview 209 2 Introduction 210 3 Carrier Aided Schemes Implementation 211
3.1 Carrier Aided Scheme Types 211
3.2 Default Carrier Aided Schemes 212
4 Aided Distance Scheme Logic 213
4.1 Permissive Underreach Scheme 213
4.2 Permissive Over-reach Scheme 214
4.2.1 Permissive Overreach Trip Reinforcement 216
4.2.2 Permissive Overreach Weak Infeed Features 217
4.3 Permissive Scheme Loss Of Guard 217
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4.4 Current Reversal Guard Logic 218
4.5 Aided Distance Blocking Schemes 219
4.6 Aided Distance Unblocking Schemes 220
4.7 Aided Distance Logic Diagrams 222
4.7.1 Aided Distance Send Logic 222
4.7.2 Carrier Aided Schemes Receive Logic 223
4.7.3 Aided Distance Tripping Logic 223
4.7.4 PUR Aided Tripping logic 224
4.7.5 POR Aided Tripping logic 225
4.7.6 Aided Scheme Blocking 1 Tripping logic 226
4.7.7 Aided Scheme Blocking 2 Tripping logic 226
5 Aided DEF Scheme Logic 227
5.1 Aided DEF Introduction 227
5.2 Implementation 227
5.3 Aided DEF Polarization 227
5.3.1 Zero Sequence Polarizing 228
5.3.2 Negative Sequence Polarizing 229
5.4 Aided DEF Setting Guidelines 230
5.5 Aided DEF POR Scheme 231
5.6 Aided DEF Blocking Scheme 232
5.7 Aided DEF Logic Diagrams 233
5.7.1 DEF Directional Signals 233
5.7.2 Aided DEF Send Logic 234
5.7.3 Carrier Aided Schemes Receive Logic 234
5.7.4 Aided DEF Tripping Logic 235
5.7.5 POR Aided Tripping logic 236
5.7.6 Aided Scheme Blocking 1 Tripping logic 237
5.7.7 Aided Scheme Blocking 2 Tripping logic 237
6 Aided Delta Scheme Logic 238
6.1 Aided Delta POR Scheme 238
6.2 Aided Delta Blocking Scheme 239
6.3 Aided Delta Logic Diagrams 241
6.3.1 Aided Delta Send Logic 241
6.3.2 Carrier Aided Schemes Receive Logic 241
6.3.3 Aided Delta Tripping Logic 242
6.3.4 POR Aided Tripping logic 243
6.3.5 Aided Scheme Blocking 1 Tripping logic 244
6.3.6 Aided Scheme Blocking 2 Tripping logic 244
7 Application Notes 245
7.1 Aided Distance PUR Scheme 245
7.2 Aided Distance POR Scheme 245
7.3 Aided Distance Blocking Scheme 245
7.4 Aided DEF POR Scheme 246
7.5 Aided DEF Blocking Scheme 246
7.6 Aided Delta POR Scheme 246
7.7 Aided Delta Blocking Scheme 246
7.8 Teed Feeder Applications 247
7.8.1 POR Schemes for Teed Feeders 248
7.8.2 PUR Schemes for Teed Feeders 248
7.8.3 Blocking Schemes for Teed Feeders 249
Chapter 9 Non-Aided Schemes 251
1 Chapter Overview 253 2 Non-Aided Schemes 254 3 Basic Schemes 255
3.1 Basic Scheme Modes 255
3.2 Basic Scheme Setting 258
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4 Trip On Close Schemes 259
4.1 Switch On To Fault (SOTF) 260
4.1.1 Switch Onto Fault Mode 260
4.1.2 SOTF Tripping 261
4.1.3 SOTF Tripping with CNV 261
4.2 Trip On Reclose (TOR) 261
4.2.1 Trip On Reclose Mode 262
4.2.2 TOR Tripping Logic for Appropriate Zones 262
4.2.3 TOR Tripping Logic with CNV 262
4.3 Polarisation during Circuit Engergisation 262
5 Zone1 Extension Scheme 264 6 Loss of Load Scheme 265
Chapter 10 Power Swing Functions 267
1 Chapter Overview 269 2 Introduction to Power Swing Blocking 270 3 Power Swing Blocking 272
3.1 Power Swing Detection 272
3.1.1 Settings-Free Power Swing Detection 272
3.1.2 Slow Power Swing Detection 275
3.2 Detection of a Fault During a Power Swing 276
3.3 Power Swing Blocking Configuration 276
3.4 Power Swing Load Blinding Boundary 277
3.5 Power Swing Blocking Logic 278
3.6 Power Swing Blocking Setting Guidelines 279
3.6.1 Setting the Resistive Limits 280
3.6.2 Setting the Reactive Limits 280
3.6.3 PSB Timer Setting Guidelines 281
4 Out of Step Protection 283
4.1 Out of Step Detection 283
4.2 Out of Step Protection Operataing Principle 284
4.3 Out of Step Logic Diagram 285
4.4 OST Application Notes 285
4.4.1 Setting the OST Mode 285
Chapter 11 Autoreclose 293
1 Chapter Overview 295 2 Introduction to Autoreclose 296 3 Autoreclose Implementation 297
3.1 Autoreclose Logic Inputs from External Sources 298
3.1.1 Circuit Breaker Healthy Input 298
3.1.2 Inhibit Autoreclose Input 298
3.1.3 Block Autoreclose Input 298
3.1.4 Reset Lockout Input 299
3.1.5 Pole Discrepancy Input 299
3.1.6 External Trip Indication 299
3.2 Autoreclose Logic Inputs 299
3.2.1 Trip Initiation Signals 299
3.2.2 Circuit Breaker Status Inputs 299
3.2.3 System Check Signals 299
3.3 Autoreclose Logic Outputs 299
3.4 Autoreclose Operating Sequence 300
3.4.1 AR Timing Sequence - Transient Fault 300
3.4.2 AR Timing Sequence - Evolving/Permanent Fault 300
3.4.3 AR Timing Sequence - Evolving/Permanent Fault Single-phase 301
4 Autoreclose System Map 302
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4.1 Autoreclose System Map Diagrams 304
4.2 Autoreclose Internal Signals 309
4.3 Autoreclose DDB Signals 311
5 Logic Modules 317
5.1 Circuit Breaker Status Monitor 317
5.1.1 CB State Monitor Logic diagram 318
5.2 Circuit Breaker Open Logic 319
5.2.1 Circuit Breaker Open Logic Diagram 319
5.3 Circuit Breaker in Service Logic 319
5.3.1 Circuit Breaker in Service Logic Diagram 319
5.3.2 Autoreclose OK Logic Diagram 320
5.4 Autoreclose Enable 320
5.4.1 Autoreclose Enable Logic Diagram 320
5.5 Autoreclose Modes 320
5.5.1 Single-Phase and Three-Phase Autoreclose 321
5.5.2 Autoreclose Modes Enable Logic Diagram 322
5.6 AR Force Three-Phase Trip Logic 322
5.6.1 AR Force Three-Phase Trip Logic Diagram 322
5.7 Autoreclose Initiation Logic 322
5.7.1 Autoreclose Initiation Logic Diagram 324
5.7.2 Autoreclose Trip Test Logic Diagram 324
5.7.3 AR External Trip Initiation Logic Diagram 325
5.7.4 Protection Reoperation and Evolving Fault Logic Diagram 326
5.7.5 Fault Memory Logic Diagram 326
5.8 Autoreclose In Progress 326
5.8.1 Autoreclose In Progress Logic Diagram 327
5.9 Sequence Counter 327
5.9.1 Autoreclose Sequence Counter Logic Diagram 328
5.10 Autoreclose Cycle Selection 328
5.10.1 Single-Phase Autoreclose Cycle Selection Logic Diagram 328
5.10.2 3-phase Autoreclose Cycle Selection 329
5.11 Dead Time Control 329
5.11.1 Dead Time Start Enable Logic Diagram 330
5.11.2 1-phase Dead Time Logic Diagram 331
5.11.3 3-phase Dead Time Logic Diagram 332
5.12 Circuit Breaker Autoclose 332
5.12.1 Circuit Breaker Autoclose Logic Diagram 333
5.13 Reclaim Time 333
5.13.1 Prepare Reclaim Initiation Logic Diagram 334
5.13.2 Reclaim Time Logic Diagram 334
5.13.3 Succesful Autoreclose Signals Logic Diagram 335
5.13.4 Autoreclose Reset Successful Indication Logic Diagram 335
5.14 CB Healthy and System Check Timers 335
5.14.1 CB Healthy and System Check Timers Logic Diagram 336
5.15 Autoreclose Shot Counters 336
5.15.1 Autoreclose Shot Counters Logic Diagram 337
5.16 Circuit Breaker Control 338
5.16.1 CB Control Logic Diagram 338
5.17 Circuit Breaker Trip Time Monitoring 339
5.17.1 CB Trip Time Monitoring Logic Diagram 339
5.18 Autoreclose Lockout 339
5.18.1 CB Lockout Logic Diagram 340
5.19 Reset Circuit Breaker Lockout 341
5.19.1 Reset CB Lockout Logic Diagram 341
5.20 Pole Discrepancy 342
5.20.1 Pole Discrepancy Logic Diagram 342
5.21 Circuit Breaker Trip Conversion 342
5.21.1 CB Trip Conversion Logic Diagram 343
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5.22 Monitor Checks for CB Closure 343
5.22.1 Check Synchronisation Monitor for CB Closure 344
5.22.2 Voltage Monitor for CB Closure 345
5.23 Synchronisation Checks for CB Closure 345
5.23.1 Three-phase Autoreclose System Check Logic Diagram 347
5.23.2 CB Manual Close System Check Logic Diagram 348
6 Setting Guidelines 349
6.1 De-ionising Time Guidance 349
6.2 Dead Timer Setting Guidelines 349
6.2.1 Example Dead Time Calculation 349
6.3 Reclaim Time Setting Guidelines 350
Chapter 12 CB Fail Protection 351
1 Chapter Overview 353 2 Circuit Breaker Fail Protection 354 3 Circuit Breaker Fail Implementation 355
3.1 Circuit Breaker Fail Timers 355
3.2 Zero Crossing Detection 355
4 Circuit Breaker Fail Logic 357
4.1 Circuit Breaker Fail Logic - Part 1 357
4.2 Circuit Breaker Fail Logic - Part 2 358
4.3 Circuit Breaker Fail Logic - Part 3 359
4.4 Circuit Breaker Fail Logic - Part 4 360
5 Application Notes 361
5.1 Reset Mechanisms for CB Fail Timers 361
5.2 Setting Guidelines (CB fail Timer) 361
5.3 Setting Guidelines (Undercurrent) 362
Chapter 13 Current Protection Functions 363
1 Chapter Overview 365 2 Phase Fault Overcurrent Protection 366
2.1 POC Implementation 366
2.2 Directional Element 366
2.3 POC Logic 368
3 Negative Sequence Overcurrent Protection 369
3.1 Negative Sequence Overcurrent Protection Implementation 369
3.2 Directional Element 369
3.3 NPSOC Logic 370
3.4 Application Notes 370
3.4.1 Setting Guidelines (Current Threshold) 370
3.4.2 Setting Guidelines (Time Delay) 370
3.4.3 Setting Guidelines (Directional element) 371
4 Earth Fault Protection 372
4.1 Earth Fault Protection Implementation 372
4.2 IDG Curve 372
4.3 Directional Element 373
4.3.1 Residual Voltage Polarisation 373
4.3.2 Negative Sequence Polarisation 374
4.4 Earth Fault Protection Logic 375
4.5 Application Notes 375
4.5.1 Residual Voltage Polarisation Setting Guidelines 375
4.5.2 Setting Guidelines (Directional Element) 375
5 Sensitive Earth Fault Protection 377
5.1 SEF Protection Implementation 377
5.2 EPATR B Curve 377
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5.3 Sensitive Earth Fault Protection Logic 378
5.4 Application Notes 379
5.4.1 Insulated Systems 379
5.4.2 Setting Guidelines (Insulated Systems) 380
6 High Impedance REF 382
6.1 High Impedance REF Principle 382
7 Thermal Overload Protection 384
7.1 Single Time Constant Characteristic 384
7.2 Dual Time Constant Characteristic 384
7.3 Thermal Overload Protection Implementation 385
7.4 Thermal Overload Protection Logic 385
7.5 Application Notes 385
7.5.1 Setting Guidelines for Dual Time Constant Characteristic 385
7.5.2 Setting Guidelines for Single Time Constant Characteristic 387
8 Broken Conductor Protection 389
8.1 Broken Conductor Protection Implementation 389
8.2 Broken Conductor Protection Logic 389
8.3 Application Notes 389
8.3.1 Setting Guidelines 389
9 Transient Earth Fault Detection 391
9.1 Transient Earth Fault Detection Implementation 392
9.2 Transient Earth Fault Detection Logic 393
9.2.1 Transient Earth Fault Detection Logic Overview 393
9.2.2 Fault Type Detector Logic 394
9.2.3 Direction Detector Logic - Standard Mode 394
9.2.4 Transient Earth Fault Detection Output Alarm Logic 394
Chapter 14 Voltage Protection Functions 395
1 Chapter Overview 397 2 Undervoltage Protection 398
2.1 Undervoltage Protection Implementation 398
2.2 Undervoltage Protection Logic 399
2.3 Application Notes 400
2.3.1 Undervoltage Setting Guidelines 400
3 Overvoltage Protection 401
3.1 Overvoltage Protection Implementation 401
3.2 Overvoltage Protection Logic 402
3.3 Application Notes 403
3.3.1 Overvoltage Setting Guidelines 403
4 Compensated Overvoltage 404 5 Residual Overvoltage Protection 405
5.1 Residual Overvoltage Protection Implementation 405
5.2 Residual Overvoltage Logic 406
5.3 Application Notes 406
5.3.1 Calculation for Solidly Earthed Systems 406
5.3.2 Calculation for Impedance Earthed Systems 407
5.3.3 Setting Guidelines 408
Chapter 15 Frequency Protection Functions 409
1 Chapter Overview 411 2 Frequency Protection 412
2.1 Underfrequency Protection 412
2.1.1 Underfrequency Protection Implementation 412
2.1.2 Underfrequency Protection logic 413
2.1.3 Application Notes 413
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2.2 Overfrequency Protection 413
2.2.1 Overfrequency Protection Implementation 413
2.2.2 Overfrequency Protection logic 414
2.2.3 Application Notes 414
3 Independent R.O.C.O.F Protection 415
3.1 Indepenent R.O.C.O.F Protection Implementation 415
3.2 Independent R.O.C.O.F Protection Logic 415
Chapter 16 Current Transformer Requirements 417
1 Chapter Overview 419 2 Recommended CT Classes 420 3 Current Differential Requirements 421 4 Distance Protection Requirements 422 5 Determining Vk for IEEE C-class CT 423 6 Worked Examples 424
6.1 Calculation of Primary X/R ratio 424
6.2 Calculation of Source Impedance 424
6.3 Calculation of Full Line Impedance 424
6.4 Calculation of Total Impedance up to Remote Busbar 425
6.5 Calculation of Through Fault X/R ratio 425
6.6 Calculation of Through Fault Current 425
6.7 Calculation of Line Impedance to Zone 1 Reach Point 425
6.8 Calculation of Total Impedance to Zone 1 Reach Point 425
6.9 Calculation of X/R to Zone 1 Reach Point 425
6.10 Calculation of Fault Current to Zone 1 Reach Point 425
6.11 Calculation of Vk for Current Differential Protection 425
6.12 Calculation of Vk for Distance Zone 1 Reach Point 425
6.13 Calculation of Vk for Distance Zone 1 Close-up Fault 426
6.14 Calculation of Vk for Distance Time Delayed Zones 426
6.15 Overcurrent Elements 426
6.16 Overcurrent Elements 426
Chapter 17 Monitoring and Control 427
1 Chapter Overview 429 2 Event Records 430
2.1 Event Types 430
2.1.1 Opto-input Events 431
2.1.2 Contact Events 431
2.1.3 Alarm Events 431
2.1.4 Fault Record Events 432
2.1.5 Maintenance Events 432
2.1.6 Protection Events 432
2.1.7 Security Events 433
2.1.8 Platform Events 433
3 Disturbance Recorder 434 4 Measurements 435
4.1 Measured Quantities 435
4.2 Measurement Setup 435
4.3 Fault Locator 435
4.4 Opto-input Time Stamping 435
5 CB Condition Monitoring 436
5.1 Broken Current Accumulator 437
5.2 CB Trip Counter 437
5.3 CB Operating Time Accumulator 438
5.4 Excessive Fault Frequency Counter 438
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5.5 Reset Lockout Alarm 439
5.6 CB Condition Monitoring Logic 440
5.7 Reset Circuit Breaker Lockout 440
5.7.1 Reset CB Lockout Logic Diagram 441
5.8 Application Notes 441
5.8.1 Setting the Thresholds for the Total Broken Current 441
5.8.2 Setting the thresholds for the Number of Operations 442
5.8.3 Setting the thresholds for the Operating Time 442
5.8.4 Setting the Thresholds for Excesssive Fault Frequency 442
6 CB State Monitoring 443
6.1 CB State Monitor Logic diagram 444
7 Circuit Breaker Control 445
7.1 CB Control using the IED Menu 445
7.2 CB Control using the Hotkeys 446
7.3 CB Control using the Function Keys 446
7.4 CB Control using the Opto-inputs 447
7.5 Remote CB Control 447
7.6 CB Healthy Check 448
7.7 Synchronisation Check 448
7.8 CB Control AR Implications 448
7.9 CB Control Logic Diagram 449
8 Pole Dead Function 450
8.1 Pole Dead Logic 450
9 System Checks 451
9.1 System Checks Implementation 451
9.1.1 VT Connections 451
9.1.2 Voltage Monitoring 452
9.1.3 Check Synchronisation 452
9.1.4 Check Syncronisation Vector Diagram 452
9.2 Voltage Monitor for CB Closure 454
9.3 Check Synchronisation Monitor for CB Closure 455
9.4 System Check PSL 456
9.5 Application Notes 456
9.5.1 Predictive Closure of Circuit Breaker 456
9.5.2 Voltage and Phase Angle Correction 456
Chapter 18 Supervision 459
1 Chapter Overview 461 2 Current Differential Supervision 462
2.1 Current Differential Starter Supervision 462
2.1.1 Current Differential Starter Supervision Logic 464
2.1.2 Current Differential Start Logic 465
2.2 Switched Communication Path Supervision 465
2.3 Communications Asymmetry Supervision 466
2.4 GPS Synchronisation Supervision 467
2.4.1 Propogation Delay Management 468
3 Voltage Transformer Supervision 470
3.1 Loss of One or Two Phase Voltages 470
3.2 Loss of all Three Phase Voltages 470
3.3 Absence of all Three Phase Voltages on Line Energisation 470
3.4 VTS Implementation 471
3.5 VTS Logic 472
4 Current Transformer Supervision 475
4.1 Differential CTS 475
4.2 Differential CTS Logic 476
4.3 CTS Implementation 476
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4.4 Standard CTS Logic 477
4.5 CTS Blocking 477
4.6 Application Notes 477
4.6.1 Setting Guidelines 477
4.6.2 Differential CTS Setting Guidelines 478
5 Trip Circuit Supervision 479
5.1 Trip Circuit Supervision Scheme 1 479
5.1.1 Resistor Values 479
5.1.2 PSL for TCS Scheme 1 480
5.2 Trip Circuit Supervision Scheme 2 480
5.2.1 Resistor Values 481
5.2.2 PSL for TCS Scheme 2 481
5.3 Trip Circuit Supervision Scheme 3 481
5.3.1 Resistor Values 482
5.3.2 PSL for TCS Scheme 3 482
Chapter 19 Digital I/O and PSL Configuration 483
1 Chapter Overview 485 2 Configuring Digital Inputs and Outputs 486 3 Scheme Logic 487
3.1 PSL Editor 488
3.2 PSL Schemes 488
3.3 PSL Scheme Version Control 488
4 Configuring the Opto-Inputs 489 5 Assigning the Output Relays 490 6 Fixed Function LEDs 491
6.1 Trip LED Logic 491
7 Configuring Programmable LEDs 492 8 Function Keys 494 9 Control Inputs 495
Chapter 20 Fibre Teleprotection 497
1 Chapter Overview 499 2 Protection Signalling Introduction 500
2.1 Unit Protection Schemes 500
2.2 Teleprotection Commands 500
2.3 Transmission Media and Interference 501
3 Fibre Teleprotection Implementation 502
3.1 Setting up the IM64 Scheme 502
3.1.1 Fibre Teleprotection Scheme Terminal Addressing 503
3.1.2 Setting up IM64 504
3.1.3 Two-Terminal IM64 Operation 504
3.1.4 Dual Redundant Two-Terminal IM64 Operation 504
3.1.5 Three-Terminal IM64 Operation 505
3.1.6 Physical Connection 506
3.2 Communications Supervision 509
4 IM64 Logic 511 5 Application Notes 513
5.1 Alarm Management 513
5.2 Alarm Logic 513
5.3 Two-ended Scheme Extended Supervision 514
5.4 Three-ended Scheme Extended Supervision 514
Chapter 21 Electrical Teleprotection 517
P54x1i-TM-EN-1 xiii
Contents P543i/P545i
1 Chapter Overview 519 2 Introduction 520 3 Teleprotection Scheme Principles 521
3.1 Direct Tripping 521
3.2 Permissive Tripping 521
4 Implementation 522 5 Configuration 523 6 Connecting to Electrical InterMiCOM 525
6.1 Short Distance 525
6.2 Long Distance 525
7 Application Notes 526
Chapter 22 Communications 529
1 Chapter Overview 531 2 Communication Interfaces 532 3 Serial Communication 533
3.1 EIA(RS)232 Bus 533
3.2 EIA(RS)485 Bus 533
3.2.1 EIA(RS)485 Biasing Requirements 534
3.3 K-Bus 534
4 Standard Ethernet Communication 536
4.1 Hot-Standby Ethernet Failover 536
5 Redundant Ethernet Communication 537
5.1 Supported Protocols 537
5.2 Parallel Redundancy Protocol 538
5.3 High-Availability Seamless Redundancy (HSR) 539
5.3.1 HSR Multicast Topology 539
5.3.2 HSR Unicast Topology 540
5.3.3 HSR Application in the Substation 540
5.4 Rapid Spanning Tree Protocol 541
5.5 Self Healing Protocol 542
5.6 Dual Homing Protocol 543
5.7 Configuring IP Addresses 545
5.7.1 Configuring the IED IP Address 546
5.7.2 Configuring the REB IP Address 546
5.8 PRP/HSR Configurator 549
5.8.1 Connecting the IED to a PC 549
5.8.2 Installing the Configurator 550
5.8.3 Starting the Configurator 550
5.8.4 PRP/HSR Device Identification 551
5.8.5 Selecting the Device Mode 551
5.8.6 PRP/HSR IP Address Configuration 551
5.8.7 SNTP IP Address Configuration 551
5.8.8 Check for Connected Equipment 551
5.8.9 PRP Configuration 551
5.8.10 HSR Configuration 552
5.8.11 Filtering Database 552
5.8.12 End of Session 553
5.9 RSTP Configurator 553
5.9.1 Connecting the IED to a PC 553
5.9.2 Installing the Configurator 554
5.9.3 Starting the Configurator 554
5.9.4 RSTP Device Identification 554
5.9.5 RSTP IP Address Configuration 555
5.9.6 SNTP IP Address Configuration 555
5.9.7 Check for Connected Equipment 555
5.9.8 RSTP Configuration 555
xiv P54x1i-TM-EN-1
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5.9.9 End of Session 556
5.10 Switch Manager 556
5.10.1 Installation 557
5.10.2 Setup 558
5.10.3 Network Setup 558
5.10.4 Bandwidth Used 558
5.10.5 Reset Counters 558
5.10.6 Check for Connected Equipment 558
5.10.7 Mirroring Function 559
5.10.8 Ports On/Off 559
5.10.9 VLAN 559
5.10.10 End of Session 559
6 Simple Network Management Protocol (SNMP) 560
6.1 SNMP Management Information Bases 560
6.2 Main Processor MIBS Structure 560
6.3 Redundant Ethernet Board MIB Structure 561
6.4 Accessing the MIB 565
6.5 Main Processor SNMP Configuration 565
7 Data Protocols 567
7.1 Courier 567
7.1.1 Physical Connection and Link Layer 567
7.1.2 Courier Database 568
7.1.3 Settings Categories 568
7.1.4 Setting Changes 568
7.1.5 Event Extraction 568
7.1.6 Disturbance Record Extraction 570
7.1.7 Programmable Scheme Logic Settings 570
7.1.8 Time Synchronisation 570
7.1.9 Courier Configuration 571
7.2 IEC 60870-5-103 572
7.2.1 Physical Connection and Link Layer 572
7.2.2 Initialisation 573
7.2.3 Time Synchronisation 573
7.2.4 Spontaneous Events 573
7.2.5 General Interrogation (GI) 573
7.2.6 Cyclic Measurements 573
7.2.7 Commands 573
7.2.8 Test Mode 574
7.2.9 Disturbance Records 574
7.2.10 Command/Monitor Blocking 574
7.2.11 IEC 60870-5-103 Configuration 574
7.3 DNP 3.0 575
7.3.1 Physical Connection and Link Layer 576
7.3.2 Object 1 Binary Inputs 576
7.3.3 Object 10 Binary Outputs 576
7.3.4 Object 20 Binary Counters 577
7.3.5 Object 30 Analogue Input 577
7.3.6 Object 40 Analogue Output 578
7.3.7 Object 50 Time Synchronisation 578
7.3.8 DNP3 Device Profile 578
7.3.9 DNP3 Configuration 586
7.4 IEC 61850 587
7.4.1 Benefits of IEC 61850 588
7.4.2 IEC 61850 Interoperability 588
7.4.3 The IEC 61850 Data Model 588
7.4.4 IEC 61850 in MiCOM IEDs 589
7.4.5 IEC 61850 Data Model Implementation 590
7.4.6 IEC 61850 Communication Services Implementation 590
7.4.7 IEC 61850 Peer-to-peer (GOOSE) communications 590
P54x1i-TM-EN-1 xv
Contents P543i/P545i
7.4.8 Mapping GOOSE Messages to Virtual Inputs 590
7.4.9 Ethernet Functionality 591
7.4.10 IEC 61850 Configuration 591
7.4.11 IEC 61850 Edition 2 592
8 Read Only Mode 596
8.1 IEC 60870-5-103 Protocol Blocking 596
8.2 Courier Protocol Blocking 596
8.3 IEC 61850 Protocol Blocking 597
8.4 Read-Only Settings 597
8.5 Read-Only DDB Signals 597
9 Time Synchronisation 598
9.1 Demodulated IRIG-B 598
9.1.1 IRIG-B Implementation 599
9.2 SNTP 599
9.2.1 Loss of SNTP Server Signal Alarm 599
9.3 IEEE 1588 Precision time Protocol 599
9.3.1 Accuracy and Delay Calculation 599
9.3.2 PTP Domains 600
9.4 Time Synchronsiation using the Communication Protocols 600
Chapter 23 Cyber-Security 601
1 Overview 603 2 The Need for Cyber-Security 604 3 Standards 605
3.1 NERC Compliance 605
3.1.1 CIP 002 606
3.1.2 CIP 003 606
3.1.3 CIP 004 606
3.1.4 CIP 005 606
3.1.5 CIP 006 606
3.1.6 CIP 007 607
3.1.7 CIP 008 607
3.1.8 CIP 009 607
3.2 IEEE 1686-2007 607
4 Cyber-Security Implementation 609
4.1 NERC-Compliant Display 609
4.2 Four-level Access 610
4.2.1 Blank Passwords 611
4.2.2 Password Rules 611
4.2.3 Access Level DDBs 612
4.3 Enhanced Password Security 612
4.3.1 Password Strengthening 612
4.3.2 Password Validation 612
4.3.3 Password Blocking 613
4.4 Password Recovery 614
4.4.1 Password Recovery 614
4.4.2 Password Encryption 615
4.5 Disabling Physical Ports 615
4.6 Disabling Logical Ports 615
4.7 Security Events Management 616
4.8 Logging Out 618
Chapter 24 Installation 619
1 Chapter Overview 621 2 Handling the Goods 622
2.1 Receipt of the Goods 622
xvi P54x1i-TM-EN-1
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2.2 Unpacking the Goods 622
2.3 Storing the Goods 622
2.4 Dismantling the Goods 622
3 Mounting the Device 623
3.1 Flush Panel Mounting 623
3.2 Rack Mounting 624
4 Cables and Connectors 626
4.1 Terminal Blocks 626
4.2 Power Supply Connections 627
4.3 Earth Connnection 627
4.4 Current Transformers 627
4.5 Voltage Transformer Connections 628
4.6 Watchdog Connections 628
4.7 EIA(RS)485 and K-Bus Connections 628
4.8 IRIG-B Connection 628
4.9 Opto-input Connections 628
4.10 Output Relay Connections 628
4.11 Ethernet Metallic Connections 629
4.12 Ethernet Fibre Connections 629
4.13 RS232 connection 629
4.14 Download/Monitor Port 629
4.15 GPS Fibre Connection 629
4.16 Fibre Communication Connections 629
5 Case Dimensions 630
5.1 Case Dimensions 40TE 630
5.2 Case Dimensions 60TE 631
5.3 Case Dimensions 80TE 632
Chapter 25 Commissioning Instructions 633
1 Chapter Overview 635 2 General Guidelines 636 3 Commissioning Test Menu 637
3.1 Opto I/P Status Cell (Opto-input Status) 637
3.2 Relay O/P Status Cell (Relay Output Status) 637
3.3 Test Port Status Cell 637
3.4 Monitor Bit 1 to 8 Cells 637
3.5 Test Mode Cell 638
3.6 Test Pattern Cell 638
3.7 Contact Test Cell 638
3.8 Test LEDs Cell 638
3.9 Test Autoreclose Cell 638
3.10 Static Test Mode 639
3.11 Loopback Mode 639
3.12 IM64 Test Pattern 640
3.13 IM64 Test Mode 640
3.14 Red and Green LED Status Cells 640
3.15 Using a Monitor Port Test Box 640
4 Commissioning Equipment 641
4.1 Recommended Commissioning Equipment 641
4.2 Essential Commissioning Equipment 641
4.3 Advisory Test Equipment 642
5 Product Checks 643
5.1 Product Checks with the IED De-energised 643
5.1.1 Visual Inspection 644
5.1.2 Current Transformer Shorting Contacts 644
5.1.3 Insulation 644
P54x1i-TM-EN-1 xvii
Contents P543i/P545i
5.1.4 External Wiring 644
5.1.5 Watchdog Contacts 645
5.1.6 Power Supply 645
5.2 Product Checks with the IED Energised 645
5.2.1 Watchdog Contacts 645
5.2.2 Test LCD 646
5.2.3 Date and Time 646
5.2.4 Test LEDs 647
5.2.5 Test Alarm and Out-of-Service LEDs 647
5.2.6 Test Trip LED 647
5.2.7 Test User-programmable LEDs 647
5.2.8 Test Field Voltage Supply 647
5.2.9 Test Opto-inputs 647
5.2.10 Test Output Relays 648
5.2.11 Test Serial Communication Port RP1 648
5.2.12 Test Serial Communication Port RP2 649
5.2.13 Test Ethernet Communication 650
5.3 Secondary Injection Tests 650
5.3.1 Test Current Inputs 650
5.3.2 Test Voltage Inputs 651
6 Electrical Intermicom Communication Loopback 652
6.1 Setting up the Loopback 652
6.2 Loopback Test 652
6.2.1 InterMicom Command Bits 653
6.2.2 InterMicom Channel Diagnostics 653
6.2.3 Simulating a Channel Failure 653
7 Intermicom 64 Communication 654
7.1 Checking the Interface 654
7.2 Setting up the Loopback 655
7.3 Loopback Test 655
8 GPS Synchronisation 656
8.1 GPS Optical Signal Strength 656
8.2 Check Synchronisation signal at the IED 656
9 Setting Checks 657
9.1 Apply Application-specific Settings 657
9.1.1 Transferring Settings from a Settings File 657
9.1.2 Entering settings using the HMI 657
10 IEC 61850 Edition 2 Testing 659
10.1 Using IEC 61850 Edition 2 Test Modes 659
10.1.1 IED Test Mode Behaviour 659
10.1.2 Sampled Value Test Mode Behaviour 659
10.2 Simulated Input Behaviour 660
10.3 Testing Examples 660
10.3.1 Test Procedure for Real Values 661
10.3.2 Test Procedure for Simulated Values - No Plant 661
10.3.3 Test Procedure for Simulated Values - With Plant 662
10.3.4 Contact Test 663
11 Current Differential Protection 664
11.1 Current Differential Bias Characteristic 664
11.1.1 Lower Slope 664
11.1.2 Upper Slope 665
11.2 Current Differential Operation and Contact Assignment 665
12 Distance Protection 667
12.1 Dependency Conditions 667
12.2 Distance Protection Single-ended Testing 667
12.2.1 Preliminaries 667
12.2.2 Zone 1 Reach Check 668
12.2.3 Zone 2 Reach Check 668
xviii P54x1i-TM-EN-1
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12.2.4 Zone 3 Reach Check 669
12.2.5 Zone 4 Reach Check 669
12.2.6 Zone P Reach Check 669
12.2.7 Zone Q Reach Check 669
12.2.8 Resistive Reach 669
12.2.9 Load Blinder 670
12.3 Operation and Contact Assignment 670
12.3.1 Phase A 670
12.3.2 Phase B 670
12.3.3 Phase C 670
12.3.4 Time Delay Settings 671
12.4 Scheme Testing 671
12.4.1 Scheme Trip Test for Zone 1 Extension 672
12.4.2 Scheme Trip Tests for Permissive Schemes 672
12.4.3 Scheme Trip Tests for Blocking Scheme 672
12.4.4 Signal Send Test for Permissive Schemes 673
12.4.5 Signal Send Test for Blocking Scheme 673
12.4.6 Scheme Timer Settings 673
13 Delta Directional Comparison 674
13.1 Single-ended Testing 674
13.1.1 Preliminaries 674
13.1.2 Single-ended Injection Test 674
13.1.3 Forward Fault Preparation 674
13.2 Operation and Contact Assignment 675
13.2.1 Phase A 675
13.2.2 Phase B 675
13.2.3 Phase C 675
13.3 Delta Protection Scheme Testing 676
13.3.1 Signal Send Test for Permissive Schemes 676
13.3.2 Signal Send Test for Blocking Schemes 676
14 DEF Aided Schemes 677
14.1 Dependency Conditions 677
14.2 Earth Current Pilot Scheme 677
14.2.1 Preliminaries 678
14.2.2 Perform the Test 678
14.2.3 Forward Fault Trip Test 678
14.3 Scheme Testing 679
14.3.1 Signal Send Test for Permissive Schemes 679
14.3.2 Signal Send Test for Blocking Schemes 679
15 Out of Step Protection 680
15.1 OST Setting 680
15.2 Predictive OST Setting 681
15.3 Predictive and OST Setting 681
15.4 OST Timer Test 681
16 Protection Timing Checks 682
16.1 Dependency Conditions 682
16.2 Overcurrent Check 682
16.3 Connecting the Test Circuit 682
16.4 Performing the Test 683
16.5 Check the Operating Time 683
17 System Check and Check Synchronism 684
17.1 Check Synchronism Pass 684
17.2 Check Synchronism Fail 684
18 Check Trip and Autoreclose Cycle 685 19 End-to-End Communication Tests 686
19.1 Remove Local Loopbacks 686
19.1.1 Restoring Direct Fibre Connections 686
19.1.2 Restoring C37.94 Fibre Connections 687
P54x1i-TM-EN-1 xix
Contents P543i/P545i
19.1.3 Communications using P59x Interface Units 687
19.2 Remove Remote Loopbacks 687
19.3 Verify Communication between IEDs 687
20 End-to-End Scheme Tests 689
20.1 Aided Scheme 1 689
20.1.1 Preparation at Remote End 689
20.1.2 Performing the Test 689
20.1.3 Channel Check in the Opposite Direction 689
20.2 Aided Scheme 2 689
21 Onload Checks 691
21.1 Confirm Voltage Connections 691
21.2 Confirm Current Connections 691
21.3 Measure Capacitive Charging Current 692
21.4 Check Differential Current 692
21.5 Check Current Transformer Polarity 692
21.6 On-load Directional Test 692
22 Final Checks 693 23 Commmissioning the P59x 694
23.1 Visual Inspection 694
23.2 Insulation 694
23.3 External Wiring 694
23.4 P59x Auxiliary Supply 694
23.5 P59x LEDs 695
23.6 Received Optical Signal Level 695
23.7 Optical Transmitter Level 695
23.8 Loopback Test 696
Chapter 26 Maintenance and Troubleshooting 697
1 Chapter Overview 699 2 Maintenance 700
2.1 Maintenance Checks 700
2.1.1 Alarms 700
2.1.2 Opto-isolators 700
2.1.3 Output Relays 700
2.1.4 Measurement Accuracy 700
2.2 Replacing the Device 701
2.3 Repairing the Device 702
2.4 Removing the front panel 702
2.5 Replacing PCBs 703
2.5.1 Replacing the main processor board 703
2.5.2 Replacement of communications boards 704
2.5.3 Replacement of the input module 705
2.5.4 Replacement of the power supply board 705
2.5.5 Replacement of the I/O boards 706
2.6 Recalibration 706
2.7 Changing the battery 706
2.7.1 Post Modification Tests 707
2.7.2 Battery Disposal 707
2.8 Cleaning 707
3 Troubleshooting 708
3.1 Self-Diagnostic Software 708
3.2 Power-up Errors 708
3.3 Error Message or Code on Power-up 708
3.4 Out of Service LED on at power-up 709
3.5 Error Code during Operation 710
3.5.1 Backup Battery 710
xx P54x1i-TM-EN-1
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3.6 Mal-operation during testing 710
3.6.1 Failure of Output Contacts 710
3.6.2 Failure of Opto-inputs 710
3.6.3 Incorrect Analogue Signals 711
3.7 Coprocessor board failures 711
3.7.1 Signalling failure alarm (on its own) 711
3.7.2 C diff failure alarm (on its own) 711
3.7.3 Signalling failure and C diff failure alarms together 711
3.7.4 Incompatible IED 711
3.7.5 Comms changed 711
3.7.6 IEEE C37.94 fail 712
3.8 PSL Editor Troubleshooting 712
3.8.1 Diagram Reconstruction 712
3.8.2 PSL Version Check 712
3.9 Repair and Modification Procedure 712
Chapter 27 Technical Specifications 715
1 Chapter Overview 717 2 Interfaces 718
2.1 Front Serial Port 718
2.2 Download/Monitor Port 718
2.3 Rear Serial Port 1 718
2.4 Fibre Rear Serial Port 1 718
2.5 Rear Serial Port 2 719
2.6 Optional Rear Serial Port (SK5) 719
2.7 IRIG-B (Demodulated) 719
2.8 IRIG-B (Modulated) 719
2.9 Rear Ethernet Port Copper 720
2.10 Rear Ethernet Port Fibre 720
2.10.1 100 Base FX Receiver Characteristics 720
2.10.2 100 Base FX Transmitter Characteristics 721
2.11 1 PPS Port 721
2.12 Fibre Teleprotection Interface 721
3 Protection Functions 722
3.1 Phase Current Differential Protection 722
3.2 Neutral Current Differential Protection 722
3.3 Distance Protection 723
3.4 Power Swing Blocking 723
3.5 Out Of Step Protection 724
3.6 Fibre Teleprotection Transfer Times 724
3.7 Autoreclose and Check Synychronism 724
3.8 Phase Overcurrent Protection 724
3.8.1 Transient Overreach and Overshoot 725
3.8.2 Phase Overcurrent Directional Parameters 725
3.9 Earth Fault Protection 725
3.9.1 Earth Fault Directional Parameters 725
3.10 Sensitive Earth Fault Protection 726
3.10.1 Sensitive Earth Fault Protection Directional Element 726
3.11 High Impedance Restricted Earth Fault Protection 726
3.12 Negative Sequence Overcurrent Protection 726
3.12.1 NPSOC Directional Parameters 727
3.13 Circuit Breaker Fail and Undercurrent Protection 727
3.14 Broken Conductor Protection 727
3.15 Thermal Overload Protection 727
4 Monitoring, Control and Supervision 728
4.1 Voltage Transformer Supervision 728
P54x1i-TM-EN-1 xxi
Contents P543i/P545i
4.2 Standard Current Transformer Supervision 728
4.3 Differential Current Transformer Supervision 728
4.4 CB State and Condition Monitoring 728
4.5 PSL Timers 729
5 Measurements and Recording 730
5.1 General 730
5.2 Disturbance Records 730
5.3 Event, Fault and Maintenance Records 730
5.4 Fault Locator 730
6 Ratings 731
6.1 AC Measuring Inputs 731
6.2 Current Transformer Inputs 731
6.3 Voltage Transformer Inputs 731
6.4 Auxiliary Supply Voltage 731
6.5 Nominal Burden 732
6.6 Power Supply Interruption 732
6.7 Battery Backup 733
7 Input / Output Connections 734
7.1 Isolated Digital Inputs 734
7.1.1 Nominal Pickup and Reset Thresholds 734
7.2 Standard Output Contacts 734
7.3 High Break Output Contacts 735
7.4 Watchdog Contacts 735
8 Mechanical Specifications 736
8.1 Physical Parameters 736
8.2 Enclosure Protection 736
8.3 Mechanical Robustness 736
8.4 Transit Packaging Performance 736
9 Type Tests 737
9.1 Insulation 737
9.2 Creepage Distances and Clearances 737
9.3 High Voltage (Dielectric) Withstand 737
9.4 Impulse Voltage Withstand Test 737
10 Environmental Conditions 738
10.1 Ambient Temperature Range 738
10.2 Temperature Endurance Test 738
10.3 Ambient Humidity Range 738
10.4 Corrosive Environments 738
11 Electromagnetic Compatibility 739
11.1 1 MHz Burst High Frequency Disturbance Test 739
11.2 Damped Oscillatory Test 739
11.3 Immunity to Electrostatic Discharge 739
11.4 Electrical Fast Transient or Burst Requirements 739
11.5 Surge Withstand Capability 739
11.6 Surge Immunity Test 740
11.7 Immunity to Radiated Electromagnetic Energy 740
11.8 Radiated Immunity from Digital Communications 740
11.9 Radiated Immunity from Digital Radio Telephones 740
11.10 Immunity to Conducted Disturbances Induced by Radio Frequency Fields 740
11.11 Magnetic Field Immunity 741
11.12 Conducted Emissions 741
11.13 Radiated Emissions 741
11.14 Power Frequency 741
12 Regulatory Compliance 742
12.1 EMC Compliance: 2014/30/EU 742
12.2 LVD Compliance: 2014/35/EU 742
xxii P54x1i-TM-EN-1
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12.3 R&TTE Compliance: 2014/53/EU 742
12.4 UL/CUL Compliance 742
12.5 ATEX Compliance: 2014/34/EU 742
Appendix A Ordering Options 745
Appendix B Settings and Signals 747
Appendix C Wiring Diagrams 749
P54x1i-TM-EN-1 xxiii
Contents P543i/P545i
xxiv P54x1i-TM-EN-1
Table of Figures
Figure 1: P40L version M85 - version evolution 7 Figure 2: Key to logic diagrams 12 Figure 3: Functional Overview 13 Figure 4: Hardware architecture 32 Figure 5: Coprocessor hardware architecture 33 Figure 6: Exploded view of IED 34 Figure 7: Front panel (60TE) 37 Figure 8: Rear view of populated case 41 Figure 9: Terminal block types 42 Figure 10: Rear connection to terminal block 43 Figure 11: Main processor board 44 Figure 12: Power supply board 45 Figure 13: Power supply assembly 46 Figure 14: Power supply terminals 47 Figure 15: Watchdog contact terminals 48 Figure 16: Rear serial port terminals 49 Figure 17: Input module - 1 transformer board 49 Figure 18: Input module schematic 50 Figure 19: Transformer board 51 Figure 20: Input board 52 Figure 21: Standard output relay board - 8 contacts 53 Figure 22: IRIG-B board 54 Figure 23: Fibre optic board 55 Figure 24: Rear communication board 56 Figure 25: Ethernet board 56 Figure 26: Redundant Ethernet board 58 Figure 27: Fully populated Coprocessor board 60 Figure 28: Software Architecture 66 Figure 29: Frequency response of FIR filters 72 Figure 30: Frequency Response (indicative only) 73 Figure 31: Navigating the HMI 80 Figure 32: Default display navigation 82 Figure 33: Circuit Breaker Trip Conversion Logic Diagram (Module 63) 89 Figure 34: Ping-pong measurement for alignment of current signals 102 Figure 35: Asymmetric propogation delay times 104 Figure 36: Dual slope current differential bias characteristic 105 Figure 37: Phase Current Differential Protection logic 107 Figure 38: Capacitive charging current 112
Table of Figures P543i/P545i
Figure 39: CT Compensation 113 Figure 40: The need for zero-sequence current filtering 116 Figure 41: Magnetising inrush phenomenon 117 Figure 42: Typical overflux current waveform 119 Figure 43: Phase Current Differential Protection logic for feeders with in-zone transformers 120 Figure 44: Second Harmonic Blocking logic 121 Figure 45: Fifth Harmonic Blocking logic 122 Figure 46: Permissive Intertripping example 123 Figure 47: Stub Bus protection 124 Figure 48: Typical two-terminal plain feeder circuit 129 Figure 49: Typical three-terminal plain feeder circuit 130 Figure 50: System Impedance Ratio 136 Figure 51: Directional mho element construction 139 Figure 52: Offset Mho characteristic 140 Figure 53: Directional Mho element construction – impedance domain 141 Figure 54: Offset Mho characteristics – impedance domain 142 Figure 55: Offset mho characteristics – voltage domain 143 Figure 56: Simplified forward fault 144 Figure 57: Mho expansion – forward fault 145 Figure 58: Simplified Reverse Fault 146 Figure 59: Mho contraction – reverse fault 147 Figure 60: Simplified quadrilateral characteristics 149 Figure 61: General Quadrilateral Characteristic Limits 150 Figure 62: Directional Quadrilateral Characteristic 151 Figure 63: Quadrilateral Characteristic featuring 2 directional forward zones and 1 offset zone 152 Figure 64: Five-sided polygon formed by Quadrilateral characteristic with Directional-Line
153
intersection of Reverse Impedance Reach Line
Figure 65: Impedance Reach line in Z1 plane 156 Figure 66: Impedance Reach line in ZLP plane 157 Figure 67: General characteristic in ZLP plane 158 Figure 68: Phase relations between I2 and Iph for leading and lagging polarizing currents 159 Figure 69: General characteristic in Z1 plane 160 Figure 70: Simplified characteristic in Z1 plane 161 Figure 71: Impedance Reach line construction 163 Figure 72: Reverse impedance reach line construction 164 Figure 73: Resistive reach of phase elements 164 Figure 74: Resistive Reach line construction 165 Figure 75: Reverse resistive reach line construction 166 Figure 76: Phase Fault Quadrilateral characteristic summary 166 Figure 77: Phase to phase current changes for C phase-to-ground (CN) fault 170
xxvi P54x1i-TM-EN-1
P543i/P545i Table of Figures
Figure 78: Biased Neutral Current Detector Characteristic 171 Figure 79: Load Blinder Characteristics 174 Figure 80: Sequence networks connection for an internal A-N fault 177 Figure 81: - DV Forward and Reverse tripping regions 178 Figure 82: Current level (amps) at which transient faults are self-extinguishing 179 Figure 83: Earth fault in Petersen Coil earthed system 180 Figure 84: Distribution of currents during a Phase C fault 180 Figure 85: Phasors for a phase C earth fault in a Petersen Coil earthed system 181 Figure 86: Zero sequence network showing residual currents 181 Figure 87: Phase C earth fault in Petersen Coil earthed system: practical case with resistance
182
present
Figure 88: Voltage distribution in an isolated system for a Phase-A-to-Earth fault 185 Figure 89: Biased Neutral Current Detector 185 Figure 90: First earth fault detection 186 Figure 91: Second earth fault detection logic 187 Figure 92: Priority setting enable logic 189 Figure 93: Zone starting logic 190 Figure 94: Zone timer logic 191 Figure 95: Zone trip logic 192 Figure 96: Settings required to apply a quadrilateral zone 193 Figure 97: Settings required to apply a mho zone 194 Figure 98: Over-tilting effect 196 Figure 99: Example power system 201 Figure 100: Apparent Impedances seen by Distance Protection on a Teed Feeder 206 Figure 101: Scheme Assignment 211 Figure 102: Aided Distance PUR scheme 214 Figure 103: Aided Distance POR scheme 216 Figure 104: Example of fault current reversal of direction 218 Figure 105: Aided Distance Blocking scheme (BOP) 220 Figure 106: Aided Distance Send logic 222 Figure 107: Carrier Aided Schemes Receive logic 223 Figure 108: Aided Distance Tripping logic 223 Figure 109: PUR Aided Tripping logic 224 Figure 110: POR Aided Tripping logic 225 Figure 111: Aided Scheme Blocking 1 Tripping logic 226 Figure 112: Aided Scheme Blocking 2 Tripping logic 226 Figure 113: Virtual Current Polarization 229 Figure 114: Directional criteria for residual voltage polarization 230 Figure 115: Aided DEF POR scheme 232 Figure 116: Aided DEF Blocking scheme 233
P54x1i-TM-EN-1 xxvii
Table of Figures P543i/P545i
Figure 117: DEF Directional Signals 233 Figure 118: Aided DEF Send logic 234 Figure 119: Carrier Aided Schemes Receive logic 234 Figure 120: Aided DEF Tripping logic 235 Figure 121: POR Aided Tripping logic 236 Figure 122: Aided Scheme Blocking 1 Tripping logic 237 Figure 123: Aided Scheme Blocking 2 Tripping logic 237 Figure 124: Aided Delta POR scheme 239 Figure 125: Aided Delta Blocking scheme 240 Figure 126: Aided Delta Send logic 241 Figure 127: Carrier Aided Schemes Receive logic 241 Figure 128: Aided Delta Tripping logic 242 Figure 129: POR Aided Tripping logic 243 Figure 130: Aided Scheme Blocking 1 Tripping logic 244 Figure 131: Aided Scheme Blocking 2 Tripping logic 244 Figure 132: Apparent Impedances seen by Distance Protection on a Teed Feeder 247 Figure 133: Problematic Fault Scenarios for PUR Scheme Application to Teed Feeders 249 Figure 134: Zone Starting Logic 256 Figure 135: Zone timer logic 257 Figure 136: Zone trip logic 257 Figure 137: Basic time stepped distance scheme 258 Figure 138: Trip On Close logic 259 Figure 139: Trip On Close based on CNV level detectors 260 Figure 140: SOTF Tripping 261 Figure 141: SOTF Tripping with CNV 261 Figure 142: TOR Tripping logic for appropriate zones 262 Figure 143: TOR Tripping logic with CNV 262 Figure 144: Zone 1 extension scheme 264 Figure 145: Zone 1 extension logic 264 Figure 146: Loss of load accelerated trip scheme 265 Figure 147: Loss of Load Logic 266 Figure 148: Power transfer related to angular difference between two generation sources 270 Figure 149: Phase selector timing for power swing condition 273 Figure 150: Phase selector timing for fault condition 274 Figure 151: Phase selector timing for fault during a power swing 274 Figure 152: Slow Power Swing detection characteristic 275 Figure 153: Load Blinder Boundary Conditions 278 Figure 154: Power swing blocking logic 279 Figure 155: Setting the resistive reaches 280 Figure 156: Reactive reach settings 281
xxviii P54x1i-TM-EN-1
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