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MiCOM P144 Agile
Technical Manual
668 pgs21.79 Mb0
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GE MiCOM P40 Agile, MiCOM P143 Agile, MiCOM P144 Agile, MiCOM P141 Agile, MiCOM P145 Agile Technical Manual

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GE Energy Connections Grid Solutions
MiCOM P40 Agile
P141, P142, P143, P144, P145
Technical Manual Feeder Management IED
Hardware Version: J Software Version: 52 Publication Reference: P14xEd1-TM-EN-1
Contents
Chapter 1 Introduction 1
1 Chapter Overview 3 2 Foreword 4
2.1 Target Audience 4
2.2 Typographical Conventions 4
2.3 Nomenclature 5
3 Product Scope 6
3.1 Ordering Options 6
4 Features and Functions 7
4.1 Protection Functions 7
4.2 Control Functions 8
4.3 Measurement Functions 8
4.4 Communication Functions 8
5 Compliance 10 6 Functional Overview 11
Chapter 2 Safety Information 13
1 Chapter Overview 15 2 Health and Safety 16 3 Symbols 17 4 Installation, Commissioning and Servicing 18
4.1 Lifting Hazards 18
4.2 Electrical Hazards 18
4.3 UL/CSA/CUL Requirements 19
4.4 Fusing Requirements 19
4.5 Equipment Connections 20
4.6 Protection Class 1 Equipment Requirements 20
4.7 Pre-energisation Checklist 21
4.8 Peripheral Circuitry 21
4.9 Upgrading/Servicing 22
5 Decommissioning and Disposal 23 6 Regulatory Compliance 24
6.1 EMC Compliance: 2014/30/EU 24
6.2 LVD Compliance: 2014/35/EU 24
6.3 R&TTE Compliance: 2014/53/EU 24
6.4 UL/CUL Compliance 24
6.5 ATEX Compliance: 2014/34/EU 24
Chapter 3 Hardware Design 27
1 Chapter Overview 29 2 Hardware Architecture 30 3 Mechanical Implementation 31
3.1 Housing Variants 31
3.2 List of Boards 32
4 Front Panel 33
4.1 Front Panel 33
4.1.1 Front Panel Compartments 33
4.1.2 HMI Panel 34
4.1.3 Front Serial Port (SK1) 34
4.1.4 Front Parallel Port (SK2) 35
4.1.5 Fixed Function LEDs 35
4.1.6 Function Keys 35
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4.1.7 Programable LEDs 36
5 Rear Panel 37 6 Boards and Modules 39
6.1 PCBs 39
6.2 Subassemblies 39
6.3 Main Processor Board 40
6.4 Power Supply Board 41
6.4.1 Watchdog 43
6.4.2 Rear Serial Port 44
6.5 Input Module - 1 Transformer Board 45
6.5.1 Input Module Circuit Description 46
6.5.2 Transformer Board 47
6.5.3 Input Board 48
6.6 Standard Output Relay Board 49
6.7 IRIG-B Board 50
6.8 Fibre Optic Board 51
6.9 Rear Communication Board 52
6.10 Ethernet Board 52
6.11 Redundant Ethernet Board 54
Chapter 4 Software Design 57
1 Chapter Overview 59 2 Sofware Design Overview 60 3 System Level Software 61
3.1 Real Time Operating System 61
3.2 System Services Software 61
3.3 Self-Diagnostic Software 61
3.4 Startup Self-Testing 61
3.4.1 System Boot 61
3.4.2 System Level Software Initialisation 62
3.4.3 Platform Software Initialisation and Monitoring 62
3.5 Continuous Self-Testing 62
4 Platform Software 63
4.1 Record Logging 63
4.2 Settings Database 63
4.3 Interfaces 63
5 Protection and Control Functions 64
5.1 Acquisition of Samples 64
5.2 Frequency Tracking 64
5.3 Direct Use of Sample Values 64
5.4 Fourier Signal Processing 64
5.5 Programmable Scheme Logic 65
5.6 Event Recording 66
5.7 Disturbance Recorder 66
5.8 Fault Locator 66
5.9 Function Key Interface 66
Chapter 5 Configuration 67
1 Chapter Overview 69 2 Settings Application Software 70 3 Using the HMI Panel 71
3.1 Navigating the HMI Panel 72
3.2 Getting Started 72
3.3 Default Display 73
3.4 Default Display Navigation 74
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3.5 Password Entry 75
3.6 Processing Alarms and Records 75
3.7 Menu Structure 76
3.8 Changing the Settings 77
3.9 Direct Access (The Hotkey menu) 78
3.9.1 Setting Group Selection Using Hotkeys 78
3.9.2 Control Inputs 78
3.9.3 Circuit Breaker Control 79
3.10 Function Keys 79
4 Date and Time Configuration 81
4.1 Using an SNTP Signal 81
4.2 Using an IRIG-B Signal 81
4.3 Using an IEEE 1588 PTP Signal 81
4.4 Without a Timing Source Signal 82
4.5 Time Zone Compensation 82
4.6 Daylight Saving Time Compensation 83
5 Settings Group Selection 84
Chapter 6 Current Protection Functions 85
1 Chapter Overview 87 2 Overcurrent Protection Principles 88
2.1 IDMT Characteristics 88
2.1.1 IEC 60255 IDMT Curves 89
2.1.2 European Standards 91
2.1.3 North American Standards 92
2.1.4 IEC and IEEE Inverse Curves 94
2.1.5 Differences Between the North american and European Standards 95
2.1.6 Programmable Curves 95
2.2 Principles of Implementation 95
2.2.1 Timer Hold Facility 96
3 Phase Overcurrent Protection 98
3.1 Phase Overcurrent Protection Implementation 98
3.2 Non-Directional Overcurrent Logic 99
3.3 Directional Element 100
3.3.1 Directional Overcurrent Logic 101
3.4 Application Notes 102
3.4.1 Parallel Feeders 102
3.4.2 Ring Main Arrangements 103
3.4.3 Setting Guidelines 103
3.4.4 Setting Guidelines (Directional Element) 104
4 Voltage Dependent Overcurrent Element 105
4.1 Voltage Dependent Overcurrent Protection Implementation 105
4.1.1 Voltage Controlled Overcurrent Protection 105
4.1.2 Voltage Restrained Overcurrent Protection 106
4.2 Voltage Dependent Overcurrent Logic 107
4.3 Application Notes 107
4.3.1 Setting Guidelines 107
5 Current Setting Threshold Selection 109 6 Cold Load Pickup 110
6.1 Implementation 110
6.2 CLP Logic 111
6.3 Application Notes 111
6.3.1 CLP for Resistive Loads 111
6.3.2 CLP for Motor Feeders 111
6.3.3 CLP for Switch Onto Fault Conditions 112
7 Selective Logic 113
7.1 Selective Logic Implementation 113
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7.2 Selective Logic Diagram 113
8 Timer Setting Selection 115 9 Negative Sequence Overcurrent Protection 116
9.1 Negative Sequence Overcurrent Protection Implementation 116
9.2 Non-Directional Negative Sequence Overcurrent Logic 117
9.3 Composite Earth Fault Start Logic 117
9.4 Directional Element 117
9.4.1 Directional Negative Sequence Overcurrent Logic 118
9.5 Application Notes 118
9.5.1 Setting Guidelines (Current Threshold) 118
9.5.2 Setting Guidelines (Time Delay) 119
9.5.3 Setting Guidelines (Directional element) 119
10 Earth Fault Protection 120
10.1 Earth Fault Protection Elements 120
10.2 Non-directional Earth Fault Logic 121
10.3 IDG Curve 121
10.4 Directional Element 122
10.4.1 Residual Voltage Polarisation 122
10.4.2 Negative Sequence Polarisation 123
10.5 Application Notes 124
10.5.1 Setting Guidelines (Directional Element) 124
10.5.2 Peterson Coil Earthed Systems 124
10.5.3 Setting Guidelines (Compensated networks) 128
11 Sensitive Earth Fault Protection 130
11.1 SEF Protection Implementation 130
11.2 Non-directional SEF Logic 130
11.3 SEF Any Start Logic 131
11.4 EPATR B Curve 131
11.5 Directional Element 132
11.5.1 Wattmetric Characteristic 133
11.5.2 Icos phi / Isin phi characteristic 134
11.5.3 Directional SEF Logic 135
11.6 Application Notes 136
11.6.1 Insulated Systems 136
11.6.2 Setting Guidelines (Insulated Systems) 137
12 Thermal Overload Protection 139
12.1 Single Time Constant Characteristic 139
12.2 Dual Time Constant Characteristic 139
12.3 Thermal Overload Protection Implementation 140
12.4 Thermal Overload Protection Logic 140
12.5 Application Notes 140
12.5.1 Setting Guidelines for Dual Time Constant Characteristic 140
12.5.2 Setting Guidelines for Single Time Constant Characteristic 142
13 Broken Conductor Protection 144
13.1 Broken Conductor Protection Implementation 144
13.2 Broken Conductor Protection Logic 144
13.3 Application Notes 144
13.3.1 Setting Guidelines 144
14 Blocked Overcurrent Protection 146
14.1 Blocked Overcurrent Implementation 146
14.2 Blocked Overcurrent Logic 146
14.3 Blocked Earth Fault Logic 146
14.4 Application Notes 147
14.4.1 Busbar Blocking Scheme 147
15 Second Harmonic Blocking 149
15.1 Second Harmonic Blocking Implementation 149
15.2 Second Harmonic Blocking Logic (POC Input) 150
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15.3 Second Harmonic Blocking Logic (SEF Input) 151
15.4 Application Notes 151
15.4.1 Setting Guidelines 151
16 Load Blinders 152
16.1 Load Blinder Implementation 152
16.2 Load Blinder Logic 153
17 Neutral Admittance Protection 156
17.1 Neutral Admittance Operation 156
17.2 Conductance Operation 156
17.3 Susceptance Operation 157
18 Busbar Protection 159
18.1 Buswire Supervision 160
Chapter 7 Restricted Earth Fault Protection 161
1 Chapter Overview 163 2 REF Protection Principles 164
2.1 Resistance-Earthed Star Windings 165
2.2 Solidly-Earthed Star Windings 165
2.3 Through Fault Stability 166
2.4 Restricted Earth Fault Types 166
2.4.1 Low Impedance REF Principle 167
2.4.2 High Impedance REF Principle 168
3 Restricted Earth Fault Protection Implementation 171
3.1 Restricted Earth Fault Protection Implementation 171
3.2 Low Impedance REF 171
3.2.1 Setting the Bias Characteristic 171
3.2.2 Delayed Bias 172
3.2.3 Transient Bias 172
3.3 High Impedance REF 172
3.3.1 High Impedance REF Calculation Principles 173
4 Application Notes 174
4.1 Star Winding Resistance Earthed 174
4.2 Low Impedance REF Protection Application 175
4.2.1 Setting Guidelines for Biased Operation 175
4.2.2 Low Impedance REF Scaling Factor 175
4.2.3 Parameter Calculations 176
4.3 High Impedance REF Protection Application 177
4.3.1 High Impedance REF Operating Modes 177
4.3.2 Setting Guidelines for High Impedance Operation 178
Chapter 8 CB Fail Protection 181
1 Chapter Overview 183 2 Circuit Breaker Fail Protection 184 3 Circuit Breaker Fail Implementation 185
3.1 Circuit Breaker Fail Timers 185
3.2 Zero Crossing Detection 185
4 Circuit Breaker Fail Logic 187 5 Undercurrent and ZCD Logic for CB Fail 190 6 CB Fail SEF Protection Logic 191 7 CB Fail Non Current Protection Logic 192 8 Circuit Breaker Mapping 193 9 Application Notes 194
9.1 Reset Mechanisms for CB Fail Timers 194
9.2 Setting Guidelines (CB fail Timer) 194
9.3 Setting Guidelines (Undercurrent) 195
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Chapter 9 Current Transformer Requirements 197
1 Chapter Overview 199 2 CT requirements 200
2.1 Phase Overcurrent Protection 200
2.1.1 Directional Elements 200
2.1.2 Non-directional Elements 200
2.2 Earth Fault Protection 201
2.2.1 Directional Elements 201
2.2.2 Non-directional Elements 201
2.3 SEF Protection (Residually Connected) 201
2.3.1 Directional Elements 201
2.3.2 Non-directional Elements 201
2.4 SEF Protection (Core-Balanced CT) 202
2.4.1 Directional Elements 202
2.4.2 Non-directional Elements 202
2.5 Low Impedance REF Protection 202
2.6 High Impedance REF Protection 202
2.7 High Impedance Busbar Protection 203
2.8 Use of Metrosil Non-linear Resistors 203
2.9 Use of ANSI C-class CTs 205
Chapter 10 Voltage Protection Functions 207
1 Chapter Overview 209 2 Undervoltage Protection 210
2.1 Undervoltage Protection Implementation 210
2.2 Undervoltage Protection Logic 211
2.3 Application Notes 212
2.3.1 Undervoltage Setting Guidelines 212
3 Overvoltage Protection 213
3.1 Overvoltage Protection Implementation 213
3.2 Overvoltage Protection Logic 214
3.3 Application Notes 215
3.3.1 Overvoltage Setting Guidelines 215
4 Rate of Change of Voltage Protection 216
4.1 Rate of Change of Voltage Protection Implementation 216
4.2 Rate of Change of Voltage Logic 216
5 Residual Overvoltage Protection 218
5.1 Residual Overvoltage Protection Implementation 218
5.2 Residual Overvoltage Logic 219
5.3 Application Notes 219
5.3.1 Calculation for Solidly Earthed Systems 219
5.3.2 Calculation for Impedance Earthed Systems 220
5.3.3 Neutral Voltage Displacement (Nvd) Protection Applied To Condenser Bushings (Capacitor Cones) 221
5.3.4 Setting Guidelines 227
6 Negative Sequence Overvoltage Protection 228
6.1 Negative Sequence Overvoltage Implementation 228
6.2 Negative Sequence Overvoltage Logic 228
6.3 Application Notes 228
6.3.1 Setting Guidelines 228
7 Sensitive Overvoltage Supervision 230
7.1 Sensitive Overvoltage Implementation 230
7.1.1 Sensitive Overvoltage Filter Mode 230
7.2 Sensitive Overvoltage Logic 231
7.2.1 Sensitive Overvoltage Operation Logic 231
7.2.2 Sensitive Overvoltage Filter Mode Logic 232
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7.2.3 Sensitive Overvoltage Blocking Logic 232
Chapter 11 Frequency Protection Functions 233
1 Chapter Overview 235 2 Frequency Protection Overview 236
2.1 Frequency Protection Implementation 236
3 Underfrequency Protection 238
3.1 Underfrequency Protection Implementation 238
3.2 Underfrequency Protection Logic 238
3.3 Application Notes 239
3.3.1 Setting Guidelines 239
4 Overfrequency Protection 240
4.1 Overfrequency Protection Implementation 240
4.2 Overfrequency Protection Logic 240
4.3 Application Notes 241
4.3.1 Setting Guidelines 241
5 Independent R.O.C.O.F Protection 242
5.1 Indepenent R.O.C.O.F Protection Implementation 242
5.2 Independent R.O.C.O.F Protection Logic 243
5.3 Application Notes 243
5.3.1 Setting Guidelines 243
6 Frequency-supervised R.O.C.O.F Protection 245
6.1 Frequency-supervised R.O.C.O.F Implementation 245
6.2 Frequency-supervised R.O.C.O.F Logic 246
6.3 Application Notes 246
6.3.1 Frequency-Supervised R.O.C.O.F Example 246
6.3.2 Setting Guidelines 247
7 Average Rate of Change of Frequency Protection 248
7.1 Average R.O.C.O.F Protection Implementation 248
7.2 Average R.O.C.O.F Logic 249
7.3 Application Notes 249
7.3.1 Setting Guidelines 249
8 Load Shedding and Restoration 251
8.1 Load Restoration Implementation 251
8.2 Holding Band 251
8.3 Load Restoration Logic 254
8.4 Application Notes 254
8.4.1 Setting Guidelines 254
Chapter 12 Power Protection Functions 257
1 Chapter Overview 259 2 Overpower Protection 260
2.1 Overpower Protection Implementation 260
2.2 Overpower Logic 261
2.3 Application Notes 261
2.3.1 Forward Overpower Setting Guidelines 261
2.3.2 Reverse Power Considerations 261
2.3.3 Reverse Overpower Setting Guidelines 262
3 Underpower Protection 263
3.1 Underpower Protection Implementation 263
3.2 Underpower Logic 264
3.3 Application Notes 264
3.3.1 Low Forward Power Considerations 264
3.3.2 Low Forward Power Setting Guidelines 264
4 Sensitive Power Protection 266
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4.1 Sensitive Power Protection Implementation 266
4.2 Sensitive Power Measurements 266
4.3 Sensitive Power Logic 267
4.4 Application Notes 267
4.4.1 Sensitive Power Calculation 267
4.4.2 Sensitive Power Setting Guidelines 269
5 Transient Earth Fault Detection 270
5.1 Transient Earth Fault Detection Implementation 271
5.1.1 Transient Earth Fault Detector 271
5.1.2 Fault Type Detector 271
5.1.3 Direction Detector 271
5.2 Transient Earth Fault Detection Logic 272
5.2.1 Transient Earth Fault Detection Logic Overview 272
5.2.2 Fault Type Detector Logic 273
5.2.3 Direction Detector Logic - Standard Mode 273
5.2.4 Transient Earth Fault Detection Output Alarm Logic 273
Chapter 13 Autoreclose 275
1 Chapter Overview 277 2 Introduction to 3-phase Autoreclose 278 3 Implementation 279 4 Autoreclose Function Inputs 280
4.1 CB Healthy 280
4.2 Block AR 280
4.3 Reset Lockout 280
4.4 AR Auto Mode 280
4.5 Auto Mode 280
4.6 LiveLine Mode 280
4.7 Telecontrol Mode 280
4.8 Circuits OK 280
4.9 AR Sys Checks OK (403) 281
4.10 Ext AR Prot Trip (External AR Protection Trip) 281
4.11 Ext AR Prot Start (External AR Protection Start) 281
4.12 DAR Complete (Delayed Autoreclose Complete) 281
4.13 CB in Service (Circuit Breaker in Service) 281
4.14 AR Restart 281
4.15 DT OK To Start (Dead Time OK to Start) 281
4.16 DeadTime Enabled 282
4.17 AR Init TripTest (Initiate Trip Test) 282
4.18 AR Skip Shot 1 282
4.19 Inh Reclaim Time (Inhibit Reclaim Time) 282
5 Autoreclose Function Outputs 283
5.1 AR In Progress 283
5.2 AR in Progress 1 (DAR In Progress) 283
5.3 Sequence Counter Status DDB signals 283
5.4 Successful Close 283
5.5 AR In Service 283
5.6 Block Main Prot (Block Main Protection) 283
5.7 Block SEF Prot (Block SEF Protection) 283
5.8 Reclose Checks 283
5.9 DeadT In Prog (Dead Time in Progress) 284
5.10 DT Complete (Dead Time Complete) 284
5.11 AR Sync Check (AR Synchronisation Check) 284
5.12 AR SysChecks OK (AR System Checks OK) 284
5.13 Auto Close 284
5.14 Protection Lockt (Protection Lockout) 284
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5.15 Reset Lckout Alm (Reset Lockout Alarm) 284
5.16 Reclaim In Prog 284
5.17 Reclaim Complete 284
6 Autoreclose Function Alarms 285
6.1 AR No Sys Check 285
6.2 AR CB Unhealthy 285
6.3 AR Lockout 285
7 Autoreclose Operation 286
7.1 Operating Modes 287
7.1.1 Four-Position Selector Switch Implementation 287
7.1.2 Operating Mode Selection Logic 289
7.2 Autoreclose Initiation 289
7.2.1 Start Signal Logic 291
7.2.2 Trip Signal Logic 291
7.2.3 Blocking Signal Logic 292
7.2.4 Shots Exceeded Logic 292
7.2.5 AR Initiation Logic 293
7.3 Blocking Instantaneous Protection for Selected Trips 293
7.4 Blocking Instantaneous Protection for Lockouts 295
7.5 Dead Time Control 296
7.5.1 AR CB Close Control 297
7.6 AR System Checks 298
7.7 Reclaim Timer Initiation 299
7.8 Autoreclose Inhibit 300
7.9 Autoreclose Lockout 301
7.10 Sequence Co-ordination 303
7.11 System Checks for First Reclose 304
8 Setting Guidelines 305
8.1 Number of Shots 305
8.2 Dead Timer Setting 305
8.2.1 Stability and Synchronism Requirements 305
8.2.2 Operational Convenience 305
8.2.3 Load Requirements 306
8.2.4 Circuit Breaker 306
8.2.5 Fault De-ionisation Time 306
8.2.6 Protection Reset Time 306
8.3 Reclaim Timer Setting 307
Chapter 14 Monitoring and Control 309
1 Chapter Overview 311 2 Event Records 312
2.1 Event Types 312
2.1.1 Opto-input Events 313
2.1.2 Contact Events 313
2.1.3 Alarm Events 313
2.1.4 Fault Record Events 314
2.1.5 Maintenance Events 314
2.1.6 Protection Events 314
2.1.7 Security Events 315
2.1.8 Platform Events 315
3 Disturbance Recorder 316 4 Measurements 317
4.1 Measured Quantities 317
4.1.1 Measured and Calculated Currents 317
4.1.2 Measured and Calculated Voltages 317
4.1.3 Power and Energy Quantities 317
4.1.4 Demand Values 318
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4.1.5 Frequency Measurements 318
4.1.6 Other Measurements 318
4.2 Measurement Setup 318
4.3 Fault Locator 319
4.3.1 Fault Locator Settings Example 319
4.4 Opto-input Time Stamping 319
5 CB Condition Monitoring 320
5.1 Application Notes 320
5.1.1 Setting the Thresholds for the Total Broken Current 320
5.1.2 Setting the thresholds for the Number of Operations 320
5.1.3 Setting the thresholds for the Operating Time 321
5.1.4 Setting the Thresholds for Excesssive Fault Frequency 321
6 CB State Monitoring 322
6.1 CB State Monitoring Logic 323
7 Circuit Breaker Control 324
7.1 CB Control using the IED Menu 324
7.2 CB Control using the Hotkeys 325
7.3 CB Control using the Function Keys 325
7.4 CB Control using the Opto-inputs 326
7.5 Remote CB Control 326
7.6 CB Control Logic 328
7.7 Synchronisation Check 328
7.8 CB Healthy Check 328
8 Pole Dead Function 329
8.1 Pole Dead Logic 329
9 System Checks 330
9.1 System Checks Implementation 330
9.1.1 VT Connections 330
9.1.2 Voltage Monitoring 330
9.1.3 Check Synchronisation 331
9.1.4 Check Syncronisation Vector Diagram 331
9.1.5 System Split 332
9.2 System Check Logic 333
9.3 System Check PSL 334
9.4 Application Notes 334
9.4.1 Slip Control 334
9.4.2 Use of Check Sync 2 and System Split 335
9.4.3 Predictive Closure of Circuit Breaker 335
9.4.4 Voltage and Phase Angle Correction 335
10 Switch Status and Control 337
10.1 Switch Status Logic 338
10.2 Switch Control Logic 339
Chapter 15 Supervision 341
1 Chapter Overview 343 2 Voltage Transformer Supervision 344
2.1 Loss of One or Two Phase Voltages 344
2.2 Loss of all Three Phase Voltages 344
2.3 Absence of all Three Phase Voltages on Line Energisation 344
2.4 VTS Implementation 345
2.5 VTS Logic 345
2.6 VTS Acceleration Indication Logic 347
3 Current Transformer Supervision 348
3.1 CTS Implementation 348
3.2 CTS Logic 348
3.3 Application Notes 349
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3.3.1 Setting Guidelines 349
4 Trip Circuit Supervision 350
4.1 Trip Circuit Supervision Scheme 1 350
4.1.1 Resistor Values 350
4.1.2 PSL for TCS Scheme 1 351
4.2 Trip Circuit Supervision Scheme 2 351
4.2.1 Resistor Values 352
4.2.2 PSL for TCS Scheme 2 352
4.3 Trip Circuit Supervision Scheme 3 352
4.3.1 Resistor Values 353
4.3.2 PSL for TCS Scheme 3 353
Chapter 16 Digital I/O and PSL Configuration 355
1 Chapter Overview 357 2 Configuring Digital Inputs and Outputs 358 3 Scheme Logic 359
3.1 PSL Editor 360
3.2 PSL Schemes 360
3.3 PSL Scheme Version Control 360
4 Configuring the Opto-Inputs 361 5 Assigning the Output Relays 362 6 Fixed Function LEDs 363
6.1 Trip LED Logic 363
7 Configuring Programmable LEDs 364 8 Function Keys 366 9 Control Inputs 367
Chapter 17 Electrical Teleprotection 369
1 Chapter Overview 371 2 Introduction 372 3 Teleprotection Scheme Principles 373
3.1 Direct Tripping 373
3.2 Permissive Tripping 373
4 Implementation 374 5 Configuration 375 6 Connecting to Electrical InterMiCOM 377
6.1 Short Distance 377
6.2 Long Distance 377
7 Application Notes 378
Chapter 18 Communications 381
1 Chapter Overview 383 2 Communication Interfaces 384 3 Serial Communication 385
3.1 EIA(RS)232 Bus 385
3.2 EIA(RS)485 Bus 385
3.2.1 EIA(RS)485 Biasing Requirements 386
3.3 K-Bus 386
4 Standard Ethernet Communication 388
4.1 Hot-Standby Ethernet Failover 388
5 Redundant Ethernet Communication 389
5.1 Supported Protocols 389
5.2 Parallel Redundancy Protocol 390
5.2.1 PRP Application in the Substation 391
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5.3 High-Availability Seamless Redundancy (HSR) 391
5.3.1 HSR Multicast Topology 391
5.3.2 HSR Unicast Topology 392
5.3.3 HSR Application in the Substation 393
5.4 Rapid Spanning Tree Protocol 394
5.5 Self Healing Protocol 395
5.6 Dual Homing Protocol 396
5.7 Configuring IP Addresses 398
5.7.1 Configuring the IED IP Address 399
5.7.2 Configuring the REB IP Address 399
6 Simple Network Management Protocol (SNMP) 403
6.1 SNMP Management Information Bases 403
6.2 Main Processor MIBS Structure 403
6.3 Redundant Ethernet Board MIB Structure 404
6.4 Accessing the MIB 408
6.5 Main Processor SNMP Configuration 408
7 Data Protocols 410
7.1 Courier 410
7.1.1 Physical Connection and Link Layer 410
7.1.2 Courier Database 411
7.1.3 Settings Categories 411
7.1.4 Setting Changes 411
7.1.5 Event Extraction 411
7.1.6 Disturbance Record Extraction 413
7.1.7 Programmable Scheme Logic Settings 413
7.1.8 Time Synchronisation 413
7.1.9 Courier Configuration 414
7.2 IEC 60870-5-103 415
7.2.1 Physical Connection and Link Layer 415
7.2.2 Initialisation 416
7.2.3 Time Synchronisation 416
7.2.4 Spontaneous Events 416
7.2.5 General Interrogation (GI) 416
7.2.6 Cyclic Measurements 416
7.2.7 Commands 416
7.2.8 Test Mode 417
7.2.9 Disturbance Records 417
7.2.10 Command/Monitor Blocking 417
7.2.11 IEC 60870-5-103 Configuration 417
7.3 DNP 3.0 418
7.3.1 Physical Connection and Link Layer 419
7.3.2 Object 1 Binary Inputs 419
7.3.3 Object 10 Binary Outputs 419
7.3.4 Object 20 Binary Counters 420
7.3.5 Object 30 Analogue Input 420
7.3.6 Object 40 Analogue Output 421
7.3.7 Object 50 Time Synchronisation 421
7.3.8 DNP3 Device Profile 421
7.3.9 DNP3 Configuration 429
7.4 MODBUS 430
7.4.1 Physical Connection and Link Layer 431
7.4.2 MODBUS Functions 431
7.4.3 Response Codes 431
7.4.4 Register Mapping 432
7.4.5 Event Extraction 432
7.4.6 Disturbance Record Extraction 433
7.4.7 Setting Changes 441
7.4.8 Password Protection 441
7.4.9 Protection and Disturbance Recorder Settings 441
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7.4.10 Time Synchronisation 442
7.4.11 Power and Energy Measurement Data Formats 443
7.4.12 MODBUS Configuration 444
7.5 IEC 61850 445
7.5.1 Benefits of IEC 61850 445
7.5.2 IEC 61850 Interoperability 446
7.5.3 The IEC 61850 Data Model 446
7.5.4 IEC 61850 in MiCOM IEDs 447
7.5.5 IEC 61850 Data Model Implementation 447
7.5.6 IEC 61850 Communication Services Implementation 447
7.5.7 IEC 61850 Peer-to-peer (GOOSE) communications 448
7.5.8 Mapping GOOSE Messages to Virtual Inputs 448
7.5.9 Ethernet Functionality 448
7.5.10 IEC 61850 Configuration 448
8 Read Only Mode 450
8.1 IEC 60870-5-103 Protocol Blocking 450
8.2 Courier Protocol Blocking 450
8.3 IEC 61850 Protocol Blocking 451
8.4 Read-Only Settings 451
8.5 Read-Only DDB Signals 451
9 Time Synchronisation 452
9.1 Demodulated IRIG-B 452
9.1.1 IRIG-B Implementation 453
9.2 SNTP 453
9.2.1 Loss of SNTP Server Signal Alarm 453
9.3 IEEE 1588 Precision time Protocol 453
9.3.1 Accuracy and Delay Calculation 453
9.3.2 PTP Domains 454
9.4 Time Synchronsiation using the Communication Protocols 454
Chapter 19 Cyber-Security 455
1 Overview 457 2 The Need for Cyber-Security 458 3 Standards 459
3.1 NERC Compliance 459
3.1.1 CIP 002 460
3.1.2 CIP 003 460
3.1.3 CIP 004 460
3.1.4 CIP 005 460
3.1.5 CIP 006 460
3.1.6 CIP 007 461
3.1.7 CIP 008 461
3.1.8 CIP 009 461
3.2 IEEE 1686-2007 461
4 Cyber-Security Implementation 463
4.1 NERC-Compliant Display 463
4.2 Four-level Access 464
4.2.1 Blank Passwords 465
4.2.2 Password Rules 465
4.2.3 Access Level DDBs 466
4.3 Enhanced Password Security 466
4.3.1 Password Strengthening 466
4.3.2 Password Validation 466
4.3.3 Password Blocking 467
4.4 Password Recovery 468
4.4.1 Password Recovery 468
4.4.2 Password Encryption 469
P14xEd1-TM-EN-1 xiii
Contents P14x
4.5 Disabling Physical Ports 469
4.6 Disabling Logical Ports 469
4.7 Security Events Management 470
4.8 Logging Out 472
Chapter 20 Installation 473
1 Chapter Overview 475 2 Handling the Goods 476
2.1 Receipt of the Goods 476
2.2 Unpacking the Goods 476
2.3 Storing the Goods 476
2.4 Dismantling the Goods 476
3 Mounting the Device 477
3.1 Flush Panel Mounting 477
3.2 Rack Mounting 478
4 Cables and Connectors 480
4.1 Terminal Blocks 480
4.2 Power Supply Connections 481
4.3 Earth Connnection 481
4.4 Current Transformers 481
4.5 Voltage Transformer Connections 482
4.6 Watchdog Connections 482
4.7 EIA(RS)485 and K-Bus Connections 482
4.8 IRIG-B Connection 482
4.9 Opto-input Connections 482
4.10 Output Relay Connections 482
4.11 Ethernet Metallic Connections 483
4.12 Ethernet Fibre Connections 483
4.13 RS232 connection 483
4.14 Download/Monitor Port 483
4.15 GPS Fibre Connection 483
4.16 Fibre Communication Connections 483
5 Case Dimensions 484
5.1 Case Dimensions 40TE 484
5.2 Case Dimensions 60TE 485
5.3 Case Dimensions 80TE 486
Chapter 21 Commissioning Instructions 487
1 Chapter Overview 489 2 General Guidelines 490 3 Commissioning Test Menu 491
3.1 Opto I/P Status Cell (Opto-input Status) 491
3.2 Relay O/P Status Cell (Relay Output Status) 491
3.3 Test Port Status Cell 491
3.4 Monitor Bit 1 to 8 Cells 491
3.5 Test Mode Cell 492
3.6 Test Pattern Cell 492
3.7 Contact Test Cell 492
3.8 Test LEDs Cell 492
3.9 Test Autoreclose Cell 492
3.10 Red and Green LED Status Cells 493
3.11 Using a Monitor Port Test Box 493
4 Commissioning Equipment 494
4.1 Recommended Commissioning Equipment 494
xiv P14xEd1-TM-EN-1
P14x Contents
4.2 Essential Commissioning Equipment 494
4.3 Advisory Test Equipment 495
5 Product Checks 496
5.1 Product Checks with the IED De-energised 496
5.1.1 Visual Inspection 497
5.1.2 Current Transformer Shorting Contacts 497
5.1.3 Insulation 497
5.1.4 External Wiring 497
5.1.5 Watchdog Contacts 498
5.1.6 Power Supply 498
5.2 Product Checks with the IED Energised 498
5.2.1 Watchdog Contacts 498
5.2.2 Test LCD 499
5.2.3 Date and Time 499
5.2.4 Test LEDs 500
5.2.5 Test Alarm and Out-of-Service LEDs 500
5.2.6 Test Trip LED 500
5.2.7 Test User-programmable LEDs 500
5.2.8 Test Opto-inputs 500
5.2.9 Test Output Relays 500
5.2.10 Test Serial Communication Port RP1 501
5.2.11 Test Serial Communication Port RP2 502
5.2.12 Test Ethernet Communication 502
5.3 Secondary Injection Tests 503
5.3.1 Test Current Inputs 503
5.3.2 Test Voltage Inputs 503
6 Setting Checks 505
6.1 Apply Application-specific Settings 505
6.1.1 Transferring Settings from a Settings File 505
6.1.2 Entering settings using the HMI 505
7 Protection Timing Checks 507
7.1 Overcurrent Check 507
7.2 Connecting the Test Circuit 507
7.3 Performing the Test 507
7.4 Check the Operating Time 507
8 Onload Checks 509
8.1 Confirm Current Connections 509
8.2 Confirm Voltage Connections 509
8.3 On-load Directional Test 510
9 Final Checks 511
Chapter 22 Maintenance and Troubleshooting 513
1 Chapter Overview 515 2 Maintenance 516
2.1 Maintenance Checks 516
2.1.1 Alarms 516
2.1.2 Opto-isolators 516
2.1.3 Output Relays 516
2.1.4 Measurement Accuracy 516
2.2 Replacing the Device 517
2.3 Repairing the Device 518
2.4 Removing the front panel 518
2.5 Replacing PCBs 519
2.5.1 Replacing the main processor board 519
2.5.2 Replacement of communications boards 520
2.5.3 Replacement of the input module 521
2.5.4 Replacement of the power supply board 521
P14xEd1-TM-EN-1 xv
Contents P14x
2.5.5 Replacement of the I/O boards 522
2.6 Recalibration 522
2.7 Changing the battery 522
2.7.1 Post Modification Tests 523
2.7.2 Battery Disposal 523
2.8 Cleaning 523
3 Troubleshooting 524
3.1 Self-Diagnostic Software 524
3.2 Power-up Errors 524
3.3 Error Message or Code on Power-up 524
3.4 Out of Service LED on at power-up 525
3.5 Error Code during Operation 526
3.5.1 Backup Battery 526
3.6 Mal-operation during testing 526
3.6.1 Failure of Output Contacts 526
3.6.2 Failure of Opto-inputs 526
3.6.3 Incorrect Analogue Signals 527
3.7 PSL Editor Troubleshooting 527
3.7.1 Diagram Reconstruction 527
3.7.2 PSL Version Check 527
4 Repair and Modification Procedure 528
Chapter 23 Technical Specifications 529
1 Chapter Overview 531 2 Interfaces 532
2.1 Front Serial Port 532
2.2 Download/Monitor Port 532
2.3 Rear Serial Port 1 532
2.4 Fibre Rear Serial Port 1 532
2.5 Rear Serial Port 2 533
2.6 Optional Rear Serial Port (SK5) 533
2.7 IRIG-B (Demodulated) 533
2.8 IRIG-B (Modulated) 533
2.9 Rear Ethernet Port Copper 534
2.10 Rear Ethernet Port Fibre 534
2.10.1 100 Base FX Receiver Characteristics 534
2.10.2 100 Base FX Transmitter Characteristics 535
3 Performance of Current Protection Functions 536
3.1 Transient Overreach and Overshoot 536
3.2 Phase Overcurrent Protection 536
3.2.1 Phase Overcurrent Directional Parameters 536
3.3 Voltage Dependent Overcurrent Protection 536
3.4 Earth Fault Protection 537
3.4.1 Earth Fault Directional Parameters 537
3.5 Sensitive Earth Fault Protection 538
3.5.1 SEF Directional Parameters 538
3.6 Restricted Earth Fault Protection 538
3.7 Negative Sequence Overcurrent Protection 539
3.7.1 NPSOC Directional Parameters 539
3.8 Circuit Breaker Fail and Undercurrent Protection 539
3.9 Broken Conductor Protection 539
3.10 Thermal Overload Protection 539
3.11 Cold Load Pickup Protection 540
3.12 Selective Overcurrent Protection 540
3.13 Voltage Dependent Overcurrent Protection 540
3.14 Neutral Admittance Protection 540
xvi P14xEd1-TM-EN-1
P14x Contents
4 Performance of Voltage Protection Functions 541
4.1 Undervoltage Protection 541
4.2 Overvoltage Protection 541
4.3 Residual Overvoltage Protection 541
4.4 Negative Sequence Voltage Protection 541
4.5 Rate of Change of Voltage Protection 542
5 Performance of Frequency Protection Functions 543
5.1 Basic Overfrequency Protection 543
5.2 Basic Underfrequency Protection 543
5.3 Advanced Overfrequency Protection 543
5.4 Advanced Underfrequency Protection 544
5.5 Supervised Rate of Change of Frequency Protection 544
5.6 Independent Rate of Change of Frequency Protection 544
5.7 Average Rate of Change of Frequency Protection 545
5.8 Load Restoration 545
6 Power Protection Functions 546
6.1 Overpower / Underpower Protection 546
6.2 Sensitive Power Protection 546
7 Performance of Monitoring and Control Functions 547
7.1 Voltage Transformer Supervision 547
7.2 Standard Current Transformer Supervision 547
7.3 CB State and Condition Monitoring 547
7.4 PSL Timers 547
8 Measurements and Recording 548
8.1 General 548
8.2 Disturbance Records 548
8.3 Event, Fault and Maintenance Records 548
8.4 Fault Locator 548
9 Ratings 549
9.1 AC Measuring Inputs 549
9.2 Current Transformer Inputs 549
9.3 Voltage Transformer Inputs 549
9.4 Auxiliary Supply Voltage 549
9.5 Nominal Burden 550
9.6 Power Supply Interruption 550
9.7 Battery Backup 551
10 Input / Output Connections 552
10.1 Isolated Digital Inputs 552
10.2 Nominal Pickup and Reset Thresholds 552
10.3 Standard Output Contacts 552
10.4 High Break Output Contacts 553
10.5 Watchdog Contacts 553
11 Mechanical Specifications 554
11.1 Physical Parameters 554
11.2 Enclosure Protection 554
11.3 Mechanical Robustness 554
11.4 Transit Packaging Performance 554
12 Type Tests 555
12.1 Insulation 555
12.2 Creepage Distances and Clearances 555
12.3 High Voltage (Dielectric) Withstand 555
12.4 Impulse Voltage Withstand Test 555
13 Environmental Conditions 556
13.1 Ambient Temperature Range 556
13.2 Temperature Endurance Test 556
13.3 Ambient Humidity Range 556
P14xEd1-TM-EN-1 xvii
Contents P14x
13.4 Corrosive Environments 556
14 Electromagnetic Compatibility 557
14.1 1 MHz Burst High Frequency Disturbance Test 557
14.2 Damped Oscillatory Test 557
14.3 Immunity to Electrostatic Discharge 557
14.4 Electrical Fast Transient or Burst Requirements 557
14.5 Surge Withstand Capability 557
14.6 Surge Immunity Test 558
14.7 Immunity to Radiated Electromagnetic Energy 558
14.8 Radiated Immunity from Digital Communications 558
14.9 Radiated Immunity from Digital Radio Telephones 558
14.10 Immunity to Conducted Disturbances Induced by Radio Frequency Fields 558
14.11 Magnetic Field Immunity 559
14.12 Conducted Emissions 559
14.13 Radiated Emissions 559
14.14 Power Frequency 559
15 Regulatory Compliance 560
15.1 EMC Compliance: 2014/30/EU 560
15.2 LVD Compliance: 2014/35/EU 560
15.3 R&TTE Compliance: 2014/53/EU 560
15.4 UL/CUL Compliance 560
15.5 ATEX Compliance: 2014/34/EU 560
Appendix A Ordering Options 563
Appendix B Settings and Signals 565
Appendix C Wiring Diagrams 567
xviii P14xEd1-TM-EN-1
Table of Figures
Figure 1: Functional Overview 11 Figure 2: Hardware architecture 30 Figure 3: Exploded view of IED 31 Figure 4: Front panel (60TE) 33 Figure 5: HMI panel 34 Figure 6: Rear view of populated case 37 Figure 7: Terminal block types 38 Figure 8: Rear connection to terminal block 39 Figure 9: Main processor board 40 Figure 10: Power supply board 41 Figure 11: Power supply assembly 42 Figure 12: Power supply terminals 43 Figure 13: Watchdog contact terminals 44 Figure 14: Rear serial port terminals 45 Figure 15: Input module - 1 transformer board 45 Figure 16: Input module schematic 46 Figure 17: Transformer board 47 Figure 18: Input board 48 Figure 19: Standard output relay board - 8 contacts 49 Figure 20: IRIG-B board 50 Figure 21: Fibre optic board 51 Figure 22: Rear communication board 52 Figure 23: Ethernet board 52 Figure 24: Redundant Ethernet board 54 Figure 25: Software Architecture 60 Figure 26: Frequency Response (indicative only) 65 Figure 27: Navigating the HMI 72 Figure 28: Default display navigation 74 Figure 29: IEC 60255 IDMT curves 91 Figure 30: IEC standard and very inverse curves 94 Figure 31: IEC Extremely inverse and IEEE moderate inverse curves 94 Figure 32: IEEE very and extremely inverse curves 95 Figure 33: Principle of protection function implementation 96 Figure 34: Non-directional Overcurrent Logic diagram 99 Figure 35: Directional Overcurrent Logic diagram (Phase A shown only) 101 Figure 36: Typical distribution system using parallel transformers 102 Figure 37: Typical ring main with associated overcurrent protection 103 Figure 38: Modification of current pickup level for voltage controlled overcurrent protection 105
Table of Figures P14x
Figure 39: Modification of current pickup level for voltage restrained overcurrent protection 106 Figure 40: Voltage dependant overcurrent logic (Phase A to phase B) 107 Figure 41: Selecting the current threshold setting 109 Figure 42: Cold Load Pickup logic 111 Figure 43: Selective Logic 113 Figure 44: Selecting the timer settings 115 Figure 45: Negative Sequence Overcurrent logic - non-directional operation 117 Figure 46: Composite Earth Fault Start Logic 117 Figure 47: Negative Sequence Overcurrent logic - directional operation 118 Figure 48: Non-directional EF logic (single stage) 121 Figure 49: IDG Characteristic 122 Figure 50: Directional EF logic with neutral voltage polarization (single stage) 123 Figure 51: Directional Earth Fault logic with negative sequence polarisation (single stage) 124 Figure 52: Current level (amps) at which transient faults are self-extinguishing 125 Figure 53: Earth fault in Petersen Coil earthed system 125 Figure 54: Distribution of currents during a Phase C fault 126 Figure 55: Phasors for a phase C earth fault in a Petersen Coil earthed system 126 Figure 56: Zero sequence network showing residual currents 127 Figure 57: Phase C earth fault in Petersen Coil earthed system: practical case with resistance
esent
pr
e 58: Non-directional SEF logic 130
Figur
128
Figure 59: SEF Any Start Logic 131 Figure 60: EPATR B characteristic shown for TMS = 1.0 132 Figure 61: Types of directional control 132 Figure 62: Resistive components of spill current 133 Figure 63: Operating characteristic for Icos 134 Figure 64: Directional SEF with VN polarisation (single stage) 135 Figure 65: Current distribution in an insulated system with C phase fault 136 Figure 66: Phasor diagrams for insulated system with C phase fault 137 Figure 67: Positioning of core balance current transformers 138 Figure 68: Thermal overload protection logic diagram 140 Figure 69: Spreadsheet calculation for dual time constant thermal characteristic 141 Figure 70: Dual time constant thermal characteristic 141 Figure 71: Broken conductor logic 144 Figure 72: Blocked Overcurrent logic 146 Figure 73: Blocked Earth Fault logic 147 Figure 74: Simple busbar blocking scheme 147 Figure 75: Simple busbar blocking scheme characteristics 148 Figure 76: 2nd Harmonic Blocking Logic (POC Input) 150 Figure 77: 2nd Harmonic Blocking Logic (SEF Input) 151
xx P14xEd1-TM-EN-1
P14x Table of Figures
Figure 78: Load blinder and angle 152 Figure 79: Load Blinder logic 3phase 153 Figure 80: Load Blinder logic phase A 154 Figure 81: Admittance protection 156 Figure 82: Conductance operation 157 Figure 83: Susceptance operation 157 Figure 84: Simplified busbar representation 159 Figure 85: High Impedance differential protection for busbars 160 Figure 86: REF protection for delta side 164 Figure 87: REF protection for star side 164 Figure 88: REF Protection for resistance-earthed systems 165 Figure 89: REF Protection for solidly earthed system 166 Figure 90: Low Impedance REF Connection 167 Figure 91: Three-slope REF bias characteristic 168 Figure 92: High Impedance REF principle 169 Figure 93: High Impedance REF Connection 170 Figure 94: REF bias characteristic 172 Figure 95: Star winding, resistance earthed 174 Figure 96: Percentage of winding protected 175 Figure 97: Low Impedance REF Scaling Factor 176 Figure 98: Hi-Z REF protection for a grounded star winding 177 Figure 99: Hi-Z REF protection for a delta winding 177 Figure 100: Hi-Z REF Protection for autotransformer configuration 178 Figure 101: High Impedance REF for the LV winding 179 Figure 102: Circuit Breaker Fail logic - three phase start 187 Figure 103: Circuit Breaker Fail logic - single phase start 188 Figure 104: Circuit Breaker Fail Trip and Alarm 189 Figure 105: Undercurrent and Zero Crossing Detection Logic for CB Fail 190 Figure 106: CB Fail SEF Protection Logic 191 Figure 107: CB Fail Non Current Protection Logic 192 Figure 108: Circuit Breaker mapping 193 Figure 109: CB Fail timing 195 Figure 110: Undervoltage - single and three phase tripping mode (single stage) 211 Figure 111: Overvoltage - single and three phase tripping mode (single stage) 214 Figure 112: Rate of Change of Voltage protection logic 216 Figure 113: Residual Overvoltage logic 219 Figure 114: Residual voltage for a solidly earthed system 220 Figure 115: Residual voltage for an impedance earthed system 221 Figure 116: Star connected condenser bushings 222 Figure 117: Theoretical earth fault in condenser bushing system 222
P14xEd1-TM-EN-1 xxi
Table of Figures P14x
Figure 118: Condenser bushing system vectors 223 Figure 119: Device connection with resistors and shorting contact 224 Figure 120: Device connection P141/ P142/ P143/ P145 226 Figure 121: Device connection P144 226 Figure 122: Negative Sequence Overvoltage logic 228 Figure 123: Sensitive Overvoltage operation logic 231 Figure 124: Sensitive Overvoltage filter mode logic 232 Figure 125: Sensitive Overvoltage blocking logic 232 Figure 126: Underfrequency logic (single stage) 238 Figure 127: Overfrequency logic (single stage) 240 Figure 128: Power system segregation based upon frequency measurements 241 Figure 129: Independent rate of change of frequency logic (single stage) 243 Figure 130: Frequency-supervised rate of change of frequency logic (single stage) 246 Figure 131: Frequency supervised rate of change of frequency protection 247 Figure 132: Average rate of change of frequency characteristic 248 Figure 133: Average rate of change of frequency logic (single stage) 249 Figure 134: Load restoration with short deviation into holding band 252 Figure 135: Load restoration with long deviation into holding band 253 Figure 136: Load Restoration logic 254 Figure 137: Overpower logic 261 Figure 138: Underpower logic 264 Figure 139: Sensitive Power logic diagram 267 Figure 140: Sensitive Power input vectors 268 Figure 141: Transient Earth Fault Logic Overview 272 Figure 142: Fault Type Detector Logic 273 Figure 143: Direction Detector Logic - Standard Mode 273 Figure 144: TEFD output alarm logic 273 Figure 145: Four-position selector switch implementation 288 Figure 146: Autoreclose mode select logic 289 Figure 147: Start signal logic 291 Figure 148: Trip signal logic 291 Figure 149: Blocking signal logic 292 Figure 150: Shots Exceeded logic 292 Figure 151: AR initiation logic 293 Figure 152: Blocking instantaneous protection for selected trips 294 Figure 153: Blocking instantaneous protection for lockouts 296 Figure 154: Dead Time Control logic 297 Figure 155: AR CB Close Control logic 298 Figure 156: AR System Check logic 299 Figure 157: Reclaim Time logic 300
xxii P14xEd1-TM-EN-1
P14x Table of Figures
Figure 158: AR Initiation inhibit 301 Figure 159: Overall Lockout logic 302 Figure 160: Lockout for protection trip when AR is not available 303 Figure 161: Fault recorder stop conditions 314 Figure 162: CB State Monitoring logic 323 Figure 163: Hotkey menu navigation 325 Figure 164: Default function key PSL 326 Figure 165: Remote Control of Circuit Breaker 327 Figure 166: CB Control logic 328 Figure 167: Pole Dead logic 329 Figure 168: Check Synchronisation vector diagram 332 Figure 169: System Check logic 333 Figure 170: System Check PSL 334 Figure 171: Representation of typical feeder bay 337 Figure 172: Switch Status logic 338 Figure 173: Switch Control logic 339 Figure 174: VTS logic 346 Figure 175: VTS Acceleration Indication Logic 347 Figure 176: CTS logic diagram 348 Figure 177: TCS Scheme 1 350 Figure 178: PSL for TCS Scheme 1 351 Figure 179: TCS Scheme 2 352 Figure 180: PSL for TCS Scheme 2 352 Figure 181: TCS Scheme 3 353 Figure 182: PSL for TCS Scheme 3 353 Figure 183: Scheme Logic Interfaces 359 Figure 184: Trip LED logic 363 Figure 185: Example assignment of InterMiCOM signals within the PSL 376 Figure 186: Direct connection 377 Figure 187: Indirect connection using modems 377 Figure 188: RS485 biasing circuit 386 Figure 189: Remote communication using K-Bus 387 Figure 190: IED attached to separate LANs 390 Figure 191: PRP application in the substation 391 Figure 192: HSR multicast topology 392 Figure 193: HSR unicast topology 393 Figure 194: HSR application in the substation 394 Figure 195: IED attached to redundant Ethernet star or ring circuit 394 Figure 196: IED, bay computer and Ethernet switch with self healing ring facilities 395 Figure 197: Redundant Ethernet ring architecture with IED, bay computer and Ethernet switches 395
P14xEd1-TM-EN-1 xxiii
Table of Figures P14x
Figure 198: Redundant Ethernet ring architecture with IED, bay computer and Ethernet switches
396
after failure
e 199: Dual homing mechanism 397
Figur Figure 200: Application of Dual Homing Star at substation level 398 Figure 201: IED and REB IP address configuration 399 Figure 202: Control input behaviour 420 Figure 203: Manual selection of a disturbance record 436 Figure 204: Automatic selection of disturbance record - method 1 437 Figure 205: Automatic selection of disturbance record - method 2 438 Figure 206: Configuration file extraction 439 Figure 207: Data file extraction 440 Figure 208: Data model layers in IEC61850 446 Figure 209: GPS Satellite timing signal 452 Figure 210: Timing error using ring or line topology 454 Figure 211: Default display navigation 464 Figure 212: Location of battery isolation strip 477 Figure 213: Rack mounting of products 478 Figure 214: Terminal block types 480 Figure 215: 40TE case dimensions 484 Figure 216: 60TE case dimensions 485 Figure 217: 80TE case dimensions 486 Figure 218: RP1 physical connection 501 Figure 219: Remote communication using K-bus 502 Figure 220: Possible terminal block types 518 Figure 221: Front panel assembly 520
xxiv P14xEd1-TM-EN-1
CHAPTER 1

INTRODUCTION

Chapter 1 - Introduction P14x
2 P14xEd1-TM-EN-1
P14x Chapter 1 - Introduction

1 CHAPTER OVERVIEW

This chapter provides some general information about the technical manual and an introduction to the device(s) described in this technical manual.
This chapter contains the following sections: Chapter Overview 3
ord 4
Forew Product Scope 6 Features and Functions 7 Compliance 10 Functional Overview 11
P14xEd1-TM-EN-1 3
Chapter 1 - Introduction P14x

2 FOREWORD

This technical manual provides a functional and technical description of General Electric's P141, P142, P143, P144, P145, as well as a compr assumes that you are already familiar with protection engineering and have experience in this discipline. The description of principles and theory is limited to that which is necessary to understand the product. For further details on general protection engineering theory, we refer you to Alstom's publication NPAG, which is available online or from our contact centre.
We have attempted to make this manual as accurate, comprehensive and user-friendly as possible. However we cannot guarantee that it is free from errors. Nor can we state that it cannot be improved. We would therefore be very pleased to hear from you if you discover any errors, or have any suggestions for improvement. Our policy is to provide the information necessary to help you safely specify, engineer, install, commission, maintain, and eventually dispose of this product. We consider that this manual provides the necessary information, but if you consider that more details are needed, please contact us.
All feedback should be sent to our contact centre via the following URL:
www.gegridsolutions.com/contact
ehensive set of instructions for using the device. The level at which this manual is written

2.1 TARGET AUDIENCE

This manual is aimed towards all professionals charged with installing, commissioning, maintaining, troubleshooting, or operating any of the pr commissioning personnel as well as engineers who will be responsible for operating the product.
The level at which this manual is written assumes that installation and commissioning engineers have knowledge of handling electronic equipment. Also, system and protection engineers have a thorough knowledge of protection systems and associated equipment.
oducts within the specified product range. This includes installation and

2.2 TYPOGRAPHICAL CONVENTIONS

The following typographical conventions are used throughout this manual.
● The names for special keys appear in capital letter
For example: ENTER
● When describing software applications, menu items, buttons, labels etc as they appear on the screen are
written in bold type. For example: Select Save from the file menu.
● Filenames and paths use the courier font
For example: Example\File.text
● Special terminology is written with leading capitals
For example: Sensitive Earth Fault
● If reference is made to the IED's internal settings and signals database, the menu group heading (column)
text is written in upper case italics For example: The SYSTEM DATA column
● If reference is made to the IED's internal settings and signals database, the setting cells and DDB signals are
written in bold italics For example: The Language cell in the SYSTEM DATA column
● If reference is made to the IED's internal settings and signals database, the value of a cell's content is
written in the Courier font For example: The Language cell in the SYSTEM DATA column contains the value English
s.
4 P14xEd1-TM-EN-1
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