Fujitsu MB91319 Series Hardware Manual
FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
CM71-10126-2E
FR60
32-BIT MICROCONTROLLER
MB91319 Series
HARDWARE MANUAL
FR60
32-BIT MICROCONTROLLER
MB91319 Series
HARDWARE MANUAL
FUJITSU LIMITED
PREFACE
■ Objectives and Intended Reader
The MB91319 is a standard single-chip microcontroller that has a 32-bit high-performance RISC
CPU as well as built-in I/O resources for embedded controller that requires high-performance
and high-speed CPU processing.
The MB91319 is most suitable for embedded applications, such as TV and PDP controllers, that
require a high level of CPU processing power.
The MB91319 is one of the FR60 series of microcontrollers, which are based on the FR30/40
family of CPUs. It has enhanced bus access and is optimized for high-speed use.
This manual is intended for engineers who will develop products using the MB91319 and
describes the functions and operations of the MB91319. Read this manual thoroughly.
For more information on instructions, see the "Instructions Manual".
■ Trademarks
FR, which is an abbreviation of FUJITSU RISC controller, is a product of Fujitsu Limited.
REALOS (Real-time Operating System) is a trademark of FUJITSU LIMITED.
■ License
The names of other systems and products appearing in this manual are the trademarks of their
respective companies or organizations.
Purchase of Fujitsu I
use, these components in an I
Specification as defined by Philips.
2
C components conveys a license under the Philips I2C Patent Rights to
2
C system provided that the system conforms to the I2C Standard
i
■ Organization of This Manual
This manual consists of the following 20 chapters and an appendix.
CHAPTER 1 "OVERVIEW"
This chapter provides basic information required to understand the MB91319 series, and
covers features, a block diagram, and functions.
CHAPTER 2 "HANDLING THE DEVICE"
This chapter provides precautions on handling the MB91319 series.
CHAPTER 3 "CPU AND CONTROL UNITS"
This chapter provides basic information required to understand the functions of the MB91319
series. It covers architecture, specifications, and instructions.
CHAPTER 4 "I/O PORT"
This chapter describes the I/O ports and the configuration and functions of registers.
CHAPTER 5 "16-BIT RELOAD TIMER"
This chapter describes the 16-bit reload timer, the configuration and functions of registers,
and 16-bit reload timer operation.
CHAPTER 6 "PROGRAMMABLE PULSE GENERATOR (PPG) TIMER"
This chapter gives an outline of the PPG (Programmable Pulse Generator) timer and
explains the register configuration and functions and the timer operations.
CHAPTER 7 "MULTIFUNCTION TIMER"
This chapter gives an overview of the multifunction timer and explains the register
configuration and functions and the timer operat ion.
CHAPTER 8 "16-BIT PULSE WIDTH COUNTER"
This chapter gives an overview of the 16-bit pulse width counter and explains the register
configuration and functions and the counter operation.
CHAPTER 9 "INTERRUPT CONTROLLER"
This chapter describes the interrupt controller, the configuration and functions of registers,
and interrupt controller operation. It also presents an example of using the hold request
cancellation request function.
CHAPTER 10 "EXTERNAL INTERRUPT AND NMI CONTROLLER"
This chapter describes the external interrupt and NMI controller, the configuration and
functions of registers, and operation of the external interrupt and NMI controller.
CHAPTER 11 "REALOS-RELATED HARDWARE"
This chapter explains the delayed interrupt module and bit search module that are REALOSrelated hardware. REALOS-related hardware is used by the real-time OS. When REALOS is
used, the hardware cannot be used with the user program.
CHAPTER 12 "10-BIT A/D CONVERTER"
This chapter gives an overview of the 10-bit A/D converter, register configuration and
functions, and 10-bit A/D converter oper at ion .
CHAPTER 13 "U-TIMER"
This chapter describes the U-TIMER, the configuration and functions of registers, and UTIMER operation.
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CHAPTER 14 "UART"
This chapter describes the UART, the configuration and functions of registers, and UART
operation.
CHAPTER 15 "I
This chapter describes the I
2
C INTERFACE"
2
C interface, the configuration and functions of registers, and I2C
interface operation.
CHAPTER 16 "DMA CONTROLLER (DMAC)"
This chapter describes the DMA controller (DMAC), the configuration and functions of
registers, and DMAC operation.
CHAPTER 17 "USB FUNCTION"
This chapter gives an overview of the USB function, register configuration and functions,
operation of the USB function, and supplement ary notes on the USB function.
CHAPTER 18 "OSDC"
This chapter explains the features, block diagram, display function, control function, and
display control command of the on-screen display controller ( OSDC).
CHAPTER 19 "FLASH MEMORY"
This chapter provides an outline of flash memory and explains its register configuration,
register functions, and operations.
CHAPTER 20 "SERIAL PROGRAMMING CONNECTION"
The built-in FLASH product supports the serial onboard writing (Fujitsu standard) of the flash
ROM. The following explains its specification.
APPENDIX
This appendix consists of the following parts: the I/O map, interrupt vector, dot clock
generation PLL, USB clock, external bus interface setting, and instruction lists. The appendix
contains detailed information that could not be included in the main text and reference
material for programming.
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• The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are
presented solely for the purpose of reference to show examples of operations and uses of FUJITSU
semiconductor device; FUJITSU does not warrant proper operation of the device with respect to use based
on such information. When you develop equipment incorporating the device based on such information, you
must assume any responsibility arising out of such use of the information. FUJITSU a ssumes no liability for
any damages whatsoever arising out of the use of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be
construed as license of the use or exercise of any intellectual property right, such as patent right or
copyright, or any other right of FUJITSU or any third party or does FUJITSU warrant non-in fringement of any
third-party's intellectual property right or other right by using such information. FUJITSU assumes no liability
for any infringement of the intellectual property rights or othe r rights of third parties which would result fro m
the use of information contained herein.
• The products described in this document are designed, developed and manufactured as contemplated fo r
general use, including without limitation, ordinary industrial use, general office use, personal use, and
household use, but are not designed, developed and manufactured as contemplated (1) for use
accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious
effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high
reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU will not be liable against you and/or any third party for any claims or d amages
arising in connection with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage o r
loss from such failures by incorporating safety design measures into your facility and equipment such as
redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.
• If any products described in this document represent goods or technolog ies subject to certain restrictions on
export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japa nese
government will be required for export of those products from Japan.
©2006 FUJITSU LIMITED Printed in Japan
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READING THIS MANUAL
■ Terms Used in This Manual
The following defines principal terms used in this manual.
Term Meaning
32-bit bus for internal instructions. In the FR family, which is based on an
I-bus
D-bus Internal 32-bit data bus. An internal resource is conn ected to the D-bus.
F-bus
internal Harvard architecture, independent buses are used for instructions and
data. A bus converter is connected to the I-bus.
Princeton bus on which internal instructio ns and da ta are multiple xed. Th e F-bu s
is connected via a switch to the I-bus and D-bus. Built-in resources such as
ROM and RAM are connected to the F-bus.
X-bus
R-bus
E-unit Execution unit for operations.
CLKP
CLKB
CLKT
External interface bus. An external interface module is conn ected to the X-bus.
Data and instructions are multiplexed on the external data bus.
Internal 16-bit data bus. The R-bus is connected to the D-bus via an adapter. I/
O, a clock generator, and an interrupt controller are connected to the R-bus.
Since addresses and data are multiplexed on an R-bus that is only 16 bits wide,
more than one cycle is required for the CPU to access these resources.
System clock. Clock generated by the clock generator for each of the internal
resources connected to the R-bus. This clock has the same frequency as the
source oscillation at its maximum, but becomes a 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7,...
or 1/16 (or 1/2, 1/4, 1/6, ... or 1/32) frequency clock as determined by the divideby rate specified by the B3 to B0 bits in the clock generator DIV0 register.
System clock. Operating clock for the CPU and each of the other resources
connected to a bus other than the R-bus and X-bus. This clock has the same
frequency as the source oscillation at its maximum, but becomes a 1, 1/2, 1/3, 1/
4, 1/5, 1/6, 1/7, ... or 1/16 (or 1/2, 1/4, 1/6, ... or 1/32) frequency clock as
determined by the divided-by rate specified by the P3 to P0 bits in the clock
generator DIV0 register.
System clock. Operating clock for the external bus interface connected to the Xbus. This clock has the same frequency as the source oscillation at its
maximum, but becomes a 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, ... or 1/16 (or 1/2, 1/4, 1/
6, ... or 1/32) frequency clock as determined by the divide-by rate specified by
the T3 to T0 bits in the clock generator DIV1 register.
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CONTENTS
CHAPTER 1 OVERVIEW ................................................................................................... 1
1.1 Featu res ..... ......... .......... .......... .......... ...... .......... ......... .......... .......... ......... .......... ....... ........................... 2
1.2 Block Diagram .................................................................................................................................... 7
1.3 External Dimensions ........................................................................................................................... 8
1.4 Pin Layout ........................................................................................................................................... 9
1.5 List of Pin Fun ctio ns .................. ... .... ... ... ... ....................................... ... ... .... ...................................... 10
1.6 Input-output Circuit Forms ................................................................................................................ 17
CHAPTER 2 HANDLING THE DEVICE .......................................................................... 23
2.1 Precautions on Handling the Device ................................................................................................. 24
CHAPTER 3 CPU AND CONTROL UNITS ..................................................................... 29
3.1 Memo ry Spa ce .............................. .... ... ....................................... ... ... ................................................ 30
3.2 Intern al Arc hite ct ur e ................................ ....................................... ... ... ... .......................................... 31
3.3 Programming Model ......................................................................................................................... 36
3.4 Data Configuration ............................................................................................................................ 43
3.5 Word Alignment ................................................................................................................................ 44
3.6 Memo ry Ma p . ... ... .... ...................................... .... ...................................... .... ... ................................... 45
3.7 Branch Instructions ........................................................................................................................... 46
3.8 EIT (Exception, Interrupt, and Trap) ................................................................................................. 49
3.8.1 EIT Interrupt Levels ..................................... ...................................... .... ... ... ................................ 50
3.8.2 Interrupt Control Unit (ICR) .......................................................................................................... 52
3.8.3 System Stack Pointer (SSP) .................................................................. ... ... ... ............................. 53
3.8.4 Table Base Register (TBR) ......................................................................................................... 54
3.8.5 Multiple EIT Processing ............................................................................................................... 58
3.8.6 EIT Operations ........................ .... ... ... ....................................... ... ................................................ 60
3.9 Opera tin g Mo d es ................................................. ... ... .... ... ... ....................................... ... . .................. 64
3.10 Reset (Device Initialization) .............................................................................................................. 67
3.10.1 Reset Levels ............ ....................................... ... ... .... ...................................... .... ... ...................... 68
3.10.2 Reset Sources ....................................................................... ... ... ... ............................................. 69
3.10.3 Reset Sequence ................................ ... ... ....................................... ... .... ... ................................... 71
3.10.4 Oscillation Stabilization Wait Time .............................................................................................. 72
3.10.5 Reset Operation Modes ........................... .... ... ....................................... ... ................................... 74
3.11 Clock Generation Control ................................. ... ... ... ....................................... ... .... ... ...................... 75
3.11.1 PLL Controls ................................................ ... ... ... ....................................... ... .... ... ...................... 76
3.11.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time ...................................................... 78
3.11.3 Clock Distribution ......................................................................................................................... 80
3.11.4 Clock Division .............................................................................................................................. 82
3.11.5 Block Diagram of Clock Generation Controller ...................................... ... ... ................................ 83
3.11.6 Register of Clock Generation Controller ......................................... ... .... ... ................................... 84
3.11.7 Peripheral Circuits of Clock Controller ....................................................................................... 100
3.12 Device State Control ....................................................................................................................... 104
3.12.1 Device States and State Transitions ......................................................................................... 105
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3.12.2 Low-power Modes ..................................................................................................................... 110
3.13 Watch Timer ................................................................................................................................... 114
3.14 Main Clock Oscillation Stabilization Wait Timer .............................................................................. 120
CHAPTER 4 I/O PORT .................................................................................................. 127
4.1 Overview of the I/O Port ................................................................................................................. 128
4.2 I/O Port Registers ........................................................................................................................... 130
CHAPTER 5 16-BIT RELOAD TIMER ........................................................................... 137
5.1 Overview of the 16-bit Reload Timer .............................................................................................. 138
5.2 16-bit Re loa d Timer Re gis ter s ...................... .... ... ... ... ....................................... ... .... ... .................... 139
5.2.1 Control Status Register (TMCSR) ............................................................................................. 140
5.2.2 16-bit Timer Register (TMR) ...................................................................................................... 143
5.2.3 16-bit Reload Register (TMRLR) ............................................................................................... 144
5.3 16-bit Re loa d Timer Op e ratio n ............... ... ... .... ... ... ....................................... ... ... .... ....................... 145
CHAPTER 6 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER ...................... 151
6.1 Outline ............................................................................................................................................ 152
6.2 Block Diagram of the PPG Timer .................................................................................................... 153
6.3 Regis te rs of the PPG Timer .................................................... .... ...................................... .............. 155
6.3.1 Control Status Register (PCNH, PCNL) .................................................................................... 156
6.3.2 PPG Cycle Setting Register (PCSR) ......................................................................................... 159
6.3.3 PPG Duty Setting Register (PDUT) ........................................................................................... 160
6.3.4 PPG Timer Register (PTMR) ..................................................................................................... 161
6.4 PWM Mode ..................................................................................................................................... 162
6.5 One-shot Mode ............................................................................................................................... 164
6.6 Interr upts ....... ............. ............. ............. ............. ............. ......... ............. ............. .............................. 166
6.7 PPG Output of ALL-L and ALL-H .................................................................................................... 167
6.8 Precautions on Using the PPG Timer ............................................................................................. 168
CHAPTER 7 MULTIFUNCTION TIMER ........................................................................ 169
7.1 Overview of the Multifunction Timer ............................................................................................... 170
7.2 Regis te rs of the Multifunction Timer ............. .... ...................................... .... ... ... .............................. 172
7.2.1 Low-Pass Filter Control Register (TxLPCR) .............................................................................. 173
7.2.2 Capture Control Register (TxCCR) ............................................................................................ 174
7.2.3 Timer Setting Register (TxTCR) ................................................................................................ 176
7.2.4 Entire Timer Control Register (TxR) ............ ...................................... .... ... ... .............................. 178
7.2.5 Timer Compare Data Register (TxDRR) ................................................................................... 179
7.2.6 Capture Data Register (TxCRR) ................................................................................................ 180
7.2.7 Test Mode Register (TMODE) ................................................................................................... 181
7.2.8 Used Bit Description for Each Mode .......................................................................................... 182
7.3 Multifunction Timer Operation ......................................................................................................... 184
CHAPTER 8 16-BIT PULSE WIDTH COUNTER .......................................................... 189
8.1 Overview of the 16-Bit Pulse Width Counter .................................................................................. 190
8.2 Registers of the 16-Bit Pulse Width Counter .................................................................................. 191
8.2.1 PWC Control Register (PWCCL) ............................................................................................... 192
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8.2.2 PWC Control Register (PWCCH) .............................................................................................. 194
8.2.3 PWC Data Register (PWCD) ..................................................................................................... 196
8.2.4 PWC Control Register 2 (PWCC2) ............................................................................................ 197
8.2.5 Upper Value Setting Register (PWCUD) ................................................................................... 198
8.3 Operation of the 16-Bit Pulse Width Counter .................................................................................. 199
CHAPTER 9 INTERRUPT CONTROLLER ................................................................... 203
9.1 Overview of the Interrupt Controller ................................................................................................ 204
9.2 Interr up t Con tr oller Re gisters ..................... ... .... ... ....................................... ... ... ... ........................... 206
9.2.1 Interrupt Control Register (ICR) ................................................................................................. 208
9.2.2 Hold Request Cancellation Request Level Setting Register (HRCL) ........................................ 210
9.3 Interr up t Con tr oller Op e ra tio n ....................... .... ... ... ....................................... ... ... .... ....................... 211
9.4 Example of Using the Hold Request Cancellation Request Function (HRCR) ............................... 214
CHAPTER 10 EXTERNAL INTERRUPT AND NMI CONTROLLER ............................... 217
10.1 Overview of the External Interrupt and NMI Controller ................................................................... 218
10.2 External Interrupt and NMI Controller Registers ............................................................................. 219
10.2.1 Interrupt Enable Register (ENIR) ............. .... ... ... ... .... ...................................... .... ....................... 220
10.2.2 External Interrupt Source Register (EIRR) ................................................................................ 221
10.2.3 External Interrupt Request Level Setting Register (ELVR) ........................................................ 222
10.3 Operation of the External Interrupt and NMI Con tr oller .................................................................. 223
CHAPTER 11 REALOS-RELATED HARDWARE .......................................................... 227
11.1 Delayed Interrupt Module ............................................................................................................... 228
11.2 Delayed Interrupt Module Registers ............................................................................................... 229
11.3 Operation of the Delayed Interrupt Module ............................. .... ... ... ....................................... ....... 230
11.4 Bit Search Module ............................................ ...................................... .... ... ... .............................. 231
11.5 Bit Search Module Registers ........ .... ... ... ....................................... ... ... ... ........................................ 232
11.6 Bit Search Module Operation ........ .... ...................................... .... ... ... ................................... ........... 235
CHAPTER 12 10-BIT A/D CONVERTER ........................................................................ 239
12.1 Overview of the 10-Bit A/D Converter ............................................................................................. 240
12.2 Registers of the 10-Bit A/D Converter ............................................................................................ 241
12.2.1 A/DC Control Register (ADCTH, ADCTL) ................................................................................. 242
12.2.2 Software Conversion Analog Input Select Register ................................................................... 244
12.2.3 A/D Conversion Result Register (Channels 0 to 9) ................................................................... 245
12.2.4 A/D Converter Test Register ..................................................................................................... 246
12.3 Operation of the 10-Bit A/D Converter ............................................................................................ 247
CHAPTER 13 U-TIMER ................................................................................................... 249
13.1 Overview .......................... ....................................... .......................................... .............................. 250
13.2 U-TIMER Registers ......................................................................................................................... 251
13.3 U-TIMER Operation ........................................................................................................................ 254
CHAPTER 14 UART ........................................................................................................ 255
14.1 Overview of the UART .................................................................................................................... 256
14.2 UART Registers ...................... ... ... .... ... ....................................... ... ... ... ........................................... 258
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14.2.1 Serial Mode Register (SMR) ...................................................................................................... 259
14.2.2 Serial Control Register (SCR) ................................................................................................... 261
14.2.3 Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) ................................... 264
14.2.4 Serial Status Register (SSR) ..................................................................................................... 265
14.2.5 UART Operation ........................................................................................................................ 269
14.2.6 Asynchronous (Start-stop Synchroniz at ion ) Mod e ................................................................... . 271
14.2.7 Clock Synchronous Mode .......................................................................................................... 272
14.2.8 Occurrence of Interrupts and Timing for Setting Flags .............................................................. 274
14.3 Example of Using the UART ........................................................................................................... 277
14.4 Example of Setting U-TIMER Baud Rates and Reload Values ...................................................... 279
CHAPTER 15 I2C INTERFACE ....................................................................................... 281
15.1 Overview of the I2C Interface .......................................................................................................... 282
15.2 I
15.3 I
15.4 Operation Flowcharts .... ... .... ... ... ... ....................................... ... ....................................... . ................ 315
2
C Interface Registers ................................................................................................................... 287
15.2.1 Bus Status Register (IBSR) ....................................................................................................... 289
15.2.2 Bus Control Register (IBCR) ..................................................................................................... 292
15.2.3 Clock Control Register (ICCR) .................................................................................................. 298
15.2.4 10-bit Slave Address Register (ITBA) ........................................................................................ 300
15.2.5 10-bit Slave Address Mask Register (ITMK) ............................................................................. 301
15.2.6 7-bit Slave Address Register (ISBA) ......................................................................................... 303
15.2.7 7-bit Slave Address Mask Register (ISMK) ............................................................................... 304
15.2.8 Data Register (IDAR) ................................................................................................................. 305
15.2.9 Clock Disable Register (IDBL) ................................................................................................... 306
2
C Interface Operation ................................................................................................................... 310
CHAPTER 16 DMA CONTROLLER (DMAC) .................................................................. 319
16.1 Overview of the DMA Controller (DMAC) ....................................................................................... 320
16.2 DMA Controller (DMAC) Registers ................................................................................................. 322
16.2.1 Control/Status Registers A (DMACA0 to DMACA4) .................................................................. 324
16.2.2 Control/Status Registers B (DMACB0 to DMACB4) .................................................................. 329
16.2.3 Transfer Source/Transfer Destination Address Setting Registers
(DMASA0 to 4/DMADA0 to 4) ................................................................................................... 336
16.2.4 All-Channel Control Register (DMACR) .................................................................................... 338
16.2.5 Other Functions ......................................................................................................................... 340
16.3 DMA Controller Operation .............................................................................................................. 341
16.3.1 Setting a Transfer Request ........................................................................................................ 344
16.3.2 Transfer Sequence ................................................................ ... ... .............................................. 346
16.3.3 General Aspects of DMA Transfer ............................................................................................. 351
16.3.4 Addressing Mode .. ... ....................................... ... ... .... ...................................... .... ... ... ... .............. 353
16.3.5 Data Types ................................................................................................................................ 354
16.3.6 Transfer Count Control ......................... ... .... ...................................... .... ... ... .............................. 355
16.3.7 CPU Control .............................................................................................................................. 356
16.3.8 Hold Arbitration .......................................................................................................................... 357
16.3.9 Operation from Starting to End/Stopping ................................................................................... 358
16.3.10 DMAC Interrupt Control ..................... ... ... ....................................... ... ........................................ 362
16.3.11 Channel Selection and Control .................................................................................................. 363
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16.3.12 Supplement on External Pin and Internal Operation Timing ..................................................... 365
16.4 Operation Flowcharts .... ... .... ... ... ... ....................................... ... ....................................... . ................ 370
16.5 Data Bus ......................................................................................................................................... 373
CHAPTER 17 USB FUNCTION ....................................................................................... 377
17.1 Overview of the USB Function ........................................................................................................ 378
17.2 USB Interface Registers ............ ....................................... ... ... .... .................................................... 381
17.2.1 Data Transmission Registers (for End Points) .......................................................................... 384
17.2.2 Status Registers ....................................................... ... ... ... ....................................... ................. 387
17.2.3 Control Registers ....................................................................................................................... 394
17.3 Operation of the USB Function ............... ....................................... ... ... ... ........................................ 409
17.3.1 Flow of Data Transfer ................................................................................................................ 410
17.3.2 CPU Access Operation .............................................................................................................. 416
17.3.3 Interrupt Sources ............................................................... .... .................................... ................ 423
17.3.4 Setting of End Point Buffer ........................................................................................................ 424
17.3.5 Examples of Software Control ..................... ...................................... .... ... ... .............................. 426
17.4 Supplementary Notes on the USB Function ................................................................................... 435
17.4.1 Double Buffer ............................................................................................................................. 436
17.4.2 Controlling the D+ Terminating Resistor on the Board .............................................................. 441
17.4.3 Automatic Response of Macro Program to USB Standard Requ e st Com m a nd s ...................... 442
17.4.4 USB Function Macro Program Operation in the Default Status ................................................ 444
17.4.5 USB Clock Control in the Suspended Status ........... ... ... ... .... ... ...................................... .... ... ... . 445
17.4.6 Detection of USB Connector Connection and Disconnection .................................................... 446
17.4.7 Accuracy of UCLK48 ................................................................................................................. 447
17.4.8 Setting of Transfer Enable bit (BFOK) during Control Transfer ................................................. 448
17.4.9 Precautions for Control Transfer ............................................................................................... 449
17.4.10 Macro Program Status after USB Bus Reset ............................................................................ 451
CHAPTER 18 OSDC ........................................................................................................ 453
18.1 ON-SCREEN DISPLAY CONTROLLER (OSDC) ................................... ........................................ 454
18.1.1 Features .................................................................................................................................... 455
18.1.2 Block Diagram ... ... ... ... .... ... ....................................... ... ... ... ....................................... ................. 457
18.2 Display Functions ........................................................................................................................... 458
18.2.1 Screen Configuration ................................................................................................................. 459
18.2.2 Screen Display Modes ............................................................................................................... 462
18.2.3 Screen Output Control ............................................................................................................... 464
18.2.4 Screen Display Position Control ................................................................................................ 465
18.2.5 Font Memory Configuration ......................................................... ... ... .... .................................... 475
18.2.6 Display Memory (VRAM) Configuration ..................................................................................... 476
18.2.7 Writing to Display Memory (VRAM) ........................................................................................... 477
18.2.8 Palette Configuration ................................................................................................................. 480
18.2.9 Character Display ........................... ... ... ....................................... ... ........................................... 481
18.2.10 Character Background Display ................................................................................. ... .............. 515
18.2.11 Line Background Display ........................................................................................................... 524
18.2.12 Screen Background Display ...................................................................................................... 533
18.2.13 Sprite Character Display .......................... ....................................... ... .... ... ................................. 538
18.3 Control Functions ............................................................................................................................ 542
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18.3.1 Dot Clock Control ........................... ....................................... ... ... ... ........................................... 543
18.3.2 Sync Signal Input .. ... ....................................... ... ....................................... ... .............................. 548
18.3.3 Display Signal Output ................................................................................................................ 556
18.3.4 Display Period Control ............................................................................................................... 559
18.3.5 Synchronization Control ............................................................................................................ 561
18.3.6 Interrupt Control ................................. ... ....................................... ... ... ........................................ 564
18.3.7 OSDC Operation Control ....................................................... ...................................... ... ........... 567
18.4 Display Control Commands ............................................................................................................ 569
18.4.1 List of Display Control Commands ............................................................................................ 570
18.4.2 VRAM Write Address Set (Command 0) ................................................................................... 572
18.4.3 Character Data Set (Commands 1 and 2) ................................................................................. 573
18.4.4 Line Control Data Set (Commands 3 and 4) ............................................................................. 575
18.4.5 Screen Output Control (Commands 5-00 and 5-1) .................................................................... 577
18.4.6 Display Position Control (Commands 5-2 and 5-3) ................................................................... 579
18.4.7 Character Vertical Size Control (Command 6-0) ....................................................................... 580
18.4.8 Shaded Background Frame Color Control (Command 6-1) ...................................................... 581
18.4.9 Transparent/Translucent Color Control (Command 6-2) ........................................................... 582
18.4.10 Graphic Color Control (Command 6-3) ...................................................................................... 583
18.4.11 Screen Background Character Control (Commands 7-1 and 7-3) ............................................ 585
18.4.12 Sprite Character Control (Commands 8-1, 8-2, 9-0 and 9-1) .................................................... 587
18.4.13 Synchronization Control (Command 11-0 ) ..................................................................... .... ... ... . 590
18.4.14 I/O Pin Control (Commands 13-0 and 13-1) .............................................................................. 591
18.4.15 Display Period Control (Commands 14-0 to 14-3) ..................................................................... 593
18.4.16 Interrupt Control (Command 15-0) ............................................................................................ 596
18.4.17 Palette Control (Commands 16-0 to 16-15) ............................................................................... 597
18.4.18 OSDC Operation Control (Commands 17-0 an d 17 -1 ) ............. ... ... ....................................... ... . 599
18.4.19 PLLA Clock Control (Commands 18-0 to 18-3) ......................................................................... 601
18.4.20 PLLB Clock Control (Commands 18-4 to 18-7) ......................................................................... 603
18.4.21 PLLC Clock Control (Commands 18-8 to 18-11) ....................................................................... 605
18.4.22 Clock Selection Control (Commands 18-12 to 18-13) ............................................................... 607
18.5 Display Control Command (CC) ..................................................................................................... 609
18.5.1 CC Screen and Display Control Command List ........................................................................ 610
18.5.2 VRAM Write Address Setting (Command 0) .. ... ... .... ... ... ....................................... ... ... ... ........... 611
18.5.3 Character Data Setting (Command 1, Comman d 2) ...................................... .... ... ... ................. 612
18.5.4 Line Control Data Setting (Command 3, Command 4) .............................................................. 614
18.5.5 Display Output Control (Command 5-00, Command 5-1) ......................................................... 616
18.5.6 Display Position Control (Command 5-2, Command 5-3) ......................................................... 618
18.5.7 Character Vertical Size Control (Command 6-0) ....................................................................... 619
18.5.8 Transparent Color Control (Command 6-2) ............................................................................... 620
18.5.9 Display Period Control (Command 14-0, 14-1, 14-2, 14-3) ....................................................... 621
18.5.10 Interrupt Control (Command 15-0) ............................................................................................ 623
18.5.11 Palette Control (Command 16-0 to Command 16-15) ............................................................... 624
18.6 FONT RAM Interface ........................................... ... ... .... ...................................... .... ....................... 625
CHAPTER 19 FLASH MEMORY ..................................................................................... 629
19.1 Outline of Flash Memory ................................................................................................................. 630
19.2 Flash Memory Registers ................................................................................................................. 637
xii
19.2.1 Flash Control/Status Register (FLCR) ....................................................................................... 638
19.2.2 Flash Memory Wait Register (FLWC) ................... ....................................... ... .... ... .................... 640
19.3 Flash Memory Access Modes ......................................................................................................... 642
19.4 Automatic Algorithm of Flash Memory ........................................... ... ... ... ........................................ 644
19.5 Execution Status of the Automatic Algorithm .................................................................................. 648
19.6 Writing to and Erasing from Flash Memory .................................................................................... 653
19.6.1 Read/Reset Status .................................................................................................................... 654
19.6.2 Data Writing ............................................................................................................................... 655
19.6.3 Data Erasure (Chip Erasure) ..................................................................................................... 657
19.6.4 Data Erasure (Sector Erasure) .................................................................................................. 658
19.6.5 Temporary Sector Erase Stop ..................... ... ... ... .... ... ....................................... ... ... ... .............. 660
19.6.6 Sector Erase Restart ................................................................................................................. 661
CHAPTER 20 SERIAL PROGRAMMING CONNECTION .............................................. 663
20.1 Serial Programming Connection ..................................................................................................... 664
APPENDIX ......................................................................................................................... 669
APPENDIX A I/O Map ................................................................................................................................ 670
APPENDIX B Interrupt Vector .................................................................................................................... 685
APPENDIX C Dot Clock Generation PLL ................................................................................................... 688
APPENDIX D USB Clock ........................................................................... ................................................. 690
APPENDIX E Macro Reset ......................................................................................................................... 691
APPENDIX F USB Low-power Consumption Mode ................................................................................... 692
APPENDIX G External Bus Interface Setting ............................................................................................. 693
APPENDIX H Pin State List ...................................................................................................... .................. 695
APPENDIX I Instruction Lists .................................................................................................................... 699
I.1 How to Read the Instruction Lists .................................................................................................. 700
I.2 FR Family Instruction Lists ............................................................................................................. 704
INDEX...................................................................................................................................721
xiii
xiv xv
Main changes in this edition
Page Changes (For details, refer to main body.)
Change pin names
-
(TO0 → TOUT0)
(TO1 → TOUT1)
(TO2 → TOUT2)
24
26
27
27
28
3
4
6
6
Change ■ Built-in RAM (MASK: Add 32KB RAM)
Change ■ A/D Converter (conversion time: about 10 µs → conversion ti me: about 8.5 µs)
Change CMOS technology of ■ Other Features
Change Supply voltage of ■ Other Features
Change the Figure 1.2-1 Block Diagram
(Add DSU)
7
(Add MASK 512KB to Flash 1MB)
(Add MASK 32KB to RAM)
(PWC 1ch → PWC 4ch)
(Add Font ROM product)
Change Figure 1.4-1 Pin Layout of the MB91319
9
(MB91F318A → MB91F318A/S)
(MB91FV319A
(Change the Note)
→ MB91FV319A/R)
Add a sentence to ■ Quartz Oscillation Circuit
Change Low Power Consumption Mode of ■ Lim itations
Change Note on using A/D
Add About Software Reset of Synchronous Mode
Change ❍ Unique characteristic of the evaluation chip MB91FV319A
(MB91FV319A → MB91FV319A/R)
30
70
70
74
81
83
85
87
90
Change Figure 3.1-1 Memory Map
(MB91F318 → MB91F318A/S and MB91FV319R)
(MB91F318, MB91316
→ MB91F318A/S, MB91316)
Add Reference: to ■ Software Reset (STCR: SRST Bit Writing)
Change ■ Watchdog Reset (watchdog reset postpone register (WPR) → time base counter clear
register (CTBR))
Add Reference: to ■ Synchronous Reset Operation
Add items to Notes: for ■ External Bus Clock (CLKT)
Change Figure 3.11-1 Block Diagram of Clock Generation Controller
(Delete WPR register)
Change [bit9, bit8] WT1, WT0 (Watchdog interval Time select) (WPR → CTBR)
Add Reference: to [bit4] SRST (Software ReSeT)
Add Note: to [bit9] SYNCR (SYNChronous Reset enable)
Page Changes (For details, refer to main body.)
90
91
94
100
106
111
130
131
137 to 150
180
182
240
240
241
Add Note: to [bit8] SYNCS (SYNChronous Standby enable)
Change ■ Time Base Counter Clear Register (CTBR)
Delete ■ Watchdog Reset Post pone Register (WPR)
Change [P ostponing a watchdog reset] (watchdog reset postpone register (WPR)
→ time base counter clear register (CTBR))
Change Figure 3.12-1 Transition of Device States
Delete [Normal and synchronous standby operations]
Change Figure 4.2-1 Configuration of the Port Data Registers (PDR) (P75 → − )
Change Figure 4.2-2 Configuration of the Data Direction Registers (DDR) (P75 → − )
Replace the entire chapter CHAPTER 5 16-BIT RELOAD TIMER
Change ■ Capture Data Register (TxCRR)
Add 7.2.8 Used Bit Description for Each Mode
Change ■ Features of the 10-Bit A/D Converter
Change Figure 12.1-2 Block Diagram of the 10-Bit A/D Converter
(Add AN9)
(Add AN8)
Change Figure 12.2-1 Register Configuration of the 10-Bit A/D Converter
244
244
247
254
254
256
258
269
276
293
353
362
365
Change the bit9 and bit8 of Figure 12.2-3 Bit Configuration of the Software Conversion Analog
Input Select Register
("0" → i9)
(
"0" → i8)
Change the [bit9 to bit0] i9 to i0 (i7 to i0 → i9 to i0)
Change ■ A/D Conversion Started by External Trigger
Change ❍ Asynchronous (start-stop synchronization) mode
Change ❍ CLK synchronous mode
Change the ■ Features (Delete "The DMAC interrupt source is cleared if the DRCL register is
written to.")
Change Figure 14.2-1 UART Registers (Delete DMA req uest clear register (DRCL))
Delete DRCL Register description
Change ■ Precautions on Usage (Delete "Write to the DRCL register befor e starting DMA transfer
due to an interrupt for the first time.")
Add a sentence to Note:
Change the second bullet under the ■ Address Register Specifications
Change ■ DMA Transfer during Sleep
Change ■ Timing to Stop a Demand Transfer Request and Timing to Inv alidate the DREQ Pin Inpu t
366
Change Figure 16.3-6 Example of the Timing for Negating the DREQ Pin Input for 2-Cycle Transfer
from an External Circuit to an Internal Circuit
xvi
Page Changes (For details, refer to main body.)
366
367
367
456
546
632
633
634
635
636
644
644
Change • For transfer from internal to external circuits:
Change ❍ For fly-by transfer
Change Figure 16.3-7 Example of the Timing for Negating the DREQ Pin Input for Fly-by (Timing to
IORD Pin) Transfer
Change ❍ Interrupt functions (MAIN is connected to the exter n al int er rupt ch5, cc is connected to
the external interrupt ch6) (Add "MAIN is connected to the external interrupt ch5, cc is connected to
the external interrupt ch6" )
Change Table 18.3-5 Oscillating VCO Selection Control
Change Figure 19.1-2 Memory Mapping for Access in Flash Memory Mode/CPU Mode
Change the title of Figure 19.1-3 Sect or Configuration in CPU Mode (MB91FV319A, MB91F318 A)
(add (MB91FV319A, MB91F318A))
Add Figure 19.1-4 Sector Configuration in CPU Mode (MB91F318S, MB91FV319R)
Change the title of Figure 19.1-5 Sector Configuration in FLASH Mode (MB91FV319A,
MB91F318A) (add (MB91FV319A, MB91F318A))
Add Figure 19.1-6 Sector Configuration in FLASH Mode (MB91F318S, MB91FV319R)
Change ■ Basic Configuration of Serial Programming Connection
Change the title of Table 19.4-1 Command Sequence (MB91FV319A, MB91F318A) (add
(MB91FV319A, MB91F318A))
644
665
666
671 to 679
688
689
Add Table 19.4-2 Command Sequence (MB91F318S, MB91FV319R)
Change Notes: (MB91FV319A Write control pin → MB91FV319A/R MB91F318A/S Write control
pin)
Change Figure 20.1-1 Example of Serial Programming Connection
(MB91FV319A → MB91FV319A/R, MB91F318A/S)
Change the Table A-1 I/O Map
(DRCL0 [W] -------- → DRCL0 --------*3)
(DRCL1 [W] -------- → DRCL1 --------*3)
(DRCL2 [W] -------- → DRCL2 --------*3)
(DRCL3 [W] -------- → DRCL3 --------*3)
(Change 000160
to 00017CH and 000180H to 00019CH to "Reserved")
H
(WPR [W] XXXXXXXX → WPR --------*3)
(Delete Address 007100
(Delete Address 007104
line)
H
line)
H
(Add *3: Reserved register. Access is disabled.)
Change Figure C-1 CP0 Pin Connection
Change the table and add a table
(Table C-2 0.25 µm: EVA, FLASH)
(Table C-3 0.18 µm: EVA, FLASH, MASK)
xvii
xviii
CHAPTER 1
OVERVIEW
This chapter provides basic inf ormation required to
understand the MB91319 series, and covers features, a
block diagram, and functions.
1.1 Features
1.2 Block Diagram
1.3 External Dimensions
1.4 Pin Layout
1.5 List of Pin Functions
1.6 Input-output Circuit Forms
1
CHAPTER 1 OVERVIEW
1.1 Features
The FR family is a single-chip microcontroller that has a 32-bit high-performance RISC
CPU as well as built-in I/O resources for embedded controllers requiring highperformance and high-speed CPU processing.
The FR family is the most suitable for embedded applications, for example, TV and PDP
control, that require a high level of CPU processing performance.
This model is an FR60 series model that is based on the FR30/40-family of CPUs. It has
enhanced bus access and is optimized for high-speed use.
■ FR CPU
• 32-bit RISC, load/store architecture, five stages pipeline
• Operating frequency of 40 MHz [PLL used, original oscillation at 10 MHz]
• 16-bit fixed-length instructions (basic instructions), one instruction per cycle
• Memory-to-memory transfer, bit processing, instructions including barrel shift, etc.:
instructions appropriate for embedded applications
• Function entry and exit instructions, multi load/store instructions:
instructions compatible with high-level languages
• Register interlock function to facilitate assembly-language coding
• Built-in multiplier/instruction-level support
• Signed 32-bit multiplication: 5 cycles
• Signed 16-bit multiplication: 3 cycles
• Interrupts (saving of PC and PS): 6 cycles, 16 priority levels
• Harvard architecture enabling simultaneous execution of both program access and data
access
• 4-word queues in the CPU provided to add an instruction prefetch function
• Instructions compat ible with the FR family
■ Bus Interface
2
This bus interface is used for macro connections (USB and OSDC).
• Maximum operating fre quency of 20 MHz
• 16-bit data inpu t-output (interface with USB and OSDC)
• Totally independent 8-area chip select outputs that can be defined in the minimum units of
64K bytes
The CS1
•CS1
•CS2
•CS3
• Basic bus cycle (2 cycles)
, CS2, and CS3 areas are reserved as shown below.
area: Reserved
area: USB function
area: OSDC
• Automatic wait cycle generator that can be programmed for each area and can insert waits
because CS1
■ Built-in RAM
• EVA: 64KB RAM, FLASH: 48KB RAM, MASK: 32KB RAM
• This RAM can be used as data RAM and instruction RAM if instruction codes are written to it.
■ DMAC (DMA Controller)
• 5 channels (channels 0 and 1 are connected to the USB function.)
• 3 transfer sources (internal peri pherals, software)
• Addressing mode with 32-b it full address specifications (increase, decrease, fixed)
• Transfer modes (deman d transfer, burst transfer, step transf er, block transfer)
• Transfer data size that can be selected from 8, 16, and 32 bits
■ Bit Search Module (Used by REALOS)
• Searches for the position of the first bit varying between 1 and 0 in the MSB of a word
, CS2, and CS3 are reserved, the setting is fixed.
CHAPTER 1 OVERVIEW
■ Reload Timer (Including One Channel for REALOS)
• 16-bit timer; 3 channels
• Internal clock that can be selected from those resulting from frequency divided by 2, 8, and 32
■ UART
• Full-duplex double buffer
• 5 channels
• Parity or no parity can be selected.
• Either asynchronous (start-stop synchronization) or CLK synchronous communication can be
selected.
• Built-in timer for dedicated baud rates
• An external clock can be used as the transfer clock.
• Plentiful error detection functions (parity, frame, overrun)
3
CHAPTER 1 OVERVIEW
2
C Interface
■ I
• 4 channels (channel 3 can b e used for two ports.)
• Master/slave transmission and reception
• Clock synchronization function
• Transfer direction detection function
• Bus error detection function
• Supports standard mode (Max. 100 Kbps) and high-speed mode (Max, 400 Kbps).
• Arbitration function
• Slave address/general call address detection function
• Start condition repetitious occurrence and detection function
• 10-bit/7-bit slave address
• Built-in FIFO function: each 16-byte sending/receiving
■ Interrupt Controller
• Total of 5 external interrupts (one unmas kable pin (NMI
• Interrupts from internal peripherals
• Priority level can be defined as programmable (16 levels) except for the unmaskable pin
• Can be used for wake-up during stop.
■ A/D Converter
• 10-bit resolution, 10 channels
• Sequential comparison and conversion type (conversion time: about 8.5 µs)
• Conversion modes (single conversion mode and scan conversion mode)
• Causes of startup (software and external triggers)
■ PPG
• 4 channels
• 16-bit data register with 16-bit down counter and cycle setting buffer
• Internal clock: Frequency-divide-by number selectable from 1, 4, 16, and 64
■ PWC
• 1 channel (1 input)
) and four regular interrupt pins (INT3
to INT0))
• 16-bit up counter
• Simple LFP digital filter
4
■ Multifunction Timer
• Low-pass filter that removes noise that is below the frequency of the set clock
• Pulse width measurement that can be performed by precise settings using seven types of
clock signals
• Event count for signals from pin input
• Interval timer using seven types of clocks and external input clocks
■ USB Function
• USB2.0 full-speed, double buffer
• CONTROL IN/OUT, BULK IN/OUT, and INTERRUPT IN
■ OSDC Function
• 3 bits per color - Red, Green and Blue (of 512 colors, 16 can be displayed)
• Analog RGB output maximum 50 MHz
• Digital RGB output maximum 90 MHz
• Display 24 × 32 dots font can be displayed as maximu m 80 × 32
CHAPTER 1 OVERVIEW
• MAIN/CC two-layer display (font is fixed at 18 dots wide for the CC layer)
• Maximum 4096 character types (font RAM: 16 characters)
■ Closed Caption Decoder Function
• 2 channels available
• CC decode function
• ID-1 (480i/4 80p) decode function
■ Video Clock PLL
• PLLs available to gene rate dot clock and VBI clock
■ Other Interval Timers
• 16-bit timer: 3 channels (U-TIMER)
• Watchdog timer
■ I/O Ports
• Maximum of 88 ports
5
CHAPTER 1 OVERVIEW
■ Other Features
• Has a built-in oscillation circuit as a clock source.
•INIT
is provided as a reset pin.
• Additionally, a watchdog timer reset and software resets are provided.
• Stop mode and sleep mode supported as low-power modes
• Gear function
• Built-in time base timer
• Package: LQFP-176, 0. 5 mm pitch, and 24 mm × 24 mm
• CMOS technology: 0.25 µm (EVA(MB91FV319A), FLASH (MB91F318A))
0.18 µm (MASK(MB91316), EVA(MB91FV319R), FLASH (MB91F318S))
• Supply voltage: two sources of 3.3 V (-0.3 V to +0.3 V) and 2.5 V (-0.2 V to +0.2 V)
(0.25 µm : EVA(MB91FV319A), FLASH (MB91F318A))
two sources of 3.3 V (-0.3 V to +0.3 V) and 1.8 V (-0.15 V to +0.15 V)
(0.18 µm : MASK(MB91316), EVA(MB91FV319R), FLASH (MB91F318S))
2
THE I
C LICENSE:
2
Purchase of Fujitsu I
C components conveys a license under the Philips I2C Patent Rights to
use, these components in an I
2
C system provided that the system conforms to the I2C
Standard Specification as defined by Philips.
6
1.2 Block Diagram
Figure 1.2-1 is a block diagram of the MB91319.
■ Block Diagram
Figure 1.2-1 Block Diagram
CHAPTER 1 OVERVIEW
Bit search
RAM
EVA 64KB
FLASH 48KB
MASK 32KB
Clock
control
Interrupt
controller
External
interrupt
32
32 to 16
adapter
FR
CPU Core
Bus converter
Font ROM
FLASH 512 KB*
ROM 384 KB*
UART
5ch
32
External
memory
I/F
2
C
I
4ch
2
2
A/D
10ch
DSU*
Flash 1MB
MASK 512KB
DMAC5ch
USB
function
OSDC
CCD
2ch
1
Port
PWC
4ch
PPG
4ch
Reload
timer 3ch
Multifunction
timer 4ch
*1 : DSU is loaded only in MB91FV319A/R
*2 : Font ROM: MB91FV319A/R: FLASH 512 KB
: MB91F318A/S, MB91316 : MASK ROM 384 KB
7
CHAPTER 1 OVERVIEW
176-pin plastic LQFP Lead pitch 0.50 mm
Package width ×
package length
24.0 × 24.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LQFP-0176-2424-0.50
176-pin plastic LQFP
(FPT-176P-M07)
(FPT-176P-M07)
C
2004 FUJITSU LIMITED F176013S-c-1-1
Details of "A" part
0˚~8˚
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
(Stand off)
(.004±.004)
0.10±0.10
1.50
+0.20
–0.10
+.008
–.004.059
(Mounting height)
0.08(.003)
(.006±.002)
0.145±0.055
"A"
INDEX
1
LEAD No.
44
45
88
89132
133
176
0.50(.020)
0.22±0.05
(.009±.002)
M
0.08(.003)
*24.00±0.10(.945±.004)SQ
26.00±0.20(1.024±.008)SQ
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1)* : Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness
Note 3) Pins width do not include tie bar cutting remainder.
1.3 External Dimensions
The MB91319 is available in one type of package.
Figure 1.3-1 shows the dimensions of the MB91319.
■ Dimensions of the MB91319
Figure 1.3-1 External Dimensions of MB91319
8
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