FUJITSU MB91302A, MB91V301A DATA SHEET
FUJITSU SEMICONDUCTOR
ROM variation
DATA SHEET
32-Bit Proprietary Microcontroller
CMOS
FR60 MB91301 Series
MB91302A/V301A
DESCRIPTION
■
The MB91301 series are a line of microcontrollers based on a 32-bit RISC CPU core (FR family) , incorporating
a variety of I/O resources and a bus control mechanism for embedded control that requires the processing of a
high-performance, fast CPU as well as an SDRAM interface that can connect SDRAM directly to the chip.
The large address space supported by the 32-bit CPU addressing means that operation is primarily based on
external bus access although instruction cache memory of 4 Kbytes and RAM of 4 Kbytes( for data) are included
for high-speed execution of CPU instructions.
The MB91302A and MB91V301A are FR60 products based on the FR30/40 CPU with enhanced bus access for
higher speed operation. The device specifications include a D/A con verter to facilitate motor control and are ideal
for use in DVD players that support fly-by transfer.
DS07-16502-3E
FEATURES
■
The MB91301 series is a line of ICs with various programs embedded in internal ROM.
Product name
MB91302A
PACKAGES
■
Built-in the real
time OS version
144-pin, Plastic LQFP 179-pin, Ceramic PGA
(FPT-144P-M12) (PGA-179C-A03)
(Internal Program Loader) version
Built-in IPL
User ROM
version
Without ROM
version
(Continued)
MB91301 Series
1. FR CPU
• 32-bit RISC, load/store architecture, 5-stage pipeline
• 68 MHz internal operating frequency (Max) [external (Max) 68 MHz] (when using PLL with base frequency
(Max) = 17 MHz)
• General purpose registers : 32 bits×16
• 16-bit fixed length instructions (basic instructions) , 1 instruction per cycle
• Instruction set optimized for embedded applications: Memory-to-memory transfer, bit manipulation, barrel shift
etc.
• Instructions adapted for high-level languages : Function entry/exit instructions, multiple-register load/store
instructions
• Easier assembler coding : Register interlock function
• Branch instructions with delay slots : Reduced overhead time in branch executions
• Built-in multiplier with instruction-level support
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
• Interrupt (PC, PS save) : 6 cycles, 16 priority levels
2. Bus interface
• Operating frequency : Max 68 MHz (when using SDRAM)
• Full 24-bit address output (16 Mbytes memory space)
• 8-bit, 16-bit or 32-bit data input/output
• Built-in pre-fetch buffer
• Unused data and address pins can be used as general-purpose input/output ports.
• Eight fully independent chip select outputs, can be set in minimum 64 Kbytes units.
• Supports the following memory interfaces
Asynchronous SRAM, asynchronous ROM/Flash
Page mode ROM/Flash ROM (selectable page size = 1, 2, 4, or 8)
Burst mode ROM/Flash ROM (MBM29BL160D/161D/162D)
• SDRAM (FCRAM Type, CAS Latency 1 to 8, 2/4 bank products.)
• Address/Data multiplex bus (only 8/16-bit width)
• Basic bus cycle : 2 cycles
• Automatic wait cycle generation function can insert wait cycles, independently progr ammable for each memory
area.
• RDY input for external wait cycles
• Endian setting of byte ordering (Big/Little)
CS0
area only for big endian
• Prohibition setting of write (only for Read)
• Permission/prohibition setting of fetch into built-in cache
• Permission/prohibition setting of prefetch function
• DMA supports fly-by transfer with independent I/O wait control
• External bus arbitration can be used using BRQ and BGRNT
.
3. Built-in memory
•4 Kbytes DATA RAM
• 4 Kbytes RAM (MB91302A)
2
(Continued)
MB91301 Series
4. Instruction cache
• Size : 4 Kbytes
• 2-way set associative
• 128 blocks/way, 4 entries/block
• Lock function enables program code to be made cache-resident
• Areas not used for instruction cache can be used as instruction RAM
5. DMAC (DMA Controller)
• 5-channel (2-channel external-to-external)
• 3 transfer triggers : External pin, internal peripheral, software
• Capable of selecting an internal peripheral as a transfer source freely for each channel
• Addressing using 32-bit full addressing mode (increment, decrement, fixed)
• Transfer modes : Demand transfer, burst transfer, step transfer, or block transfer
• Supports fly-by transfer (between external I/O and memory)
• Selectable transfer data size : 8, 16, or 32-bit
6. Bit search module
• Searches words from MSB for position of first 1/0 bit value change
7. Reload Timers
• 16-bit timer : 3 channels
• Internal clock : 2 clock cycle resolution, divide by 2/8/32 selective
8. UART
• Full duplex, double buffer UART
• Independent 3 channels
• Data length : 7 bits to 9 bits (without parity) , 6 bits to 8 bits (with parity)
• Asynchronous (start-stop synchronized) or CLK-synchronous communications selectable
Multi-processor mode
• Built-in 16-bit timer (U-TIMER) as a baud rate generator to generate arbitrary baud rates
• External clock can be used as transfer clock
• Variety of error detection functions (parity, frame, overrun)
9. Interrupt controller
• External interrupt input : 1 non-maskable interrupt pin and 8 normal interrupt pins (INT0 to INT7)
• Internal internal resources : UART, DMAC, A/D, U-TIMER, Delay interrupt, I
• Programmable priorities (16 levels) for all interrupts except the non-maskable interrupt
2
C, Free-run timer, Input capture
10. A/D converter
• 10-bit resolution, 4 channels
• Successive approximation type, conversion time : 4.1 µs at 34 MHz
• Built-in sample and hold circuit
• Conversion modes : Single con v ersion mode , scan con v ersion mode and repeat conversion mode selectable
• Conversion triggers : Software, external trigger and built-in timer selectable
11. I2C* interface
• Internal 2-channels master/slave transmit/receive
• Internal arbitration function, clock synch function
12. Free-run timer
• 16 bit : 1channel
(Continued)
3
MB91301 Series
(Continued)
13. Input capture
• 4 channels
14. Other interval timers
• 16-bit timer : 3 channels (U-TIMER)
• PPG timer : 4 channels
• Watchdog timer : 1 channel
15. Other features
• Reset resources : watchdog timer/software reset/ex ternal reset (INIT pin)
• Power-saving modes : Stop mode, sleep mode
• Clock control
Gear function : Allows arbitrary different operating clock frequencies to be set for the CPU and peripherals.
You can select one of the 16 gear clock factors of 1/1 to 1/16. PLL multiplication can also be selected. Note,
however, that peripherals operate at a maximum of 34 MHz.
• CMOS technology : 0.25 µm
• Power supply (analog power supply): 3.3 V ± 0.3 V (internal regulator used)
* : Purchase of Fujitsu I
components in an I
by Philips.
2
C components conveys a license under the Philips I2C Patent Rights to use, these
2
C system provided that the system conforms to the I2C Standard Specification as defined
PRODUCT LINEUP
■
MB91302A MB91V301A
Type
RAM
ROM has non-ROM model, the optimal real time
ROM
DSU ⎯ DSU4
Package
*1 : The Fujitsu product of real time OS REALOS/FR by conforming to the µITRON 3.0 is stored and optimized
with the MB91302A.
*2 : The ROM stores the IPL (Internal Program Loader) . Loading various programs can be executed from the
external system by the internal UART/SIO. Using this function, for example, writing on board to the Flash
memory connected to the external can be executed.
OS internal model*
Loader) internal model*
Mask ROM product
(for volume production)
4 Kbytes
(only for data)
4 Kbytes
1
, and the IPL (Internal Program
2
by adding the user ROM
model.
LQFP-144
(0.4 mm pitch)
Evaluation version
(For evaluation and develop-
ment)
16 Kbytes
(data 8 KB+8 KB)
8 Kbytes (RAM)
PGA-179
4
PIN ASSIGNMENTS
P
P
5
4
K
P
■
MB91301 Series
• MB91302A
DQMUU/WR0(UUB)
85/DQMUL/WR1(ULB)
86/DQMLU/WR2(LUB)
P87/DQMLL/WR3(LLB)
P13/D11
P14/D12
P15/D13
P16/D14
P17/D15
SS
V
V
CC
P20/D16
P21/D17
P22/D18
P23/D19
P24/D20
P25/D21
P26/D22
P27/D23
V
SS
V
CC
D24
D25
D26
D27
D28
D29
D30
D31
V
SS
V
CC
P80/RDY
P81/BGRNT
P82/BRQ
RD
P90/SYSCLK
(TOP VIEW)
D10/P12
D09/P11
D08/P10
VCCVSSD07/P07
D06/P06
D05/P05
D04/P04
D03/P03
D02/P02
D01/P01
D00/P00
VCCVSSCS7/PA7
CS6/PA6
CS5/PPG2/PA
CS4/TRG2/PA
CS3/PA3
CS2/PA2
CS1/PA1
CS0/PA0
VCCNMI
INIT
MD2
MD1
MD0
VCCVSSX1X0VCCIORD/PB7
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
3738394041424344454647484950515253545556575859606162636465666768697071
115
114
113
112
111
IOWR/PB6
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
DEOP1/PPG1/PB5
DACK1/TRG1/PB4
DREQ1/PB3
DEOP0/PB2
DACK0/PB1
DREQ0/PB0
C
V
SS
TIN2/TRG3/PH2
TIN1/PPG3/PH1
TIN0/PH0
TRG0/PJ7
PPG0/PJ6
SCK1/PJ5
SOT1/PJ4
SIN1/PJ3
SCK0/PJ2
SOT0/PJ1
SIN0/PJ0
V
CC
INT7/SCK2/PG7
INT6/SOT2/PG6
INT5/SIN2/PG5
INT4/ATG/PG4/FRC
INT3/PG3/ICU3
INT2/PG2/ICU2
INT1/PG1/ICU1
INT0/PG0/ICU0
AV
SS
/AVRL
AN0
AN1
AN2
AN3
AVR
AVRH
AV
CC
SS
CC
V
P93
P92/MCLK
P91/MCLKE
V
A00
A01
A02
P96/SWE/WR
P95/SCAS/BAA
94/SRAS/LBA/AS
A03
(FPT-144P-M12)
A04
A05
A06
A07
SS
V
CC
V
A08
A09
A10
A11
A12
A13
A14
A15
SS
V
P60/A16
P61/A17
P62/A18
P63/A19
CC
V
P65/A21/SCL0
P67/A23/SCL1
P64/A20/SDA0
P66/A22/SDA1
5
MB91301 Series
1
1
1
1
1
1
• MB91V301A
(TOP VIEW)
INDEX
5
1
2
3
4
5
6
7
8
9
0
1
2
3
178 174 172 168 165 161 160 156 155 151 150 145 142
7
179 177
10 4 2
15 9 3
20 14 12
21 19 18
25 22 24 23
26 27 28 29
30 31 32 35
33 34 36
37 38 41
39 42 47 48
173
176
180
6
11
17
40 46
45
169
171
175
1
51 56
53
166
167
170
57
162
163
164
62
63
157
159
158
68
69
154
149
153
147
152
146
74 80 85
73
77
148
143
141
13616 13 8
91
81
144
138
135
130
125
119
113
107
101
96
90
86
139
137
131
126
122
118
114
108
102
98
93
92
134
132
128
124
121
117
112
109
104
103
99
94
140
133
129
127
123
120
116
115
111
110
106
105
100
4
5
43 44 49 54
50 52 55 60
ABCDEFGHJKLMNP
58
61
59
65
64
66
67
70
72
71
76
75
79
78
83
82
87
84
89
88
97
95
R
(PGA-179C-A03)
6
MB91301 Series
•
MB91V301A Pin No. Table
No. PIN Pin Name No. PIN Pin Name No. PIN Pin Name
1E5 N.C. 31B10 V
SS
61 E15 A07
2 C3 P13/D11 32 C10 V
3C4 V
4B3 V
SS
CC
33 A11 P80/RDY 63 G13 V
34 B11 P81/BGRNT 64 G14 A08
CC
62 G12 V
SS
CC
5 A1 P14/D12 35 D10 P82/BRQ 65 F15 A09
6 D5 P15/D13 36 C11 RD
7 A2 P16/D14 37 A12 DQMUU/WR0
8 C5 P17/D15 38 B12
9B4 V
10 A3 V
SS
CC
39 A13
40 D11
P85/DQMUL/WR1
P86/DQMLU/WR2
P87/DQMLL/WR3
11 D6 P20/D16 41 C12 V
12 C6 P21/D17 42 B13 V
(UUB) 67 H14 A11
(ULB
)
(LUB
)
(LLB
)
SS
CC
13 B5 P22/D18 43 A14 P90/SYSCLK 73 J13 V
66 G15 A10
68 H12 A12
69 H13 A13
70 H15 A14
71 J15 A15
72 J14 V
SS
CC
14 B6 P23/D19 44 B14 P91/MCLKE 74 J12 P60/A16
15 A4 P24/D20 45 D12 P92/MCLK 75 K15 P61/A17
16 A5 P25/D21 46 E11 P93 76 K14 P62/A18
17 D7 P26/D22 47 C13 V
18 C7 P27/D23 48 D13 V
19 B7 V
20 A6 V
SS
CC
49 C14 P94/SRAS/LBA/AS 79 L14 SCL0/P65/A21
50 A15 P95/SCAS/BAA 80 K12 SDA1/P66/A22
SS
CC
77 K13 P63/A19
78 L15 SDA0/P64/A20
21 A7 D24 51 E12 P96/SWE/WR 81 L13 SCL1/P67/A23
22 B8 D25 52 B15 V
23 D8 D26 53 E13 V
SS
CC
82 M15 V
83 M14 V
CC
CC
24 C8 D27 54 D14 A00 84 N15 EWR3
25 A8 V
26 A9 V
SS
CC
55 C15 A01 85 L12 EWR2
56 F12 A02 86 M13 EWR1
27 B9 D28 57 F13 A03 87 N14 EWR0
28 C9 D29 58 E14 A04 88 P15 ECS
29 D9 D30 59 F14 A05 89 P14 EMRAM
30 A10 D31 60 D15 A06 90 M12 ICD3
(Continued)
7
MB91301 Series
(Continued)
No. PIN Pin Name No. PIN Pin Name No. PIN Pin Name
91 L11 ICD2 121 P6 SOT0/PJ1 151 L1 V
CC
92 N13 ICD1 122 N6 SCK0/PJ2 152 J4 INIT
93 N12 ICD0 123 R5 SIN1/PJ3 153 J3 NMI
94 P13 V
95 R15 V
SS
CC
124 P5 SOT1/PJ4 154 J2 V
125 M6 SCK1/PJ5 155 K1 V
SS
CC
96 M11 BREAK 126 N5 PPG0/PJ6 156 J1 CS0/PA0
97 R14 ICLK 127 R4 TRG0/PJ7 157 H2 CS1
98 N11 ICS2 128 P4 TIN0/PH0 158 H4 CS2
/PA1
/PA2
99 P12 ICS1 129 R3 TIN1/PPG3/PH1 159 H3 CS3/PA3
100 R13 ICS0 130 M5 TIN2/TRG3/PH2 160 H1 CS4
101 M10 TRST
131 N4 V
SS
161 G1 CS5/PPG2/PA5
/TRG2/PA4
102 N10 C 132 P3 C 162 G2 CS6/PA6
103 P11 AV
CC
104 P10 AVRH 134 P2 DACK0/PB1 164 G4 V
105 R12 AVR 135 M4 DEOP0/PB2 165 F1 V
133 R2 DREQ0/PB0 163 G3 CS7/PA7
SS
CC
106 R11 AN3 136 L5 DREQ1/PB3 166 F2 D00/P00
107 M9 AN2 137 N3 DACK1/TRG1/PB4 167 F3 D01/P01
108 N9 AN1 138 M3 DEOP1/PPG1/PB5 168 E1 D02/P02
109 P9 AN0 139 N2 IOWR
/PB6 169 E2 D03/P03
110 R10 AV
111 R9 INT0/PG0/ICU0 141 L4 V
112 P8 INT1/PG1/ICU1 142 P1 V
/AVRL 140 R1 IORD/PB7 170 F4 V
SS
CC
SS
171 E3 V
172 D1 D04/P04
SS
CC
113 M8 INT2/PG2/ICU2 143 L3 X0 173 D2 D05/P05
114 N8 INT3/PG3/ICU3 144 M2 X1 174 C1 D06/P06
115 R8 INT4/ATG
116 R7 INT5/SIN2/PG5 146 K4 V
117 P7 INT6/SOT2/PG6 147 K3 MD0 177 C2 V
/PG4/FRCK 145 N1 V
SS
CC
175 E4 D07/P07
176 D3 V
SS
CC
118 N7 INT7/SCK2/PG7 148 L2 MD1 178 B1 D08/P10
119 M7 V
CC
120 R6 SIN0/PJ0 150 M1 V
149 K2 MD2 179 B2 D09/P11
CC
180 D4 D10/P12
8
PIN DESCRIPTIONS
■
• Except for Power supply, GND, and Tool pins
Pin no.
MB91302A MB91V301A
Pin name
I/O circuit
type
MB91301 Series
Function
132 to 139
142 to 144,
1 to 5
8 to 15 11 to 18
18 to 25
28 33
29 34
166 to 169,
172 to 175
178 to 180, 2,
5 to 8
21 to 24,
27 to 30
D00 to D07
J
P00 to P07
D08 to D15
J
P10 to P17
D16 to D23
J
P20 to P27 Can be used as ports in 8-bit external bus mode.
D24 to D31 C
RDY
J
P80
BGRNT
J
P81
External data bus bits 0 to 7. It is available in the
external bus mode.
Can be used as ports in 8-bit or 16-bit external bus
mode.
External data bus bits 8 to 15.
It is available in the external bus mode.
Can be used as ports in 8-bit or 16-bit external bus
mode.
External data bus bits 16 to 23.
It is available in the external bus mode.
External data bus bits 24 to 31.
It is available in the external bus mode.
External ready input. The pin has this function when
external ready input is enabled.
General purpose input/output port. The pin has this
function when external ready input is disabled.
Acknowledge output for external bus release.
Outputs "L" when the external bus is released. The
pin has this function when output is enabled.
General purpose input/output port. The pin has this
function when output is disabled for external bus
release acknowledge.
BRQ
30 35
P82
31 36 RD
WR0
32 37
/ (UUB) /
DQMUU
External bus release request input. Input "1" to
request release of the external bus. The pin has this
J
C External bus read strobe output.
C
function when input is enabled.
General purpose input/output port. The pin has this
function when the external bus release request
input is disabled.
External bus write strobe output. When WR
as the write strobe, this becomes the byte-enable
pin (UUB
Select signal (DQMUU) of D31 to D24 at using of
SDRAM.
).
is used
(Continued)
9
MB91301 Series
Pin no.
MB91302A MB91V301A
33 38
34 39
35 40
36 43
37 40
38 45
39 46 P93 C General purpose input/output port.
Pin name
/ (ULB) /
WR1
DQMUL
P85
/ (LUB) /
WR2
DQMLU
P86
/ (LLB) /
WR3
DQMLL
P87
SYSCLK
P90
MCLKE
P91
MCLK
P92
I/O circuit
type
J
J
J
C
J
C
Function
External bus write strobe output. The pin has this
function when WR1 output is enabled. When WR is
used as the write strobe, this becomes the byteenable pin (ULB
D16 at using of SDRAM.
General purpose input/output port. The pin has this
function when the external bus write-enable output
is disabled.
External bus write strobe output. The pin has this
function when WR2 output is enabled. When WR is
used as the write strobe, this becomes the byteenable pin (LUB
D05 at using of SDRAM.
General purpose input/output port. The pin has this
function when the external bus write-enable output
is disabled.
External bus write strobe output. The pin has this
function when WR3 output is enabled. When WR is
used as the write strobe, this becomes the byteenable pin (LLB
D00 at using of SDRAM.
General purpose input/output port. The pin has this
functions when the external bus write-enable output
is disabled.
System clock output. The pin has this function when
system clock output is enabled. This outputs the
same clock as the external bus operating frequency.
(Output halts in stop mode.)
General purpose input/output port. The pin has this
function when system clock output is disabled.
Clock enable signal for memory.
General purpose input/output port. The pin has this
function when clock enable output is disabled.
Memory clock output. The pin has this function
when memory clock output is enabled. This outputs
the same clock as the external bus operating
frequency. (Output halts in sleep mode.)
General purpose input/output port. The pin has this
function when memory clock output is disabled.
). Select signal (DQMUL) of D23 to
). Select signal (DQMLU) of D08 to
). Select signal (DQMLL) of D07 to
(Continued)
10
MB91301 Series
Pin no.
MB91302A MB91V301A
40 49
41 50
42 51
45 to 52 54 to 61 A00 to A07 C External address bits 0 to 7.
55 to 62 64 to 71 A08 to A15 C External address bits 8 to 15.
64 to 67 74 to 77
Pin name
AS
LBA
SRAS
P94
BAA
SCAS
P95
WR
SWE
P96
A16 to A19
P60 to P63
I/O circuit
type
J
J
J
J
Function
Address strobe output. The pin has this function
when ASE
“1”.
Address strobe output for burst flash ROM. The pin
has this function when ASE
register 9 is enabled “1”.
RAS single for SDRAM. This pin has this function
when ASE
“1”.
General purpose input/output port. The pin has this
function when ASE
"0" general purpose port.
Address advance output for burst Flash ROM. The
pin has this function when BAAE bit of port function
register (PFR9) is enabled.
CAS signal for SDRAM. This pin has this function
when BAAE bit of port function register (PFR9) is
enabled.
General purpose input/output port. The pin has this
function when BAAE bit of port function register is
general purpose port.
Memory write strobe output. This pin has this
function when WRXE bit of port function register is
enabled.
Write output for SDRAM. This pin has this function
when WRXE bit of port function register is enabled.
General purpose input/output port. This pin has this
function when WRXE bit of port function register is
general purpose port.
External address bits 16 to 19. It is available in
external bus mode.
Can be used as ports when external address bus is
not used.
bit of port function register 9 is enabled
bit of port function register 9 is enabled
bit of port function register 9 is
bit of port function
(Continued)
11
MB91301 Series
Pin no.
MB91302A MB91V301A
68 78
69 79
70 80
Pin name
SDA0
A20
P64
SCL0
A21
P65
SDA1
A22
P66
I/O circuit
type
T
T
T
Function
2
Data input pin for I
enable when typical operation of I
C bus function. This function is
2
C is enable. The
port output must remains off unless intentionally
turned on. (Open drain output) (This function is only
for MB91302A, MB91V301A.)
External address bus bit 20.
2
This function is enable during prohibited I
C
operation and using external bus.
General-purpose I/O port.
2
This function is enable during prohibited I
C and
nonused external address bus.
CLK input pin for I
enable when typical operation of I
2
C bus function. This function is
2
C is enable. The
port output must remains off unless intentionally
turned on. (open drain output) (This function is only
for MB91302A, MB91V301A.)
External address bus bit 21.
2
This function is enable during prohibited I
C
operation and using external bus.
General-purpose I/O port.
2
This function is enable during prohibited I
C and
nonused external address bus.
DATA input pin for I
enable when typical operation of I
2
C bus function. This function is
2
C is enable. The
output must remains off unless intentionally turned
on. (open drain output) (This function is only for
MB91302A, MB91V301A.)
External address bus bit 20.
2
This function is enable during prohibited I
C
operation and using external bus.
General-purpose I/O port.
2
This function is enable during prohibited I
C and
nonused external address bus.
(Continued)
12
MB91301 Series
Pin no.
MB91302A MB91V301A
Pin name
I/O circuit
type
CLK input pin for I
enable when typical operation of I
SCL1
port output must remains off unless intentionally
turned on. (open drain output) (This function is only
for MB91302A, MB91V301A.)
71 81
A23
T
External address bus bit 21.
This function is enable during prohibited I
operation and using external bus.
General-purpose I/O port.
P67
This function is enable during prohibited I
operation and nonused external address bus.
76 to 79 106 to 109 AN3 to AN0 D Analog input pin.
External interrupt inputs. These inputs are used con-
INT0 to INT3
tinuously when the corresponding external
interrupt is enabled. In this case, do not output to
these ports unless doing so intentionally.
81 to 84 111 to 114
PG0 to PG3 General purpose input/output ports.
V
Input capture input pins. These inputs are used con-
ICU0 to ICU3
tinuously when selected as input capture inputs. In
this case, do not output to these ports unless
doing so intentionally.
External interrupt input. These inputs are used
INT4
continuously when the corresponding external
interrupt is enabled. In this case, do not output to
these ports unless doing so intentionally.
External trigger input for A/D converter. This input is
used continuously when selected as the A/D
converter start trigger. In this case, do not output to
85 115
ATG
V
this port unless doing so intentionally.
PG4 General purpose input/output ports.
External clock input pin for free-run timer. This input
FRCK
is used continuously when selected as the external
clock input pin for the free-run timer. In this case, do
not output to this port unless doing so intentionally.
External interrupt input. These inputs are used
INT5
continuously when the corresponding external
interrupt is enabled. In this case, do not output to
these ports unless doing so intentionally.
86 116
SIN2
V
UART2 data input pin. This input is used continuously when UART2 is performing input. In this case, do
not output to this port unless doing so intentionally.
PG5 General purpose input/output port.
Function
2
C bus function. This function is
2
C is enable. The
2
C
2
C
(Continued)
13
MB91301 Series
Pin no.
MB91302A MB91V301A
87 117
88 118
90 120
91 121
92 122
93 123
94 124
95 125
96 126
Pin name
INT6
SOT2
PG6 General purpose input/output port.
INT7
SCK2
PG7 General purpose input/output port.
SIN0
PJ0 General purpose input/output port.
SOT0
PJ1 General purpose input/output port.
SCK0
PJ2 General purpose input/output port.
SIN1
PJ3 General purpose input/output port.
SOT1
PJ4 General purpose input/output port.
SCK1
PJ5 General purpose input/output port.
PPG0
PJ6 General purpose input/output port.
I/O circuit
type
V
V
U
U
U
U
U
U
U
Function
External interrupt input. This input is used
continuously when the corresponding external
interrupt is enabled. In this case, do not output to
these ports unless doing so intentionally.
UART2 data output pin. The pin has this function
when UART2 data output is enabled.
External interrupt input. This input is used
continuously when the corresponding external
interrupt is enabled. In this case, do not output to
these ports unless doing so intentionally.
UART2 clock input/output pin. The pin has this
function when UART2 clock output is enabled.
UART0 data input pin. This input is used continuously
when UART0 is performing input. In this case, do not
output to this port unless doing so intentionally.
UART0 data output pin. The pin has this function
when UART0 data output is enabled.
UART0 clock input/output pin. The pin has this
function when UART0 clock output is enabled.
UART1 data input pin. This input is used continuously
when UART1 is performing input. In this case, do not
output to this port unless doing so intentionally.
UART1 data output pin. The pin has this function
when UART1 data output is enabled.
UART1 clock input/output pin. The pin has this
function when UART1 clock output is enabled.
PPG timer output. This pin has this function when
PPG0 output is enabled.
(Continued)
14
MB91301 Series
Pin no.
MB91302A MB91V301A
97 127
98 128
99 129
100 130
103 133
104 134
105 135
Pin name
TRG0
PJ7 General purpose input/output port.
TIN0
PH0 General purpose input/output port.
TIN1
PPG3
PH1 General purpose input/output port.
TIN2
TRG3
PH2 General purpose input/output port.
DREQ0
PB0 General purpose input/output port.
DACK0
PB1 General purpose input/output port.
DEOP0
PB2 General purpose input/output port.
I/O circuit
type
U
J
J
J
J
J
J
Function
External trigger input for PPG timer.
This input is used continuously when the
corresponding timer input is enabled. In this case, do
not output to this port unless doing so intentionally.
Reload timer input. This input is used continuously
when the corresponding timer input is enabled. In
this case, do not output to this port unless doing so
intentionally.
Reload timer input. This input is used continuously
when the corresponding timer input is enabled. In
this case, do not output to this port unless doing so
intentionally.
PPG timer output. The pin has this function when
PPG3 output is enabled.
Reload timer input. This input is used continuously
when the corresponding timer input is enabled. In
this case, do not output to this port unless doing so
intentionally.
External trigger input for PPG timer. This input is
used continuously when the corresponding timer
input is enabled. In this case, do not output to this
port unless doing so intentionally.
External input for DMA transfer requests. This input
is used continuously when selected as a DMA
activation trigger. In this case, do not output to this
port unless doing so intentionally.
External acknowledge output for DMA transfer
requests. The pin has this function when outputting
DMA transfer request acknowledgement is enabled.
Completion output for DMA external transfer. The
pin has this function when outputting DMA transfer
completion is enabled.
(Continued)
15
MB91301 Series
Pin no.
MB91302A MB91V301A
106 136
107 137
108 138
109 139
110 140
112 143 X0 A Clock (oscillation) input.
113 144 X1 A Clock (oscillation) output.
116 to 118 147 to 149 MD0 to MD2 G
119 152 INIT
120 053 NMI
Pin name
DREQ1
PB3
DACK1
TRG1
PB4 General purpose input/output port.
DEOP1
PPG1
PB5 General purpose input/output port.
IOWR
PB6
IORD
PB7
I/O circuit
type
DMA External input for DMA transfer requests. This
input is used continuously when selected as a DMA
activation trigger. In this case, do not output to this
J
J
J
J
J
B
M NMI (Non Maskable Interrupt) input (“L” active)
port unless doing so intentionally.
General purpose input/output port. The pin has this
function when completion output and stop input are
disabled for DMA transfer.
External acknowledge output for DMA transfer
requests. The pin has this function when outputting
DMA transfer request acknowledgement is enabled.
External trigger input for PPG timer. This input is
used continuously when the corresponding timer
input is enabled. In this case, do not output to this
port unless doing so intentionally.
Completion output for DMA external transfer. The
pin has this function when outputting DMA transfer
completion is enabled.
PPG timer output. The pin has this function when
PPG1 bit is enabled.
Write strobe output for DMA fly-by transfer. The pin
has this function when outputting a write strobe for
DMA fly-by transfer is enabled.
General purpose input/output port. The pin has this
function when outputting a write strobe for DMA
fly-by transfer is disabled.
Read strobe output for DMA fly-by transfer. The pin
has this function when outputting a read strobe for
DMA fly-by transfer is disabled.
General purpose input/output port. The pin has this
function when outputting a write strobe for DMA
fly-by transfer is disabled.
Mode pins 0 to 2. The levels applied to these pins
set the basic operating mode. Connect V
External reset input (Reset to initialize settings)
(“L” active)
Function
or VSS.
CC
(Continued)
16
(Continued)
Pin no.
MB91302A MB91V301A
122 156
123 157
124 158
125 159
126 160
127 161
128 162
129 163
Pin name
CS0
PA0
CS1
PA1
CS2
PA2
CS3
PA3
CS4
TRG2
PA4
CS5
PPG2
PA5
CS6
PA6
CS7
PA7
I/O circuit
type
J
J
J
J
J
J
J
J
MB91301 Series
Function
Chip select 0 output. The pin has this function when
chip select 0 output is enabled.
General purpose input/output port. The pin has this
function when chip select 0 output is disabled.
Chip select 1 output. The pin has this function when
chip select 1 output is enabled.
General purpose input/output port. The pin has this
function when chip select 1 output is disabled.
Chip select 2 output. The pin has this function when
chip select 2 output are enabled.
General purpose input/output port. The pin has this
function when chip select 2 output is disabled.
Chip select 3 output. The pin has this function when
chip select 3 output are enabled.
General purpose input/output port. The pin has this
function when chip select 3 output is disabled.
Chip select 4 output. The pin has this function when
chip select 4 output is enabled.
External trigger input for PPG timer. This input is
used continuously when the corresponding timer
input is enabled. In this case, do not output to this
port unless doing so intentionally.
General purpose input/output port. The pin has this
function when chip select 4 output is disabled.
Chip select 5 output. The pin has this function when
chip select 5 output are enabled.
PPG timer output. The pin has this function when
PPG2 bit is enabled.
General purpose input/output port. The pin has this
function when chip select 5 output and PPG timer
output are disabled.
Chip select 6 output. The pin has this function when
chip select 6 output is enabled.
General purpose input/output port. The pin has this
function when chip select 6 output are disabled.
Chip select 7 output. The pin has this function when
chip select 7 output are enabled.
General purpose input/output port. The pin has this
function when chip select 7 output is disabled.
17
MB91301 Series
I/O CIRCUIT TYPE
■
Type Circuit Remarks
X1
Clock input
•Oscillation feedback resistance
approx. 1 MΩ
A
X0
Standby control
•CMOS hysteresis input with pull-up
resistor
P-ch
P-ch
B
N-ch
Digital input
P-ch
•CMOS level I/O with standby control
= 4 mA
•I
OL
Digital output
N-ch
Digital output
C
18
Digital input
Standby control
•Analog input
With switch
P-ch
N-ch
D
Analog input
Control
(Continued)
MB91301 Series
Type Circuit Remarks
P-ch
•CMOS level output
No standby control
G
N-ch
Digital input
Pull-up control
P-chP-ch
Digital output
N-ch
J
Digital output
•With Pull-up control
•CMOS level I/O
with standby control
•With Pull-up control
= 4 mA
•I
OL
Digital input
Standby control
Pull-up control
P-chP-ch
Digital output
N-ch
K
Digital output
•With Pull-up control
•CMOS level output
CMOS level hysteresis input
with standby control
= 4 mA
•I
OL
M
Digital input
Standby control
Pull-up control
P-ch
P-ch
Digital output
L
N-ch
Digital output
•With Pull-up control
•CMOS level output
CMOS level hysteresis input
no standby control
•I
= 4 mA
OL
Digital input
P-ch
N-ch
•CMOS level hysteresis input
no standby control
Digital input
(Continued)
19
MB91301 Series
Type Circuit Remarks
P-ch
Digital output
•Output buffer
•CMOS level output
= 4 mA
•I
OL
N
O
N-ch
Digital output
Digital input
•Input buffer
•CMOS level input
•Input buffer with pull-down
•Pull-down resistor value = 25 kΩ
P
N-ch
Digital input
approx. (Typ)
•Input buffer with Pull-up
P-ch
Q
P-ch
Digital input
Digital output
•I/O buffer with pull-down
•CMOS level output
= 4 mA
•I
OL
20
R
N-ch
N-ch
Digital output
Digital input
P-ch
S
N-ch
Digital output
Digital output
•I/O buffer
•CMOS level output
= 4 mA
•I
OL
Digital input
(Continued)
MB91301 Series
(Continued)
Type Circuit Remarks
•N-ch open-drain output
P-ch
P-ch
Pull-up control
Digital output with
T
N-ch
open-drain control
Digital output
Digital input
P-ch
Digital output
N-ch
U
Digital output
•CMOS level I/O with standby control
•Without pull-up control
= 4 mA
OL
•I
•CMOS level output
•CMOS level hysteresis input
with standby control
•5 V tolerant
•I
= 4 mA
OL
Digital input
•CMOS level output
•CMOS level hysteresis input
P-ch
Digital output
V
N-ch
with standby control
•5 V tolerant
= 4 mA
•I
OL
Digital output
Digital input
21
MB91301 Series
HANDLING DEVICES
■
❍MB91301 series
•
Operation at start-up
Always apply a settings initialization (INIT) to the INIT
pin immediately after turning on the power.
Also, in order to provide a delay while the oscillator circuits stabilize immediately after start-up, maintain the “L”
level input to the INIT
by the INIT
•
External clock input at start-up
pin initializes the oscillation stabilization delay time to the minimum setting.)
pin for the required stabilization delay time. (The initialization processing (INIT) triggered
At power-on start-up, always input a clock signal until the oscillation stabilization delay time is ended.
•
Output indeterminate at power-on time
When the power is turned on, the output pin may remain indeterminate until the internal power supply becomes
stable.
•
Built-in DC/DC regulator
This device has a built-in regulator, requiring 3.3 V input to the Vcc pin and a bypass capacitor of approximately
4.7 µF connected to the C pin for the regulator.
3.3 V VCC
AVCC
AVRH
0.05 µF
AVR
AV
SS/AVRL
C
4.7 µF
V
SS
MB91301 series
GND
SS
V
Note of built-in DC/DC regulator
•
Note on use of the A/D converter
As the MB91301 series contains an A/D converter, be sure to supply po wer to A Vcc at 3.3 V and insert a capacitor
of at least 0.05 µF between the AVR pin and the AVss/AVRL pin.
3.3 V AVCC
AVRH
0.05 µF
AVR
SS/AVRL
AV
MB91301 series
Note on Use of A/D Converter
22
MB91301 Series
•
Preventing Latchup
at input and output
When CMOS integrated circuit devices are subjected to applied voltages higher than V
pins, or to voltages lower than V
, as well as when voltages in excess of rated levels are applied between V
SS
and VSS, a phenomenon known as latchup can occur. When a latchup condition occurs, the supply current can
increase dramatically and may destroy semiconductor elements. In using semiconductor devices, always take
sufficient care to avoid exceeding maximum ratings.
•
Power supply pins
Devices with multiple V
and VSS supply pins are designed to prevent problems such as latchup occurring by
CC
providing internal connections between pins at the same potential. However, in order to reduce unwanted
radiation, prevent abnor mal operation of strobe signals due to a rise in ground level, and to maintain the total
output current ratings, all such pins should always be connected externally to power supply or ground. Also,
ensure that the impedance of the V
and VSS connections to the power supply are as low as possible.
CC
In addition, it is recommended that a bypass capacitor of approximately 0.1µF be connected between V
V
. Connect the capacitor close to the VCC and VSS pins.
SS
•
Crystal oscillators
Noise in proximity to the X0 and X1 pins can cause abnormal operation in this device. Pr inted circuit boards
should be designed so that the X0 and X1 pins, crystal (or ceramic) oscillator, and b ypass capacitor connected
to ground are placed as close together as possible.
Also, to ensure stab le operation, it is strongly recommended that the printed circuit board art work be designed
such that the X0 and X1 pins are surrounded by ground.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
CC
CC
CC
and
•
Treatment of NC and OPEN pins
Pins marked as "NC" or "OPEN" must be left open-circuit.
•
Treatment of unused input pins
If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected
to pull-up or pull-down resistors.
•
Mode pins (MD0 to MD2)
These pins should be connected directly to V
due to noise, design the printed circuit board such that the distance between the mode pins and V
or VSS. To prev ent the device erroneously s witching to test mode
CC
or VSS is
CC
as short as possible and the connection impedance is low.
•
Remarks for External Clock Operation
When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to
X0 must be supplied to X1 pin. Howe v er, in this case the stop mode must not be used (because X1 pin stops at
“H” output in stop mode) .
When operating at 12.5 MHz or less, the microcontroller can be used with the clock signal supplied only to pin X0.
“Using an external clock (normal) and (12.5 MHz) ” shows examples of how the MB91301 uses the e xternal clock.
23
MB91301 Series
X0
X1
MB91301 series
Note: Stop mode (oscillation stop mode) can not be used.
Using an external clock (normal)
X0
OPEN
X1
MB91301 series
Using an external clock (12.5 MHz Max)
•
Notes on during operation of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
•
Clock control block
For L-level input to the INIT
•
Bit search module
pin, allow for the regulator settling time or oscillation settling time.
The 0-detection, 1-detection, and transition-detection data registers (BSD0, BSD1, and BSDC) are only wordaccessible.
•
I/O port access
Byte access only for access to port
•
Shared port function switching
To switch a pin that also serves as a port, use the port function register (PFR). Note, however, that bus pins are
switched depending on external bus settings.
•
D-bus memory
Do not set a code area in D-bus memory.
No instruction fetch is performed to the D-bus.
Instruction fetches to the D-bus area result in incorrect data interpreted as code, which can cause the microcontroller to lose control.
Do not set a data area in I-bus memory.
24
MB91301 Series
•
I-bus memory
Do not set a stack area or vector table in I-bus memory.
It may cause a hang during EIT processing (including RETI).
Recovery from the hang requires a reset.
Do not perform DMA transfer to I-bus memory.
•
Low-power consumption modes
• To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the
TBCR, or time-base counter control register) and be sure to use the following sequence:
(LDI #value_of_standby, R0)
(LDI #_STCR, R12)
STB R0, @R12 ; Write to standby control register (STCR)
LDUB @R12, R0 ; Read STCR for synchronous standby
LDUB @R12, R0 ; Read STCR again for dummy read
NOP ; NOP x 5 for timing adjustment
NOP
NOP
NOP
NOP
• If you use the monitor debugger, follow the precautions below:
Do not set a breakpoint within the above array of instructions.
Do not single-step the above array of instructions.
•
Prefetch
When accessing a prefetch-enabled little endian area, use word access only (access in 32 bits).
Byte or halfword access results in wrong data read.
•
MCLK and SYSCLK
MCLK causes a stop in SLEEP/STOP mode while SYSCLK causes a stop only in STOP mode. Use either
depending on each application.
•
Pull-up control
When function pins listed in the AC specifications (such as exter nal bus control pins) have pull-up control,
enabling the pull-up resistor for a pin causes the actual pin load conditions to change. As all AC specifications
for this device were measured under the condition of pull-up resistors disabled, the values are not guaranteed
of AC specifications when pull-up resistors are enabled.
Even if the pull-up resistor is set to enabled f or a pin, if the HIZ bit in the standby control register (STCR) specifies
setting output pins to high impedance during stop mode (HIZ = 1) , changing to stop mode (STOP = 1) causes
the pull-up resistor to be disabled.
25
MB91301 Series
•
R15 (General purpose register)
When any of the following instructions is executed, the SSP* or USP* value is not used as R15, resulting in an
incorrect value written to memory.
AND R15, @Ri ANDH R15, @Ri ANDB R15, @Ri
OR R15, @Ri ORH R15, @Ri ORB R15, @Ri
EOR R15, @Ri EORH R15, @Ri EORB R15, @Ri
XCHB @Rj, R15
* : R15 is a virtual register. When a program attempts to access R15, the SSP or USP is accessed depending
on the status of the “S” flag as an SP flag. When coding the above ten instructions using an assembler,
specify a general-purpose register other than R15.
•
RETI instruction
Please do not neither control register of the instruction cache nor the data access to RAM of the instruction
cache immediately before the instruction of RETI.
•
Notes on the PS register
Since some instructions manipulate the PS register earlier, the following exceptions may cause the interrupt
handler to break or the PS flag to update its display setting when the debugger is being used. As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs operations before and after the EIT as specified in either case.
• The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS
instruction is (a) halted by a user interrupt or NMI, (b) single-stepped, or (c) breaks in response to a data
event or emulator menu:
(1) D0 and D1 flags are updated earlier.
(2) The EIT handler (user interrupt/NMI or emulator) is executed.
(3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are
updated to the same values as those in (1) above.
• The following operations are performed when the ORCCR/STILM/MOV Ri and PS instructions are executed
to enable interruptions when a user interrupt or NMI trigger event has occurred.
(1) The PS register is updated earlier.
(2) The EIT handler (user interrupt/NMI or emulator) is executed.
(3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to the
same value as that in (1) above.
•
A/D converter
When the device is turned on or returns from a reset or stop, it takes time f or the external capacitor to be charged,
requiring the A/D converter to wait for at least 10 ms.
•
Watchdog timer
The watchdog timer function of this model monitors that a program dela ys a reset within a certain period of time
and resets the CPU if the program fails to delay it, for example, because the progr am runs out of control. Once
the watchdog timer function is enabled, therefore, the watchdog timer continues to operate until a reset takes
place.
An exception, f or example during stop, sleep and DMA tr ansfer modes, is the automatic dela ying of a reset under
a condition in which the CPU stops program execution.
Note, however, that a watchdog reset may not occur in the above state caused when the system runs out of
control. If this is the case, use the external INIT
pin to cause a reset (INIT) .
26
❍Unique to the evaluation chip MB91V301A
•
Tool reset
MB91301 Series
On an evaluation board, use the chip with INIT
•
Simultaneous occurrences of a software break and a user interrupt/NMI
When a software break and a user interrupt /NMI take place at the same time, the emulator deb ugger can cause
the following phenomena:
• The debugger stops pointing to a location other than the programmed breakpoints.
• The halted program is not re-executed correctly.
If these phenomena occur, use a hardware break instead of the software break. If the monitor debugger has
been used, avoid setting any break at the relevant location.
•
Single-stepping the RETI instruction
If an interrupt occurs frequently during single stepping, execute only the rele v ant processing routine repeatedly
after single-stepping RETI. This will prevent the main routine and low-interrupt-level programs from being
ex ecuted. Do not single-step the RETI instruction for a voidance purposes. When the debugging of the rele v ant
interrupt routine becomes unnecessary, perform debugging with that interrupt disabled.
•
Operand break
A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a data
event break to access to the area containing the address of a system stack pointer.
and TRST connected together.
•
ICE startup sequence
When using the ICE, when you start debugging, ensure that the bus configuration is set correctly for the area
being used before downloading. After turning on the power to the target, the states of the RD
pins are undefined until you perform the abov e setting. Accordingly , include enabling pull-up as part of the startup
sequence. If using these pins as general-purpose ports, set as output por ts to prevent conflict with the output
signals during the time the pin states are undefined.
External bus width
Pin name
RD
WR0
(P85) Pull-up Pull-up *
WR1
(P86) Pull-up * *
WR2
(P87) Pull-up * *
WR3
* : Use as output ports.
32 bit 16 bit 8 bit
Pull-up Pull-up Pull-up
Pull-up Pull-up Pull-up
and WR0 to WR3
27
MB91301 Series
•
Configuration batch file
The example batch file below sets the mode v ector and sets up the CS0 configur ation register f or the download
area. Use values appropriate to the hardware in the wait, timing, and other settings.
#--------------------------------------------------------# Set MODR (0x7fd) =Enable In memory+16 bit External Bus
set mem/byte 0x7fd=0x5
#--------------------------------------------------------# Set ASR0 (0x640); 0x0010_0000 - 0x002f_ffff
set mem/halfword 0x640=0x0010
#--------------------------------------------------------# Set ACR0 (0x642)
# ; ASZ [3:0]=0101:2 Mbytes
# ; DBW [1:0]=01:16 bit width, automatically set from
MODR
# ; BST [1:0]=00:1 burst (16 bit x 2)
# ; SREN=0:Disable BRQ
# ; PFEN=1:Enable Pre fetch buffer
# ; WREN=1:Enable Write operation
# ; LEND=0: Big endian
# ; TYPE [3:0]=0010:WEX: Disable RDY
set mem/harfword 0x642=0x5462
#--------------------------------------------------------# Set AWR0 (0x660)
# ; W15-12=0010:auto wait=2
# ; WR07, 06=01:RD, WR delay=1cycle
# ; W05, 04=01:WR->WR delay=1cycle (for WEX)
# ; W03 =1:MCLK->RD/WR delay=0.5cycle
# ; :for async Memory
# ; W02 =0:ADR->CS delay=0
# ; W01 =0:ADR->RD/WR setup 0cycle
# ; W00 =RD/WR->ADR hold 0cycle
set mem/halfword 0x660=0x2058
#---------------------------------------------------------
•
Emulation memory
If SRAM as the emulation memory is built on target board, SRAM for be accessed by RD, WR signal, and +BYTE
control signal can not be used. (The external bus is initialized to the b us mode for accessing RD
28
, WRn after reset.)
BLOCK DIAGRAM
M
S
S
1
1
1
■
• MB91302A, MB91V301A
MB91301 Series
FR CPU
Core
32 32
Bit search module
MB91302A : RAM 4 KB
Instruction Cache
4 KB
DMAC
5 channels
DREQ0, DREQ
DACK0, DACK
DEOP0, DEOP
IOWR
IORD
MB91V301A : RAM 8 KB (stack)
A23 to A00
D31 to D16
D15 to D00
RD, WR
WR0 to WR3
CS0 to CS7
RDY
BRQ
BGRNT
SYSCLK
MCLK
AS
MCLKE
X0, X1
D0 to MD2
INIT
MB91302A : ROM 4 KB*
MB91V301A : RAM 8 KB
Clock
control
32
Adapter
16
32
16
Bus
Converter
32
External memory
I/F
Interrupt
controller
SDRAM I/F
INT0 to INT7
NMI
SIN0 to SIN2
OT0 to SOT2
CK0 to SCK2
8 channels
External interrupts
3 channels
UART
4 channels
PPG timer
SRAS
SCAS
SWE
DQMUU, L
DQMLU,L
LBA
BAA
PPG0 to PPG3
TRG0 to TRG3
3 channels
U-TIMER
AN0 to AN3
ATG
AVRH, AV
AVSS/AVRL
TIN0 to TIN2
CC
4 channels
A/D converter
3 channels
PORT I/F
2 channels
2
I
C I/F
PORT
SDA0, SDA1
SCL0, SCL1
Reload timer
Free Run Timer
FRCK
4 channels
Input Capture
ICU0 to ICU3
* : ROM has non-ROM model, the optimal real time OS internal model, and the IPL (Internal Program
Loader) internal model by adding the user ROM model.
29
MB91301 Series
CPU
■
1. Memory Space
The FR family has 4 Gbytes (232 addresses) of logical address space with linear access from the CPU.
• Direct Addressing Areas
The following areas of address space are used for I/O operations.
These areas are called direct addressing areas, in which the address of an operand can be specified directly
during an instruction.
The direct areas differ according to the size of the data accessed, as follows.
→ byte data access : 000
→ half word data access : 000
→ word data access : 000
to 0FF
H
to 1FF
H
to 3FF
H
H
H
H
30
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