FUJITSU MB91302A, MB91V301A DATA SHEET

FUJITSU SEMICONDUCTOR

ROM variation

DATA SHEET

32-Bit Proprietary Microcontroller

CMOS

FR60 MB91301 Series MB91302A/V301A

DESCRIPTION

■

The MB91301 series are a line of microcontrollers based on a 32-bit RISC CPU core (FR family) , incorporating a variety of I/O resources and a bus control mechanism for embedded control that requires the processing of a high-performance, fast CPU as well as an SDRAM interface that can connect SDRAM directly to the chip. The large address space supported by the 32-bit CPU addressing means that operation is primarily based on external bus access although instruction cache memory of 4 Kbytes and RAM of 4 Kbytes( for data) are included for high-speed execution of CPU instructions. The MB91302A and MB91V301A are FR60 products based on the FR30/40 CPU with enhanced bus access for higher speed operation. The device specifications include a D/A con verter to facilitate motor control and are ideal for use in DVD players that support fly-by transfer.

DS07-16502-3E

FEATURES

■

The MB91301 series is a line of ICs with various programs embedded in internal ROM.

Product name

MB91302A

PACKAGES

■

Built-in the real

time OS version

144-pin, Plastic LQFP 179-pin, Ceramic PGA

(FPT-144P-M12) (PGA-179C-A03)

(Internal Program Loader) version

Built-in IPL

User ROM

version

Without ROM

version

(Continued)

MB91301 Series

1. FR CPU

• 32-bit RISC, load/store architecture, 5-stage pipeline

• 68 MHz internal operating frequency (Max) [external (Max) 68 MHz] (when using PLL with base frequency (Max) = 17 MHz)

• General purpose registers : 32 bits×16

• 16-bit fixed length instructions (basic instructions) , 1 instruction per cycle

• Instruction set optimized for embedded applications: Memory-to-memory transfer, bit manipulation, barrel shift etc.

• Instructions adapted for high-level languages : Function entry/exit instructions, multiple-register load/store instructions

• Easier assembler coding : Register interlock function

• Branch instructions with delay slots : Reduced overhead time in branch executions

• Built-in multiplier with instruction-level support

Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles

• Interrupt (PC, PS save) : 6 cycles, 16 priority levels

2. Bus interface

• Operating frequency : Max 68 MHz (when using SDRAM)

• Full 24-bit address output (16 Mbytes memory space)

• 8-bit, 16-bit or 32-bit data input/output

• Built-in pre-fetch buffer

• Unused data and address pins can be used as general-purpose input/output ports.

• Eight fully independent chip select outputs, can be set in minimum 64 Kbytes units.

• Supports the following memory interfaces

Asynchronous SRAM, asynchronous ROM/Flash Page mode ROM/Flash ROM (selectable page size = 1, 2, 4, or 8) Burst mode ROM/Flash ROM (MBM29BL160D/161D/162D)

• SDRAM (FCRAM Type, CAS Latency 1 to 8, 2/4 bank products.)

• Address/Data multiplex bus (only 8/16-bit width)

• Basic bus cycle : 2 cycles

• Automatic wait cycle generation function can insert wait cycles, independently progr ammable for each memory area.

• RDY input for external wait cycles

• Endian setting of byte ordering (Big/Little) CS0

area only for big endian

• Prohibition setting of write (only for Read)

• Permission/prohibition setting of fetch into built-in cache

• Permission/prohibition setting of prefetch function

• DMA supports fly-by transfer with independent I/O wait control

• External bus arbitration can be used using BRQ and BGRNT

.

3. Built-in memory

•4 Kbytes DATA RAM

• 4 Kbytes RAM (MB91302A)

2

(Continued)

MB91301 Series

4. Instruction cache

• Size : 4 Kbytes

• 2-way set associative

• 128 blocks/way, 4 entries/block

• Lock function enables program code to be made cache-resident

• Areas not used for instruction cache can be used as instruction RAM

5. DMAC (DMA Controller)

• 5-channel (2-channel external-to-external)

• 3 transfer triggers : External pin, internal peripheral, software

• Capable of selecting an internal peripheral as a transfer source freely for each channel

• Addressing using 32-bit full addressing mode (increment, decrement, fixed)

• Transfer modes : Demand transfer, burst transfer, step transfer, or block transfer

• Supports fly-by transfer (between external I/O and memory)

• Selectable transfer data size : 8, 16, or 32-bit

6. Bit search module

• Searches words from MSB for position of first 1/0 bit value change

7. Reload Timers

• 16-bit timer : 3 channels

• Internal clock : 2 clock cycle resolution, divide by 2/8/32 selective

8. UART

• Full duplex, double buffer UART

• Independent 3 channels

• Data length : 7 bits to 9 bits (without parity) , 6 bits to 8 bits (with parity)

• Asynchronous (start-stop synchronized) or CLK-synchronous communications selectable Multi-processor mode

• Built-in 16-bit timer (U-TIMER) as a baud rate generator to generate arbitrary baud rates

• External clock can be used as transfer clock

• Variety of error detection functions (parity, frame, overrun)

9. Interrupt controller

• External interrupt input : 1 non-maskable interrupt pin and 8 normal interrupt pins (INT0 to INT7)

• Internal internal resources : UART, DMAC, A/D, U-TIMER, Delay interrupt, I

• Programmable priorities (16 levels) for all interrupts except the non-maskable interrupt

2

C, Free-run timer, Input capture

10. A/D converter

• 10-bit resolution, 4 channels

• Successive approximation type, conversion time : 4.1 µs at 34 MHz

• Built-in sample and hold circuit

• Conversion modes : Single con v ersion mode , scan con v ersion mode and repeat conversion mode selectable

• Conversion triggers : Software, external trigger and built-in timer selectable

11. I2C* interface

• Internal 2-channels master/slave transmit/receive

• Internal arbitration function, clock synch function

12. Free-run timer

• 16 bit : 1channel

(Continued)

3

MB91301 Series

(Continued)

13. Input capture

• 4 channels

14. Other interval timers

• 16-bit timer : 3 channels (U-TIMER)

• PPG timer : 4 channels

• Watchdog timer : 1 channel

15. Other features

• Reset resources : watchdog timer/software reset/ex ternal reset (INIT pin)

• Power-saving modes : Stop mode, sleep mode

• Clock control Gear function : Allows arbitrary different operating clock frequencies to be set for the CPU and peripherals. You can select one of the 16 gear clock factors of 1/1 to 1/16. PLL multiplication can also be selected. Note, however, that peripherals operate at a maximum of 34 MHz.

• CMOS technology : 0.25 µm

• Power supply (analog power supply): 3.3 V ± 0.3 V (internal regulator used)

* : Purchase of Fujitsu I

components in an I by Philips.

2

C components conveys a license under the Philips I2C Patent Rights to use, these

2

C system provided that the system conforms to the I2C Standard Specification as defined

PRODUCT LINEUP

■

MB91302A MB91V301A

Type

RAM

ROM has non-ROM model, the optimal real time

ROM

DSU ⎯ DSU4 Package

*1 : The Fujitsu product of real time OS REALOS/FR by conforming to the µITRON 3.0 is stored and optimized

with the MB91302A.

*2 : The ROM stores the IPL (Internal Program Loader) . Loading various programs can be executed from the

external system by the internal UART/SIO. Using this function, for example, writing on board to the Flash memory connected to the external can be executed.

OS internal model*

Loader) internal model*

Mask ROM product

(for volume production)

4 Kbytes

(only for data)

4 Kbytes

1

, and the IPL (Internal Program

2

by adding the user ROM

model.

LQFP-144

(0.4 mm pitch)

Evaluation version

(For evaluation and develop-

ment)

16 Kbytes

(data 8 KB+8 KB)

8 Kbytes (RAM)

PGA-179

4

PIN ASSIGNMENTS

P P

5

4

K

P

■

MB91301 Series

• MB91302A

DQMUU/WR0(UUB) 85/DQMUL/WR1(ULB) 86/DQMLU/WR2(LUB)

P87/DQMLL/WR3(LLB)

P13/D11 P14/D12 P15/D13 P16/D14 P17/D15

SS

V V

CC

P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 P26/D22 P27/D23

V

SS

V

CC

D24 D25 D26 D27 D28 D29 D30 D31

V

SS

V

CC

P80/RDY

P81/BGRNT

P82/BRQ

RD

P90/SYSCLK

(TOP VIEW)

D10/P12

D09/P11

D08/P10

VCCVSSD07/P07

D06/P06

D05/P05

D04/P04

D03/P03

D02/P02

D01/P01

D00/P00

VCCVSSCS7/PA7

CS6/PA6

CS5/PPG2/PA

CS4/TRG2/PA

CS3/PA3

CS2/PA2

CS1/PA1

CS0/PA0

VCCNMI

INIT

MD2

MD1

MD0

VCCVSSX1X0VCCIORD/PB7

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

3738394041424344454647484950515253545556575859606162636465666768697071

115

114

113

112

111

IOWR/PB6

110

109

108 107 106 105 104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

72

DEOP1/PPG1/PB5 DACK1/TRG1/PB4 DREQ1/PB3 DEOP0/PB2 DACK0/PB1 DREQ0/PB0 C V

SS

TIN2/TRG3/PH2 TIN1/PPG3/PH1 TIN0/PH0 TRG0/PJ7 PPG0/PJ6 SCK1/PJ5 SOT1/PJ4 SIN1/PJ3 SCK0/PJ2 SOT0/PJ1 SIN0/PJ0 V

CC

INT7/SCK2/PG7 INT6/SOT2/PG6 INT5/SIN2/PG5 INT4/ATG/PG4/FRC INT3/PG3/ICU3 INT2/PG2/ICU2 INT1/PG1/ICU1 INT0/PG0/ICU0 AV

SS

/AVRL AN0 AN1 AN2 AN3 AVR AVRH AV

CC

SS

CC

V

P93

P92/MCLK

P91/MCLKE

V

A00

A01

A02

P96/SWE/WR

P95/SCAS/BAA

94/SRAS/LBA/AS

A03

(FPT-144P-M12)

A04

A05

A06

A07

SS

V

CC

V

A08

A09

A10

A11

A12

A13

A14

A15

SS

V

P60/A16

P61/A17

P62/A18

P63/A19

CC

V

P65/A21/SCL0

P67/A23/SCL1

P64/A20/SDA0

P66/A22/SDA1

5

MB91301 Series

1

• MB91V301A (TOP VIEW)

INDEX

5

1

2

3

4

5

6

7

8

9

0

1

2

3

178 174 172 168 165 161 160 156 155 151 150 145 142

7

179 177

10 4 2

15 9 3

20 14 12

21 19 18

25 22 24 23

26 27 28 29

30 31 32 35

33 34 36

37 38 41

39 42 47 48

173

176

180

6

11

17

40 46

45

169

171

175

1

51 56

53

166

167

170

57

162

163

164

62

63

157

159

158

68

69

154

149

153

147

152

146

74 80 85

73

77

148

143

141

13616 13 8

91

81

144

138

135

130

125

119

113

107

101

96

90

86

139

137

131

126

122

118

114

108

102

98

93

92

134

132

128

124

121

117

112

109

104

103

99

94

140

133

129

127

123

120

116

115

111

110

106

105

100

4

5

43 44 49 54

50 52 55 60

ABCDEFGHJKLMNP

58

61

59

65

64

66

67

70

72

71

76

75

79

78

83

82

87

84

89

88

97

95

R

(PGA-179C-A03)

6

MB91301 Series

•

MB91V301A Pin No. Table

No. PIN Pin Name No. PIN Pin Name No. PIN Pin Name

1E5 N.C. 31B10 V

SS

61 E15 A07 2 C3 P13/D11 32 C10 V 3C4 V 4B3 V

SS

CC

33 A11 P80/RDY 63 G13 V 34 B11 P81/BGRNT 64 G14 A08

CC

62 G12 V

SS

CC

5 A1 P14/D12 35 D10 P82/BRQ 65 F15 A09 6 D5 P15/D13 36 C11 RD 7 A2 P16/D14 37 A12 DQMUU/WR0

8 C5 P17/D15 38 B12

9B4 V

10 A3 V

SS

CC

39 A13

40 D11

P85/DQMUL/WR1

P86/DQMLU/WR2

P87/DQMLL/WR3

11 D6 P20/D16 41 C12 V 12 C6 P21/D17 42 B13 V

(UUB) 67 H14 A11

(ULB

)

(LUB

)

(LLB

)

SS

CC

13 B5 P22/D18 43 A14 P90/SYSCLK 73 J13 V

66 G15 A10

68 H12 A12

69 H13 A13

70 H15 A14

71 J15 A15

72 J14 V

SS

CC

14 B6 P23/D19 44 B14 P91/MCLKE 74 J12 P60/A16 15 A4 P24/D20 45 D12 P92/MCLK 75 K15 P61/A17 16 A5 P25/D21 46 E11 P93 76 K14 P62/A18 17 D7 P26/D22 47 C13 V 18 C7 P27/D23 48 D13 V 19 B7 V 20 A6 V

SS

CC

49 C14 P94/SRAS/LBA/AS 79 L14 SCL0/P65/A21 50 A15 P95/SCAS/BAA 80 K12 SDA1/P66/A22

SS

CC

77 K13 P63/A19

78 L15 SDA0/P64/A20

21 A7 D24 51 E12 P96/SWE/WR 81 L13 SCL1/P67/A23 22 B8 D25 52 B15 V 23 D8 D26 53 E13 V

SS

CC

82 M15 V

83 M14 V

CC

24 C8 D27 54 D14 A00 84 N15 EWR3 25 A8 V 26 A9 V

SS

CC

55 C15 A01 85 L12 EWR2

56 F12 A02 86 M13 EWR1 27 B9 D28 57 F13 A03 87 N14 EWR0 28 C9 D29 58 E14 A04 88 P15 ECS 29 D9 D30 59 F14 A05 89 P14 EMRAM 30 A10 D31 60 D15 A06 90 M12 ICD3

(Continued)

7

MB91301 Series

(Continued)

No. PIN Pin Name No. PIN Pin Name No. PIN Pin Name

91 L11 ICD2 121 P6 SOT0/PJ1 151 L1 V

CC

92 N13 ICD1 122 N6 SCK0/PJ2 152 J4 INIT 93 N12 ICD0 123 R5 SIN1/PJ3 153 J3 NMI 94 P13 V 95 R15 V

SS

CC

124 P5 SOT1/PJ4 154 J2 V 125 M6 SCK1/PJ5 155 K1 V

SS

CC

96 M11 BREAK 126 N5 PPG0/PJ6 156 J1 CS0/PA0 97 R14 ICLK 127 R4 TRG0/PJ7 157 H2 CS1 98 N11 ICS2 128 P4 TIN0/PH0 158 H4 CS2

/PA1 /PA2

99 P12 ICS1 129 R3 TIN1/PPG3/PH1 159 H3 CS3/PA3 100 R13 ICS0 130 M5 TIN2/TRG3/PH2 160 H1 CS4 101 M10 TRST

131 N4 V

SS

161 G1 CS5/PPG2/PA5

/TRG2/PA4

102 N10 C 132 P3 C 162 G2 CS6/PA6 103 P11 AV

CC

104 P10 AVRH 134 P2 DACK0/PB1 164 G4 V 105 R12 AVR 135 M4 DEOP0/PB2 165 F1 V

133 R2 DREQ0/PB0 163 G3 CS7/PA7

SS

CC

106 R11 AN3 136 L5 DREQ1/PB3 166 F2 D00/P00 107 M9 AN2 137 N3 DACK1/TRG1/PB4 167 F3 D01/P01 108 N9 AN1 138 M3 DEOP1/PPG1/PB5 168 E1 D02/P02 109 P9 AN0 139 N2 IOWR

/PB6 169 E2 D03/P03 110 R10 AV 111 R9 INT0/PG0/ICU0 141 L4 V 112 P8 INT1/PG1/ICU1 142 P1 V

/AVRL 140 R1 IORD/PB7 170 F4 V

SS

CC

SS

171 E3 V 172 D1 D04/P04

SS

CC

113 M8 INT2/PG2/ICU2 143 L3 X0 173 D2 D05/P05 114 N8 INT3/PG3/ICU3 144 M2 X1 174 C1 D06/P06 115 R8 INT4/ATG 116 R7 INT5/SIN2/PG5 146 K4 V 117 P7 INT6/SOT2/PG6 147 K3 MD0 177 C2 V

/PG4/FRCK 145 N1 V

SS

CC

175 E4 D07/P07 176 D3 V

SS

CC

118 N7 INT7/SCK2/PG7 148 L2 MD1 178 B1 D08/P10 119 M7 V

CC

120 R6 SIN0/PJ0 150 M1 V

149 K2 MD2 179 B2 D09/P11

CC

180 D4 D10/P12

8

PIN DESCRIPTIONS

■

• Except for Power supply, GND, and Tool pins

Pin no.

MB91302A MB91V301A

Pin name

I/O circuit

type

MB91301 Series

Function

132 to 139

142 to 144,

1 to 5

8 to 15 11 to 18

18 to 25

28 33

29 34

166 to 169,

172 to 175

178 to 180, 2,

5 to 8

21 to 24,

27 to 30

D00 to D07

J

P00 to P07

D08 to D15

J

P10 to P17

D16 to D23

J

P20 to P27 Can be used as ports in 8-bit external bus mode. D24 to D31 C

RDY

J

P80

BGRNT

J

P81

External data bus bits 0 to 7. It is available in the external bus mode.

Can be used as ports in 8-bit or 16-bit external bus mode.

External data bus bits 8 to 15. It is available in the external bus mode.

Can be used as ports in 8-bit or 16-bit external bus mode.

External data bus bits 16 to 23. It is available in the external bus mode.

External data bus bits 24 to 31. It is available in the external bus mode.

External ready input. The pin has this function when external ready input is enabled.

General purpose input/output port. The pin has this function when external ready input is disabled.

Acknowledge output for external bus release. Outputs "L" when the external bus is released. The pin has this function when output is enabled.

General purpose input/output port. The pin has this function when output is disabled for external bus release acknowledge.

BRQ

30 35

P82

31 36 RD

WR0

32 37

/ (UUB) /

DQMUU

External bus release request input. Input "1" to request release of the external bus. The pin has this

J

C External bus read strobe output.

C

function when input is enabled. General purpose input/output port. The pin has this

function when the external bus release request input is disabled.

External bus write strobe output. When WR as the write strobe, this becomes the byte-enable pin (UUB Select signal (DQMUU) of D31 to D24 at using of SDRAM.

).

is used

(Continued)

9

MB91301 Series

Pin no.

MB91302A MB91V301A

33 38

34 39

35 40

36 43

37 40

38 45

39 46 P93 C General purpose input/output port.

Pin name

/ (ULB) /

WR1

DQMUL

P85

/ (LUB) /

WR2

DQMLU

P86

/ (LLB) /

WR3

DQMLL

P87

SYSCLK

P90

MCLKE

P91

MCLK

P92

I/O circuit

type

J

C

J

C

Function

External bus write strobe output. The pin has this function when WR1 output is enabled. When WR is used as the write strobe, this becomes the byteenable pin (ULB D16 at using of SDRAM.

General purpose input/output port. The pin has this function when the external bus write-enable output is disabled.

External bus write strobe output. The pin has this function when WR2 output is enabled. When WR is used as the write strobe, this becomes the byteenable pin (LUB D05 at using of SDRAM.

General purpose input/output port. The pin has this function when the external bus write-enable output is disabled.

External bus write strobe output. The pin has this function when WR3 output is enabled. When WR is used as the write strobe, this becomes the byteenable pin (LLB D00 at using of SDRAM.

General purpose input/output port. The pin has this functions when the external bus write-enable output is disabled.

System clock output. The pin has this function when system clock output is enabled. This outputs the same clock as the external bus operating frequency. (Output halts in stop mode.)

General purpose input/output port. The pin has this function when system clock output is disabled.

Clock enable signal for memory. General purpose input/output port. The pin has this

function when clock enable output is disabled. Memory clock output. The pin has this function

when memory clock output is enabled. This outputs the same clock as the external bus operating frequency. (Output halts in sleep mode.)

General purpose input/output port. The pin has this function when memory clock output is disabled.

). Select signal (DQMUL) of D23 to

). Select signal (DQMLU) of D08 to

). Select signal (DQMLL) of D07 to

(Continued)

10

MB91301 Series

Pin no.

MB91302A MB91V301A

40 49

41 50

42 51

45 to 52 54 to 61 A00 to A07 C External address bits 0 to 7. 55 to 62 64 to 71 A08 to A15 C External address bits 8 to 15.

64 to 67 74 to 77

Pin name

AS

LBA

SRAS

P94

BAA

SCAS

P95

WR

SWE

P96

A16 to A19

P60 to P63

I/O circuit

type

J

Function

Address strobe output. The pin has this function when ASE “1”.

Address strobe output for burst flash ROM. The pin has this function when ASE register 9 is enabled “1”.

RAS single for SDRAM. This pin has this function when ASE “1”.

General purpose input/output port. The pin has this function when ASE "0" general purpose port.

Address advance output for burst Flash ROM. The pin has this function when BAAE bit of port function register (PFR9) is enabled.

CAS signal for SDRAM. This pin has this function when BAAE bit of port function register (PFR9) is enabled.

General purpose input/output port. The pin has this function when BAAE bit of port function register is general purpose port.

Memory write strobe output. This pin has this function when WRXE bit of port function register is enabled.

Write output for SDRAM. This pin has this function when WRXE bit of port function register is enabled.

General purpose input/output port. This pin has this function when WRXE bit of port function register is general purpose port.

External address bits 16 to 19. It is available in external bus mode.

Can be used as ports when external address bus is not used.

bit of port function register 9 is enabled

bit of port function register 9 is

bit of port function

(Continued)

11

MB91301 Series

Pin no.

MB91302A MB91V301A

68 78

69 79

70 80

Pin name

SDA0

A20

P64

SCL0

A21

P65

SDA1

A22

P66

I/O circuit

type

T

Function

2

Data input pin for I enable when typical operation of I

C bus function. This function is

2

C is enable. The port output must remains off unless intentionally turned on. (Open drain output) (This function is only for MB91302A, MB91V301A.)

External address bus bit 20.

2

This function is enable during prohibited I

C

operation and using external bus. General-purpose I/O port.

2

This function is enable during prohibited I

C and

nonused external address bus. CLK input pin for I

enable when typical operation of I

2

C bus function. This function is

2

C is enable. The port output must remains off unless intentionally turned on. (open drain output) (This function is only for MB91302A, MB91V301A.)

External address bus bit 21.

2

This function is enable during prohibited I

C

operation and using external bus. General-purpose I/O port.

2

This function is enable during prohibited I

C and

nonused external address bus. DATA input pin for I

enable when typical operation of I

2

C bus function. This function is

2

C is enable. The output must remains off unless intentionally turned on. (open drain output) (This function is only for MB91302A, MB91V301A.)

External address bus bit 20.

2

This function is enable during prohibited I

C

operation and using external bus. General-purpose I/O port.

2

This function is enable during prohibited I

C and

nonused external address bus.

(Continued)

12

MB91301 Series

Pin no.

MB91302A MB91V301A

Pin name

I/O circuit

type

CLK input pin for I enable when typical operation of I

SCL1

port output must remains off unless intentionally turned on. (open drain output) (This function is only for MB91302A, MB91V301A.)

71 81

A23

T

External address bus bit 21. This function is enable during prohibited I operation and using external bus.

General-purpose I/O port.

P67

This function is enable during prohibited I operation and nonused external address bus.

76 to 79 106 to 109 AN3 to AN0 D Analog input pin.

External interrupt inputs. These inputs are used con-

INT0 to INT3

tinuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally.

81 to 84 111 to 114

PG0 to PG3 General purpose input/output ports.

V

Input capture input pins. These inputs are used con-

ICU0 to ICU3

tinuously when selected as input capture inputs. In this case, do not output to these ports unless doing so intentionally.

External interrupt input. These inputs are used

INT4

continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally.

External trigger input for A/D converter. This input is used continuously when selected as the A/D converter start trigger. In this case, do not output to

85 115

ATG

V

this port unless doing so intentionally.

PG4 General purpose input/output ports.

External clock input pin for free-run timer. This input

FRCK

is used continuously when selected as the external clock input pin for the free-run timer. In this case, do not output to this port unless doing so intentionally.

External interrupt input. These inputs are used

INT5

continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally.

86 116

SIN2

V

UART2 data input pin. This input is used continuously when UART2 is performing input. In this case, do not output to this port unless doing so intentionally.

PG5 General purpose input/output port.

Function

2

C bus function. This function is

2

C is enable. The

2

C

2

C

(Continued)

13

MB91301 Series

Pin no.

MB91302A MB91V301A

87 117

88 118

90 120

91 121

92 122

93 123

94 124

95 125

96 126

Pin name

INT6

SOT2

PG6 General purpose input/output port.

INT7

SCK2

PG7 General purpose input/output port.

SIN0

PJ0 General purpose input/output port.

SOT0

PJ1 General purpose input/output port.

SCK0

PJ2 General purpose input/output port.

SIN1

PJ3 General purpose input/output port.

SOT1

PJ4 General purpose input/output port.

SCK1

PJ5 General purpose input/output port.

PPG0

PJ6 General purpose input/output port.

I/O circuit

type

V

U

Function

External interrupt input. This input is used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally.

UART2 data output pin. The pin has this function when UART2 data output is enabled.

External interrupt input. This input is used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally.

UART2 clock input/output pin. The pin has this function when UART2 clock output is enabled.

UART0 data input pin. This input is used continuously when UART0 is performing input. In this case, do not output to this port unless doing so intentionally.

UART0 data output pin. The pin has this function when UART0 data output is enabled.

UART0 clock input/output pin. The pin has this function when UART0 clock output is enabled.

UART1 data input pin. This input is used continuously when UART1 is performing input. In this case, do not output to this port unless doing so intentionally.

UART1 data output pin. The pin has this function when UART1 data output is enabled.

UART1 clock input/output pin. The pin has this function when UART1 clock output is enabled.

PPG timer output. This pin has this function when PPG0 output is enabled.

(Continued)

14

MB91301 Series

Pin no.

MB91302A MB91V301A

97 127

98 128

99 129

100 130

103 133

104 134

105 135

Pin name

TRG0

PJ7 General purpose input/output port.

TIN0

PH0 General purpose input/output port.

TIN1

PPG3

PH1 General purpose input/output port.

TIN2

TRG3

PH2 General purpose input/output port.

DREQ0

PB0 General purpose input/output port.

DACK0

PB1 General purpose input/output port.

DEOP0

PB2 General purpose input/output port.

I/O circuit

type

U

J

Function

External trigger input for PPG timer. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally.

Reload timer input. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally.

PPG timer output. The pin has this function when PPG3 output is enabled.

Reload timer input. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally.

External trigger input for PPG timer. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally.

External input for DMA transfer requests. This input is used continuously when selected as a DMA activation trigger. In this case, do not output to this port unless doing so intentionally.

External acknowledge output for DMA transfer requests. The pin has this function when outputting DMA transfer request acknowledgement is enabled.

Completion output for DMA external transfer. The pin has this function when outputting DMA transfer completion is enabled.

(Continued)

15

MB91301 Series

Pin no.

MB91302A MB91V301A

106 136

107 137

108 138

109 139

110 140

112 143 X0 A Clock (oscillation) input. 113 144 X1 A Clock (oscillation) output.

116 to 118 147 to 149 MD0 to MD2 G

119 152 INIT 120 053 NMI

Pin name

DREQ1

PB3

DACK1

TRG1

PB4 General purpose input/output port.

DEOP1

PPG1

PB5 General purpose input/output port.

IOWR

PB6

IORD

PB7

I/O circuit

type

DMA External input for DMA transfer requests. This input is used continuously when selected as a DMA activation trigger. In this case, do not output to this

J

B

M NMI (Non Maskable Interrupt) input (“L” active)

port unless doing so intentionally. General purpose input/output port. The pin has this

function when completion output and stop input are disabled for DMA transfer.

External acknowledge output for DMA transfer requests. The pin has this function when outputting DMA transfer request acknowledgement is enabled.

External trigger input for PPG timer. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally.

Completion output for DMA external transfer. The pin has this function when outputting DMA transfer completion is enabled.

PPG timer output. The pin has this function when PPG1 bit is enabled.

Write strobe output for DMA fly-by transfer. The pin has this function when outputting a write strobe for DMA fly-by transfer is enabled.

General purpose input/output port. The pin has this function when outputting a write strobe for DMA fly-by transfer is disabled.

Read strobe output for DMA fly-by transfer. The pin has this function when outputting a read strobe for DMA fly-by transfer is disabled.

General purpose input/output port. The pin has this function when outputting a write strobe for DMA fly-by transfer is disabled.

Mode pins 0 to 2. The levels applied to these pins set the basic operating mode. Connect V

External reset input (Reset to initialize settings) (“L” active)

Function

or VSS.

CC

(Continued)

16

(Continued)

Pin no.

MB91302A MB91V301A

122 156

123 157

124 158

125 159

126 160

127 161

128 162

129 163

Pin name

CS0

PA0

CS1

PA1

CS2

PA2

CS3

PA3

CS4

TRG2

PA4

CS5

PPG2

PA5

CS6

PA6

CS7

PA7

I/O circuit

type

J

MB91301 Series

Function

Chip select 0 output. The pin has this function when chip select 0 output is enabled.

General purpose input/output port. The pin has this function when chip select 0 output is disabled.

Chip select 1 output. The pin has this function when chip select 1 output is enabled.

General purpose input/output port. The pin has this function when chip select 1 output is disabled.

Chip select 2 output. The pin has this function when chip select 2 output are enabled.

General purpose input/output port. The pin has this function when chip select 2 output is disabled.

Chip select 3 output. The pin has this function when chip select 3 output are enabled.

General purpose input/output port. The pin has this function when chip select 3 output is disabled.

Chip select 4 output. The pin has this function when chip select 4 output is enabled.

External trigger input for PPG timer. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally.

General purpose input/output port. The pin has this function when chip select 4 output is disabled.

Chip select 5 output. The pin has this function when chip select 5 output are enabled.

PPG timer output. The pin has this function when PPG2 bit is enabled.

General purpose input/output port. The pin has this function when chip select 5 output and PPG timer output are disabled.

Chip select 6 output. The pin has this function when chip select 6 output is enabled.

General purpose input/output port. The pin has this function when chip select 6 output are disabled.

Chip select 7 output. The pin has this function when chip select 7 output are enabled.

General purpose input/output port. The pin has this function when chip select 7 output is disabled.

17

MB91301 Series

I/O CIRCUIT TYPE

■

Type Circuit Remarks

X1

Clock input

•Oscillation feedback resistance approx. 1 MΩ

A

X0

Standby control

•CMOS hysteresis input with pull-up

resistor

P-ch

B

N-ch

Digital input

P-ch

•CMOS level I/O with standby control

= 4 mA

•I

OL

Digital output

N-ch

Digital output

C

18

Digital input

Standby control

•Analog input

With switch

P-ch

N-ch

D

Analog input

Control

(Continued)

MB91301 Series

Type Circuit Remarks

P-ch

•CMOS level output

No standby control

G

N-ch

Digital input

Pull-up control

P-chP-ch

Digital output

N-ch

J

Digital output

•With Pull-up control

•CMOS level I/O

with standby control

•With Pull-up control

= 4 mA

•I

OL

Digital input

Standby control

Pull-up control

P-chP-ch

Digital output

N-ch

K

Digital output

•With Pull-up control

•CMOS level output

CMOS level hysteresis input with standby control

= 4 mA

•I

OL

M

Digital input

Standby control

Pull-up control

P-ch

Digital output

L

N-ch

Digital output

•With Pull-up control

•CMOS level output

CMOS level hysteresis input no standby control

•I

= 4 mA

OL

Digital input

P-ch

N-ch

•CMOS level hysteresis input

no standby control

Digital input

(Continued)

19

MB91301 Series

Type Circuit Remarks

P-ch

Digital output

•Output buffer

•CMOS level output

= 4 mA

•I

OL

N

O

N-ch

Digital output

Digital input

•Input buffer

•CMOS level input

•Input buffer with pull-down

•Pull-down resistor value = 25 kΩ

P

N-ch

Digital input

approx. (Typ)

•Input buffer with Pull-up

P-ch

Q

P-ch

Digital input

Digital output

•I/O buffer with pull-down

•CMOS level output

= 4 mA

•I

OL

20

R

N-ch

Digital output

Digital input

P-ch

S

N-ch

Digital output

•I/O buffer

•CMOS level output

= 4 mA

•I

OL

Digital input

(Continued)

MB91301 Series

(Continued)

Type Circuit Remarks

•N-ch open-drain output

P-ch

Pull-up control Digital output with

T

N-ch

open-drain control Digital output

Digital input

P-ch

Digital output

N-ch

U

Digital output

•CMOS level I/O with standby control

•Without pull-up control

= 4 mA

OL

•I

•CMOS level output

•CMOS level hysteresis input

with standby control

•5 V tolerant

•I

= 4 mA

OL

Digital input

•CMOS level output

•CMOS level hysteresis input

P-ch

Digital output

V

N-ch

with standby control

•5 V tolerant

= 4 mA

•I

OL

Digital output

Digital input

21

MB91301 Series

HANDLING DEVICES

■

❍MB91301 series

•

Operation at start-up

Always apply a settings initialization (INIT) to the INIT

pin immediately after turning on the power. Also, in order to provide a delay while the oscillator circuits stabilize immediately after start-up, maintain the “L” level input to the INIT by the INIT

•

External clock input at start-up

pin initializes the oscillation stabilization delay time to the minimum setting.)

pin for the required stabilization delay time. (The initialization processing (INIT) triggered

At power-on start-up, always input a clock signal until the oscillation stabilization delay time is ended.

•

Output indeterminate at power-on time

When the power is turned on, the output pin may remain indeterminate until the internal power supply becomes stable.

•

Built-in DC/DC regulator

This device has a built-in regulator, requiring 3.3 V input to the Vcc pin and a bypass capacitor of approximately

4.7 µF connected to the C pin for the regulator.

3.3 V VCC AVCC

AVRH

0.05 µF

AVR AV

SS/AVRL

C

4.7 µF

V

SS

MB91301 series

GND

SS

V

Note of built-in DC/DC regulator

•

Note on use of the A/D converter

As the MB91301 series contains an A/D converter, be sure to supply po wer to A Vcc at 3.3 V and insert a capacitor of at least 0.05 µF between the AVR pin and the AVss/AVRL pin.

3.3 V AVCC AVRH

0.05 µF

AVR

SS/AVRL

AV

MB91301 series

Note on Use of A/D Converter

22

MB91301 Series

•

Preventing Latchup

at input and output

When CMOS integrated circuit devices are subjected to applied voltages higher than V pins, or to voltages lower than V

, as well as when voltages in excess of rated levels are applied between V

SS

and VSS, a phenomenon known as latchup can occur. When a latchup condition occurs, the supply current can increase dramatically and may destroy semiconductor elements. In using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings.

•

Power supply pins

Devices with multiple V

and VSS supply pins are designed to prevent problems such as latchup occurring by

CC

providing internal connections between pins at the same potential. However, in order to reduce unwanted radiation, prevent abnor mal operation of strobe signals due to a rise in ground level, and to maintain the total output current ratings, all such pins should always be connected externally to power supply or ground. Also, ensure that the impedance of the V

and VSS connections to the power supply are as low as possible.

CC

In addition, it is recommended that a bypass capacitor of approximately 0.1µF be connected between V V

. Connect the capacitor close to the VCC and VSS pins.

SS

•

Crystal oscillators

Noise in proximity to the X0 and X1 pins can cause abnormal operation in this device. Pr inted circuit boards should be designed so that the X0 and X1 pins, crystal (or ceramic) oscillator, and b ypass capacitor connected to ground are placed as close together as possible. Also, to ensure stab le operation, it is strongly recommended that the printed circuit board art work be designed such that the X0 and X1 pins are surrounded by ground. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.

CC

and

•

Treatment of NC and OPEN pins

Pins marked as "NC" or "OPEN" must be left open-circuit.

•

Treatment of unused input pins

If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected to pull-up or pull-down resistors.

•

Mode pins (MD0 to MD2)

These pins should be connected directly to V due to noise, design the printed circuit board such that the distance between the mode pins and V

or VSS. To prev ent the device erroneously s witching to test mode

CC

or VSS is

CC

as short as possible and the connection impedance is low.

•

Remarks for External Clock Operation

When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to X0 must be supplied to X1 pin. Howe v er, in this case the stop mode must not be used (because X1 pin stops at “H” output in stop mode) . When operating at 12.5 MHz or less, the microcontroller can be used with the clock signal supplied only to pin X0. “Using an external clock (normal) and (12.5 MHz) ” shows examples of how the MB91301 uses the e xternal clock.

23

MB91301 Series

X0

X1

MB91301 series

Note: Stop mode (oscillation stop mode) can not be used.

Using an external clock (normal)

X0

OPEN

X1

MB91301 series

Using an external clock (12.5 MHz Max)

•

Notes on during operation of PLL clock mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed.

•

Clock control block

For L-level input to the INIT

•

Bit search module

pin, allow for the regulator settling time or oscillation settling time.

The 0-detection, 1-detection, and transition-detection data registers (BSD0, BSD1, and BSDC) are only wordaccessible.

•

I/O port access

Byte access only for access to port

•

Shared port function switching

To switch a pin that also serves as a port, use the port function register (PFR). Note, however, that bus pins are switched depending on external bus settings.

•

D-bus memory

Do not set a code area in D-bus memory. No instruction fetch is performed to the D-bus. Instruction fetches to the D-bus area result in incorrect data interpreted as code, which can cause the microcontroller to lose control. Do not set a data area in I-bus memory.

24

MB91301 Series

•

I-bus memory

Do not set a stack area or vector table in I-bus memory. It may cause a hang during EIT processing (including RETI). Recovery from the hang requires a reset. Do not perform DMA transfer to I-bus memory.

•

Low-power consumption modes

• To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the TBCR, or time-base counter control register) and be sure to use the following sequence:

(LDI #value_of_standby, R0) (LDI #_STCR, R12)

STB R0, @R12 ; Write to standby control register (STCR)

LDUB @R12, R0 ; Read STCR for synchronous standby LDUB @R12, R0 ; Read STCR again for dummy read NOP ; NOP x 5 for timing adjustment NOP NOP NOP NOP

• If you use the monitor debugger, follow the precautions below:

Do not set a breakpoint within the above array of instructions. Do not single-step the above array of instructions.

•

Prefetch

When accessing a prefetch-enabled little endian area, use word access only (access in 32 bits). Byte or halfword access results in wrong data read.

•

MCLK and SYSCLK

MCLK causes a stop in SLEEP/STOP mode while SYSCLK causes a stop only in STOP mode. Use either depending on each application.

•

Pull-up control

When function pins listed in the AC specifications (such as exter nal bus control pins) have pull-up control, enabling the pull-up resistor for a pin causes the actual pin load conditions to change. As all AC specifications for this device were measured under the condition of pull-up resistors disabled, the values are not guaranteed of AC specifications when pull-up resistors are enabled.

Even if the pull-up resistor is set to enabled f or a pin, if the HIZ bit in the standby control register (STCR) specifies setting output pins to high impedance during stop mode (HIZ = 1) , changing to stop mode (STOP = 1) causes the pull-up resistor to be disabled.

25

MB91301 Series

•

R15 (General purpose register)

When any of the following instructions is executed, the SSP* or USP* value is not used as R15, resulting in an incorrect value written to memory.

AND R15, @Ri ANDH R15, @Ri ANDB R15, @Ri OR R15, @Ri ORH R15, @Ri ORB R15, @Ri EOR R15, @Ri EORH R15, @Ri EORB R15, @Ri XCHB @Rj, R15

* : R15 is a virtual register. When a program attempts to access R15, the SSP or USP is accessed depending

on the status of the “S” flag as an SP flag. When coding the above ten instructions using an assembler, specify a general-purpose register other than R15.

•

RETI instruction

Please do not neither control register of the instruction cache nor the data access to RAM of the instruction cache immediately before the instruction of RETI.

•

Notes on the PS register

Since some instructions manipulate the PS register earlier, the following exceptions may cause the interrupt handler to break or the PS flag to update its display setting when the debugger is being used. As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs operations before and after the EIT as specified in either case.

• The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS instruction is (a) halted by a user interrupt or NMI, (b) single-stepped, or (c) breaks in response to a data event or emulator menu: (1) D0 and D1 flags are updated earlier. (2) The EIT handler (user interrupt/NMI or emulator) is executed. (3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are

updated to the same values as those in (1) above.

• The following operations are performed when the ORCCR/STILM/MOV Ri and PS instructions are executed to enable interruptions when a user interrupt or NMI trigger event has occurred. (1) The PS register is updated earlier. (2) The EIT handler (user interrupt/NMI or emulator) is executed. (3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to the

same value as that in (1) above.

•

A/D converter

When the device is turned on or returns from a reset or stop, it takes time f or the external capacitor to be charged, requiring the A/D converter to wait for at least 10 ms.

•

Watchdog timer

The watchdog timer function of this model monitors that a program dela ys a reset within a certain period of time and resets the CPU if the program fails to delay it, for example, because the progr am runs out of control. Once the watchdog timer function is enabled, therefore, the watchdog timer continues to operate until a reset takes place.

An exception, f or example during stop, sleep and DMA tr ansfer modes, is the automatic dela ying of a reset under a condition in which the CPU stops program execution.

Note, however, that a watchdog reset may not occur in the above state caused when the system runs out of control. If this is the case, use the external INIT

pin to cause a reset (INIT) .

26

❍Unique to the evaluation chip MB91V301A

•

Tool reset

MB91301 Series

On an evaluation board, use the chip with INIT

•

Simultaneous occurrences of a software break and a user interrupt/NMI

When a software break and a user interrupt /NMI take place at the same time, the emulator deb ugger can cause the following phenomena:

• The debugger stops pointing to a location other than the programmed breakpoints.

• The halted program is not re-executed correctly.

If these phenomena occur, use a hardware break instead of the software break. If the monitor debugger has been used, avoid setting any break at the relevant location.

•

Single-stepping the RETI instruction

If an interrupt occurs frequently during single stepping, execute only the rele v ant processing routine repeatedly after single-stepping RETI. This will prevent the main routine and low-interrupt-level programs from being ex ecuted. Do not single-step the RETI instruction for a voidance purposes. When the debugging of the rele v ant interrupt routine becomes unnecessary, perform debugging with that interrupt disabled.

•

Operand break

A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a data event break to access to the area containing the address of a system stack pointer.

and TRST connected together.

•

ICE startup sequence

When using the ICE, when you start debugging, ensure that the bus configuration is set correctly for the area being used before downloading. After turning on the power to the target, the states of the RD pins are undefined until you perform the abov e setting. Accordingly , include enabling pull-up as part of the startup sequence. If using these pins as general-purpose ports, set as output por ts to prevent conflict with the output signals during the time the pin states are undefined.

External bus width

Pin name

RD WR0

(P85) Pull-up Pull-up *

WR1

(P86) Pull-up * *

WR2

(P87) Pull-up * *

WR3

* : Use as output ports.

32 bit 16 bit 8 bit

Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up

and WR0 to WR3

27

MB91301 Series

•

Configuration batch file

The example batch file below sets the mode v ector and sets up the CS0 configur ation register f or the download area. Use values appropriate to the hardware in the wait, timing, and other settings.

#--------------------------------------------------------# Set MODR (0x7fd) =Enable In memory+16 bit External Bus set mem/byte 0x7fd=0x5 #--------------------------------------------------------# Set ASR0 (0x640); 0x0010_0000 - 0x002f_ffff set mem/halfword 0x640=0x0010 #--------------------------------------------------------# Set ACR0 (0x642) # ; ASZ [3:0]=0101:2 Mbytes # ; DBW [1:0]=01:16 bit width, automatically set from MODR # ; BST [1:0]=00:1 burst (16 bit x 2) # ; SREN=0:Disable BRQ # ; PFEN=1:Enable Pre fetch buffer # ; WREN=1:Enable Write operation # ; LEND=0: Big endian # ; TYPE [3:0]=0010:WEX: Disable RDY set mem/harfword 0x642=0x5462 #--------------------------------------------------------# Set AWR0 (0x660) # ; W15-12=0010:auto wait=2 # ; WR07, 06=01:RD, WR delay=1cycle # ; W05, 04=01:WR->WR delay=1cycle (for WEX) # ; W03 =1:MCLK->RD/WR delay=0.5cycle # ; :for async Memory # ; W02 =0:ADR->CS delay=0 # ; W01 =0:ADR->RD/WR setup 0cycle # ; W00 =RD/WR->ADR hold 0cycle set mem/halfword 0x660=0x2058 #---------------------------------------------------------

•

Emulation memory

If SRAM as the emulation memory is built on target board, SRAM for be accessed by RD, WR signal, and +BYTE control signal can not be used. (The external bus is initialized to the b us mode for accessing RD

28

, WRn after reset.)

BLOCK DIAGRAM

M

S

1

■

• MB91302A, MB91V301A

MB91301 Series

FR CPU

Core

32 32

Bit search module

MB91302A : RAM 4 KB

Instruction Cache

4 KB

DMAC

5 channels

DREQ0, DREQ DACK0, DACK DEOP0, DEOP IOWR IORD

MB91V301A : RAM 8 KB (stack)

A23 to A00 D31 to D16 D15 to D00 RD, WR WR0 to WR3 CS0 to CS7 RDY BRQ BGRNT SYSCLK MCLK AS

MCLKE

X0, X1

D0 to MD2

INIT

MB91302A : ROM 4 KB* MB91V301A : RAM 8 KB

Clock

control

32

Adapter

16

32

16

Bus

Converter

32

External memory

I/F

Interrupt

controller

SDRAM I/F

INT0 to INT7

NMI

SIN0 to SIN2 OT0 to SOT2 CK0 to SCK2

8 channels

External interrupts

3 channels

UART

4 channels

PPG timer

SRAS SCAS SWE DQMUU, L DQMLU,L LBA BAA

PPG0 to PPG3 TRG0 to TRG3

3 channels

U-TIMER

AN0 to AN3

ATG

AVRH, AV

AVSS/AVRL

TIN0 to TIN2

CC

4 channels

A/D converter

3 channels

PORT I/F

2 channels

2

I

C I/F

PORT

SDA0, SDA1 SCL0, SCL1

Reload timer

Free Run Timer

FRCK

4 channels

Input Capture

ICU0 to ICU3

* : ROM has non-ROM model, the optimal real time OS internal model, and the IPL (Internal Program

Loader) internal model by adding the user ROM model.

29

MB91301 Series

CPU

■

1. Memory Space

The FR family has 4 Gbytes (232 addresses) of logical address space with linear access from the CPU.

• Direct Addressing Areas The following areas of address space are used for I/O operations.

These areas are called direct addressing areas, in which the address of an operand can be specified directly during an instruction. The direct areas differ according to the size of the data accessed, as follows.

→ byte data access : 000 → half word data access : 000 → word data access : 000

to 0FF

H

to 1FF

H

to 3FF

H

H H H

30

MB91301 Series

0

0 0

0

0 0

0

F

• Memory map

(MB91302A)

(Single chip

mode)

000 0000

H

I/O

000 0400

H

I/O

001 0000 002 0000

H

I-RAM

1

∗

Access

H

prohib-

003 E000

ited

003 F000

H

Internal

RAM

H

H H

H

4 Kbytes

Access prohib-

ited

Internal

ROM

4

Kbytes*

004 0000

004 2000

006 0000 00E 0000

00F E000

00F F000

010 0000

Access

FFF FFFF

MB91302A has non-ROM model, the optimal real time OS internal model, and the IPL (Internal program Loader) internal model by adding the user ROM model.

prohib-

ited

H

“■I/O MAP”

2

(MB91302A) Internal ROM

External bus

Direct addre

ssing

area

see

I/O

Access

prohib-

Internal

4 Kbytes

External

Access

prohib-

4

External

mode

I/O

I-RAM

ited

RAM

area

ited

Internal

ROM

Kbytes*

area

(MB91302A)

External ROM

External bus

mode

(MB91V301A)

Internal ROM External bus mode (MODR register at

(MB91V301A)

External ROM

External bus

mode

ROAM = 1)

Direct

addre ssing

area

see

“■I/O

MAP”

I/O

1

∗

I/O

I-RAM

Access prohib-

ited

Internal

RAM

Direct addre ssing

area

see “■I/O MAP”

I/O

1

∗

I/O

I-RAM

Access

prohibited

Internal

RAM

8 Kbytes

Direct addre

ssing

area

see “■I/O MAP”

I/O

1

∗

I/O

I-RAM

Access

prohibited

Internal

RAM

8 Kbytes

Direct addre

ssing

area

see

“■I/O

MAP”

I/O

1

∗

4 Kbytes

Internal

RAM

8 Kbytes

Access

prohibit-

ed

External

area

External

area

External

area

Internal

RAM

8 Kbytes

emula-

2

External

area

tion

External

area

External

area

*1 : On specific area between 10000

and 2000H, 4 Kbytes RAM can be used.

H

Refer to “■INSTRUCTION CACHE”.

*2 : The real time OS internal model stores the real time OS kernel. The program loader internal model stores

the program loader.

Note : Internal ROM emulation : only MB91V301A

Note : Each mode is set depending on the mode vector fetch after INIT

is negated. (For mode setting, see “■MODE

SETTINGS”.)

31

MB91301 Series

H

H H

0

P

0

T

2. Registers

The FR series has two types of registers: application-specific registers in the CPU and general purpose registers in memory.

• Dedicated registers Program counter (PC) : 32-bit register. Stores the current instruction address.

Program status (PS) : 32-bit register. Contains the register pointer and condition code. Table base register (TBR) : Stores the top address of the vector table used by the EIT (exception/interrupt/

trap) function. Return pointer (RP) : Stores the subroutine return address. System stack pointer (SSP) : Points to the system stack area. User stack pointer (USP) : Points to the user stack area. Multiplication and division

result register (MDH/MDL)

: 32-bit registers used for multiplication and division.

32 bit

PC

PS

TBR

RP

SSP

USP

MDH MDL

Program counter

Program status

Table base register

Return pointer

System stack pointer

User stack pointer

Multiplication and division result register

Initial value

XXXX XXXX

000F FC00H

XXXX XXXX

0000 0000H

XXXX XXXX

XXXX XXXX XXXX XXXX

• PC (Program Counter) The PC is the program counter and stores the address of the currently executing instruction.

31

C

PC

• Table base register (TBR) The TBR is the table base register and stores the top address of the vector table used by the EIT function.

31

BR

TBR

32

• Return pointer (RP)

0

R

0

S

0

U

0

M M

The RP is the return pointer and stores the subroutine return address.

31

P

RP

• System stack pointer (SSP) The SSP is the system stack pointer and functions as R15 when the S flag is “0”.

31

SP

SSP

• User stack pointer (USP) The USP is the user stack pointer and functions as R15 when the S flag is “1”.

MB91301 Series

31

SP

USP

• Multiplication and division result register (MDH/MDL) MDH/MDL : 32-bit registers used for multiplication and division.

MDH : Remainder MDL : Quotient

31

DH DL

Multiplication and division result register

33

MB91301 Series

0

• Program status (PS) This register holds the program status and is divided into the ILM, SCR, and CCR.

Bit position→

31 20 16

⎯⎯

ILM SCR CCR

10

78

PS

• Condition code register (CCR)

S flag : Specifies which stack pointer to use as R15. I flag : Enables or disables user interrupt requests. N flag : Indicates the sign when an operation result is represented as a “2” complement integer. Z flag : Indicates whether an operation result is “0”. V flag : Indicates whether an overflow occurred for an operation result when the operation operand is

represented as a “2” complement integer.

C flag : Indicates whether an operation resulted in a borrow or a carry from the most significant bit.

76543210

⎯⎯ SINZVC

Initial Value

- - 00XXXX

B

CCR

• System condition code register (SCR)

D1, D0 flags : Stores intermediate data for stepwise multiplication operations. T flags : A flag specifying whether the step trace trap function is enabled or not.

10 9 8

D1 D0 T

Initial Value

XX0

B

SCR

• Interrupt level mask register(ILM)

ILM4 to ILM0 : This register stores the interrupt level mask value. The value in the ILM register is used as

the level mask. Only interrupt requests to the CPU that have an interrupt level that is higher than the level specified in ILM are accepted.

20 19 18 17 16 Initial Value

ILM4 ILM3 ILM2 ILM1 ILM0 Interrupt Level 01111

B

00000 0 High

• • • • • • ↑

01000 15(Medium)

• • • • • • ↓

11111 31 Low

ILM

34

MB91301 Series

R R

R R R R

H

GENERAL PURPOSE REGISTERS

■

General purpose registers R0 to R15 are used by the CPU. The registers are used as the accumulator and memory access pointers for CPU operations.

0 1

12 13 14 15

32-bit

AC (Accumulator)

FP (Frame Pointer)

SP (Stack Pointer)

Initial Value

XXXX XXXX

XXXX XXXX 0000 0000H

The following three registers are treated as ha ving special meanings to enhance the operation of some instructions.

R13 : Virtual accumulator (AC) R14 : Frame pointer (FP) R15 : Stack pointer (SP)

The values of R0 to R14 after a reset are undefined. R15 is initialized to 0000 0000

(SSP value) .

H

35

MB91301 Series

Operation mode setting bits

WWW

Operation mode setting bits

MODE SETTINGS

■

In the FR series, the mode is set by the mode pins (MD2, MD1, and MD0) and mode register (MODR).

1. Mode Pins

The MD2, MD1, and MD0 pins specify how the mode vector fetch is performed.

Mode Pins

Mode name

MD2 MD1 MD0

0 0 0 Internal ROM vector mode Internal Single-chip mode*

Reset vector access

area

Remarks

0 0 1 External ROM vector mode External

The bus width is specified by the mode register.

Values other than those listed in the table are prohibited.

* : Single chip mode is able to set only MB91302A.

2. Mode Register (MODR)

• Details of mode register (MODR)

The data written to the mode register by the mode vector fetch operation (see “3.11.3 reset sequences”) is called the mode data. After the data is set to the mode register (MODR), the device operates with the operating mode specified by this data. The mode register is set by all types of reset. The register cannot be written to by user programs.

Initial Value

bit

Address

23 22 21 20 19 18 17 16

⎯⎯⎯⎯⎯ROMA WTH1 WTH0

WWW

XXXXXXXX

B

bit

Address

31 30 29 28 27 26 25 24

⎯⎯⎯⎯⎯ROMA WTH1 WTH0

Bit31 to bit24 are all reserved bits. Be sure to set this bit to “00000.” Operation is not guaranteed when any value other than “00000.” is set.

36

Initial Value

XXXXXXXX

B

MB91301 Series

• Operating mode

Bus mode

Single chip

Internal ROM external bus 32-bit bus width

External ROM external bus 8-bit bus width

• Bus mode

The bus mode controls the operations of internal ROM and the exter nal access function. It is specified with the mode setting pins (MD2, MD1, and MD0) and the ROMA bit in mode data.

• Access mode

The access mode controls the external data bus width. It is specified with the WTH1 and WTH0 bits in the mode register and the DBW1 and DBW0 bits in area configuration registers 0 to 7 (ACR0 to ACR7).

• Bus Modes

The FR family has three bus modes: b us mode 0 (single-chip mode), bus mode 1 (internal-ROM, e xternal-bus mode), and bus mode 2 (external-ROM, external-bus mode). The MB91V301A supports only bus mode 2 (external-ROM, external-bus mode). See “1. Memory Space” in ■CPU for details.

Access mode

16-bit bus width

• Bus mode0 (single chip mode) (only MB91302A)

The internal I/O, 4 Kbytes D-bus RAM, 32 Kbytes F-bus RAM (FRAM) and 96 Kbytes F-bus ROM are valid, while access to any other areas is inv alid under this mode. The function of external pin is peripheral or general-

purpose port. The pin can not be used as the bus pin.

• Bus mode 1 (internal ROM external bus mode)

The internal I/O, D-bus RAM, F-bus RAM (FRAM) and F-bus ROM are valid, and access to areas where external access is enabled will access e xternal space under this mode. A part of an external terminal functions as a bus terminal.

• Bus mode 2 (External-ROM, external-bus mode)

This mode enables internal I/O and D-bus RAM, in which any access is access to external space. Some external pins serve as bus pins.

37

MB91301 Series

I/O MAP

■

This shows the location of the various peripheral resource registers in the memory space.

[How to read the table]

Address

000000

Note : Initial values of register bits are represented as follows :

“1” : Initial value“1” “0” : Initial value“0”

“X” : Initial value“X”

“-” : No physical register at this location

H

+

0

PDR0 [R/W] B

XXXXXXXX

PDR1 [R/W] B

XXXXXXXX

Read/write attribute, Access type

Initial value after a reset

Register name (Address of column 1 register is 4n, address of column 2 register is 4n+2, etc.)

Location of left-most register (When using word access, the register in column 1 is in the MSB side of the data.)

+

1

Register

PDR2 [R/W] B

XXXXXXXX

+

2

(B : Byte, H : Half-word, W : Word)

+

3

PDR3 [R/W] B

XXXXXXXX

Block

T-unit

Port Data Register

38

MB91301 Series

Address

000000

000004

000008

00000C

000010

000014

to

00003C

000040

000044

000048

00004C

+

0

PDR0 [R/W] B

H

XXXXXXXX

⎯⎯

PDR8 [R/W] B

XXXXXXXX

PDRG [R/W] B

XXXXXXXX

EIRR [R/W] B, H, W

00000000

DICR [R/W] B, H, W

-

- - - - - -

XXXXXXXX XXXXXXXX

PDR1 [R/W] B

XXXXXXXX

PDR9 [R/W] B

-

XXXXXXX

PDRH [R/W] B

-

- - - -

ENIR [R/W] B, H, W

00000000

HRCL [R/W] B, H, W

0

0 - - 11111

TMRLR0 [W] H, W

⎯

+

1

XXX

Register

+

2

PDR2 [R/W] B

XXXXXXXX

PDR6 [R/W] B

XXXXXXXX

PDRA [R/W] B

XXXXXXXX

+

3

⎯

PDRB [R/W] B

XXXXXXXX

Port Data

Register

⎯

PDRJ [R/W] B

XXXXXXXX

Port Data

Register

⎯ Reserved

ELVR [R/W] B, H, W

00000000

⎯ DLYI/I-unit

TMR0 [R] H, W

XXXXXXXX XXXXXXXX

TMCSR0 [R/W] B, H, W

XX0000 00000000

-

Reload

Timer 0

Block

T-unit

R-bus

Ext int

000050

000054

000058

00005C

000060

000064

000068

00006C

H

SSR0 [R/W] B, H, W

H

UTIM0 [R] H, W (UTIMR0 [W] H, W)

H

SSR1 [R/W] B, H, W

H

UTIM1 [R] H, W (UTIMR1 [W] H, W )

H

TMRLR1 [W] H, W

XXXXXXXX XXXXXXXX

⎯

TMRLR2 [W] H, W

XXXXXXXX XXXXXXXX

⎯

00001000

SODR0 [W] B, H, W

00000000 00000000

00001000

SODR1 [W] B, H, W

00000000 00000000

SIDR0 [R]

XXXXXXXX

SIDR1 [R]

XXXXXXXX

TMR1 [R] H, W

XXXXXXXX XXXXXXXX

TMCSR1 [R/W] B, H, W

XX0000 00000000

-

TMR2 [R] H, W

XXXXXXXX XXXXXXXX

TMCSR2 [R/W] B, H, W

XX0000 00000000

-

SCR0 [R/W] B, H, W

00000100

DRCL0 [W] B

-

- - - - - -

-

SCR1 [R/W] B, H, W

00000100

DRCL1 [W] B

-

- - - - - -

-

SMR0 [R/W] B, H, W

00

- - 0 - 0 -

UTIMC0 [R/W] B

0 - - 00001

SMR1 [R/W] B, H, W

00

- - 0 - 0

-

UTIMC1 [R/W] B

0 - - 00001

Reload

Timer 1

Reload

Timer 2

UART0

U-TIMER 0

UART1

U-TIMER 1

(Continued)

39

MB91301 Series

Address

000070

000074

000078

00007C 000080

to

000090 000094

000098

00009C

0000A0 0000A4 0000A8

to

0000B0 0000B4

0000B8

0000BC

0000C0 0000C4 0000C8

to

0000D0 0000D4

0000D8

+

0

SSR2 [R/W] B, H, W

H

00001000

UTIM2 [R] H, W (UTIMR2 [W] H, W )

00000000 00000000

ADCR [R] B, H, W

000000XX XXXXXXXX

ADCR0 [R] B, H, W

XXXXXXXX

IBCR0 [R/W] B, H, W

00000000

ITMK0 [R, R/W] B, H, W

00111111 11111111

⎯

⎯⎯⎯⎯ ⎯⎯⎯⎯

IBCR1 [R/W] B, H, W

00000000

ITMK1 [R, R/W] B, H, W

00111111 11111111

⎯

⎯⎯⎯⎯ ⎯⎯⎯⎯

SIDR2 [R]

SODR2 [W] B, H, W

XXXXXXXX

ADCR1 [R] B, H, W

XXXXXXXX

IBSR0 [R] B, H, W

00000000

IDAR0 [R/W] B, H, W

00000000

IBSR1 [R] B, H, W

00000000

IDAR1 [R/W] B, H, W

00000000

⎯⎯⎯⎯

H

TCDT [R/W] H, W

00000000 00000000

IPCP1 [R/W] H, W

XXXXXXXX_XXXXXXXX

Register

Block

+

1

SCR2 [R/W] B, H, W

ADCR2 [R] B, H, W

+

2

00000100

DRCL2 [W] B

-

- - - - - -

-

ADCS [R/W] B, H, W 00000000 00000000

XXXXXXXX

+

3

SMR2 [R/W] B, H, W

00

- - 0 - 0

-

UTIMC2 [R/W] B

0 - - 00001

ADCR3 [R] B, H, W

XXXXXXXX

UART2

U-TIMER 2

A/D

Converter

Sequential

Comparator

⎯ Reserved

ITBA0 [R, R/W] B, H, W

00000000 00000000

ISMK0 [R/W] B, H, W

01111111

ICCR0 [R, W, R/W]

B, H, W

00011111

ISBA0 [R, R/W]

B, H, W

00000000

IDBL0 [R, R/W]

B, H, W

00000000

2

C

I

interface0

Reserved

⎯ Reserved

ITBA1 [R, R/W] B, H, W

00000000 00000000

ISMK1 [R/W] B, H, W

01111111

ICCR1 [R, W, R/W]

B, H, W

00011111

ISBA1 [R, R/W]

B, H, W

00000000

IDBL1 [R, R/W]

B, H, W

00000000

2

C

I

interface1

Reserved

⎯

TCCS [R/W] B, H, W

00000000

IPCP0 [R/W] H, W

XXXXXXXX_XXXXXXXX

16 bit Free

Run Timer

16 bit Input

Capture

(Continued)

40

MB91301 Series

Address

0000DC

0000E0 0000E4

to

000114 000118

000011C

000120

000124

000128

00012C

000130

000134

Register

Block

+

0

H

IPCP3 [R/W] H, W

XXXXXXXX_XXXXXXXX

+

1

+

2

+

IPCP2 [R/W] H, W

XXXXXXXX_XXXXXXXX

3

16 bit

Input

H

⎯

ICS23 [R/W] B, H, W

00000000

⎯

ICS01 [R/W] B, H, W

00000000

capture

⎯ Reserved

H

GCN10 [R/W] H

00110010 00010000

⎯ Reserved

PTMR0 [R] H

11111111 11111111

⎯

PCSR0 [W] H, W

XXXXXXXX XXXXXXXX

GCN20 [R/W] B

00000000

PPG timer

PPG0

H

PDUT0 [W] H, W

XXXXXXXX XXXXXXXX

PTMR1[R] H

11111111 11111111

PCNH0 [R/W] B

00000000

PCSR1 [W] H, W

XXXXXXXX XXXXXXXX

PCNL0 [R/W] B

000000X0

PPG1

H

PDUT1 [W] H, W

XXXXXXXX XXXXXXXX

PTMR2 [R] H

11111111 11111111

PCNH1 [R/W] B

00000000

PCSR2 [W] H, W

XXXXXXXX XXXXXXXX

PCNL1 [R/W] B

000000X0

PPG2

H

PDUT2 [W] H, W

XXXXXXXX XXXXXXXX

PCNH2 [R/W] B

00000000

PCNL2 [R/W] B

000000X0

000138

00013C

000140

to

0001FC

000200

000204

000208

00020C

000210

H

PTMR3[R] H

11111111 11111111

PCSR3 [W] H, W

XXXXXXXX XXXXXXXX

PPG3

H

PDUT3 [W] H, W

XXXXXXXX XXXXXXXX

PCNH3 [R/W] B

00000000

PCNL3 [R/W] B

000000X0

⎯ Reserved

H

00000000 0000XXXX XXXXXXXX XXXXXXXX

00000000 00000000 XXXXXXXX XXXXXXXX

00000000 0000XXXX XXXXXXXX XXXXXXXX

00000000 00000000 XXXXXXXX XXXXXXXX

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMACA0 [R/W] B, H, W*

DMACB0 [R/W] B, H, W

DMACA1 [R/W] B, H, W*

DMACB1 [R/W] B, H, W

DMACA2 [R/W] B, H, W*

1

DMAC

1

(Continued)

41

MB91301 Series

Address

000214

000218

00021C

000220

000224 000228

to

00023C

000240 000244

to

000300

Register

Block

+

0

H

00000000 00000000 XXXXXXXX XXXXXXXX

00000000 0000XXXX XXXXXXXX XXXXXXXX

00000000 00000000 XXXXXXXX XXXXXXXX

00000000 0000XXXX XXXXXXXX XXXXXXXX

00000000 00000000 XXXXXXXX XXXXXXXX

+

1

+

DMACB2 [R/W] B, H, W

DMACA3 [R/W] B, H, W*

DMACB3 [R/W] B, H, W

DMACA4 [R/W] B, H, W*

DMACB4 [R/W] B, H, W

2

1

+

3

DMAC

1

⎯ Reserved

H

0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX

DMACR [R/W] B

DMAC

⎯ Reserved

H

000304 000308

to

0003E0 0003E4 0003E8

to

0003EF

0003F0

0003F4

0003F8

0003FC

000400

H

DDRG [R/W] B

H

00000000

⎯

ISIZE [R/W] B, H, W

⎯ Reserved

⎯

ICHCR [R/W] B, H, W

⎯ Reserved

BSD0 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

BSD1 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

BSDC [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

BSRR [R] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DDRH [R/W] B

-

000

- - - -

⎯

- - - - -

000000

-

10

-

0

DDRJ [R/W] B

00000000

I-Cache

Bit Search

Module

R-bus Data

Direction

Register

(Continued)

42

MB91301 Series

Address

000404

to

00040C

000410

000414

to

00041C

000420

000424

to

00043C

000440

000444

000448

+

0

H

PFRG [R/W] B

H

00

- - - - -

⎯

ICR00 [R/W] B, H, W

-

11111

- -

ICR04 [R/W] B, H, W

-

11111

- -

ICR08 [R/W] B, H, W

-

11111

- -

Register

Block

+

1

+

2

+

3

⎯ Reserved

PFRH [R/W] B

-

- - - - - - 0 -

⎯

PFRJ [R/W] B

- 000 - 00 -

R-bus Port

Function

Register

⎯ Reserved

R-bus

PCRH [R/W] B

000

-

- - - -

⎯⎯

Pull-up

Resistance

Control

Register

⎯ Reserved

ICR01 [R/W] B, H, W

- - - 11111

ICR05 [R/W] B, H, W

- - - 11111

ICR09 [R/W] B, H, W

- - - 11111

ICR02 [R/W] B, H, W

- - - 11111

ICR06 [R/W] B, H, W

- - - 11111

ICR10 [R/W] B, H, W

- - - 11111

ICR03 [R/W] B, H, W

- - - 11111

ICR07 [R/W] B, H, W

- - - 11111

ICR11 [R/W] B, H, W

- - - 11111

00044C

000450

000454

000458

00045C

000460

000464

000468

ICR12 [R/W] B, H, W

H

-

11111

- -

ICR16 [R/W] B, H, W

-

11111

- -

ICR20 [R/W] B, H, W

-

11111

- -

ICR24 [R/W] B, H, W

-

11111

- -

ICR28 [R/W] B, H, W

-

11111

- -

ICR32 [R/W] B, H, W

-

11111

- -

ICR36 [R/W] B, H, W

-

11111

- -

ICR40 [R/W] B, H, W

-

11111

- -

ICR13 [R/W] B, H, W

- - - 11111

ICR17 [R/W] B, H, W

- - - 11111

ICR21 [R/W] B, H, W

- - - 11111

ICR25 [R/W] B, H, W

- - - 11111

ICR29 [R/W] B, H, W

- - - 11111

ICR33 [R/W] B, H, W

- - - 11111

ICR37 [R/W] B, H, W

- - - 11111

ICR41 [R/W] B, H, W

- - - 11111

ICR14 [R/W] B, H, W

- - - 11111

ICR18 [R/W] B, H, W

- - - 11111

ICR22 [R/W] B, H, W

- - - 11111

ICR26 [R/W] B, H, W

- - - 11111

ICR30 [R/W] B, H, W

- - - 11111

ICR34 [R/W] B, H, W

- - - 11111

ICR38 [R/W] B, H, W

- - - 11111

ICR42 [R/W] B, H, W

- - - 11111

ICR15 [R/W] B, H, W

- - - 11111

ICR19 [R/W] B, H, W

- - - 11111

ICR23 [R/W] B, H, W

- - - 11111

ICR27 [R/W] B, H, W

- - - 11111

ICR31 [R/W] B, H, W

- - - 11111

ICR35 [R/W] B, H, W

- - - 11111

ICR39 [R/W] B, H, W

- - - 11111

ICR43 [R/W] B, H, W

- - - 11111

Interrupt

Controller

(Continued)

43

MB91301 Series

Address

00046C

000470

to

00047C

000480

000484

000488

to

0005FC

000600

000604

000608

+

0

ICR44 [R/W] B, H, W

H

-

- -

11111

RSRR [R, R/W]

B, H, W

10000000 (INIT

H

-

0 - XX -

XXX

00 (INIT)

X00 (RST)

- -

CLKR [R/W] B, H, W

000 - 000 (INIT)

H

-

XXX - XXX (RST)

-

H

DDR0 [R/W] B

H

00000000

DDR8 [R/W] B

00000000

+

1

ICR45 [R/W] B, H, W

- - - 11111

STCR [R/W] B, H, W

)

001100

0011XX

00X1XX

-

WPR [W] B, H, W

XXXXXXXX (INIT)

XXXXXXXX (RST)

DDR1 [R/W] B

00000000

⎯

DDR9 [R/W] B

-

0000000

Register

1 (INIT)

X (RST)

+

2

ICR46 [R/W] B, H, W

- - - 11111

ICR47 [R/W] B, H, W

+

3

- - - 11111 Interrupt

Controller

⎯

Block

TBCR [R/W] B, H, W

00XXX

00 (INIT)

-

XX (RST)

-

CTBR [W] B, H, W

XXXXXXXX (INIT)

XXXXXXXX (RST)

Clock

Control

unit

DIVR0 [R/W] B, H, W

00000011 (INIT)

XXXXXXXX (RST)

DIVR1 [R/W] B, H, W

- - - -

(INIT)

(RST)

0000

XXXX

⎯ Reserved

DDR2 [R/W] B

00000000

DDR6 [R/W] B

00000000

⎯

T-unit

Data

Direction

DDRA [R/W] B

00000000

DDRB [R/W] B

00000000

Register

00060C

000610 000614

000618

00061C

000620

000624

000628

00062C

H

PFR8 [R/W] B

H

PFRB2 [R/W] B

H

PCR0 [R/W] B

H

PCR8 [R/W] B

H

⎯ ⎯

⎯⎯

PFR9 [R/W] B

111

000

- - 0 -

- - -

00

-

- 0000111

⎯

PCR1 [R/W] B

00000000

⎯

PCR9 [R/W] B

00000000

-

000 - - 0 -

⎯

PFR6 [R/W] B

11111111

PFRA1 [R/W] B

11111111

PFRA2 [R/W] B

- - 0 - - - - -

PCR2 [R/W] B

00000000

PCR6 [R/W] B

00000000

PCRA [R/W] B

00000000

PFR61 [R/W] B

0000

- -

PFRB1 [R/W] B

00000000

⎯

PCRB [R/W] B

00000000

T-unit

Port

Function

Register

T-unit

Pull-up

Resis-

tance

Control

Register

(Continued)

44

MB91301 Series

Address

000630

to

00063C

000640

000644

000648

00064C

000650

000654

000658

00065C

000660

000664

000668

00066C

000670 000674 000678

00067C

000680

000684

+

0

H

MCRA [R/W] B, H, W

H

XXXXXXXX

IOWR0 [R/W] B, H, W

XXXXXXXX

CSER [R/W] B, H, W

00000001

ASR0 [R/W] H, W

00000000 00000000

ASR1 [R/W] H, W

XXXXXXXX XXXXXXXX

ASR2 [R/W] H, W

XXXXXXXX XXXXXXXX

ASR3 [R/W] H, W

XXXXXXXX XXXXXXXX

ASR4 [R/W] H, W

XXXXXXXX XXXXXXXX

ASR5 [R/W] H, W

XXXXXXXX XXXXXXXX

ASR6 [R/W] H, W

XXXXXXXX XXXXXXXX

ASR7 [R/W] H, W

XXXXXXXX XXXXXXXX

AWR0 [R/W] B, H, W

01111111 11111011

AWR2 [R/W] B, H, W

XXXXXXXX XXXXXXXX

AWR4 [R/W] B, H, W

XXXXXXXX XXXXXXXX

AWR6 [R/W] B, H, W

XXXXXXXX XXXXXXXX

RCR [R/W] B, H, W

00XXXXXX XXXX0XXX

Register

+

1

MCRB [R/W] B, H, W

XXXXXXXX

IOWR1 [R/W] B, H, W

XXXXXXXX

CHER [R/W] B, H, W

11111111

+

2

+

3

⎯ Reserved

ACR0 [R/W] H, W

1111XX00 00000000

ACR1 [R/W] B, H, W

XXXXXXXX XXXXXXXX

ACR2 [R/W] B, H, W

XXXXXXXX XXXXXXXX

ACR3 [R/W] B, H, W

XXXXXXXX XXXXXXXX

ACR4 [R/W] B, H, W

XXXXXXXX XXXXXXXX

ACR5 [R/W] B, H, W

XXXXXXXX XXXXXXXX

ACR6 [R/W] B, H, W

XXXXXXXX XXXXXXXX

ACR7 [R/W] B, H, W

XXXXXXXX XXXXXXXX

AWR1 [R/W] B, H, W

Block

XXXXXXXX XXXXXXXX

T-unit

AWR3 [R/W] B, H, W

XXXXXXXX XXXXXXXX

AWR5 [R/W] B, H, W

XXXXXXXX XXXXXXXX

AWR7 [R/W] B, H, W

XXXXXXXX XXXXXXXX

⎯

IOWR2 [R/W] B, H, W

XXXXXXXX

⎯

TCR [R/W] B, H, W

⎯

00000000 (INIT)

0000XXXX (RST)

⎯

(Continued)

45

MB91301 Series

Address

00068C

to

0007F8

0007FC

000800

to

000AFC

000B00

000B04

000B08

000B0C

000B10 000B14

to

000B1C

000B20

000B24

000B28

000B2C

000B30

000B34

000B38

000B3C

000B40

000B44

H

ESTS0 [R/W] B

H

X0000000

ECTL0 [R/W] B

0X000000

ECNT0 [W] B

XXXXXXXX

+

⎯

0

+

MODR [W] *

XXXXXXXX

ESTS1 [R/W] B

XXXXXXXX

ECTL1 [R/W] B

00000000

ECNT1 [W] B

XXXXXXXX

EWPT [R] H

00000000 00000000

EDTR0 [W] H

XXXXXXXX XXXXXXXX

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

Register

1

⎯ Reserved

2

⎯ Reserved

⎯

EIA0 [W] W

EIA1 [W] W

EIA2 [W] W

EIA3 [W] W

EIA4 [W] W

EIA5 [W] W

EIA6 [W] W

EIA7 [W] W

EDTA [R/W] W

EDTM [R/W] W

+

2

ESTS2 [R] B

1XXXXXXX

ECTL2 [W] B

000X0000

EUSA [W] B

XXX00000

ECTL4 [R] ([R/W]) B

-

0X00000

EDTR1 [W] H

XXXXXXXX XXXXXXXX

+

3

⎯ T-unit

⎯

ECTL3 [R/W] B

00X00X11

EDTC [W] B

0000XXXX

ECTL5 [R] ([R/W]) B

- - - - 000X

DSU

(Evaluation

chip only)

(Continued)

Block

46

MB91301 Series

Address

000B48

000B4C

000B50

000B54

000B58

000B5C

000B60

000B64

000B68

000B6C

000B70

to

000FFC

001000

001004

001008

00100C

001010

001014

001018

00101C

001020

Register

Block

+

0

H

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

+

1

EOA0 [W] W

EOA1 [W] W

EPCR [R/W] W

EPSR [R/W] W

EIAM0 [W] W

EIAM1 [W] W

EOAM0/EODM0 [W] W

EOAM1/EODM1 [W] W

EOD0 [W] W

EOD1 [W] W

+

2

+

3

DSU

Evaluation

(

chip only

)

⎯ Reserved

H

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMASA0 [R/W] W

DMADA0 [R/W] W

DMASA1 [R/W] W

DMADA1 [R/W] W

DMASA2 [R/W] W

DMADA2 [R/W] W

DMASA3 [R/W] W

DMADA3 [R/W] W

DMASA4 [R/W] W

DMAC

(Continued)

47

MB91301 Series

(Continued)

Address

001024 001028

+

0

H

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

+

to

001FFC

H

*1 : Byte access is not permitted for the lower 16 bits of DMAC0 to DMAC4 (DTC15 to DTC0) . *2 : This register is accessed through mode vector fetch; it cannot be accessed in normal mode.

Register

1

DMADA4 [R/W] W

⎯ Reserved

+

2

+

3

Block

DMAC

48

INTERRUPT VECTORS

■

MB91301 Series

Interrupt

Interrupt No.

10 16

Interrupt

1

level*

Offset

Reset 0 00 ⎯ 3FC Mode vector 1 01 ⎯ 3F8 System reserved 2 02 ⎯ 3F4 System reserved 3 03 ⎯ 3F0 System reserved 4 04 ⎯ 3EC System reserved 5 05 ⎯ 3E8 System reserved 6 06 ⎯ 3E4 Coprocessor absent trap 7 07 ⎯ 3E0 Coprocessor error trap 8 08 ⎯ 3DC INTE instruction 9 09 ⎯ 3D8 Instruction break exception 10 0A ⎯ 3D4 Operand break trap 11 0B ⎯ 3D0 Step trace trap 12 0C ⎯ 3CC NMI request (tool) 13 0D ⎯ 3C8 Undefined instruction exception 14 0E ⎯ 3C4

NMI request 15 0F

H

fixed

3C0

)

15 (F

External interrupt 0 16 10 ICR00 3BC

TBR default

address*

H

000FFFFC

000FFFF8 000FFFF4 000FFFF0

000FFFEC

000FFFE8 000FFFE4 000FFFE0

000FFFDC

000FFFD8 000FFFD4 000FFFD0

000FFFCC

000FFFC8 000FFFC4

000FFFC0

000FFFBC

2

H

RN

H

⎯ ⎯ ⎯ ⎯

H

⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯

⎯

6 External interrupt 1 17 11 ICR01 3B8 External interrupt 2 18 12 ICR02 3B4 External interrupt 3 19 13 ICR03 3B0 External interrupt 4 20 14 ICR04 3AC External interrupt 5 21 15 ICR05 3A8 External interrupt 6 22 16 ICR06 3A4 External interrupt 7 23 17 ICR07 3A0 Reload timer 0 24 18 ICR08 39C Reload timer 1 25 19 ICR09 398 Reload timer 2 26 1A ICR10 394 UART0 (RX completed) 27 1B ICR11 390 UART1 (RX completed) 28 1C ICR12 38C UART2 (RX completed) 29 1D ICR13 388 UART0 (TX completed) 30 1E ICR14 384 UART1 (TX completed) 31 1F ICR15 380 UART2 (TX completed) 32 20 ICR16 37C

H

000FFFB8 000FFFB4 000FFFB0

000FFFAC

000FFFA8 000FFFA4 000FFFA0 000FFF9C

000FFF98 000FFF94 000FFF90

000FFF8C

000FFF88 000FFF84 000FFF80

000FFF7C

H

7

11 12

⎯ ⎯ ⎯ ⎯

8

9

10

0

1

2

3

4

5

(Continued)

49

MB91301 Series

Interrupt

Interrupt No.

10 16

Interrupt

1

level*

Offset

DMAC0 (end, error) 33 21 ICR17 378 DMAC1 (end, error) 34 22 ICR18 374 DMAC2 (end, error) 35 23 ICR19 370 DMAC3 (end, error) 36 24 ICR20 36C DMAC4 (end, error) 37 25 ICR21 368 A/D 38 26 ICR22 364 PPG0 39 27 ICR23 360 PPG1 40 28 ICR24 35C PPG2 41 29 ICR25 358 PPG3 42 2A ICR26 354 System reserved 43 2B ICR27 350 U-TIMER0 44 2C ICR28 34C U-TIMER1 45 2D ICR29 348 U-TIMER2 46 2E ICR30 344 Time base timer overflow 47 2F ICR31 340

2

C I/F0 48 30 ICR32 33C

I

2

C I/F1 49 31 ICR33 338

I

TBR default

address*

H

000FFF78 000FFF74 000FFF70

000FFF6C

000FFF68 000FFF64 000FFF60

000FFF5C

000FFF58 000FFF54 000FFF50

000FFF4C

000FFF48 000FFF44 000FFF40

000FFF3F

000FFF38

2

H

RN

⎯ ⎯ ⎯

H

⎯ ⎯

15 13

H

14

⎯ ⎯ ⎯

H

⎯ ⎯ ⎯ ⎯ ⎯ ⎯

System reserved 50 32 ICR34 334 System reserved 51 33 ICR35 330 16 bit Free Run Timer 52 34 ICR36 32C ICU0 (load) 53 35 ICR37 328 ICU1 (load) 54 36 ICR38 324 ICU2 (load) 55 37 ICR39 320 ICU3 (load) 56 38 ICR40 31C System reserved 57 39 ICR41 318 System reserved 58 3A ICR42 314 System reserved 59 3B ICR43 310 System reserved 60 3C ICR44 30C System reserved 61 3D ICR45 308 System reserved 62 3E ICR46 304 Delay interrupt bit 63 3F ICR47 300 System reserved (Used by REALOS) 64 40 ⎯ 2FC System reserved (Used by REALOS) 65 41 ⎯ 2F8 System reserved 66 42 ⎯ 2F4

H

000FFF34 000FFF30

000FFF2C

000FFF28 000FFF24 000FFF20

000FFF1C

000FFF18 000FFF14 000FFF10

000FFF0C

000FFF08 000FFF04

000FFF00 000FFEFC 000FFEF8 000FFEF4

H

⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯

(Continued)

50

(Continued)

Interrupt

Interrupt No.

10 16

Interrupt

1

level*

MB91301 Series

Offset

TBR default

address*

2

RN

System reserved 67 43 ⎯ 2F0 System reserved 68 44 ⎯ 2EC System reserved 69 45 ⎯ 2E8 System reserved 70 46 ⎯ 2E4 System reserved 71 47 ⎯ 2E0 System reserved 72 48 ⎯ 2DC System reserved 73 49 ⎯ 2D8 System reserved 74 4A ⎯ 2D4 System reserved 75 4B ⎯ 2D0 System reserved 76 4C ⎯ 2CC System reserved 77 4D ⎯ 2C8 System reserved 78 4E ⎯ 2C4 System reserved 79 4F ⎯ 2C0

Used by INT instruction

80 to

255

50 to

FF

⎯

2BC

to

000

H

000FFEF0 000FFEEC 000FFEE8 000FFEE4 000FFEE0 000FFEDC 000FFED8 000FFED4 000FFED0 000FFECC 000FFEC8 000FFEC4 000FFEC0 000FFEBC

to

000FFC00

H

*1 : ICRs are registers built in the interrupt controller to set interrupt levels for individual interrupt requests.

The ICRs are provided for the different interrupt levels.

⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯

⎯

*2 : The TBR is the register holding the start address of the EIT vector table.

The TBR value and the offset value preset for each EIT source are added together to be the vector address.

Note: The 1 Kbyte area from the TBR address is the EIT vector area.

The vector size is 4 b ytes and the relationship between v e ctor number and vector address is expressed as follows:

Vctadr = TBR + vctofs

= TBR + (3FC

− 4 × vct)

H

vctadr : vector address vctofs : vector offset vct : vector number

51

MB91301 Series

INSTRUCTION CACHE

■

The instruction cache is a fast local memory for temporary storage. Once an instruction code is accessed from external slower memory , the instruction cache holds the instruction code inside to increase the speed of accessing the same code from then on. By setting the RAM mode, the instruction cache data RAM is made directly read/write-accessible by software.

• Configuration

• FR family’s basic instruction length : Two bytes

• Block layout : Two-way set associative

• Blocks : 128 blocks per way 16 bytes per block ( = 4 sub-blocks) 4 bytes per sub-block ( = 1 bus access unit)

• Instruction Cache Configuration

4 bytes 4 bytes 4 bytes 4 bytes 4 bytes

Way 1

I3 I2 I1 I0

128 block

Way 2

128

block

Cash tag

Sub

block 3

Sub

block 3

Sub

block 3

Sub

block 3

Sub

block 2

Sub

block 2

Sub

block 2

Sub

block 2

Sub

block 1

Sub

block 1

Sub

block 1

Sub

block 1

Sub

block 0

Sub

block 0

Sub

block 0

Sub

block 0

block 127

block 0

block 127

52

MB91301 Series

• Instruction Cache Tags Way 1

31 09 08

Address tag

07 06 05 04 03 02 01 00

SBV2SBV3 SBV1 SBV0 TAGV LRU ETLK

Way 2

31 09 08

Address tag

07 06 05 04 03 02 01 00

SBV2SBV3 SBV1 SBV0 TAGV ETLK

[bit 31 to bit 9] Address tag

The address tag stores the upper 23 bits of the memory address of the instruction cached in the corresponding block. For example, memor y address IA of the instruction data stored in sub-block k in block i is obtained from the following equation:

IA = address tag × 2

9

+ i × 24 + k × 2

2

The address tag is used to check for a match with the instruction address requested for access by the CPU. The CPU and cache behave as follows depending on the result of the tag check:

Vacancy

• When the requested instruction data exists in the cache (hit), the cache transfers the data to the CPU within the cycle.

• When the requested instruction data does not exist in the cache (miss), the CPU and cache obtain the data loaded by external access at the same time.

[bit 7 to bit4] SBV3 to SBV0 : Sub-block validation

When SBV

contains "1", the corresponding sub-block holds the current instruction data at the address located

n

by the tag. Each sub-block usually holds two instructions (excluding immediate-value transfer instructions).

[bit 3] TAGV : Tag validation bit

This bit indicates whether the address tag value is valid. When the bit contains "0", the corresponding block is invalid regardless of the settings of the sub-b lock v alidation bits. (The bit is set to "0" when the cache is flushed.)

[bit 1] LRU (only in way 1)

This bit exists only in the instruction cache tag in wa y 1. The bit indicates w ay 1 or 2 as the way containing the last entry accessed in the selected set. When set to "1", the LRU bit indicates that the entry of the set in way 1 is the last entry accessed. When set to "0", it indicates that the one in way 2 is the last entry accessed.

[bit 0] ETLK : Entry lock

This bit is used to lock all the entries in the block corresponding to the tag in the cache. When the ETLK bit is set to "1", the entries are locked and are not updated when a cache miss occurs. Note, however, that invalid sub-blocks are updated. If a cache miss occurs with both of ways 1 and 2 in the entr y lock states, access to external memory takes place after losing one cycle used for evaluating the cache miss.

53

MB91301 Series

76543210

A 0 0 0 0 0 0

T 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Control Registers

• Cache Size Register (ISIZE) bit Initial value

Address : 00000307

76543210

H

⎯⎯⎯⎯⎯⎯SIZE1 ⎯⎯⎯⎯⎯⎯R/W

• Instruction Cache Control Register (ICHCR)

The instruction cache (I-cache) control register (ICHCR) controls the operations of the instruction cache. Writing a value to the ICHCR has no effect on the caching of an y instruction fetched within three cycles that follow .

bit Initial value

Address : 000003E7

ddress 0010000H 0010200H 0010400H 0010600H 0010800H 0010FFFH 0014000H

54

0014200H 0014400H 0014600H 0014800H 0014FFFH 0018000H 0018200H 0018400H 0018600H 0018800H 0018FFFH 001C000H 001C200H 001C400H 001C600H 001C800H 001CFFFH

AG RAM 0010000H 0010004H 0010008H 001000CH 0010010H 0010014H

TAG1 ⋅⋅⋅TAG RAM (way1) TAG2 ⋅⋅⋅TAG RAM (way2) <> ⋅⋅⋅Mirror area RAM on/off⋅⋅⋅RAM bit = I/O

H

Cache off

RAM off

IRAM1 IRAM1

IRAM2 IRAM2

<IRAM2>

Cache off

RAM on

TAG1

<TAG1>

TAG2

<TAG2>

←Entry at address 00x ←Mirror of 00x

⎯RAM GBLK ALFL EOLK ELKR FLSH ⎯R/W R/W R/W R/W R/W R/W

Cache 4 K

RAM off

Cache 4 K

RAM on

TAG1

<TAG1>

TAG2

<TAG2>

$RAM1

<$RAM1>

$RAM2

<$RAM2>

Cache 2 K

RAM off

IRAM1

<IRAM1>

IRAM2

<IRAM2>

Cache 2 K

RAM on

TAG1

TAG2

$RAM1 IRAM1

<$RAM1>

$RAM2 IRAM2

<$RAM2>

SIZE0

R/W

ENAB

R/W

Cache 1 K

RAM off

IRAM1

<IRAM1>

IRAM2

- - - - - - 10

0 - 000000

RAM on

<$RAM1>

<$RAM2>

Cache

TAG1 <TAG1> <TAG1> <TAG1> <TAG1>

TAG2 <TAG2>

$RAM1 IRAM1

$RAM2 IRAM2

B

$RAM1 ⋅⋅⋅Cache RAM (way1) IRAM1 ⋅⋅⋅I-bus RAM (way1) $RAM2 ⋅⋅⋅Cache RAM (way2) IRAM1 ⋅⋅⋅I-bus RAM (way2)

Cache RAM 00018000 00018004H 00018008H 0001800CH 00018010H 00018014H

H

Instruction at address 000 (SBV0) Instruction at address 004 (SBV1) Instruction at address 008 (SBV2) Instruction at address 00C (SBV3) Instruction at address 010 (SBV0) Instruction at address 014 (SBV1)

⋅⋅⋅

MB91301 Series

A

0

0 0 0 0

0 F

ddress Cache 4 K Cache 2 K Cache 1 K Cache off

000 200H 400H 600H

000H 200H 400H 600H

H

$RAM1

IRAM1

$RAM2

$RAM2 IRAM2

IRAM2

$RAM1 IRAM1

$RAM2 IRAM2

IRAM1

Address

0000000H

0010000H 0020000H 0030000H 0040000H

0100000H FFFFFFFH

ROMA = 0

(ROM absent)

ROMA = 1

(ROM present)

Direct area Direct area

IRAM IRAM

Internal

Cache area

memory

Cache area

(Even the D-bus RAM area is cashed, when it is transferred to the IA-Bus.) Internal ROM/RAM area should be cached.

Each chip-select area can be set as a non-cache area.

55

MB91301 Series

PERIPHERAL RESOURCES

■

1. External Bus Interface Controller

•

External Bus Interface Controller Features

• Maximum output address width = 32-bit (4 Gbytes memory space)

• Various diff erent types of external memory (8-bit, 16-bit, or 32-bit devices) can be directly connected and the controller can support multiple devices with different access timings. Asynchronous SRAM, asynchronous ROM/FLASH memory (supports multiple write strobe access or byteenable access) Page mode ROM/FLASH memory (2, 4, or 8 page size) Burst mode ROM/FLASH memory Address/data multiplexed bus (8-bit or 16-bit width only) Synchronous memory (built-in ASIC memory, etc.)

Synchronous SRAM cannot be directly connected.

Note:

• Memory can be divided into eight independent banks (chip select areas) with a separate chip select output for each bank. The size of each area can be set in 64 Kbytes increments (the size of each chip select area can range from 64 Kbytes to 2 Gbytes) Each area can be located anywhere in the physical address space (subject to boundary limitations based on the area size)

• The following functions can be set independently for each chip select area : Chip select area enable/disable (Access is not performed to disabled areas) Setting of an access timing type to support each type of memory (For SDRAM, only the CS6 can be connected.) Detailed access timing settings (wait cycles and similar settings for each access type) Data bus width (8-bit, 16-bit, 32-bit) Byte-ordering setting (big or little endian)

The CS0 area must be big endian.

Note:

Write-prohibit setting (read-only areas) Enable or disable loading into built-in cache Enable or disable prefetch function Maximum burst length setting (1, 2, 4, 8)

• Different detailed timing settings can be set for each timing type Even for the same type, different settings can be used for each chip select area. Up to 15 auto-wait cycles can be specified. (For asynchronous SRAM, ROM, Flash, and I/O areas) The bus cycle can be extended by the external RDY input. (For asynchronous SRAM, ROM, Flash, and I/O areas) Fast access wait and page wait settings are supported (For burst/page mode ROM and Flash areas) Idle cycles, recovery cycles, setup delays, and similar can be inserted. Capable of setting timing values such as the CAS latency and RAS-CAS delay (SDRAM area) Capable of controlling the distributed/centralized auto-refresh, self-refresh, and other refresh timings (SDRAM area)

• DMA supports fly-by transfer Transfer between memory and I/O can be performed by a single access. Memory wait cycles can be synchronized with the I/O wait period during fly-by transfer. Hold times can be maintained by extending access to the data source only. Separate idle and recovery cycle settings can be specified for use in fly-by transfer.

• Supports external bus arbitration using BRQ and BGRNT

• Pins not used by the external interface can be set as general purpose I/O ports.

.

and CS7 areas

56

• Block Diagram

L,

MB91301 Series

Internal

address bus

Internal

data bus

3232

write buffer

read buffer

switch

+1 or +2

MUX

DATA BLOCK

ADDRESS BLOCK

External data bus

External address bus

address buffer

ASR ASZ

comparator

CS0 to CS7

SDRAM control

RCR under flow

refresh counter

External pin controller

All block control

registers

&

control

SRAS, SCAS, SWE, MCLKE, DQMUU, DQMU DQMLU, DQMLL

RD WR0, WR1, WR2, WR3, AS, BAA

BRQ BGRNT RDY

57

MB91301 Series

• I/O pin External interface pin (Some pins are general purpose pins.) The following shows I/O pins of each interface.

• Normal bus interface A23 to A00, D31 to D00 (AD15 to AD00)

, CS1, CS2, CS3, CS4, CS5, CS6, CS7

CS0 AS, SYSCLK, MCLK, RD WR, WR0 (UUB) , WR1 (ULB) , WR2 (ULB) , WR3 (LLB) , RDY, BRQ, BGRNT

• Memory interface MCLK, MCLKE MCLKI (for SDRAM) LBA

( = AS) , BAA (for burst ROM/FLASH)

SRAS

, SCAS, SWE ( = WR) (for SDRAM)

DQMUU, DQMUL, DQMLU, DQMLL (for SDRAM ( = WR0, WR1, WR2, WR3) )

• DMA interface IOWR

, IORD DACK0, DACK1 DREQ0, DREQ1 DEOP0, DEOP1

58

• Register List

)

31 2324 1516 0708 00

ASR0 ACR0 ASR1 ACR1 ASR2 ACR2 ASR3 ACR3 ASR4 ACR4 ASR5 ACR5 ASR6 ACR6

ASR7 ACR7 AWR0 AWR1 AWR2 AWR3 AWR4 AWR5 AWR6

MCRA MCRB

Reserved

IOWR0 IOWR1

Reserved

CSER CHER TCR

Reserved Reserved Reserved Reserved Reserved

Reserved

RCR

Reserved Reserved Reserved

Reserved

(MODR)

Reserved Reserved Reserved Reserved Reserved Reserved

Reserved Reserved Reserved Reserved

Reserved

AWR7

Reserved

Reserved Reserved Reserved

Reserved Reserved Reserved Reserved Reserved Reserved

MB91301 Series

Area select registers 0 to 7 (ASR0 to ASR7) Area configuration registers 0 to 7 (ACR0 to ACR7)

Area weight register (AWR0 to AWR7)

Memory setting register

(For SDRAM/FCRAM auto-precharge OFF mode) (MCRA Memory setting register (For FCRAM auto-precharge ON mode) (MCRB)

DMAC I/O wait registers (IOWR0 and IOWR1) Chip-select area enable register (CSER)

Cache fetch enable register (CHER)

Terminal and timing control register (TCR)

Refresh control register (RCR)

Notes : • Reserved indicates a reserved register. When writing, always set to “0”.

• The MODR register cannot be accessed by the user program.

59

MB91301 Series

P

2. I/O Ports

MB91301 series pins can be used as I/O ports when not set for use by the external bus interface or the various peripheral I/O functions.

• I/O port (with pull-up resistor) block diagram

ort Bus

Peripheral output

PDR

PFR

DDR

PCR

PDR read

Peripheral input

1

0

PCR = 0 : No pull-up resistor PCR = 1 : Use pull-up resistor

0

1

PDR

: Port Data Register

DDR

: Data Direction Register

PFR

: Port Function Register

PCR

: Pull-up Control Register

Pull-up resistor (approx. 25 kΩ)

Note : For port output, the pull-up resistor is disabled irrespective of the setting.

I/O ports with pull-up resistors have the following registers :

• PDR (Port Data Register)

• DDR (Data Direction Register)

• PFR (Port Function Register)

• PCR (Pull-up Control Register)

I/O ports have three following modes

• When port is in input mode (PFR = “0” & DDR = “0”) PDR read : Reads the level of the corresponding external pin. PDR write : Writes the value to the PDR.

• When port is in output mode (PFR = “0” & DDR = “1”) PDR read : Reads the PDR value. PDR write : Outputs the PDR value to the corresponding external pin.

• When port is in peripheral output mode (PFR = “1” & DDR = “X”) PDR : Reads the value of the corresponding peripheral output. PDR write : Writes the value to the PDR.

60

Notes : • Use byte access to access ports.

• The external bus function has priority for port 0 to port A when these are used as external bus pins. Accordingly, writing to the DDR has no effect on the pin input/output setting while the pins are operating as external bus pins. The value set in the DDR becomes meaningful when the PFR register is modified to set the pins as general purpose ports.

• In stop mode (HIZ = 0), the pull-up resistor control register setting is used.

• In stop mode (HIZ = 1), the pull-up resistor control register (PCR) setting is ignored during hardware

standby.

• Using pull-up resistors is prohibited when these pins are used as external bus pins. In this case, do not write “1” to the corresponding bit in the pull-up resistor control register (PCR).

MB91301 Series

61

MB91301 Series

R/W

R/WR/W R/W R/W R/W R/W R/W

R/W

R/WR/W R/W R/W R/W R/W R/W

R/W

R/WR/W R/W R/W R/W R/W R/W

R/W

R/WR/W R/W R/W R/W R/W R/W

R/W

R/WR/W R/W R/W R/W R/W R/W

R/W

R/WR/W R/W R/W R/W R/W R/W

R/W

R/WR/W R/W R/W R/W R/W R/W

• Port Data Register (PDR) PDR0 Initial value

Address : 00000000

76543210

H

P06P07 P05 P04 P03 P02 P01 P00

XXXXXXXX

B

PDR1 Initial value

Address : 00000001

PDR2 Initial value

Address : 00000002

PDR6 Initial value

Address : 00000006

PDR8 Initial value

Address : 00000008

PDR9 Initial value

Address : 00000009

PDRA Initial value

Address : 0000000A

76543210

H

P16P17 P15 P14 P13 P12 P11 P10

76543210

P26P27 P25 P24 P23 P22 P21 P20 R/WR/W R/W R/W R/W R/W R/W

76543210

P66P67 P65 P64 P63 P62 P61 P60

76543210

P86P87

76543210

P96⎯ P95 P94 P93 P92 P91 P90

76543210

PA6PA7 PA5 PA4 PA3 PA2 PA1 PA0

P85 P84 P83 P82 P81 P80

R/W

XXXXXXXX

- XXXXXXX

XXXXXXXX

B

PDRB Initial value

Address : 0000000B

PDRG Initial value

Address : 00000010

PDRH Initial value

Address : 00000011

PDRJ Initial value

Address : 00000013

76543210

H

PB6PB7 PB5 PB4 PB3 PB2 PB1 PB0 R/WR/W R/W R/W R/W R/W R/W

76543210

PG6PG7 PG5 PG4 PG3 PG2 PG1 PG0

R/WR/W R/W R/W R/W R/W R/W

76543210

⎯⎯⎯⎯⎯PH2 PH1 PH0

76543210

PJ6PJ7 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 R/WR/W R/W R/W R/W R/W R/W

XXXXXXXX

R/W

XXXXXXXX

R/W

- - - - - XXX

XXXXXXXX

R/W

• PDR0 to PDR2, PDR6, PDR8 to PDRB, PDRG, PDRH and PDRJ are the I/O data registers for the I/O pots.

• The corresponding PDR0 to DDRJ and PFR6 to PFRJ registers control input/output.

• P00 to P07, P10 to P17 and P20 to P27 do not have a PFR (port function register).

62

B

• Data Direction Register (DDR)

R/W

R/WR/W R/W R/W R/W R/W R/W

R/W

R/WR/W R/W R/W R/W R/W R/W

76543210

R/W

R/WR/W R/W R/W R/W R/W R/W

R/W

R/WR/W R/W R/W R/W R/W R/W

76543210

DDR0 Initial value

Address : 00000600

76543210

H

MB91301 Series

P06P07 P05 P04 P03 P02 P01 P00

00000000

B

DDR1 Initial value

Address : 00000601

DDR2 Initial value

Address : 00000602

DDR6 Initial value

Address : 00000606

DDR8 Initial value

Address : 00000608

DDR9 Initial value

Address : 00000609

DDRA Initial value

Address : 0000060A

76543210

H

P16P17 P15 P14 P13 P12 P11 P10

P26P27 P25 P24 P23 P22 P21 P20

76543210

P66P67 P65 P64 P63 P62 P61 P60

76543210

P86P87

76543210

P96⎯ P95 P94 P93 P92 P91 P90

76543210

PA6PA7 PA5 PA4 PA3 PA2 PA1 PA0

P85 P84 P83 P82 P81 P80

00000000

- 0000000

00000000

B

DDRB Initial value

Address : 0000060B

DDRG Initial value

Address : 00000400

DDRH Initial value

Address : 00000401

76543210

H

PB6PB7 PB5 PB4 PB3 PB2 PB1 PB0

76543210

PG6PG7 PG5 PG4 PG3 PG2 PG1 PG0

76543210

⎯⎯⎯⎯⎯PH2 PH1 PH0

00000000

- - - - - 000

B

DDRJ Initial value

Address : 00000403H

PJ6PJ7 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0

00000000

B

DDR0 to DDR2, DDR6, DDR8 to DDRB, DDRG, DDRH and DDRJ control the direction (input or output) of each bit in the corresponding port.

When PFR = 0DDR = 0 : Port input

DDR = 1 : Port output

When PFR = 1DDR = 0 : Peripheral input

DDR = 1 : Peripheral output

63

MB91301 Series

• Pull-up Resistor Control Register (PCR)

PCR0 bit Initial value

Address : 00000620

PCR1 bit Initial value

Address : 00000621

PCR2 bit Initial value

Address : 00000622

PCR6 bit Initial value

Address : 00000626

PCR8 bit Initial value

Address : 00000628

PCR9 bit Initial value

Address : 00000629

PCRA bit Initial value

Address : 0000062A

PCRB bit Initial value

Address : 0000062B

PCRH bit Initial value

Address : 00000421

H

76543210

P06P07 P05 P04 P03 P02 P01 P00

R/WR/W R/W R/W R/W R/W R/W

76543210

P16P17 P15 P14 P13 P12 P11 P10

R/WR/W R/W R/W R/W R/W R/W

76543210

P26P27 P25 P24 P23 P22 P21 P20

R/WR/W R/W R/W R/W R/W R/W

76543210

P66P67 P65 P64 P63 P62 P61 P60

R/WR/W R/W R/W R/W R/W R/W

76543210

P86P87

R/WR/W R/W R/W R/W R/W R/W

76543210

P96⎯ P95 P94 ⎯⎯P91 ⎯

R/WR/W R/W R/W R/W R/W R/W

76543210

PA6PA7 PA5 PA4 PA3 PA2 PA1 PA0 R/WR/W R/W R/W R/W R/W R/W

76543210

PB6PB7 PB5 PB4 PB3 PB2 PB1 PB0 R/WR/W R/W R/W R/W R/W R/W

76543210

⎯⎯⎯⎯⎯PH2 PH1 PH0

R/WR/W R/W R/W R/W R/W R/W

P85 P84 P83 P82 P81 P80

R/W

00000000

- 000 - - 0 -

00000000

- - - - - 000

B

PCR0 to PCR2, PCR6, PCR8 to PCRB, PCRG, PCRH and PCRJ control the pull-up resistors for the corresponding port.

PCR = 0 : No pull-up resistor PCR = 1 : Use pull-up resistor

64

• Port Function Register (PFR)

MB91301 Series

PFR6 bit Initial value

Address : 00000616

PFR8 bit Initial value

Address : 00000618

PFR9 bit Initial value

Address : 00000619

PFRA1 bit Initial value

Address : 0000061A

PFRB1 bit Initial value

Address : 0000061B

PFRB2 bit Initial value

Address : 0000061C

PFRA2 bit Initial value

Address : 0000061E

PFRG bit Initial value

Address : 00000410

PFRH bit Initial value

Address : 00000411

PFRJ bit Initial value

Address : 00000413

PFR61 bit Initial value

Address : 00000617

H

76543210

A22EA23E A21E A20E A19E A18E A17E A16E

R/WR/W R/W R/W R/W R/W R/W

76543210

WR2XEWR3XE WR1XE ⎯⎯BRQE ⎯⎯

R/WR/W R/W R/W R/W R/W R/W

76543210

WRXE⎯ BAAE ASXE ⎯ MCKE MCKEE SYSE

R/WR/W R/W R/W R/W R/W R/W

76543210

CS6XECS7XE CS5XE CS4XE CS3XE CS2XE CS1XE CS0XE

R/WR/W R/W R/W R/W R/W R/W

76543210

AK12DES1 AK11 AK10 DES0 AK02 AK01 AK00

R/WR/W R/W R/W R/W R/W R/W

76543210

DWREDRDE PPE1 ⎯⎯⎯AKH1 AKH0

R/WR/W R/W R/W R/W R/W R/W

76543210

⎯⎯ PPE2 ⎯⎯⎯⎯⎯

R/WR/W R/W R/W R/W R/W R/W

76543210

SOE2SCE2 ⎯⎯⎯⎯⎯⎯

R/WR/W R/W R/W R/W R/W R/W

76543210

⎯⎯⎯⎯⎯⎯PPE3 ⎯

R/WR/W R/W R/W R/W R/W R/W

76543210

PPE0⎯ SCE1 SOE1 ⎯ SCE0 SOE0 ⎯

R/WR/W R/W R/W R/W R/W R/W

76543210

⎯⎯⎯⎯ TEST0 I2CE1 I2CE0TEST1

R/WR/W R/W R/W R/W R/W R/W

R/W

11111111

111 - - 0 - -

- 0000111

11111111

00000000

000 - - - 00

- - 0 - - - - -

00 - - - - - -

- - - - - - 0 -

- 000 - 00 -

- - - - 0000

B

PFR6, PFR8 to PFRB, PFRA2, PFRG, PFRH and PFRJ control the output for the corresponding external bus interface or peripheral output bit. Always write "0" to unused bits in the PFR.

65

MB91301 Series

3. Interrupt Controller

The interrupt controller receives and processes interrupts.

•

Hardware Configuration

The interrupt controller consists of the following :

• ICR register

• Interrupt priority determination circuit

• Interrupt level and interrupt number (vector) generator

• Hold request removal request generator

•

Principal Functions

The main functions of the interrupt controller are as follows :

• Detect NMI and interrupt requests

• Prioritize interrupts (according to level and number)

• Notify interrupt level of selected interrupt request (to CPU)

• Notify interrupt number of selected interrupt request (to CPU) If an NMI or interrupt request with an interrupt level other than "11111 (to CPU)

• Generate hold request removal requests to the bus master

" occurs, notify recovery from stop mode

B

• Block Diagram

RI00

RI47

(DLYIRQ)

UNMI WAKEUP

Determine order of priority

NMI

processing

LEVEL

determination

ICR00

determination

ICR47

VECTOR

5

VECTOR

(“1” when LEVEL

(“1” when LEVEL ≠ 11111B)

LEVEL,

VECTOR

genera-

tion

6

11111B)

≠

HLDREQ

removal

request

LEVEL4 to LEVEL40

MHALTI

VCT5 to VCT50

66

R-bus

MB91301 Series

0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

0

0 0 0

0

0 0 0

0

• Register List

7bit 654 321 0

Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address :

00000440H 00000441H 00000442H 00000443H 00000444H 00000445H 00000446H 00000447H 00000448H 00000449H

000044AH 000044BH 000044CH 000044DH 000044EH

000044FH 00000450H 00000451H 00000452H 00000453H 00000454H 00000455H 00000456H 00000457H 00000458H 00000459H

000045AH 000045BH 000045CH 000045DH 000045EH

000045FH

⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0

ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR3 ICR3

(Continued)

67

MB91301 Series

2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7

L

0

0 0 0

0

(Continued)

7bit 654 321 0

Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address :

00000460 00000461 00000462 00000463 00000464 00000465 00000466 00000467 00000468 00000469

000046A 000046B 000046C 000046D 000046E

000046F

H H H H H H H H H H H H H H H H

⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0 ⎯⎯⎯ICR4 ICR3 ICR2 ICR1 ICR0

ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4

Address :

0000045

MHALTI LVL4 LVL3 LVL2 LVL1 LVL0

H

⎯⎯

HRC

68

MB91301 Series

4. External Interrupt/NMI Control Block

The external interrupt control block controls e xternal interrupt requests input to the NMI and INT0 to INT7 pins. The interrupt trigger level can be selected from "H", "L", "rising edge", or "falling edge" (except for NMI).

• Block Diagram

R-bus

Interrupt

8

9

Interrupt enable register

Gate

request

8

Interrupt request register

Interrupt level setting register

• Register List External interrupt enable register (ENIR)

bit

76543210

EN6EN7 EN5 EN4 EN3 EN2 EN1 EN0

External interrupt request register (EIRR)

bit

15 14 13 12 11 10 9 8

ER6ER7 ER5 ER4 ER3 ER2 ER1 ER0

Request level setting register (ELVR)

bit

15 14 13 12 11 10 9 8

LA7LB7 LB6 LA6 LB5 LA5 LB4 LA4

Request F/F

Edge detection circuit

9

INT0 to INT7 NMI

bit

76543210

LA3LB3 LB2 LA2 LB1 LA1 LB0 LA0

69

MB91301 Series

76543210

5. Delay Interrupt Module

The delay interrupt module is used to generate interrupts for task switching. This module can be used to generate and cancel interrupts to the CPU via software.

• Block Diagram

R-bus

DLYI

Interrupt request

• Register List

Delay interrupt control register (DICR)

bit

⎯⎯ ⎯ ⎯⎯⎯⎯DLYI

70

MB91301 Series

6. PPG Timer

The PPG timer can output highly precise PWM waveforms efficiently. The MB91301 series contains four channels of PPG timer.

• Features of the PPG Timer

• Each channel consists of a 16-bit down counter , a 16-bit data register with cycle setting buffer , a 16-bit compare register with duty setting buffer, and pin control section.

• The count clocks for the 16-bit down counter can be selected from the following four types : Internal clock φ, φ/4, φ/16, φ/64

• The counter is initialized to “FFFF

• Each channel has a PPG output.

• Register outline

Cycle setting register: Reload data register with buffer Duty setting register: Compare register with buffer Transfer from the buffer takes place upon a counter borrow.

• Pin control overview

A duty match sets the pin control section to 1. (Preferential) A counter borrow resets it to 0. The output value fix mode is available, which can each output all "L" (or "H"). A polarity can also be specified.

• An interrupt request can be generated at a combination of the following events :

Activation of the PPG timer Counter borrow (cycle match) Duty match Counter borrow (cycle match) or duty match

DMA transfer can be initiated by the above interrupt request.

• It is possible to set the simultaneous activation of two or more channels by means of software or another interval timer. Restarting during operation can also be set.

• The request lev el to be detected can be selected from among "rising edge", "falling edge", and "both edges".

” at a reset or counter borrow.

H

71

MB91301 Series

0

1

2

3

• Block diagram

16-bit reload timer

ch0

16

bit reload timer

ch1

General control

register 2

External TRG0 to TRG3

• Block diagram for 1 channel

Prescaler

4

PCSR

General

control

register 1

(resource select)

PDUT

TRG input PPG timer ch0

TRG input PPG timer ch1

TRG input PPG timer ch2

TRG input PPG timer ch3

PPG

1 / 1 1 / 4

1 / 16

1 / 64

Peripheral clock

TRG input

CK

16-bit down counter

Start Borrow

Enable

Edge

detection

Soft trigger

Load

PPG mask

SRQ

Conversion

bit

Interrupt

cmp

IRQ

selection

PPG output

72

• Register List

b

0

it

15 7

GCN10

MB91301 Series

General control register 10

GCN20

PTMR0

PCSR0

PCNH0

PCNH1

PDUT0

PTMR1

PCSR1

PDUT1

PTMR2

PCNL0

PCNL1

General control register 20

ch0 timer register

ch0 cycle setting register

ch0 duty setting register

ch0 control status register

ch1 timer register

ch1 cycle setting register

ch1 duty setting register

ch1 control status register

ch2 timer register

PCNH2

PCNH3

PCSR2

PDUT2

PTMR3

PCSR3

PDUT3

PCNL2

PCNL3

ch2 cycle setting register

ch2 duty setting register

ch2 control status register

ch3 timer register

ch3 cycle setting register

duty setting register

ch3

ch3 control status register

73

MB91301 Series

Q

7. 16-Bit Reload Timer

The 16-bit timer consists of a 16-bit down-counter, 16-bit reload register, prescaler for generating the internal count clock, and a control register. The clock source can be selected from three internal clock signals (machine clock divided by 2, 8, or 32) or the external event. The interrupt can be used to initiate DMA transfer. The MB91301 series has three 16-bit reload timer channels.

• Block Diagram

16

7

16

R-bus

3

CLKP input

16-bit reload register (TMRLR)

16-bit down counter (TMR) UF

Count enable

Clock selector

EXCK

φ 2

1

φ2φ

35

2

Prescaler

clear

CSL1 CSL0

3

IN CTL.

MOD0 MOD1 MOD2

Reload

OUT CTL.

Re-trigger

External

trigger

selection

RELD

INTE

UF

CNTE

TRG

IR

External trigger input (TI)

74

3

• Register List

15 14 13 12 11 10 9 8

76543210

1

0

1

0

MB91301 Series

Control status register (TMCSR

bit

16-bit timer register (TMR

bit

)

5

16-bit reload register (TMRLR

bit

5

)

⎯⎯⎯⎯CSL1 CSL0 MOD2 MOD1

⎯MOD0 OUTL RELD INTE UF CNTE TRG

)

75

MB91301 Series

u

8. U-TIMER (16 bit timer for UART baud rate generation)

The U-TIMER is a 16-bit timer used to generate the baud rate for the UART. Any desired baud rate can be set using the combination of the chip operating frequency and U-TIMER reload value. The U-TIMER can also be used as an interval timer by generating an interrupt from a count underflow event. The MB91301 series has three U-TIMER channels. When used as an interval timer, two U-TIMER channels can be connected in cascade for a maximum count interval of up to 2 Cascade connection is only available for ch0 and ch1 or ch0 and ch2.

• Block Diagram

32

× φ.

φ (CLKP)

(Peripheral clock)

nder flow U-TIMER 1

15

MUX

ch0 only

UTIMR (reload register)

load

UTIM (timer)

clock

underflow

f.f.

0

control

to UART

76

• Register List

MB91301 Series

15 0

87

UTIM

UTIMR

UTIMC

• U-TIMER (UTIM)

Address bit Initial value 000064

00006C 000074

(ch 0)

H

(ch 1)

H

(ch 2)

H

15 14 2 1 0

b14b15 b2 b1 b0

RRRR

00000000 00000000

R

UTIM contains the timer value. Use a 16-bit transfer instruction to access the register. Reload register (UTIMR)

Address bit Initial value 000064

00006C 000074

(ch 0)

H

(ch 1)

H

(ch 2)

H

15 14 2 1 0

b14b15 b2 b1 b0

WWWW

W

00000000 00000000

UTIMR is the register that contains the value to be reloaded to UTIM when UTIM causes an underflow. Use a 16-bit transfer instruction to access the register.

B

77

MB91301 Series

9. UART

The UART is a serial I/O port for asynchronous (start-stop synchronized) or CLK synchronized transmission. The MB91301 series has three UART channels.

•

UART Features

• Full duplex double buffer

• Asynchronous (start-stop synchronized) or CLK synchronized transmission

• Supports multi-processor mode

• Fully programmable baud rate The internal timer can be set to any desired baud rate (see “8. U-TIMER” description)

• Variable baud rate can be input from an external clock.

• Error detection functions (parity, framing, overrun)

• Transmission signal format is NRZ

• The interrupt can be used to initiate DMA transfer.

• The DMAC interrupt can be cleared by writing to the DRCL register.

78

• Block Diagram

Control signal

MB91301 Series

RX interrupt

(to CPU)

SCK (clock)

From U-TIMER

External clock SCK

SI (Receive data)

Receive status decision circuit

Clock

selection

circuit

RX clock

RX control circuit

Start bit detect

Receive bit

Receive parity

TX clock

TX control circuit

circuit

counter

Send parity

counter

SO (Send data)

RX shifter

RX

complete

SIDR SODR

TX shifter

TX interrupt

(to CPU)

TX start

circuit

Send bit

counter

TX start

SMR

register

Receive error signal for DMA (to DMAC)

MD1 MD0

CS0

SCKE

R - bus

SCR

register

PEN P SBL CL A/D REC RXE TXE

SSR

register

PE ORE FRE RDRF TDRE BDS RIE TIE

Control

signal

79

MB91301 Series

)

• Register List

15 0

SSR

DRCL

8 bit 8 bit

Serial input data register Serial output data register (SIDR/SODR)

bit

76543210

D6D7 D5 D4 D3 D2 D1 D0

Serial status register (SSR)

bit

76543210

OREPE FRE RDRF TDRE BDS RIE TIE

Serial mode register (SMR)

bit

76543210

MD0MD1 ⎯⎯CS0 ⎯ SCKE ⎯

Serial control register (SCR)

bit

76543210

PPEN SBL CL A/D REC RXE TXE

87

SMRSCR

SIDR (R)/SODR (W)

(R/W (R/W

(W

DRCL register (DRCL)

bit

76543210

⎯⎯ ⎯ ⎯⎯⎯⎯ ⎯

80

MB91301 Series

10. A/D Converter (Successive Approximation Type)

The A/D converter converts analog input voltages to digital values.

•

A/D Converter Features

• Peripheral clock (CLKP) 140 clock cycle

• Minimum conversion time 4.1 µs/ch (for machine clock 34 MHz = CLKP)

• Built-in sample & hold circuit

• Resolution = 10-bit

• 4 channel program-selectable analog inputs

Single conversion mode : Convert 1 specified channel Scan conversion mode : Continuous conversion of multiple channels. Con version can be specified f or up

to 4 channels.

• Single, continuous, and stop conversion operation is supported.

Single conversion mode : Convert specified channel then stop. Continuous conversion mode : Perform continuous conversion for the selected channel. Stop conversion mode : Perform conv ersion f or one channel, then wait f or the next activ ation trigger

(synchronizes the conversion start timing)

• DMA transfer can be initiated by an interrupt.

• Selectable conv ersion activation trigger: Software, e xternal trigger (falling edge), or reload timer (rising edge)

81

MB91301 Series

A A A A

• Block Diagram

Sample & hold circuit

N0 N1 N2

Input switch

N3

Channel decoder

Timing generation circuit

AVRH AV

AVCC

SS AVR

Internal voltage

generator

Successive

approximation register

Data register

(ADCR : 10 bit)

Upper 8 bit COPY

Data register

(ADCR0 to ADCR7 : 8bit)

A/D control register

(ADCS)

R-bus

Machine clock φ (CLKP)

ATG

(External pin trigger)

Prescaler

Reload timer ch2 (internal connection)

• Register List Control status register (ADCS)

bit

Data register (ADCR)

bit

15 14 13 12 11 10 9 8

INTBUSY INTE CRF STS1 STS0 STRT ⎯

76543210

MD0MD1 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0

15 14 13 12 11 10 9 8

⎯⎯⎯⎯⎯⎯98

76543210

67 543210

Conversion result register (ADCR0 to ADCR3)

bit

76543210

67 543210

82

MB91301 Series

11. DMAC (DMA Controller)

The DMA controller is used to perform DMA (direct memory access) transfer on the FR family device. Using DMA transfer under the control of the DMA controller improves system performance by enabling data to be transferred at high speed independently of the CPU.

•

Hardware Configuration

• Independent DMA channels × 5 channels

• 5-channel independent access control circuits

• 32-bit address register (Supports reloading : 2 per channel)

• 16-bit transfer count register (Supports reloading : 1 per channel)

• 4-bit block count register (1 per channel)

• External transfer request input pins : DREQ0, DREQ1 (ch0, ch1 only)

• External transfer request acknowledge output pins : DACK0, DACK1 (ch0, ch1 only)

• DMA completion output pins : DEOP0, DEOP1 (ch0, ch1 only)

• fly-by transfer (memory to I/O , I/O to memory) (ch0, ch1 only)

• Two-cycle transfer

•

Main Functions of the DMA Controller

• Supports independent data transfer for multiple channels (5 channels) (1) Priority order (ch 0 > ch 1 > ch 2 > ch 3 > ch 4)

(2) Order can be reversed for ch 0 and ch 1 (3) DMAC activation triggers

• Input from dedicated external pin (edge detection/level detection, ch 0, ch 1 only)

• Request from built-in peripheral (shared interrupt request, including external interrupts)

• Software request (register write)

(4) Transfer modes

• Demand transfer, burst transfer, step transfer, or block transfer Addressing mode: Full 32-bit address (increment/decrement/fixed) (address increment can be in the range−255 to +255)

• Data type : byte/half-word/word

• Single-shot or reload operation selectable

83

MB91301 Series

Q

• Block Diagram

To bus

controller

DMA transfer

request to bus

controller

Read Write

Read/write

DDNO

Bus control block

Access

Counter

Selector

DTC two-stage register

Counter

Selector

control

BLK register

DDNO register

Selector

DSAD two-stage register

Selector

Write back

Buffer

back

Write

DTCR

DMA control

DMA

start trigger

selection

circuit & request

acknowledge

control

Priority

circuit

Status

transition

circuit

SDAM, SASZ [7:0] SADR

Peripheral start request/

Stop input

External pin start

request/Stop input

DSS [3:0]

To interrupt controller

ERIR, EDIR

Clear peripheral interrupt

TYPE, MOD, WS

IRQ [4:0]

MCLRE

X-bus

Bus control block

ad-

dress

Address counter

Write back

Counter buffer Counter buffer

DDAD

Selector

two-stage register

5-channel DMAC block diagram

DADM, DASZ [7:0] DADR

84

• Register List

0

D D D D D D D D D D

D

D D D D D D D D D D

ch 0 control status register A ch 0 control status register B ch 1 control status register A ch 1 control status register B ch 2 control status register A ch 2 control status register B ch 3 control status register A ch 3 control status register B ch 4 control status register A ch 4 control status register B

Overall control register

MACA0 MACB0 MACA1 MACB1 MACA2 MACB2 MACA3 MACB3 MACA4 MACB4

MACR

MB91301 Series

bit 31 24 23 16 15 08 07 0

0000200H 0000204H 0000208H 000020CH 0000210H 0000214H 0000218H 000021CH 0000220H 0000224H

bit 31 24 23 16 15 08 07 0

0000240H

ch 0 transfer source address register ch 0 transfer destination address register ch 1 transfer source address register ch 1 transfer destination address register ch 2 transfer source address register ch 2 transfer destination address register ch 3 transfer source address register ch 3 transfer destination address register ch 4 transfer source address register ch 4 transfer destination address register

MASA0 MADA0 MASA1 MADA1 MASA2 MADA2 MASA3 MADA3 MASA4 MADA4

0001000H 0001004H 0001008H 000100CH 0001010H 0001014H 0001018H 000101CH 0001020H 0001024H

85

MB91301 Series

12. I2C Interface

I2C interface is the serial I/O port that suppor t INTER IC BUS and functions as the master/slave device on the

2

I

C bus. It has the features below.

• Master/slave transmission and reception

• Arbitration function

• Clock synchronization

• Slave address/general call address detection function

• Forwarding direction detection function

• The function of generating/detecting repeat “START” conditions.

• Bus error detection function

• 10-bit/7-bit slave address

• Control slave address receiving at the master mode

• For support multiple slave address

• Can be interrupt at transmitting or bus mirror

• For normal mode (Max 100 Kbps) /fast mode (Max 400 Kbps)

86

• Block Diagram (1 ch)

/1

ICCR

EN

IDBL

DBL

ICCR

CS4 CS3 CS2 CS1 CS0

IBSR

BB

RSC

LRB TRX ADT

AL

R-bus

IBCR

BER

BEIE INTE

INT

I2C operating enable

2345 32

Bus busy

Repeat start

Last Bit

Transmission/

reception

Clock enable

Clock dividing 2

Clock select 2 (1/12)

Start/stop condition

detection

First Byte

Arbitration lost

detection

Interrupt request

MB91301 Series

CLKP

Sync

Shift clock edge

change timing

Error

IRQ SDA0

Shift clock

generation

SCL0

IBCR

SCC MSS ACK

GCAA

IBSR

AAS GCA

ISMK

FNSB

ITMK

ENTB

Start

Master

ACK enable

GC-ACK enable

Slave

Global call

RAL

End

Start/stop condition

generation

IDAR

Slave address

comparison

ITBA ITMK ISBA ISMK

87

MB91301 Series

• Register List

• Bus control register (IBCR0/1)

Address :

/0000B4

000094

H

Initial value = >

• Bus status register (IBSR0/1) Address :

000095

/0000B5

H

Initial value = >

• 10-bit slave address register (ITBA0/1) Address :

000096

/0000B6

H

Initial value = >

H

15 14 13 12 11 10 9 8

BER SCC MSS ACK GCAA INTE INT R/W

BB AL LRB TRX AAS GCA ADT

BEIE

R/W

0

76543210

R

0

15 14 13 12 11 10 9 8

⎯⎯⎯⎯⎯⎯

R

0

RSC

R

0

R

0

W

R/W0R/W0R/W0R/W0R/W

0

R 0

R

0

R 0

R

0

R 0

0

R

0

TA9

R/W0R/W

R 0

TA8

0

Address : 000097

/0000B7

H

Initial value = >

76543210

H

TA7 TA5 TA4 TA3 TA2 TA1 TA0 R/W

TA6 R/W0R/W0R/W0R/W0R/W0R/W0R/W

0

(Continued)

88

(Continued)

• 10-bit slave address mask register (ITMK0/1) Address :

/0000B8

000098

H

Initial value = >

H

15 14 13 12 11 10 9 8

ENTB ⎯⎯⎯⎯ TM8TM9

R/W

RAL

R

0

MB91301 Series

R

1

R

1

R

1

R

1

R/W1R/W

1

Address : 000099

/0000B9

H

Initial value = >

H

76543210

TM7 TM0TM1TM2TM4TM5TM6 TM3

R/W

R/W1R/W1R/W1R/W1R/W1R/W1R/W

1

• 7-bit slave address register (ISBA0/1) Address :

00009B

/0000BB

H

Initial value = >

H

76543210

SA6 R/W0R/W0R/W0R/W0R/W0R/W0R/W

R

0

• 7-bit slave address mask register (ISMK0/1) Address :

00009A

/0000BA

H

Initial value = >

H

15 14 13 12 11 10 9 8

SM6ENSB

R/W

R/W1R/W1R/W1R/W1R/W1R/W1R/W

0

•Data register (IDAR0/1) Address :

00009D

/0000BD

H

Initial value = >

H

76543210

D6D7

R/W

R/W0R/W0R/W0R/W0R/W0R/W0R/W

0

•Clock control register (ICCR0/1) Address :

00009E

/0000BE

H

Initial value = >

H

15 14 13 12 11 10 9 8

TEST EN CS4 CS3 CS2 CS1⎯ CS0

W

0

R

0

•Clock disable register (IDBL0/1) Address :

00009F

/0000BF

H

Initial value = >

H

76543210

⎯⎯⎯⎯⎯⎯⎯ DBL

R

0

R

0

1

SA5 SA4 SA3 SA2 SA1⎯ SA0

0

SM5 SM4 SM3 SM2 SM1 SM0

1

D5 D4 D3 D2 D1 D0

0

R/W0R/W1R/W1R/W1R/W1R/W

1

R

0

R

0

R

0

R

0

R

R/W

0

89

MB91301 Series

13. 16 bit Free Run Timer

16-bit free-run timer consists of a 16-bit up counter and a control status register. The timer count value is used as the base timer of output compare and input capture.

• The count clock can be selected from four different clocks.

• Can be generated the interrupt by the counter ov er-flow.

• Setting the mode enables initialization of counter through compare-match operation with the value of the compare clear register0 in the output compare.

90

•Block Diagram

K

MB91301 Series

Interrupt

ECLK IVF IVFE STOP MODE CLK1 CLK0CLR

F-bus

•Register List

Clock selector

16-bit Free run Timer

(TCDT)

Clock

To internal circuit (T15 to T00)

Comparator0

15 14 13 12 11 10 9 8

T15 T14 T13 T12 T11 T10 T9 T8

76543210

T07 T06 T05 T04 T03 T02 T01 T00

Prescaler

φ

FRC

Timer data register (upper)

(TCDT)

Timer data register (lower)

(TCDT)

76543210

ECLK

CLK0IVF IVFE STOP MODE CLR CLK1

Timer control status register

(lower)

(TCCS)

91

MB91301 Series

14. Input Capture

This module has a function that detects a rising edge, falling edge or both edges and holds a value of the 16-bit free-run timer in a register at the time of detection. It can also generate an interrupt when detecting an edge.

The input capture consist of input capture and control registers. Each input capture have the corresponded external input pins.

• The valid edge of the external input can be selected from three types : Rising edge Falling edge Both edges

• It can generate an interrupt when it detects the valid edge of the external input.

92

•Block Diagram

MB91301 Series

16-bit timer count value (T15 to T00)

Capture data register

ch (0, 2)

R-bus

16-bit timer count value (T15 to T00)

Capture data register

ch (1, 3)

Edge detection

EG11 EG10

EG31 EG30

Edge detection

ICP1 ICP0 ICE1 ICE0

ICP3 ICP2 ICE3 ICE2

ICU0, ICU2

input pin

EG01 EG00

EG21 EG20

ICU1, ICU3

input pin

Interrupt

93

MB91301 Series

•Register List

15 14 13 12 11 10 9 8

CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08

76543210

CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00

76543210

ICP3

76543210

ICP1

EG20ICP2 ICE3 ICE2 EG31 EG30 EG21

EG00ICP0 ICE1 ICE0 EG11 EG10 EG01

Input capture data register (upper)

(IPCP)

Input capture data register (lower)

(IPCP)

Capture control register

(ICS23)

Capture control register

(ICS01)

94

MB91301 Series

15. Clock Generation Control

The internal operating clock is generated as follows in MB91301 series.

• Source clock selection : Selects the clock source.

• Base clock generation : The base clock is generated by dividing the source clock by 2 or using a PLL.

• Generation in each internal block : The base clock is divided to generate the oper ating clock f or each bloc k.

95

MB91301 Series

X X

• Block Diagram

[Clock generator]

DIVR0, 1 register

R-bus

CPU clock division

Peripheral clock

division

External bus clock

division

tor

Selec-

tor

Selec-

tor

Selec-

Stop control

CPU clock

(CLKB)

Peripheral clock

(CLKP)

External bus

clock (CLKT)

CLKR register

0 1

tion

circu

it

PLL

1/2

Selector

illa-

Osc

[Stop/sleep

Internal interrupt

Internal reset

controller]

STCR register

State

transi-

tion

control

circuit

Reset F/F

Stop state

SLEEP state

Internal reset (RST)

Internal reset (INIT)

[Reset circuit]

96

INIT pin

RSRR register

[Watchdog controller]

WPR register

CTBR register

TBCR register

Interrupt enable

Watchdog F/F

Timebase counter

Selector

Overflow detection F/F

Count clock

Timebase timer

interrupt request

• Register List

• RSRR : Reset initiation register/Watchdog timer control register

bit151413121110 9 8

Address : 00000480

INIT ⎯ WDOG ⎯ SRST ⎯ WT1 WT0

H

RRRRRRR/WR/W

MB91301 Series

Initial value (INIT

pin) 10000000 Initial value (INIT) − 0 − XX− 00 Initial value (RST) X X X −−X00

• STCR : Standby control register

bit76543210

Address : 00000481

STOP SLEEP HIZ SRST OS1 OS0 ⎯ OSCD1

H

R/W R/W R/W R/W R/W R/W ⎯ R/W

Initial value (INIT

pin) 001100− 1 Initial value (INIT) 0 0 1 1 X X − 1 Initial value (RST) 0 0 X 1 X X − X

• TBCR : Timebase counter control register

bit151413121110 9 8

Address : 00000482

TBIF TBIE TBC2 TBC1 TBC0 ⎯ SYNCR SYNCS

H

R/W R/W R/W R/W R/W ⎯ R/W R/W

Initial value (INIT) 0 0 X X X − 00 Initial value (RST) 0 0 X X X − XX

• CTBR : Timebase counter clear register

bit76543210

Address : 00000483

D7 D6 D5 D4 D3 D2 D1 D0

H

WWWWWWWW

Initial value (INIT) XXXXXXXX Initial value (RST) XXXXXXXX

• CLKR : Clock source control register

bit151413121110 9 8

Address : 00000484

⎯ PLL1S2 PLL1S1 PLL1S0 ⎯ PLL1EN CLKS1 CLKS0

H

⎯ R/W R/W R/W ⎯ R/W R/W R/W

Initial value (INIT) − 000− 000 Initial value (RST) − XXX− XXX

(Continued)

97

MB91301 Series

(Continued)

WPR : Watchdog reset generation delay register

•

bit76543210

D7 D6 D5 D4 D3 D2 D1 D0

Address : 00000485

Initial value (INIT) XXXXXXXX

Initial value (RST) XXXXXXXX

DIVR0 : Base clock division setting register 0

•

Address : 00000486

Initial value (INIT) 00000011

Initial value (RST) XXXXXXXX

H

WWWWWWWW

bit151413121110 9 8

B3 B2 B1 B0 P3 P2 P1 P0

H

R/W R/W R/W R/W R/W R/W R/W R/W

DIVR1 : Base clock division setting register 1

•

bit76543210

Address : 00000487

T3 T2 T1 T0 ⎯⎯⎯⎯

H

R/WR/WR/WR/W ⎯⎯⎯⎯

Initial value (INIT) 0 0 0 0 −−−−

Initial value (RST) X X X X −−−−

− : Changes depending on what triggered the reset. × : Not initialized

98

ELECTRICAL CHARACTERISTICS

■

1. Absolute Maximum Ratings

Parameter Symbol

MB91301 Series

(VSS = AVSS = 0 V)

Rating

Unit Remarks

Min Max

Supply voltage V Analog supply voltage AV

Analog reference voltage

AVRH,

AVRL Input voltage V Analog pin input voltage V Output voltage V “L” level maximum output

current “L” level average output current I “L” level total maximum output

current “L” level total average output

current

OLAV

ΣI

“H” level maximum output current

“H” level average output current I “H” level total maximum output

current

OHAV

ΣI

CC

IA

OH

I

OL

OLAV

I

OH

CC

I

VSS − 0.5 VSS + 4.0 V *1 VSS − 0.5 VSS + 4.0 V *2

V

− 0.5 AV

SS

CC

V*2

VSS − 0.3 VCC + 0.3 V VSS − 0.3 AVCC + 0.3 V VSS − 0.3 VCC + 0.3 V

⎯ 10 mA *3 ⎯ 8mA*4 ⎯ 100 mA

⎯ 50 mA *5

⎯−10 mA *3 ⎯−4mA*4 ⎯−50 mA

“H” level total average output current

Power consumption P

ΣI

OHAV

D

⎯−20 mA *5 ⎯ 1000 mW

Operating temperature Ta 0 +70 °C Storage temperature T

must not be lower than VSS − 0.3 V.

CC

*1 : V *2 : A V

, A VRH and A VRL should not exceed V

CC

. Also AVRL should not exceed AVRH.

AV

CC

STG

−50 +150 °C

+0.3 V, including at power-on. A VRH and A VRL should not exceed

CC

*3 : The maximum output current is the peak value for a single pin. *4 : The average output current is the average current for a single pin over a period of 100ms. *5 : The total average output current is the average current for all pins over a period of 100ms.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

99

MB91301 Series

2. Recommended Operating Conditions

Parameter Symbol

(VSS = AVSS = 0 V)

Value

Unit Remarks

Min Max

Supply voltage V Analog supply voltage AV

AVRH AV

CC

3.0 3.6 V Normal operation

VSS + 33.6 V

SS

AV

CC

V

Analog reference voltage

AVRL AV

SS

AVRH V

Operating temperature Ta 0 +70 °C

<Notes on turning the power on> The maximum power rising slope (∆V/∆t) must be 0.05 V/µs when the 3 V power supply is turned on. It takes about 100 µs until the 2.5 V power supply becomes stable after the 3 V power supply becomes stable. Keep INIT

input during that interval.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.

100

FUJITSU MB91302A, MB91V301A DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual

DESCRIPTION

FEATURES

PACKAGES

PRODUCT LINEUP

PIN ASSIGNMENTS

PIN DESCRIPTIONS

I/O CIRCUIT TYPE

HANDLING DEVICES

BLOCK DIAGRAM

GENERAL PURPOSE REGISTERS

MODE SETTINGS

I/O MAP

INTERRUPT VECTORS

INSTRUCTION CACHE

PERIPHERAL RESOURCES

ELECTRICAL CHARACTERISTICS