FUJITSU MB91230 User Guide
FUJITSU SEMICONDUCTOR
DATA SHEET
32-bit Microcontroller
CMOS
DS07-16506-2E
FR60Lite
MB91230 Series
MB91233L/MB91F233A/MB91F233L/MB91V230
DESCRIPTION
■
The MB91230 series is a line of standard microcontrollers, based on a 32-bit high-performance RISC CPU and
containing variety of I/O resources, for embedded control applications which require high CPU performance at
high speed processing.
Audio motor control storage : Designed to specifications for embedded control applications which high CPU
performance power processing.
The MB91230 series belongs to the FR60Lite.
FEATURES
■
• 32-bit RISC, load/store architecture with a 5 stage pipeline
• Maximum operating frequency: 33.6 MHz (oscillation frequency = 4.2 MHz, oscillation frequency 8-multiplier
(PLL clock multiplication method) )
• 16-bit fixed length instructions (basic instructions)
• Execution speed of instructions : 1 instruction per cycle
(Continued)
PACKAGES
■
401-pin Ceramic PGA 120-pin Plastic LQFP 128-pin plastic FLGA
(PGA-401C-A02) (FPT-120P-M05) (LGA-128P-M01)
MB91230 Series
(Continued)
• Memory-to-memory transfer, bit handling, and barrel shift instructions, etc. : Instructions suitable f or embedded
applications
• Function entry/exit instructions, multiple-register load/store instructions : Instructions adapted for C-language
• Register interlock function : Facilitates coding in assembler
• Built-in multiplier with instruction-level support
- 32-bit multiplication with sign : 5 cycles
- 16-bit multiplication with sign : 3 cycles
• Interrupt (PC and PS save) : 6 cycles (16 priority levels)
• Harvard architecture allowing program access and data access to be executed simultaneously
• Instruction compatible with FR family
• Capacity of built-in ROM and ROM type
- MASK ROM : 256 Kbytes
- FLASH ROM : 256 Kbytes
• Capacity of built-in RAM : 16 Kbytes
• General-purpose ports : Maximum 98 ports (including N-ch open-drain port : 4 ports)
• A/D converter (series-parallel type)
- Resolution : 10-bit : 8 channels (4 channels × 2 unit)
- Conversion time : 1.69 µs (Minimum conversion time)
• D/A converter (R-2R type)
- Resolution : 8-bit : 2 channels (independence)
- Conversion speed : 0.6 µs (when load capacitance 20 pF)
• External interrupt input : 16 channels
• Bit search module (for REALOS)
- Function for searching the MSB (Upper bit) in each word for the first “0” or “1” inverted point
• UART (full-duplex double buffer) : 4 channels
- Selectable parity On/Off
- Asynchronous (start-stop synchronized) or clock-synchronous communications selectable
- Internal timer for dedicated baud rate (U-timer) on each channel
- External clock can be used as transfer clock
- Error detection function for parity, frame and overrun
• PPG : 16-bit × 6 channels
• Up/down counter : 2 channels (8-bit × 2 channels or 16-bit × 1 channel)
• Reload timer : 16-bit × 4 channels
• Free-run timer : 16-bit × 2 channels
• Watch timer : 15-bit × 1 channel
• PWC : 8-bit × 2 channels
• Input capture : 2 channels (interface with free-run timer 0)
• Output compare : 4 channels (free-run timer 0 and output compare unit 0/1 cooperate, free-run timer 1
and output compare units 2/3)
• LCD controller : SEG0 to SEG31/COM0 to COM3 (also serving as a port)
• Clock monitor (peripheral clock output function) : 1 channel
• Timebase/watchdog timer (26-bit)
• Real-time clock (counting even with the real-time clock stopped)
• Low Power Consumption Mode
• Sleep/stop function
• Package : LQFP-120, FLGA-128
• Technology : CMOS 0.35 µm
• Power supply
• Dual power supply configuration [internal logic 3.3 V, I/O 5.5 V(3.3 V for A/D converter and D/A converter
input/output)]
Note : Do not set the external bus mode in which the MB91230 series cannot operate.
2
PIN ASSIGNMENT
P
P
P
3
2
1
0
■
• MB91233L, MB91F233A, MB91F233L
P25/SOT2
P24/SIN2
P23/PWI1/OP
120
119
118
X0A
X1A
CC
3B
SS
V
VCC3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P26/SCK2
P27/SIN3
P30/SOT3
P31/SCK3
P32/AIN0
P33/BIN0
P34/ZIN0
P35/AIN1
P36/BIN1
P37/ZIN1
P40/PPG0
P41/PPG1
V
P42/PPG2
P43/PPG3
P44/TOT0
P45/TOT1
P46/TOT2
P47/CKOT
P50/INT8
P51/INT9
P52/INT10
53/INT11/PPG4
54/INT12/PPG5
P55/INT13/TIN2
P56/INT14/TIN1
P22/PWI0/OP
P21/CKI1/OP
P20/CKI0/OP
P17/INT7
P16/INT6
P15/INT5
117
116
115
114
113
112
(TOP VIEW)
P14/INT4
P13/INT3
P12/INT2X0X1
111
110
109
108
107
VSSVCCP11/INT1
P10/INT0
P07/IC1
P06/IC0
106
105
104
103
102
101
MB91230 Series
P05/SCK1
P04/SOT1
P03/SIN1
P02/SCK0
P01/SOT0
P00/SIN0V3V2V1V0
999897969594939291
100
INIT
90
MD0
89
MD1
88
MD2
87
P73/COM3
86
P72/COM2
85
P71/COM1
84
P70/COM0
83
P67/SEG31
82
P66/SEG30
81
P65/SEG29
80
P64/SEG28
79
PB3/SEG27
78
PB2/SEG26
77
V
76
SS
75
V
CC
74
PB1/SEG25
73
PB0/SEG24
72
PA7/SEG23
71
PA6/SEG22
70
PA5/SEG21
69
PA4/SEG20
68
PA3/SEG19
67
PA2/SEG18
66
PA1/SEG17
65
PA0/SEG16
64
P97/SEG15
63
P96/SEG14
62
P95/SEG13
61
P94/SEG12
∗
∗
∗
∗
3132333435363738394041424344454647484950515253545556575859
SS
CC
AV
AV
AVRH
PD0/DA0
PD1/DA1
PF3/TOT3
PF4/TIN3/ADTG1
57/INT15/TIN0/ADTG0
PC0/AN0
PC1/AN1
PC2/AN2
PC3/AN3
PC4/AN4
SS
V
PC5/AN5
PC6/AN6
PC7/AN7
3IO
CC
V
P80/SEG0
P81/SEG1
P82/SEG2
P83/SEG3
P84/SEG4
P85/SEG5
P86/SEG6
P87/SEG7
60
P90/SEG8
P91/SEG9
P92/SEG10
P93/SEG11
* : Open-drain
(FPT-120P-M05)
(Continued)
3
MB91230 Series
M
H
G
D
C
(Continued)
• MB91F233L
M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12
L
K
J
F
E
B
A A2A3A4A5A6A7A8A9A10A11A12
INDEX
L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12
H1 H2 H3 H4 H9 H10 H11 H12
G1 G2 G3 G4 G9 G10 G11 G12
BOTTOM VIEW
F1 F2 F3 F4 F9 F10 F11 F12
E1 E2 E3 E4 E9 E10 E11 E12
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12
A1
123456789101112
(LGA-128P-M01)
4
MB91230 Series
Pin correspondence table of LQFP-120 and FLGA-128 in MB91230 series (LGA-128P-M01)
FLGA-128
LQFP-120
No.
No.
(JEDEC
Signal
name
LQFP-120
No.
No.)
1 A1 P26/SCK2 98 C9 P03/SIN1 18 G1 P42/PPG2
120 A2 P25/SOT2 93 C10 V2 15 G2 V
FLGA-128
No.
(JEDEC
No.)
Signal
name
LQFP-120
No.
FLGA-128
No.
(JEDEC
)
No.
Signal
name
3B
CC
117 A3
P22/PWI0/
OP2
85 C11 P72/COM2 *
2
G3*
4
VCC3*
4
114 A4 P17/INT7 87 C12 MD2 17 G4 VCC3
⎯ A5 *
5
10 D1 P37/ZIN1 71 G9
109 A6 P12/INT2 6 D2 P33/BIN0 75 G10 V
107 A7 X1 8 D3 P35/AIN1 74 G11
103 A8 P10/INT0 119 D4 P24/SIN2 77 G12
PA6/
SEG22
CC
PB1/
SEG25
PB2/
SEG26
100 A9 P05/SCK1 111 D5 P14/INT4 21 H1 P45/TOT1
97 A10 P02/SCK0 ⎯ D6 *
5
19 H2 P43/PPG3
94 A11 V3 101 D7 P06/IC0 23 H3 P47/CKOT
91 A12 V0 95 D8 P00/SIN0 20 H4 P44/TOT0
4 B1 P31/SCK3 89 D9 MD0 65 H9
118 B2
115 B3
P23/PWI1/
OP3
P20/CKI0/
OP0
86 D10 P73/COM3 72 H10
82 D11
P67/
SEG31*
1
69 H11
PA0/
SEG16
PA7/
SEG23
PA4/
SEG20
112 B4 P15/INT5 84 D12 P71/COM1 73 H12
PB0/
SEG24
110 B5 P13/INT3 13 E1 X0A 24 J1 P50/INT8
106 B6 V
SS
9 E2 P36/BIN1 22 J2 P46/TOT2
104 B7 P11/INT1 12 E3 P41/PPG1 26 J3 P52/INT10
99 B8 P04/SOT1 5 E4 P32/AIN0 29 J4
96 B9 P01/SOT0 81 E9
P66/
SEG30*
1
35 J5 PD1/DA1
P55/INT13/
TIN2
92 B10 V1 83 E10 P70/COM0 40 J6 PC1/AN1
88 B11 MD1 80 E11
90 B12 INIT
⎯ E12 *
P65/
SEG29*
5
1
47 J7 V
SS
50 J8 P81/SEG1
(Continued)
5
MB91230 Series
(Continued)
FLGA-128
LQFP-120
No.
No.
(JEDEC
Signal
name
LQFP-120
No.
No.)
7 C1 P34/ZIN0 16 F1 V
2 C2 P27/SIN3 ⎯ F2 *
3 C3 P30/SOT3 14 F3 X1A 66 J11
116 C4
P21/CKI1/
OP1
11 F4 P40/PPG0 70 J12
113 C5 P16/INT6 78 F9
108 C6 X0 79 F10
105 C7 V
CC
76 F11 V
102 C8 P07/IC1 ⎯ F12 *
41 K5 PC2/AN2 36 L4 AV
44 K6 PC5/AN5 *
3IO 43 L6 PC4/AN4 42 M5 PC3/AN3
48 K7 V
CC
3
53 K8 P84/SEG4 45 L7 PC6/AN6 46 M6 PC7/AN7
56 K9 P87/SEG7 49 L8 P80/SEG0 ⎯ M7 *
63 K10
62 K11
67 K12
P96/
SEG14
P95/
SEG13
PA2/
SEG18
52 L9 P83/SEG3 51 M8 P82/SEG2
55 L10 P86/SEG6 54 M9 P85/SEG5
58 L11 P91/SEG9 57 M10 P90/SEG8
P56/
30 L1
INT14/
64 L12
TIN1
P54/
28 L2
INT12/
31 M1
PPG5
32 L3 PF3/TOT3 34 M2 PD0/DA0
FLGA-128
No.
(JEDEC
No.)
4
L5*
Signal
name
SS
5
PB3/
SEG27
P64/
SEG28*
SS
5
CC
AVRL*
P97/
SEG15
P57/
INT15/
TIN0/
ADTG0
LQFP-120
1
4
FLGA-128
No.
No.
(JEDEC
)
No.
59 J9
68 J10
27 K1
25 K2 P51/INT9
33 K3
38 K4 AV
37 M3 AVRH
39 M4 PC0/AN0
60 M11
61 M12
Signal
name
P92/
SEG10
PA3/
SEG19
PA1/
SEG17
PA5/
SEG21
P53/
INT11/
PPG4
PF4/TIN3/
ADTG1
SS
5
P93/
SEG11
P94/
SEG12
*1 : Open-drain
3) on the LQFP product
*2 : Connected to pin 17(V
*3 : Connected to pin 38(AV
CC
) on the LQFP product
SS
*4 : Signals added to the FLGA product
*5 : NC pin on the FLGA product
6
PIN DESCRIPTION
■
MB91230 Series
Pin no.
LQFP FLGA
1A1
2C2
3C3
4B1
5E4
6D2
7C1
8D3
Pin name Circuit type Description
UART2 clock input/output.
SCK2
D
P26
SIN3
D
P27
SOT3
B
P30
SCK3
B
P31
AIN0
B
P32
BIN0
B
P33
ZIN0
B
P34
AIN1
B
P35
This function is valid when corresponding bit of PFR2
register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.
UART3 data input.
When using this function, corresponding bit of DDR2
register is set to input.
General purpose input/output port.
This function is always valid.
UART3 data output.
This function is valid when corresponding bit of PFR3
register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFR3
register is set to port function.
UART3 clock input/output.
This function is valid when corresponding bit of PFR3
register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFR3
register is set to port function.
Up/down counter 0 AIN input.
When using this function, corresponding bit of DDR3
register is set to input.
General purpose input/output port.
This function is always valid.
Up/down counter 0 BIN input.
When using this function, corresponding bit of DDR3
register is set to input.
General purpose input/output port.
This function is always valid.
Up/down counter 0 ZIN input.
When using this function, corresponding bit of DDR3
register is set to input.
General purpose input/output port.
This function is always valid.
Up/down counter 1 AIN input.
When using this function, corresponding bit of DDR3
register is set to input.
General purpose input/output port.
This function is always valid.
(Continued)
7
MB91230 Series
Pin no.
LQFP FLGA
9E2
10 D1
11 F4
12 E3
Pin name Circuit type Description
Up/down counter 1 BIN input.
BIN1
B
P36
When using this function, corresponding bit of DDR3
register is set to input.
General purpose input/output port.
This function is always valid.
Up/down counter 1 ZIN input.
ZIN1
B
P37
When using this function, corresponding bit of DDR3
register is set to input.
General purpose input/output port.
This function is always valid.
PPG0 output.
PPG0
This function is valid when corresponding bit of PFR4
register is set to peripheral function.
D
General purpose input/output port.
P40
This function is valid when corresponding bit of PFR4
register is set to port function.
PPG1 output.
PPG1
This function is valid when corresponding bit of PFR4
register is set to peripheral function.
D
General purpose input/output port.
P41
This function is valid when corresponding bit of PFR4
register is set to port function.
13 E1 X0A
14 F3 X1A
15 G2 V
16 F1 V
17 G4 V
CC
SS
CC
PPG2
18 G1
P42
PPG3
19 H2
P43
K Sub-clock oscillation pin (32 kHz)
3B ⎯ Power supply pin for backup (RTC)
⎯ Power supply pin (GND)
3 ⎯ Power supply pin (3.3 V internal logic)
PPG2 output.
This function is valid when corresponding bit of PFR4
register is set to peripheral function.
D
General purpose input/output port.
This function is valid when corresponding bit of PFR4
register is set to port function.
PPG3 output.
This function is valid when corresponding bit of PFR4
register is set to peripheral function.
D
General purpose input/output port.
This function is valid when corresponding bit of PFR4
register is set to port function.
(Continued)
8
MB91230 Series
Pin no.
LQFP FLGA
20 H4
21 H1
22 J2
23 H3
24 J1
Pin name Circuit type Description
Reload timer 0 output port.
TOT0
D
P44
TOT1
D
P45
TOT2
D
P46
CKOT
D
P47
INT8
C
P50
This function is valid when corresponding bit of PFR4
register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFR4
register is set to port function.
Reload timer 1 output port.
This function is valid when corresponding bit of PFR4
register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFR4
register is set to port function.
Reload timer 2 output port.
This function is valid when corresponding bit of PFR4
register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFR4
register is set to port function.
Clock monitor function output pin.
This function is valid when corresponding bit of PFR4
register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFR4
register is set to port function.
External interrupt input.
When using this function, corresponding bit of DDR5
register is set to input.
General purpose input/output port.
This function is always valid.
25 K2
26 J3
INT9
P51
INT10
P52
External interrupt input.
When using this function, corresponding bit of DDR5
C
C
register is set to input.
General purpose input/output port.
This function is always valid.
External interrupt input.
When using this function, corresponding bit of DDR5
register is set to input.
General purpose input/output port.
This function is always valid.
(Continued)
9
MB91230 Series
Pin no.
LQFP FLGA
27 K1
28 L2
Pin name Circuit type Description
PPG4 output.
PPG4
INT11
P53
PPG5
INT12
P54
C
C
This function is valid when corresponding bit of PFR5
register is set to peripheral function.
External interrupt input.
This function is enabled when corresponding bit of
PFR5 register is set to port function and corresponding
bit of DDR5 resister is set to input.
General purpose input/output port.
This function is valid when corresponding bit of PFR5
register is set to port function.
PPG5 output.
This function is valid when corresponding bit of PFR5
register is set to peripheral function.
External interrupt input.
This function is enabled when corresponding bit of
PFR5 register is set to port function and corresponding
bit of DDR5 resister is set to input.
General purpose input/output port.
This function is valid when corresponding bit of PFR5
register is set to port function.
29 J4
30 L1
TIN2
INT13
P55
TIN1
INT14
P56
Reload timer 2 event input pin.
This function is valid when corresponding bit of DDR5
register is set to input.
C
C
External interrupt input.
This function is valid when corresponding bit of DDR5
register is set to input.
General purpose input/output port.
This function is always valid.
Reload timer 1 event input pin.
This function is valid when corresponding bit of DDR5
register is set to input.
External interrupt input.
This function is valid when corresponding bit of DDR5
register is set to input.
General purpose input/output port.
This function is always valid.
(Continued)
10
MB91230 Series
Pin no.
LQFP FLGA
31 M1
32 L3
33 K3
34 M2
35 J5
36 L4 AV
37 M3 AVRH ⎯ Analog reference power supply (for A/D, D/A converter) .
38 K4 AV
Pin name
ADTG0
TIN0
INT15
P57
TOT3
PF3
ADTG1
TIN3
PF4
DA0
PD0
DA1
PD1
CC
SS
Circuit
type
External trigger input pin of A/D converter 0.
This function is valid when corresponding bit of DDR5 register is set to input.
Reload timer 0 event input pin.
This function is valid when corresponding bit of DDR5 reg-
C
D
D
F
F
⎯ Analog power supply (for A/D, D/A converter) .
⎯ GND level input for analog circuit (for A/D, D/A converter) .
ister is set to input.
External interrupt input.
This function is valid when corresponding bit of DDR5 register is set to input.
General purpose input/output port.
This function is always valid.
Reload timer 3 output port.
This function is valid when corresponding bit of PFRF
register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFRF
register is set to port function.
External trigger input pin of A/D converter 1.
This function is valid when corresponding bit of DDRF
register is set to input.
Reload timer 3 event input pin.
This function is valid when corresponding bit of DDRF
register is set to input.
General purpose input/output port.
This function is always valid.
D/A converter 0 output pin.
This function is valid when corresponding bit of PFRD
register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFRD
register is set to port function.
D/A converter 1 output pin.
This function is valid when corresponding bit of PFRD
register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFRD
register is set to port function.
Description
(Continued)
11
MB91230 Series
Pin no.
LQFP FLGA
M4, J6, K5,
39 to 46
M5, L6, K6,
L7, M6
47 J7 V
48 K7 V
L8, J8, M8,
49 to 56
L9, K8, M9,
L10, K9
M10, L11, J9,
57 to 64
M11, M12,
K11, K10, L12
Pin name Circuit type Description
Analog input pin for A/D converter.
AN0 to AN7
This function is valid when corresponding bit of PFRC
register is set to peripheral function.
E
General purpose input/output port.
PC0 to PC7
This function is valid when corresponding bit of PFRC
register is set to port function.
SS
3IO ⎯ Power supply pin (analog-shared pin I/O)
CC
SEG0 to
SEG7
⎯ Power supply pin (GND)
LCD controller/driver LCD segment output pin.
This function is valid when corresponding bit of PFR8
register is set to peripheral function.
I
General purpose input/output port.
P80 to P87
This function is valid when corresponding bit of PFR8
register is set to port function.
SEG8 to
SEG15
LCD controller/driver LCD segment output pin.
This function is valid when corresponding bit of PFR9
register is set to peripheral function.
I
General purpose input/output port.
P90 to P97
This function is valid when corresponding bit of PFR9
register is set to port function.
H9, J11, K12,
65 to 72
J10, H11, J12,
G9, H10
73, 74 H12, G11
75 G10 V
76 F11 V
77, 78 G12, F9
SEG16 to
SEG23
PA0 to PA7
SEG24,
SEG25
PB0, PB1
CC
SS
SEG26,
SEG27
PB2, PB3
LCD controller/driver LCD segment output pin.
This function is valid when corresponding bit of PFRA
register is set to peripheral function.
I
General purpose input/output port.
This function is valid when corresponding bit of PFRA
register is set to port function.
LCD controller/driver LCD segment output pin.
This function is valid when corresponding bit of PFRB
register is set to peripheral function.
I
General purpose input/output port.
This function is valid when corresponding bit of PFRB
register is set to port function.
Power supply pin (5 V I/O MB91V230/F233A)
⎯
Power supply pin (3.3 V internal logic, I/O MB91F233L/
MB91233L)
⎯ Power supply pin (GND)
LCD controller/driver LCD segment output pin.
This function is valid when corresponding bit of PFRB
register is set to peripheral function.
I
General purpose input/output port.
This function is valid when corresponding bit of PFRB
register is set to port function.
(Continued)
12
MB91230 Series
Pin no.
LQFP FLGA
79 to 82
83 to 86
87 to 89 C12, B11, D9
90 B12 INIT
91 to 94
95 D8
F10, E11, E9,
D11
P64 to P67
E10, D12,
C11, D10
P70 to P73
A12, B10,
C10, A11
Pin name Circuit type Description
SEG28 to
SEG31
COM0 to
COM3
MD2,
MD1,
MD0
V0 to V3 ⎯
SIN0
P00
J
I
H Mode input pin.
G External reset input.
D
LCD controller/driver LCD segment output pin.
This function is valid when corresponding bit of PFR6
register is set to peripheral function.
General purpose input/output port. (open-drain)
This function is valid when corresponding bit of PFR6
register is set to port function.
LCD controller/driver common pins.
This function is valid when corresponding bit of PFR7
register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFR7
register is set to port function.
LCD controller/driver reference power supply input
pins.
UART0 data input.
When using this function, corresponding bit of DDR0
register is set to input.
General purpose input/output port.
This function is always valid.
96 B9
97 A10
98 C9
SOT0
P01
SCK0
P02
SIN1
P03
UART0 data output.
This function is valid when corresponding bit of PFR0
D
D
D
register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFR0
register is set to port function.
UART0 clock input/output.
This function is valid when corresponding bit of PFR0
register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFR0
register is set to port function.
UART1 data input.
This function is valid when corresponding bit of DDR0
register is set to input.
General purpose input/output port.
This function is always valid.
(Continued)
13
MB91230 Series
Pin no.
LQFP FLGA
99 B8
100 A9
101 D7
102 C8
Pin name Circuit type Description
UART1 data output.
SOT1
D
P04
SCK1
D
P05
IC0
D
P06
IC1
D
P07
This function is valid when corresponding bit of PFR0 register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFR0 register is set to port function.
UART1 clock input/output.
This function is valid when corresponding bit of PFR0 register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFR0 register is set to port function.
Input capture input 0.
This function is valid when corresponding bit of DDR0
register is set to input.
General purpose input/output port.
This function is always valid.
Input capture input 1.
This function is valid when corresponding bit of DDR0
register is set to input.
General purpose input/output port.
This function is always valid.
INT0
103 A8
P10
INT1
104 B7
P11
105 C7 V
106 B6 V
107 A7 X1
108 C6 X0
CC
SS
External interrupt input.
This function is valid when corresponding bit of DDR1
A
A
⎯
⎯ Power supply pin (GND)
K Main-clock oscillation pin
register is set to input.
General purpose input/output port.
This function is always valid.
External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.
General purpose input/output port.
This function is always valid.
Power supply pin (5 V I/O MB91V230/F233A)
Power supply pin (3.3 V internal logic, I/O MB91F233L/
MB91233L)
(Continued)
14
MB91230 Series
Pin no.
LQFP FLGA
109 A6
110 B5
111 D5
112 B4
Pin name Circuit type Description
External interrupt input.
INT2
A
P12
INT3
A
P13
INT4
A
P14
INT5
A
P15
This function is valid when corresponding bit of DDR1
register is set to input.
General purpose input/output port.
This function is always valid.
External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.
General purpose input/output port.
This function is always valid.
External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.
General purpose input/output port.
This function is always valid.
External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.
General purpose input/output port.
This function is always valid.
113 C5
114 A4
115 B3
INT6
P16
INT7
P17
CKI0
OP0
P20
External interrupt input.
This function is valid when corresponding bit of DDR1
A
A
D
register is set to input.
General purpose input/output port.
This function is always valid.
External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.
General purpose input/output port.
This function is always valid.
External clock input pin for free-run timer 0.
This function is enabled when corresponding bit of PFR2
register is set to port function and corresponding bit of
DDR2 register is set to input.
Output compare 0 output pin.
This function is valid when corresponding bit of PFR2
register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.
(Continued)
15
MB91230 Series
(Continued)
Pin no.
LQFP FLGA
116 C4
117 A3
118 B2
119 D4
120 A2
(38) L5 AVRL ⎯
⎯
A5, D6, E12,
F2, F12, M7
Pin name Circuit type Description
CKI1
OP1
P21
PWI0
OP2
P22
PWI1
OP3
P23
SIN2
P24
SOT2
P25
NC ⎯ Unconnected pin.
External clock input pin for free-run timer 1.
This function is enabled when corresponding bit of
PFR2 register is set to port function and corresponding
bit of DDR2 register is set to input.
D
D
D
D
D
Output compare1 output pin.
This function is valid when corresponding bit of PFR2
register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.
Pulse width counter 0 input.
This function is enabled when corresponding bit of
PFR2 register is set to port function and corresponding
bit of DDR2 register is set to input.
Output compare2 output pin.
This function is valid when corresponding bit of PFR2
register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.
Pulse width counter 1 input.
This function is enabled when corresponding bit of
PFR2 register is set to port function and corresponding
bit of DDR2 register is set to input.
Output compare3 output pin.
This function is valid when corresponding bit of PFR2
register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.
UART2 data input.
This function is valid when corresponding bit of DDR2
register is set to input.
General purpose input/output port.
This function is always valid.
UART2 data output.
This function is valid when corresponding bit of PFR2
register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.
Analog reference power supply (for A/D converter)
inside the IC on LQFP
AVRL pin is connected to AV
package product.
SS
16
MB91230 Series
I/O CIRCUIT TYPE
■
Type Circuit type Remarks
With Pull-up control (50 kΩ)
Pull-up control
PP
A
N
Output drive Pch
Output drive Nch
CMOS level output
I
= 4 mA/IOL = 4 mA
OH
CMOS hysteresis input (with standby control)
CMOS hysteresis
input
Standby control
Pull-up control
PP
Output drive Pch
With Pull-up control (50 kΩ)
CMOS level output
I
= 4 mA/IOL = 4 mA
OH
CMOS hysteresis input (with standby control)
N
B
Output drive Nch
CMOS hysteresis
input
Test pin for FLASH
Standby control
Test pin for FLASH
Analog SW control
N
CMOS level output
P
C
N
Output drive Pch
Output drive Nch
CMOS hysteresis input (with standby control)
CMOS hysteresis
input
Standby control
P
N
D
Output drive Pch
Output drive Nch
CMOS hysteresis
input
CMOS level output
I
= 4 mA/IOL = 4 mA
OH
CMOS hysteresis input (with standby control)
Test pin for FLASH
Standby control
Test pin for FLASH
Analog SW control
N
(Continued)
17
MB91230 Series
t
ut
Type Circuit type Remarks
P
N
Output drive Pch
Output drive Nch
CMOS level output
I
= 4 mA/IOL = 4 mA
OH
CMOS hysteresis input (with standby control)
Also serving as an analog input
E
CMOS hysteresis
input
Standby control
Analog input
Analog SW control
N
P
N
F
Output drive Pch
Output drive Nch
CMOS hysteresis
input
CMOS level output
I
= 4 mA/IOL = 4 mA
OH
CMOS hysteresis input (with standby control)
Also serving as an analog input
Standby control
Analog input
Analog SW control
N
With Pull-up (50 kΩ)
CMOS hysteresis input
PP
18
G
N
CMOS hysteresis
input
High withstand-voltage input
CMOS input (hysteresis level)
N
Low impedance inpu
High impedance inp
H
N
N
N
N
High voltage
detection
output
(Continued)
MB91230 Series
X
X
(Continued)
Type Circuit type Remarks
P
N
Output drive Pch
Output drive Nch
I
CMOS hysteresis
input
Standby control
LCDC output
CMOS level output
I
= 4 mA/IOL = 4 mA
OH
CMOS hysteresis input (with standby control)
LCDC output
P
CMOS level output (open-drain)
I
= 20 mA
OL
CMOS hysteresis input (with standby control)
LCDC output
N
Output drive Nch
J
CMOS hysteresis
input
Standby control
LCDC output
1, X1A
Oscillation circuit
Oscillation
output
K
0, X0A
Standby
control
19
MB91230 Series
HANDLING DEVICES
■
Preventing Latch-up
Latch-up may occur in a CMOS IC if a voltage greater than V
pin or if an above-rating voltage is applied between V
and VSS.
CC
A latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of
an element. When you use a CMOS IC, be very careful not to exceed the absolute maximum rating.
Treatment of Unused Pins
Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example , using a pullup or pull-down resistor.
Treatment of Pins at Unusing LCD
Leave COM0 to COM3 pins open.
V0 to V3 pins should always be pulled up or down through resistance of at least 2 kΩ.
About Power Supply Pins
or less than VSS is applied to an input or output
CC
In products with multiple V
or VSS pins, the pins of the same potential are internally connected in the device
CC
to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission le vel, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the V
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between V
and VSS pins of this device at the low impedance.
CC
and VSS near
CC
this device.
About Crystal Oscillator Circuit
Noise near the X0, X1, X0A and X1A pins may cause the de vice to malfunction. Design the printed circuit board
so that X0, X1, X0A and X1A the crystal oscillator (or ceramic oscillator) , and the bypass capacitor to ground
are located as close to the device as possible.
It is strongly recommended to design the PC board artwork with the X0, X1, X0A and X1A pins surrounded by
ground plane because stable operation can be expected with such a layout.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
Treatment of NC and OPEN Pins
Pins marked as NC and OPEN must be left open-circuit.
About Mode Pins (MD0 to MD2)
These pins should be connected directly to V
or VSS.
CC
To prev ent the device erroneously s witching to test mode due to noise, design the printed circuit board such that
the distance between the mode pins and V
or VSS is as short as possible and the connection impedance is low.
CC
20
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