FUJITSU MB91230 User Guide

FUJITSU SEMICONDUCTOR

DATA SHEET

32-bit Microcontroller

CMOS

DS07-16506-2E

FR60Lite

MB91230 Series

MB91233L/MB91F233A/MB91F233L/MB91V230

DESCRIPTION

■

The MB91230 series is a line of standard microcontrollers, based on a 32-bit high-performance RISC CPU and
containing variety of I/O resources, for embedded control applications which require high CPU performance at
high speed processing.

Audio motor control storage : Designed to specifications for embedded control applications which high CPU
performance power processing.

The MB91230 series belongs to the FR60Lite.

FEATURES

■

• 32-bit RISC, load/store architecture with a 5 stage pipeline

• Maximum operating frequency: 33.6 MHz (oscillation frequency = 4.2 MHz, oscillation frequency 8-multiplier
(PLL clock multiplication method) )

• 16-bit fixed length instructions (basic instructions)

• Execution speed of instructions : 1 instruction per cycle

(Continued)

PACKAGES

■

401-pin Ceramic PGA 120-pin Plastic LQFP 128-pin plastic FLGA

(PGA-401C-A02) (FPT-120P-M05) (LGA-128P-M01)

MB91230 Series

(Continued)

• Memory-to-memory transfer, bit handling, and barrel shift instructions, etc. : Instructions suitable f or embedded
applications

• Function entry/exit instructions, multiple-register load/store instructions : Instructions adapted for C-language

• Register interlock function : Facilitates coding in assembler

• Built-in multiplier with instruction-level support

- 32-bit multiplication with sign : 5 cycles

- 16-bit multiplication with sign : 3 cycles

• Interrupt (PC and PS save) : 6 cycles (16 priority levels)

• Harvard architecture allowing program access and data access to be executed simultaneously

• Instruction compatible with FR family

• Capacity of built-in ROM and ROM type

- MASK ROM : 256 Kbytes

- FLASH ROM : 256 Kbytes

• Capacity of built-in RAM : 16 Kbytes

• General-purpose ports : Maximum 98 ports (including N-ch open-drain port : 4 ports)

• A/D converter (series-parallel type)

- Resolution : 10-bit : 8 channels (4 channels × 2 unit)

- Conversion time : 1.69 µs (Minimum conversion time)

• D/A converter (R-2R type)

- Resolution : 8-bit : 2 channels (independence)

- Conversion speed : 0.6 µs (when load capacitance 20 pF)

• External interrupt input : 16 channels

• Bit search module (for REALOS)

- Function for searching the MSB (Upper bit) in each word for the first “0” or “1” inverted point

• UART (full-duplex double buffer) : 4 channels

- Selectable parity On/Off

- Asynchronous (start-stop synchronized) or clock-synchronous communications selectable

- Internal timer for dedicated baud rate (U-timer) on each channel

- External clock can be used as transfer clock

- Error detection function for parity, frame and overrun

• PPG : 16-bit × 6 channels

• Up/down counter : 2 channels (8-bit × 2 channels or 16-bit × 1 channel)

• Reload timer : 16-bit × 4 channels

• Free-run timer : 16-bit × 2 channels

• Watch timer : 15-bit × 1 channel

• PWC : 8-bit × 2 channels

• Input capture : 2 channels (interface with free-run timer 0)

• Output compare : 4 channels (free-run timer 0 and output compare unit 0/1 cooperate, free-run timer 1

and output compare units 2/3)

• LCD controller : SEG0 to SEG31/COM0 to COM3 (also serving as a port)

• Clock monitor (peripheral clock output function) : 1 channel

• Timebase/watchdog timer (26-bit)

• Real-time clock (counting even with the real-time clock stopped)

• Low Power Consumption Mode

• Sleep/stop function

• Package : LQFP-120, FLGA-128

• Technology : CMOS 0.35 µm

• Power supply

• Dual power supply configuration [internal logic 3.3 V, I/O 5.5 V(3.3 V for A/D converter and D/A converter

input/output)]

Note : Do not set the external bus mode in which the MB91230 series cannot operate.

2

PIN ASSIGNMENT

P
P

P

3

2

1

0

■

• MB91233L, MB91F233A, MB91F233L

P25/SOT2

P24/SIN2

P23/PWI1/OP

120

119

118

X0A
X1A

CC

3B

SS

V

VCC3

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

P26/SCK2

P27/SIN3
P30/SOT3
P31/SCK3

P32/AIN0

P33/BIN0

P34/ZIN0

P35/AIN1

P36/BIN1

P37/ZIN1
P40/PPG0
P41/PPG1

V

P42/PPG2
P43/PPG3

P44/TOT0
P45/TOT1
P46/TOT2

P47/CKOT

P50/INT8

P51/INT9

P52/INT10
53/INT11/PPG4
54/INT12/PPG5

P55/INT13/TIN2
P56/INT14/TIN1

P22/PWI0/OP

P21/CKI1/OP

P20/CKI0/OP

P17/INT7

P16/INT6

P15/INT5

117

116

115

114

113

112

(TOP VIEW)

P14/INT4

P13/INT3

P12/INT2X0X1

111

110

109

108

107

VSSVCCP11/INT1

P10/INT0

P07/IC1

P06/IC0

106

105

104

103

102

101

MB91230 Series

P05/SCK1

P04/SOT1

P03/SIN1

P02/SCK0

P01/SOT0

P00/SIN0V3V2V1V0

999897969594939291

100

INIT

90

MD0

89

MD1

88

MD2

87

P73/COM3

86

P72/COM2

85

P71/COM1

84

P70/COM0

83

P67/SEG31

82

P66/SEG30

81

P65/SEG29

80

P64/SEG28

79

PB3/SEG27

78

PB2/SEG26

77

V

76

SS

75

V

CC

74

PB1/SEG25

73

PB0/SEG24

72

PA7/SEG23

71

PA6/SEG22

70

PA5/SEG21

69

PA4/SEG20

68

PA3/SEG19

67

PA2/SEG18

66

PA1/SEG17

65

PA0/SEG16

64

P97/SEG15

63

P96/SEG14

62

P95/SEG13

61

P94/SEG12

∗
∗
∗
∗

3132333435363738394041424344454647484950515253545556575859

SS

CC

AV

AV

AVRH

PD0/DA0

PD1/DA1

PF3/TOT3

PF4/TIN3/ADTG1

57/INT15/TIN0/ADTG0

PC0/AN0

PC1/AN1

PC2/AN2

PC3/AN3

PC4/AN4

SS

V

PC5/AN5

PC6/AN6

PC7/AN7

3IO

CC

V

P80/SEG0

P81/SEG1

P82/SEG2

P83/SEG3

P84/SEG4

P85/SEG5

P86/SEG6

P87/SEG7

60

P90/SEG8

P91/SEG9

P92/SEG10

P93/SEG11

* : Open-drain

(FPT-120P-M05)

(Continued)

3

MB91230 Series

M

H
G

D
C

(Continued)

• MB91F233L

M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12

L

K

J

F
E

B
A A2A3A4A5A6A7A8A9A10A11A12

INDEX

L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12

K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12

J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12
H1 H2 H3 H4 H9 H10 H11 H12
G1 G2 G3 G4 G9 G10 G11 G12

BOTTOM VIEW

F1 F2 F3 F4 F9 F10 F11 F12
E1 E2 E3 E4 E9 E10 E11 E12
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12
A1

123456789101112

(LGA-128P-M01)

4

MB91230 Series

Pin correspondence table of LQFP-120 and FLGA-128 in MB91230 series (LGA-128P-M01)

FLGA-128

LQFP-120

No.

No.

(JEDEC

Signal

name

LQFP-120

No.

No.)

1 A1 P26/SCK2 98 C9 P03/SIN1 18 G1 P42/PPG2

120 A2 P25/SOT2 93 C10 V2 15 G2 V

FLGA-128

No.

(JEDEC

No.)

Signal

name

LQFP-120

No.

FLGA-128

No.

(JEDEC

)

No.

Signal

name

3B

CC

117 A3

P22/PWI0/

OP2

85 C11 P72/COM2 *

2

G3*

4

VCC3*

4

114 A4 P17/INT7 87 C12 MD2 17 G4 VCC3

⎯ A5 *

5

10 D1 P37/ZIN1 71 G9
109 A6 P12/INT2 6 D2 P33/BIN0 75 G10 V
107 A7 X1 8 D3 P35/AIN1 74 G11

103 A8 P10/INT0 119 D4 P24/SIN2 77 G12

PA6/

SEG22

CC

PB1/

SEG25

PB2/

SEG26

100 A9 P05/SCK1 111 D5 P14/INT4 21 H1 P45/TOT1

97 A10 P02/SCK0 ⎯ D6 *

5

19 H2 P43/PPG3
94 A11 V3 101 D7 P06/IC0 23 H3 P47/CKOT
91 A12 V0 95 D8 P00/SIN0 20 H4 P44/TOT0

4 B1 P31/SCK3 89 D9 MD0 65 H9

118 B2

115 B3

P23/PWI1/

OP3

P20/CKI0/

OP0

86 D10 P73/COM3 72 H10

82 D11

P67/

SEG31*

1

69 H11

PA0/

SEG16

PA7/

SEG23

PA4/

SEG20

112 B4 P15/INT5 84 D12 P71/COM1 73 H12

PB0/

SEG24
110 B5 P13/INT3 13 E1 X0A 24 J1 P50/INT8
106 B6 V

SS

9 E2 P36/BIN1 22 J2 P46/TOT2

104 B7 P11/INT1 12 E3 P41/PPG1 26 J3 P52/INT10

99 B8 P04/SOT1 5 E4 P32/AIN0 29 J4

96 B9 P01/SOT0 81 E9

P66/

SEG30*

1

35 J5 PD1/DA1

P55/INT13/

TIN2

92 B10 V1 83 E10 P70/COM0 40 J6 PC1/AN1
88 B11 MD1 80 E11
90 B12 INIT

⎯ E12 *

P65/

SEG29*

5

1

47 J7 V

SS

50 J8 P81/SEG1

(Continued)

5

MB91230 Series

(Continued)

FLGA-128

LQFP-120

No.

No.

(JEDEC

Signal

name

LQFP-120

No.

No.)

7 C1 P34/ZIN0 16 F1 V

2 C2 P27/SIN3 ⎯ F2 *

3 C3 P30/SOT3 14 F3 X1A 66 J11

116 C4

P21/CKI1/

OP1

11 F4 P40/PPG0 70 J12

113 C5 P16/INT6 78 F9

108 C6 X0 79 F10

105 C7 V

CC

76 F11 V

102 C8 P07/IC1 ⎯ F12 *

41 K5 PC2/AN2 36 L4 AV
44 K6 PC5/AN5 *

3IO 43 L6 PC4/AN4 42 M5 PC3/AN3

48 K7 V

CC

3

53 K8 P84/SEG4 45 L7 PC6/AN6 46 M6 PC7/AN7
56 K9 P87/SEG7 49 L8 P80/SEG0 ⎯ M7 *

63 K10

62 K11

67 K12

P96/

SEG14

P95/

SEG13

PA2/

SEG18

52 L9 P83/SEG3 51 M8 P82/SEG2

55 L10 P86/SEG6 54 M9 P85/SEG5

58 L11 P91/SEG9 57 M10 P90/SEG8

P56/

30 L1

INT14/

64 L12

TIN1
P54/

28 L2

INT12/

31 M1

PPG5

32 L3 PF3/TOT3 34 M2 PD0/DA0

FLGA-128

No.

(JEDEC

No.)

4

L5*

Signal

name

SS

5

PB3/

SEG27

P64/

SEG28*

SS

5

CC

AVRL*

P97/

SEG15

P57/

INT15/

TIN0/

ADTG0

LQFP-120

1

4

FLGA-128

No.

No.

(JEDEC

)

No.

59 J9

68 J10

27 K1

25 K2 P51/INT9

33 K3
38 K4 AV

37 M3 AVRH
39 M4 PC0/AN0

60 M11

61 M12

Signal

name

P92/

SEG10

PA3/

SEG19

PA1/

SEG17

PA5/

SEG21

P53/

INT11/

PPG4

PF4/TIN3/

ADTG1

SS

5

P93/

SEG11

P94/

SEG12

*1 : Open-drain

3) on the LQFP product

*2 : Connected to pin 17(V
*3 : Connected to pin 38(AV

CC

) on the LQFP product

SS

*4 : Signals added to the FLGA product
*5 : NC pin on the FLGA product

6

PIN DESCRIPTION

■

MB91230 Series

Pin no.

LQFP FLGA

1A1

2C2

3C3

4B1

5E4

6D2

7C1

8D3

Pin name Circuit type Description

UART2 clock input/output.

SCK2

D

P26

SIN3

D

P27

SOT3

B

P30

SCK3

B

P31

AIN0

B

P32

BIN0

B

P33

ZIN0

B

P34

AIN1

B

P35

This function is valid when corresponding bit of PFR2
register is set to peripheral function.

General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.

UART3 data input.
When using this function, corresponding bit of DDR2
register is set to input.

General purpose input/output port.
This function is always valid.

UART3 data output.
This function is valid when corresponding bit of PFR3
register is set to peripheral function.

General purpose input/output port.
This function is valid when corresponding bit of PFR3
register is set to port function.

UART3 clock input/output.
This function is valid when corresponding bit of PFR3
register is set to peripheral function.

General purpose input/output port.
This function is valid when corresponding bit of PFR3
register is set to port function.

Up/down counter 0 AIN input.
When using this function, corresponding bit of DDR3
register is set to input.

General purpose input/output port.
This function is always valid.

Up/down counter 0 BIN input.
When using this function, corresponding bit of DDR3
register is set to input.

General purpose input/output port.
This function is always valid.

Up/down counter 0 ZIN input.
When using this function, corresponding bit of DDR3
register is set to input.

General purpose input/output port.
This function is always valid.

Up/down counter 1 AIN input.
When using this function, corresponding bit of DDR3
register is set to input.

General purpose input/output port.
This function is always valid.

(Continued)

7

MB91230 Series

Pin no.

LQFP FLGA

9E2

10 D1

11 F4

12 E3

Pin name Circuit type Description

Up/down counter 1 BIN input.

BIN1

B

P36

When using this function, corresponding bit of DDR3
register is set to input.

General purpose input/output port.
This function is always valid.

Up/down counter 1 ZIN input.

ZIN1

B

P37

When using this function, corresponding bit of DDR3
register is set to input.

General purpose input/output port.
This function is always valid.

PPG0 output.

PPG0

This function is valid when corresponding bit of PFR4
register is set to peripheral function.

D

General purpose input/output port.

P40

This function is valid when corresponding bit of PFR4
register is set to port function.

PPG1 output.

PPG1

This function is valid when corresponding bit of PFR4
register is set to peripheral function.

D

General purpose input/output port.

P41

This function is valid when corresponding bit of PFR4

register is set to port function.
13 E1 X0A
14 F3 X1A
15 G2 V
16 F1 V
17 G4 V

CC

SS

CC

PPG2

18 G1

P42

PPG3

19 H2

P43

K Sub-clock oscillation pin (32 kHz)

3B ⎯ Power supply pin for backup (RTC)

⎯ Power supply pin (GND)

3 ⎯ Power supply pin (3.3 V internal logic)

PPG2 output.

This function is valid when corresponding bit of PFR4

register is set to peripheral function.

D

General purpose input/output port.

This function is valid when corresponding bit of PFR4

register is set to port function.

PPG3 output.

This function is valid when corresponding bit of PFR4

register is set to peripheral function.

D

General purpose input/output port.

This function is valid when corresponding bit of PFR4

register is set to port function.

(Continued)

8

MB91230 Series

Pin no.

LQFP FLGA

20 H4

21 H1

22 J2

23 H3

24 J1

Pin name Circuit type Description

Reload timer 0 output port.

TOT0

D

P44

TOT1

D

P45

TOT2

D

P46

CKOT

D

P47

INT8

C

P50

This function is valid when corresponding bit of PFR4

register is set to peripheral function.

General purpose input/output port.

This function is valid when corresponding bit of PFR4

register is set to port function.

Reload timer 1 output port.

This function is valid when corresponding bit of PFR4

register is set to peripheral function.

General purpose input/output port.

This function is valid when corresponding bit of PFR4

register is set to port function.

Reload timer 2 output port.

This function is valid when corresponding bit of PFR4

register is set to peripheral function.

General purpose input/output port.

This function is valid when corresponding bit of PFR4

register is set to port function.

Clock monitor function output pin.

This function is valid when corresponding bit of PFR4

register is set to peripheral function.

General purpose input/output port.

This function is valid when corresponding bit of PFR4

register is set to port function.

External interrupt input.

When using this function, corresponding bit of DDR5

register is set to input.

General purpose input/output port.

This function is always valid.

25 K2

26 J3

INT9

P51

INT10

P52

External interrupt input.

When using this function, corresponding bit of DDR5

C

C

register is set to input.

General purpose input/output port.

This function is always valid.

External interrupt input.

When using this function, corresponding bit of DDR5

register is set to input.

General purpose input/output port.

This function is always valid.

(Continued)

9

MB91230 Series

Pin no.

LQFP FLGA

27 K1

28 L2

Pin name Circuit type Description

PPG4 output.

PPG4

INT11

P53

PPG5

INT12

P54

C

C

This function is valid when corresponding bit of PFR5

register is set to peripheral function.

External interrupt input.

This function is enabled when corresponding bit of

PFR5 register is set to port function and corresponding

bit of DDR5 resister is set to input.

General purpose input/output port.

This function is valid when corresponding bit of PFR5

register is set to port function.

PPG5 output.

This function is valid when corresponding bit of PFR5

register is set to peripheral function.

External interrupt input.

This function is enabled when corresponding bit of

PFR5 register is set to port function and corresponding

bit of DDR5 resister is set to input.

General purpose input/output port.

This function is valid when corresponding bit of PFR5

register is set to port function.

29 J4

30 L1

TIN2

INT13

P55

TIN1

INT14

P56

Reload timer 2 event input pin.

This function is valid when corresponding bit of DDR5

register is set to input.

C

C

External interrupt input.

This function is valid when corresponding bit of DDR5

register is set to input.

General purpose input/output port.

This function is always valid.

Reload timer 1 event input pin.

This function is valid when corresponding bit of DDR5

register is set to input.

External interrupt input.

This function is valid when corresponding bit of DDR5

register is set to input.

General purpose input/output port.

This function is always valid.

(Continued)

10

MB91230 Series

Pin no.

LQFP FLGA

31 M1

32 L3

33 K3

34 M2

35 J5

36 L4 AV
37 M3 AVRH ⎯ Analog reference power supply (for A/D, D/A converter) .
38 K4 AV

Pin name

ADTG0

TIN0

INT15

P57

TOT3

PF3

ADTG1

TIN3

PF4

DA0

PD0

DA1

PD1

CC

SS

Circuit

type

External trigger input pin of A/D converter 0.
This function is valid when corresponding bit of DDR5 reg­ister is set to input.

Reload timer 0 event input pin.
This function is valid when corresponding bit of DDR5 reg-

C

D

D

F

F

⎯ Analog power supply (for A/D, D/A converter) .

⎯ GND level input for analog circuit (for A/D, D/A converter) .

ister is set to input.
External interrupt input.

This function is valid when corresponding bit of DDR5 reg­ister is set to input.

General purpose input/output port.
This function is always valid.

Reload timer 3 output port.
This function is valid when corresponding bit of PFRF
register is set to peripheral function.

General purpose input/output port.
This function is valid when corresponding bit of PFRF
register is set to port function.

External trigger input pin of A/D converter 1.
This function is valid when corresponding bit of DDRF
register is set to input.

Reload timer 3 event input pin.
This function is valid when corresponding bit of DDRF
register is set to input.

General purpose input/output port.
This function is always valid.

D/A converter 0 output pin.
This function is valid when corresponding bit of PFRD
register is set to peripheral function.

General purpose input/output port.
This function is valid when corresponding bit of PFRD
register is set to port function.

D/A converter 1 output pin.
This function is valid when corresponding bit of PFRD
register is set to peripheral function.

General purpose input/output port.
This function is valid when corresponding bit of PFRD
register is set to port function.

Description

(Continued)

11

MB91230 Series

Pin no.

LQFP FLGA

M4, J6, K5,

39 to 46

M5, L6, K6,

L7, M6

47 J7 V
48 K7 V

L8, J8, M8,

49 to 56

L9, K8, M9,

L10, K9

M10, L11, J9,

57 to 64

M11, M12,

K11, K10, L12

Pin name Circuit type Description

Analog input pin for A/D converter.

AN0 to AN7

This function is valid when corresponding bit of PFRC
register is set to peripheral function.

E

General purpose input/output port.

PC0 to PC7

This function is valid when corresponding bit of PFRC
register is set to port function.

SS

3IO ⎯ Power supply pin (analog-shared pin I/O)

CC

SEG0 to

SEG7

⎯ Power supply pin (GND)

LCD controller/driver LCD segment output pin.
This function is valid when corresponding bit of PFR8
register is set to peripheral function.

I

General purpose input/output port.

P80 to P87

This function is valid when corresponding bit of PFR8
register is set to port function.

SEG8 to

SEG15

LCD controller/driver LCD segment output pin.
This function is valid when corresponding bit of PFR9
register is set to peripheral function.

I

General purpose input/output port.

P90 to P97

This function is valid when corresponding bit of PFR9
register is set to port function.

H9, J11, K12,

65 to 72

J10, H11, J12,

G9, H10

73, 74 H12, G11

75 G10 V

76 F11 V

77, 78 G12, F9

SEG16 to

SEG23

PA0 to PA7

SEG24,

SEG25

PB0, PB1

CC

SS

SEG26,

SEG27

PB2, PB3

LCD controller/driver LCD segment output pin.
This function is valid when corresponding bit of PFRA
register is set to peripheral function.

I

General purpose input/output port.
This function is valid when corresponding bit of PFRA
register is set to port function.

LCD controller/driver LCD segment output pin.
This function is valid when corresponding bit of PFRB
register is set to peripheral function.

I

General purpose input/output port.
This function is valid when corresponding bit of PFRB
register is set to port function.

Power supply pin (5 V I/O MB91V230/F233A)

⎯

Power supply pin (3.3 V internal logic, I/O MB91F233L/
MB91233L)

⎯ Power supply pin (GND)

LCD controller/driver LCD segment output pin.
This function is valid when corresponding bit of PFRB
register is set to peripheral function.

I

General purpose input/output port.
This function is valid when corresponding bit of PFRB
register is set to port function.

(Continued)

12

MB91230 Series

Pin no.

LQFP FLGA

79 to 82

83 to 86

87 to 89 C12, B11, D9

90 B12 INIT

91 to 94

95 D8

F10, E11, E9,

D11

P64 to P67

E10, D12,

C11, D10

P70 to P73

A12, B10,

C10, A11

Pin name Circuit type Description

SEG28 to

SEG31

COM0 to

COM3

MD2,
MD1,

MD0

V0 to V3 ⎯

SIN0

P00

J

I

H Mode input pin.

G External reset input.

D

LCD controller/driver LCD segment output pin.
This function is valid when corresponding bit of PFR6
register is set to peripheral function.

General purpose input/output port. (open-drain)
This function is valid when corresponding bit of PFR6
register is set to port function.

LCD controller/driver common pins.
This function is valid when corresponding bit of PFR7
register is set to peripheral function.

General purpose input/output port.
This function is valid when corresponding bit of PFR7
register is set to port function.

LCD controller/driver reference power supply input
pins.

UART0 data input.
When using this function, corresponding bit of DDR0
register is set to input.

General purpose input/output port.
This function is always valid.

96 B9

97 A10

98 C9

SOT0

P01

SCK0

P02

SIN1

P03

UART0 data output.
This function is valid when corresponding bit of PFR0

D

D

D

register is set to peripheral function.
General purpose input/output port.

This function is valid when corresponding bit of PFR0
register is set to port function.

UART0 clock input/output.
This function is valid when corresponding bit of PFR0
register is set to peripheral function.

General purpose input/output port.
This function is valid when corresponding bit of PFR0
register is set to port function.

UART1 data input.
This function is valid when corresponding bit of DDR0
register is set to input.

General purpose input/output port.
This function is always valid.

(Continued)

13

MB91230 Series

Pin no.

LQFP FLGA

99 B8

100 A9

101 D7

102 C8

Pin name Circuit type Description

UART1 data output.

SOT1

D

P04

SCK1

D

P05

IC0

D

P06

IC1

D

P07

This function is valid when corresponding bit of PFR0 reg­ister is set to peripheral function.

General purpose input/output port.
This function is valid when corresponding bit of PFR0 reg­ister is set to port function.

UART1 clock input/output.
This function is valid when corresponding bit of PFR0 reg­ister is set to peripheral function.

General purpose input/output port.
This function is valid when corresponding bit of PFR0 reg­ister is set to port function.

Input capture input 0.
This function is valid when corresponding bit of DDR0
register is set to input.

General purpose input/output port.
This function is always valid.

Input capture input 1.
This function is valid when corresponding bit of DDR0
register is set to input.

General purpose input/output port.
This function is always valid.

INT0

103 A8

P10

INT1

104 B7

P11

105 C7 V

106 B6 V
107 A7 X1
108 C6 X0

CC

SS

External interrupt input.
This function is valid when corresponding bit of DDR1

A

A

⎯

⎯ Power supply pin (GND)

K Main-clock oscillation pin

register is set to input.
General purpose input/output port.

This function is always valid.
External interrupt input.

This function is valid when corresponding bit of DDR1
register is set to input.

General purpose input/output port.
This function is always valid.

Power supply pin (5 V I/O MB91V230/F233A)
Power supply pin (3.3 V internal logic, I/O MB91F233L/

MB91233L)

(Continued)

14

MB91230 Series

Pin no.

LQFP FLGA

109 A6

110 B5

111 D5

112 B4

Pin name Circuit type Description

External interrupt input.

INT2

A

P12

INT3

A

P13

INT4

A

P14

INT5

A

P15

This function is valid when corresponding bit of DDR1
register is set to input.

General purpose input/output port.
This function is always valid.

External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.

General purpose input/output port.
This function is always valid.

External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.

General purpose input/output port.
This function is always valid.

External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.

General purpose input/output port.
This function is always valid.

113 C5

114 A4

115 B3

INT6

P16

INT7

P17

CKI0

OP0

P20

External interrupt input.
This function is valid when corresponding bit of DDR1

A

A

D

register is set to input.
General purpose input/output port.

This function is always valid.
External interrupt input.

This function is valid when corresponding bit of DDR1
register is set to input.

General purpose input/output port.
This function is always valid.

External clock input pin for free-run timer 0.
This function is enabled when corresponding bit of PFR2
register is set to port function and corresponding bit of
DDR2 register is set to input.

Output compare 0 output pin.
This function is valid when corresponding bit of PFR2
register is set to peripheral function.

General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.

(Continued)

15

MB91230 Series

(Continued)

Pin no.

LQFP FLGA

116 C4

117 A3

118 B2

119 D4

120 A2

(38) L5 AVRL ⎯

⎯

A5, D6, E12,

F2, F12, M7

Pin name Circuit type Description

CKI1

OP1

P21

PWI0

OP2

P22

PWI1

OP3

P23

SIN2

P24

SOT2

P25

NC ⎯ Unconnected pin.

External clock input pin for free-run timer 1.
This function is enabled when corresponding bit of
PFR2 register is set to port function and corresponding
bit of DDR2 register is set to input.

D

D

D

D

D

Output compare1 output pin.
This function is valid when corresponding bit of PFR2
register is set to peripheral function.

General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.

Pulse width counter 0 input.
This function is enabled when corresponding bit of
PFR2 register is set to port function and corresponding
bit of DDR2 register is set to input.

Output compare2 output pin.
This function is valid when corresponding bit of PFR2
register is set to peripheral function.

General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.

Pulse width counter 1 input.
This function is enabled when corresponding bit of
PFR2 register is set to port function and corresponding
bit of DDR2 register is set to input.

Output compare3 output pin.
This function is valid when corresponding bit of PFR2
register is set to peripheral function.

General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.

UART2 data input.
This function is valid when corresponding bit of DDR2
register is set to input.

General purpose input/output port.
This function is always valid.

UART2 data output.
This function is valid when corresponding bit of PFR2
register is set to peripheral function.

General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.

Analog reference power supply (for A/D converter)

inside the IC on LQFP

AVRL pin is connected to AV
package product.

SS

16

MB91230 Series

I/O CIRCUIT TYPE

■

Type Circuit type Remarks

With Pull-up control (50 kΩ)

Pull-up control

PP

A

N

Output drive Pch
Output drive Nch

CMOS level output
I

= 4 mA/IOL = 4 mA

OH

CMOS hysteresis input (with standby control)

CMOS hysteresis
input

Standby control

Pull-up control

PP

Output drive Pch

With Pull-up control (50 kΩ)
CMOS level output

I

= 4 mA/IOL = 4 mA

OH

CMOS hysteresis input (with standby control)

N

B

Output drive Nch

CMOS hysteresis
input

Test pin for FLASH

Standby control
Test pin for FLASH
Analog SW control

N

CMOS level output

P

C

N

Output drive Pch
Output drive Nch

CMOS hysteresis input (with standby control)

CMOS hysteresis
input

Standby control

P

N

D

Output drive Pch
Output drive Nch

CMOS hysteresis
input

CMOS level output
I

= 4 mA/IOL = 4 mA

OH

CMOS hysteresis input (with standby control)
Test pin for FLASH

Standby control
Test pin for FLASH

Analog SW control

N

(Continued)

17

MB91230 Series

t

ut

Type Circuit type Remarks

P

N

Output drive Pch
Output drive Nch

CMOS level output
I

= 4 mA/IOL = 4 mA

OH

CMOS hysteresis input (with standby control)
Also serving as an analog input

E

CMOS hysteresis
input

Standby control
Analog input

Analog SW control

N

P

N

F

Output drive Pch
Output drive Nch

CMOS hysteresis
input

CMOS level output
I

= 4 mA/IOL = 4 mA

OH

CMOS hysteresis input (with standby control)
Also serving as an analog input

Standby control
Analog input

Analog SW control

N

With Pull-up (50 kΩ)
CMOS hysteresis input

PP

18

G

N

CMOS hysteresis
input

High withstand-voltage input
CMOS input (hysteresis level)

N

Low impedance inpu
High impedance inp

H

N

N

N

N

High voltage
detection
output

(Continued)

MB91230 Series

X

X

(Continued)

Type Circuit type Remarks

P

N

Output drive Pch
Output drive Nch

I

CMOS hysteresis
input

Standby control
LCDC output

CMOS level output

I

= 4 mA/IOL = 4 mA

OH

CMOS hysteresis input (with standby control)
LCDC output

P

CMOS level output (open-drain)

I

= 20 mA

OL

CMOS hysteresis input (with standby control)
LCDC output

N

Output drive Nch

J

CMOS hysteresis
input

Standby control
LCDC output

1, X1A

Oscillation circuit

Oscillation
output

K

0, X0A

Standby
control

19

MB91230 Series

HANDLING DEVICES

■

Preventing Latch-up

Latch-up may occur in a CMOS IC if a voltage greater than V
pin or if an above-rating voltage is applied between V

and VSS.

CC

A latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of
an element. When you use a CMOS IC, be very careful not to exceed the absolute maximum rating.

Treatment of Unused Pins

Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example , using a pull­up or pull-down resistor.

Treatment of Pins at Unusing LCD

Leave COM0 to COM3 pins open.
V0 to V3 pins should always be pulled up or down through resistance of at least 2 kΩ.

About Power Supply Pins

or less than VSS is applied to an input or output

CC

In products with multiple V

or VSS pins, the pins of the same potential are internally connected in the device

CC

to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission le vel, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating.

Moreover, connect the current supply source with the V
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between V

and VSS pins of this device at the low impedance.

CC

and VSS near

CC

this device.

About Crystal Oscillator Circuit

Noise near the X0, X1, X0A and X1A pins may cause the de vice to malfunction. Design the printed circuit board
so that X0, X1, X0A and X1A the crystal oscillator (or ceramic oscillator) , and the bypass capacitor to ground
are located as close to the device as possible.

It is strongly recommended to design the PC board artwork with the X0, X1, X0A and X1A pins surrounded by
ground plane because stable operation can be expected with such a layout.

Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.

Treatment of NC and OPEN Pins

Pins marked as NC and OPEN must be left open-circuit.

About Mode Pins (MD0 to MD2)

These pins should be connected directly to V

or VSS.

CC

To prev ent the device erroneously s witching to test mode due to noise, design the printed circuit board such that
the distance between the mode pins and V

or VSS is as short as possible and the connection impedance is low.

CC

20

Operation at Start-up

MB91230 Series

Be sure to execute setting initialized reset (INIT) with INIT

pin immediately after start-up.

Also, in order to provide the oscillation stabilization w ait time f or the oscillation circuit immediately after start-up,
hold the “L” level input to the INIT

pin for the required stabilization wait time. (For INIT via the INIT pin, the

oscillation stabilization wait time setting is initialized to the minimum value) .

About Oscillation Input at Power On

When turning the power on, maintain clock input until the device is released from the oscillation stabilization
wait state.

Clock Control Block

Input the “L” signal to the INIT

pin to assure the clock oscillation stabilization wait time.

Switch Shared Port Function

To switch between the use as a port and the use as a dedicated pin, use the port function register (PFR) .

Low Power Consumption Mode

To enter the standby mode, use the synchronous standb y mode (set with the SYNCS bit as bit 8 in the TBCR :
timebase counter control register) and be sure to use the following sequence

(LDI #value_of_standby, R0) : value_of_standby is write data to STCR.

) of STCR.

(LDI #_STCR, R12) : _STCR is address (481

H

STB R0, @R12 : Writing to standby control register (STCR)
LDUB @R12, R0 : STCR read for synchronous standby
LDUB @R12, R0 : Dummy re-read of STCR
NOP : NOP × 5 for arrangement of timing
NOP
NOP
NOP
NOP

In addition, please set I flag, ILM, and ICR to diverge to the interruption handler that is the return factor after the
standby returns.

• Please do not do the following when the monitor debugger is used.

• Break point setting for above instruction lines

• Step execution for above instruction lines

Power-on sequence for dual-power-supply model

• Notes on the power-on and power-off sequences
Power-on sequence : Vcc3B, Vcc3→Vcc→Vcc3IO, AVRH, V0 to V3
Power-off sequence : Vcc3IO, AVRH, V0 to V3, Vcc3→Vcc→Vcc3B, Vcc3

When V

• The LCD power supply V3 must not exceed V

• Turn on V

is turned on earlier, a potential difference between VCC and VCC3 must fall within 3.6 V.

CC

in voltage. Apply V3 after turning on VCC3.

CC

3 before applying the analog power supply AVCC or an analog signal.

CC

21

MB91230 Series

Notes on the PS register

As the PS register is processed by some instructions in advance, exception handling below may cause the
interrupt handling routine to break when the debugger is used or the display contents of flags in the PS register
to be updated.

As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it
performs operations before and after the EIT as specified in either case.

• The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS

instruction is (a) acceptance of a user interrupt, (b) single-stepped, or (c) breaks in response to a data event
or emulator menu :

1) The D0 and D1 flags are updated in advance.

2) An EIT handling routine (user interrupt or emulator) is executed.

3) Upon returning from the EIT , the DIVOU/DIV OS instruction is e xecuted, and the D0 and D1 flags are updated
to the same values as in 1).

• The following operations are performed when the ORCCR/STILM/MOVRi and PS instructions are executed
to allow the interrupt.

1) The PS register is updated in advance.

2) An EIT handling routine (user interrupt) is executed.

3) Upon returning from the EIT, the above instructions are executed, and the PS register is updated to the
same value as in 1).

Watchdog Timer

The watchdog timer built in this model monitors a program that it defers a reset within a certain period of time.
The watchdog timer resets the CPU if the program runs out of controls, preventing the reset defer function from
being executed. Once the function of the watchdog timer is enabled, therefore, the watchdog timer keeps on
operating programs until it resets the CPU.

As an exception, the watchdog timer defers a reset automatically under the condition in which the CPU stops
program execution.

For those conditions to which this exception applies, see the function description of watchdog timer.

Step execution of RETI instruction

If an interrupt occurs frequently during step execution, the corresponding interrupt handling routine is ex ecuted
repeatedly after step execution. This will prevent the main routine and low-interrupt-level programs from being
executed.

Do not execute step of RETI instruction for escape.
Disable the corresponding interrupt and execute debugger when the corresponding interrupt routine no longer

needs debugging.

Operand Break

Do not apply a data event break to access to the area containing the address of a system stack pointer.

22

BLOCK DIAGRAM

■

MB91230 Series

FR60Lite

CPU Core

3232

Bit Search

X0, X1

MD0 to MD2

INIT

X0A, X1A

CC

3B

V

INT0 to INT15

SIN0 to SIN3
SOT0 to SOT3
SCK0 to SCK3

ROM 256 Kbytes

FLASH 256 Kbytes

RAM 16 Kbytes

Clock Control

(Clock, Standby,

Reset, Watchdog,

TBT ,

Main-Clock-

Stabilization-

Timer)

Watch Timer

Real Time Clock

Interruption

Controller

External interrupt

0 to 15

UART
0 to 3

U-TIMER

0 to 3

32 ↔ 16

Adapter

16

Bus Converter

32

Clock Monitor

External Memory

I/F

(MB91230 series

is not supported)

PORT I/F

LCDC, Driver/

Internal Reference

Voltage

Up/Down Counter

0, 1

Reload Timer

0 to 3

PPG

0 to 5

V

CC

PORTs
CKOT

COM0 to COM3
SEG0 to SEG31

V0 to V3

AIN0, AIN1
BIN0, BIN1

ZIN0, ZIN1

TO0 to TO3

PPG0 to PPG5

AN0 to AN3

ADTG0

AVRH

AN4 to AN7

ADTG1

AV

DA0, DA1

CC

4-channel Input
A/D converter 0

4-channel Input
A/D converter 1

2-channel Output

D/A converter 0, 1

Input Capture 0, 1

Free Run Timer 0

Output Compare 0, 1

Free Run Timer 1

Output Compare 2, 3

8-bit PWC 0, 1

IC0, IC1
CKI0

OP0, OP1

CKI1

OP2, OP3

PWI0, PWI1

: Trriger signal

23

MB91230 Series

0

0

0

0

0

0

0

F

L

MEMORY SPACE

■

1. Memory space

FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access.

• Direct Addressing Areas
The following address space areas are used as I/O areas.
These areas are called direct addressing areas, in which the address of an operand can be specified directly

during an instruction.
The size of directly addressable areas depends on the length of the data being accessed as shown below.

• byte data access : 000

• half word data access : 000

• word data access : 000

to 0FF

H

to 1FF

H

to 3FF

H

H

H

H

2. Memory Map

MB91V230 MB91F233A/L, MB91233

000 0000

000 0400

001 0000

H

H

H

I/O

I/O

Access

disallowed

003 A000

H

Built-in RAM

24 Kbytes

004 0000

H

Access

disallowed

008 0000

H

Emulation

SRAM area

512 Kbytes

010 0000

H

Access

disallowed

FFF FFFF

H

Direct Addressing
Areas

“Refer to “■I/O MAP”.

0001 0000

0003 C000

0004 0000

000C 0000

0010 0000

FFFF FFFF

I/O

I/O

H

Access

disallowed

H

Built-in RAM

16 Kbytes

H

Access

disallowed

H

Built-in

FLASH ROM

256 Kbytes

H

Access

disallowed

H

Note : The external bus mode cannot be used in the MB91230 series.

24

MB91230 Series

b

0

0

MODE SETTINGS

■

The FR family uses mode pins (MD2 to MD0) and a mode data to set the operation mode.

• Mode Pins
The MD2 to MD0 pins specify how the mode vector fetch and reset vector fetch is performed.
Setting is prohibited other than that shown in the following table.

Mode Pins

Mode name

MD2 MD1 MD0

Reset vector

access area

Remarks

0 0 0 Internal ROM mode vector Internal

0 0 1 External ROM mode vector External Not supported by this model.

• Mode data
Data written to the internal mode register (MODR) by a mode vector fetch is called mode data.
After an operation mode has been set in the mode register, the device operates in the operation mode.
The mode data is set by all reset source. User programs cannot set data to the mode register.

Details of mode data description

31

it 30 29 28 27 26 25 24

00000111

Operation mode setting bits

Bit31 to bit24 are all reserved bits.
Be sure to set this bit to “00000111”.

Operation is not guaranteed when any value other than “00000111” is set.

Note : Mode data set in the mode vector must be placed as byte data at 0x000FFFF8

.

H

Use the highest byte from bit31 to bit24 for placement as the FR family uses the big endian for byte
endian.

31bit 24 23 16 15 8 7

Incorrect

0x000FFFF8H

Correct

x000FFFFCH

XXXXXXXX0x000FFFF8H

Mode Data

XXXXXXXX XXXXXXXX Mode Data

XXXXXXXX XXXXXXXX XXXXXXXX

Reset Vector

25

MB91230 Series

I/O MAP

■

[How to read the table]

Address

000000

Note : Initial values of register bits are represented as follows :

Access is barred with an undefined data access attribute.

H

“ 1 ” : Initial Value “ 1 ”
“ 0 ” : Initial Value “ 0 ”
“ X ” : Initial Value “ undefined”
“ - ” : No physical register at this location

+ 0 + 1 + 2 + 3

PDR0 [R/W] B

XXXXXXXX

PDR1 [R/W] B

XXXXXXXX

Read/write attribute Access unit
(B : byte, H : half word, W : word)

Initial value of register after reset
Register name (column 1 of the register is at address 4n, column 2 is

at address 4n + 1...)
Leftmost register address (For word-length access, column 1 of the

register becomes the MSB of the data.)

Register

PDR2 [R/W] B

XXXXXXXX

PDR3 [R/W] B

XXXXXXXX

Block

T-unit

Port data register

26

MB91230 Series

Address

000000

000004

000008

00000C
000010

to

00003C

000040

000044

000048

00004C

PDR0 [R/W] B

H

XXXXXXXX

PDR4 [R/W] B

H

XXXXXXXX

PDR8 [R/W] B

H

XXXXXXXX

PDRC [R/W] B

H

XXXXXXXX

H

H

EIRR0 [R/W]

H

DICR [R/W]

H

H

H

Register

+ 0 + 1 + 2 + 3

PDR1 [R/W] B

XXXXXXXX

PDR5 [R/W] B

XXXXXXXX

PDR9 [R/W] B

XXXXXXXX

PDRD [R/W] B

------XX

PDR2 [R/W] B

XXXXXXXX

PDR6 [R/W] B

XXXX----

PDRA [R/W] B

XXXXXXXX

⎯

PDR3 [R/W] B

XXXXXXXX

PDR7 [R/W] B

----XXXX

PDRB [R/W] B

----XXXX

PDRF [R/W]

---XX---

⎯⎯⎯⎯Unused

B, H, W

00000000

B, H, W

ENIR0 [R/W]

B, H, W

00000000

⎯⎯Delay interrupt

ELVR0 [R/W] B, H, W

00000000 00000000

-------0
TMRLR0 [W] H

XXXXXXXX XXXXXXXX

⎯

TMR0 [R] H

XXXXXXXX XXXXXXXX

TMCSR0 [R/W] H

----0000 00000000

Block

Port data register

External interrupt
(INT0 to INT7)

Reload timer 0

000050

000054

000058

00005C

000060

000064

000068

00006C

H

H

H

H

H

H

H

H

TMRLR1 [W] H

XXXXXXXX XXXXXXXX

⎯

TMRLR2 [W] H

XXXXXXXX XXXXXXXX

⎯

SSR0 [R/W]

B, H, W

00001000

SIDR0 [R] B, H, W

SODR0 [W] B, H,

W

XXXXXXXX

UTIM0 [R] H (UTIMR0 [W] H)

00000000 00000000

SSR1 [R/W]

B, H, W

00001000

SIDR1 [R] B, H, W

SODR1 [W] B, H,

W

XXXXXXXX

UTIM1 [R] H (UTIMR1 [W] H)

00000000 00000000

TMR1 [W] H

XXXXXXXX XXXXXXXX

TMCSR1 [R/W] H

----0000 00000000
TMR2 [W] H

XXXXXXXX XXXXXXXX

TMCSR2 [R/W] H

----0000 00000000

SCR0 [R/W]

SMR0 [R/W]

B, H, W

00000100

⎯

SCR1 [R/W]

UTIMC0 [R/W] B

SMR1 [R/W]

B, H, W

00000100

⎯

UTIMC1 [R/W] B

B, H, W
00--0-0-

0--00001

B, H, W
00--0-0-

0--00001

Reload timer 1

Reload timer 2

UART0

U-TIMER0

UART1

U-TIMER1

(Continued)

27

MB91230 Series

Address

000070

000074

000078

00007C

000080

000084

000088

00008C

000090

000094

000098

00009C

0000A0

0000A4

0000A8

0000AC

+ 0 + 1 + 2 + 3

SSR2 [R/W]

H

B, H, W

00001000

H

H

H

H

H

H

H

H

H

UTIM2 [R] H (UTIMR1 [W] H)

00000000 00000000

ADCS0 [R/W] H, W

XXXXXXXX XXXXXXXX

ADT00 (ADTH00/ADTL00) [R] B, H, W

000000XX XXXXXXXX

ADT02 (ADTH02/ADTL02) [R] B, H, W

000000XX XXXXXXXX

ADCS1 [R/W] H, W

XXXXXXXX XXXXXXXX

ADT10 (ADTH10/ADTL10) [R] B, H, W

000000XX XXXXXXXX

ADT12 (ADTH12/ADTL12) [R] B, H, W

000000XX XXXXXXXX

⎯⎯

⎯⎯

SIDR2 [R] B, H, W

SODR2 [W] B, H,

W

XXXXXXXX

LCDCMR [R/W]

H

B, H, W

⎯

----0000

VRAM0 [R/W]

H

B, H, W

XXXXXXXX

VRAM4 [R/W]

H

B, H, W

XXXXXXXX

VRAM8 [R/W]

H

B, H, W

XXXXXXXX

VRAM12 [R/W]

H

B, H, W

XXXXXXXX

VRAM1 [R/W]

B, H, W

XXXXXXXX

VRAM5 [R/W]

B, H, W

XXXXXXXX

VRAM9 [R/W]

B, H, W

XXXXXXXX

VRAM13 [R/W]

B, H, W

XXXXXXXX

CKR [R/W]

H

B, H, W

⎯⎯⎯Clock monitor

----0000

Register

SCR2 [R/W]

B, H, W

00000100

⎯

SMR2 [R/W]

B, H, W

00--0-0-

UTIMC2 [R/W] B

0--00001

ADCT0 [R/W] H, W

000-0000 -000--00

ADT01 (ADTH01/ADTL01) [R] B, H, W

000000XX XXXXXXXX

ADT03 (ADTH03/ADTL03) [R] B, H, W

000000XX XXXXXXXX

ADCT1 [R/W] H, W

000-0000 --000--00

ADT11 (ADTH11/ADTL11) [R] B, H, W

000000XX XXXXXXXX

ADT13 (ADTH13/ADTL13) [R] B, H, W

000000XX XXXXXXXX

DACR1 [R/W]

B, H, W

-------0

DADR1 [R/W]

B, H, W

XXXXXXXX
LCR0 [R/W]

B, H, W

00010000

VRAM2 [R/W]

B, H, W

XXXXXXXX

VRAM6 [R/W]

B, H, W

XXXXXXXX

VRAM10 [R/W]

B, H, W

XXXXXXXX

VRAM14 [R/W]

B, H, W

XXXXXXXX

DACR0 [R/W]

B, H, W

-------0

DADR0 [R/W]

B, H, W

XXXXXXXX
LCR1 [R/W]

B, H, W

00000000

VRAM3 [R/W]

B, H, W

XXXXXXXX

VRAM7 [R/W]

B, H, W

XXXXXXXX

VRAM11 [R/W]

B, H, W

XXXXXXXX

VRAM15 [R/W]

B, H, W

XXXXXXXX

Block

UART2

U-TIMER2

A/D converter 0
(series-parallel
type)

A/D converter 1
(series-parallel
type)

D/A converter

LCD controller/
driver

(Continued)

28

MB91230 Series

Address

0000B0

0000B8

0000BC

0000C0

0000C4

0000C8

0000CC

RCR1 [W]

H

00000000

CCRH0 [R/W]

H

00000000

CCRH1 [R/W]

H

00000000

H

SSR3 [R/W]

H

00001000

H

H

H

Register

+ 0 + 1 + 2 + 3

B, H, W

B, H, W

B, H, W

RCR0 [W]

B, H, W

00000000

CCRL0 [R/W]

B, H, W

00001000

CCRL1 [R/W]

B, H, W

00001000

UDCR1 [R]

B, H, W

00000000

⎯

⎯

UDCR0 [R]

B, H, W

00000000

CSR0 [R/W]

B, H, W

00000000

CSR1 [R/W]

B, H, W

00000000

⎯⎯⎯⎯unused

SIDR3 [R] B, H, W

B, H, W

SODR3 [W] B, H, W

XXXXXXXX

UTIM3 [R] H (UTIMR [W] H)

00000000 00000000

TMRLR3 [W] H

XXXXXXXX XXXXXXXX

⎯

SCR3 [R/W]

SMR3 [R/W]

B, H, W

00000100

⎯

UTIMC3 [R/W] B

TMR3 [W] H

XXXXXXXX XXXXXXXX

TMCSR3 [R/W] H

---00000 00000000

B, H, W
00--0-0-

0--00001

Block

Up/down counter0, 10000B4

UART3

U-TIMER3

Reload
timer 3

0000D0

0000D4

0000D8

0000DC

0000E0

0000E4

0000E8

0000EC

EIRR1 [R/W]

H

H

H

H

H

H

H

H

ENIR1 [R/W]

B, H, W

00000000

TCDT0 [R/W] H, W

00000000 00000000

TCDT1 [R/W] H, W

00000000 00000000

IPCP1 [R] H, W

XXXXXXXX XXXXXXXX

B, H, W

00000000

ELVR1 [R/W] B, H, W

00000000 00000000

⎯

⎯

IPCP0 [R] H, W

XXXXXXXX XXXXXXXX

⎯⎯⎯

OCCP1 [R/W] H, W

XXXXXXXX XXXXXXXX

OCCP3 [R/W] H, W

XXXXXXXX XXXXXXXX

OCS23 [R/W] B, H, W

---0--00 0000--00

OCCP0 [R/W] H, W

XXXXXXXX XXXXXXXX

OCCP2 [R/W] H, W

XXXXXXXX XXXXXXXX

OCS01 [R/W] B, H, W

---0-00 0000--00

TCCS0 [R/W]

B, H, W

00000000

TCCS1 [R/W]

B, H, W

00000000

ICS01 [R/W]

B, H, W

00000000

External interrupt
(INT8 to INT15)

Free-run timer 0

Free-run timer 1

Input capture 0, 1

Output compare
0 to 3

(Continued)

29

MB91230 Series

Address

0000F0

0000F4

0000F8

0000FC

000100

to

000114
000118

00011C

000120

000124

PWCC0 [R/W]

H

H

H

WTHR [R/W]

H

---XXXXX

H

H

H

H

H

H

Register

+ 0 + 1 + 2 + 3

B, H, W
0---00-0

⎯

⎯

B, H

PWCD0 [R]

B, H, W

XXXXXXXX

WTDBL [R/W] B

-------0

WTBR0 [R/W] B

---XXXXX

WTMR [R/W]

B, H

--XXXXXX

PWCC1 [R/W]

B, H, W
0---00-0

WTCR [R/W] B, H

00000000 000-00-X

WTBR1 [R/W] B

XXXXXXXX

WTSR [R/W] B

--XXXXXX

PWCD1 [R]

B, H, W

XXXXXXXX

WTBR2 [R/W] B

XXXXXXXX

⎯

PWC0, 1

Real-time clock

⎯⎯⎯⎯Unused

GCN10 [R/W] H

00110010 00010000

⎯

GCN20 [R/W] B

00000000

PPG

⎯⎯Unused

PTMR0 [R] H

11111111 11111111

PDUT0 [W] H

XXXXXXXX XXXXXXXX

PCNH0 [R/W]

00000000

PCSR0 [W] H

XXXXXXXX XXXXXXXX

PCNL0 [R/W]

B, H

B, H

00000000

PPG0

Block

000128

00012C

000130

000134

000138

00013C

000140

000144

H

H

H

H

H

H

H

H

PTMR1 [R] H

11111111 11111111

PDUT1 [W] H

XXXXXXXX XXXXXXXX

PTMR2 [R] H

11111111 11111111

PDUT2 [W] H

XXXXXXXX XXXXXXXX

PTMR3 [R] H

11111111 11111111

PDUT3 [W] H

XXXXXXXX XXXXXXXX

PTMR4 [R] H

11111111 11111111

PDUT4 [W] H

XXXXXXXX XXXXXXXX

PCNH1 [R/W]

00000000

PCNH2 [R/W]

00000000

PCNH3 [R/W]

00000000

PCNH4 [R/W]

00000000

PCSR1 [W] H

XXXXXXXX XXXXXXXX

PCNL1 [R/W]

B, H

B, H

00000000

PCSR2 [W] H

XXXXXXXX XXXXXXXX

PCNL2 [R/W]

B, H

B, H

00000000

PCSR3 [W] H

XXXXXXXX XXXXXXXX

PCNL3 [R/W]

B, H

B, H

00000000

PCSR4 [W] H

XXXXXXXX XXXXXXXX

PCNL4 [R/W]

B, H

B, H

00000000

PPG1

PPG2

PPG3

PPG4

(Continued)

30

MB91230 Series

Address

000148

00014C

000150

to

0001FC

000200

to

0003EC

0003F0

0003F4

0003F8

0003FC

Register

Block

+ 0 + 1 + 2 + 3

H

H

H

PTMR5 [R] H

11111111 11111111

PDUT5 [W] H

XXXXXXXX XXXXXXXX

PCNH5 [R/W]

00000000

PCSR5 [W] H

XXXXXXXX XXXXXXXX

PCNL5 [R/W]

B, H

B, H

00000000

PPG5

⎯⎯⎯⎯Unused

H

H

⎯⎯⎯⎯Unused

H

H

H

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

BSD0 [W] W

BSD1 [R/W] W

Bit search

H

H

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

BSDC [W] W

BSRR [R] W

000400

000404

000408

00040C

000410

to

00041C

000420

000424

000428

00042C

000430

to

00043C

DDR0 [R/W] B

H

H

H

H

H

H

H

H

H

H

H

H

00000000

DDR4 [R/W] B

00000000

DDR8 [R/W] B

00000000

DDRC [R/W] B

00000000

PFR0 [R/W] B

PFR4 [R/W] B

00000000

PFR8 [R/W] B

00000000

PFRC [R/W] B

DDR1 [R/W] B

00000000

DDR5 [R/W] B

00000000

DDR9 [R/W] B

00000000

DDRD [R/W] B

------00

DDR2 [R/W] B

00000000

DDR6 [R/W] B

0000----

DDRA [R/W] B

00000000

⎯

DDR3 [R/W]

B00000000

DDR7 [R/W] B

----0000

DDRB [R/W] B

----0000

DDRF [R/W] B

---00---

Data direction
register

⎯⎯⎯⎯Unused

--00-00-

PFR1 [R/W] B

--------

PFR5 [R/W] B

---00---

PFR2 [R/W] B

-00-0000

PFR6 [R/W] B

0000----

PFR3 [R/W] B

------00

PFR7 [R/W] B

----0000
Port function register

--------

PFR9 [R/W] B

00000000

PFRD [R/W] B

------00

PFRA [R/W] B

00000000

⎯

PFRB [R/W] B

----0000

PFRF [R/W] B

----0---

⎯⎯⎯⎯Unused

(Continued)

31

MB91230 Series

Address

000440

000444

000448

00044C

000450

000454

000458

H

H

H

H

H

H

H

Register

+ 0 + 1 + 2 + 3

ICR00 [R/W]

B, H, W

---11111

ICR04 [R/W]

B, H, W

---11111

ICR08 [R/W]

B, H, W

---11111

ICR12 [R/W]

B, H, W

---11111

ICR16 [R/W]

B, H, W

---11111

ICR20 [R/W]

B, H, W

---11111

ICR24 [R/W]

B, H, W

---11111

ICR01 [R/W]

B, H, W

---11111

ICR05 [R/W]

B, H, W

---11111

ICR09 [R/W]

B, H, W

---11111

ICR13 [R/W]

B, H, W

---11111

ICR17 [R/W]

B, H, W

---11111

ICR21 [R/W]

B, H, W

---11111

ICR25 [R/W]

B, H, W

---11111

ICR02 [R/W]

B, H, W

---11111

ICR06 [R/W]

B, H, W

---11111

ICR10 [R/W]

B, H, W

---11111

ICR14 [R/W]

B, H, W

---11111

ICR18 [R/W]

B, H, W

---11111

ICR22 [R/W]

B, H, W

---11111

ICR26 [R/W]

B, H, W

---11111

Block

ICR03 [R/W]

B, H, W

---11111

ICR07 [R/W]

B, H, W

---11111

ICR11 [R/W]

B, H, W

---11111

ICR15 [R/W]

B, H, W

---11111

ICR19 [R/W]

B, H, W

---11111

ICR23 [R/W]

B, H, W

---11111
Interrupt controller

ICR27 [R/W]

B, H, W

---11111

00045C

000460

000464

000468

00046C

000470

to

00047C

H

H

H

H

H

H

H

ICR28 [R/W]

B, H, W

---11111

ICR32 [R/W]

B, H, W

---11111

ICR36 [R/W]

B, H, W

---11111

ICR40 [R/W]

B, H, W

---11111

ICR44 [R/W]

B, H, W

---11111

ICR29 [R/W]

B, H, W

---11111

ICR33 [R/W]

B, H, W

---11111

ICR37 [R/W]

B, H, W

---11111

ICR41 [R/W]

B, H, W

---11111

ICR45 [R/W]

B, H, W

---11111

ICR30 [R/W]

B, H, W

---11111

ICR34 [R/W]

B, H, W

---11111

ICR38 [R/W]

B, H, W

---11111

ICR42 [R/W]

B, H, W

---11111

ICR46 [R/W]

B, H, W

---11111

ICR31 [R/W]

B, H, W

---11111

ICR35 [R/W]

B, H, W

---11111

ICR39 [R/W]

B, H, W

---11111

ICR43 [R/W]

B, H, W

---11111

ICR47 [R/W]

B, H, W

---11111

⎯⎯⎯⎯Unused

(Continued)

32

(Continued)

Address

MB91230 Series

Register

Block

+ 0 + 1 + 2 + 3

000480

000484

000488

00048C

000490
000494

to

0004FC

000500
000504

to

00051C

000520

to

0007F8

RSRR [R/W]

H

10000000

CLKR [R/W]

H

00000000

H

WPCR [R/W] B

H

OSCR [R/W] B

H

H

H

H

H

H

H

H

STCR [R/W]

B, H

B, H

00110011

WPR [R/W]

B

B

XXXXXXXX

⎯⎯

00---000

00---000

⎯⎯⎯Watch timer

⎯⎯⎯

TBCR [R/W]

B

00XXXX00

DIVR0 [R/W]

B, H

00000011

OSCCR [R/W] B

XXXXXXX0

CTBR [W]

B

XXXXXXXX

DIVR1 [R/W]

B, H

00000000

⎯

⎯⎯⎯⎯Unused

⎯

PCR1 [R/W] B

00000000

⎯

PCR3 [R/W] B

00000000

⎯⎯⎯⎯Unused

⎯⎯⎯⎯Unused

Clock control

Main clock oscillation
stabilization wait timer

Pull-up control
register

0007FC

000800

to

000AFC

000B00

to

000FFC

001000

to

006FFC

007000

007004
007008

to

00FFFC

H

H

H

H

H

H

H

FLCR [R/W] B

H

FLWC [R/W] B

H

H

H

⎯

⎯⎯⎯⎯Unused

⎯⎯⎯⎯Unused

⎯⎯⎯⎯Unused

01101000

00000011

⎯⎯⎯⎯Unused

MODR*

XXXXXXXX

⎯⎯Operation mode

⎯⎯⎯

⎯⎯⎯

* : This register is set when the mode vector is fetched. Not user-accessible.

FLASH

33

MB91230 Series

INTERRUPT VECTOR

■

Interrupt source

Interrupt level Offset

10 16

Reset 0 00 ⎯ 3FC
Mode vector 1 01 ⎯ 3F8
System reserved 2 02 ⎯ 3F4
System reserved 3 03 ⎯ 3F0
System reserved 4 04 ⎯ 3EC
System reserved 5 05 ⎯ 3E8
System reserved 6 06 ⎯ 3E4
Coprocessor absent trap 7 07 ⎯ 3E0
Coprocessor error trap 8 08 ⎯ 3DC
INTE instruction 9 09 ⎯ 3D8
Instruction break exception 10 0A ⎯ 3D4
Operand break trap 11 0B ⎯ 3C0
Step trace trap 12 0C ⎯ 3CC
NMI request (tool) 13 0D ⎯ 3C8
Undefined instruction exception 14 0E ⎯ 3C4

Interrupt number

NMI request
(This model has no NMI request)

15 0F 15 (F

) fixed 3C0

H

TBR default

address

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

000FFFFC

000FFFF8
000FFFF4

000FFFF0
000FFFEC
000FFFE8
000FFFE4
000FFFE0
000FFFDC
000FFFD8
000FFFD4
000FFFD0
000FFFCC
000FFFC8
000FFFC4

000FFFC0

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

External interrupt 0 16 10 ICR00 3BC
External interrupt 1 17 11 ICR01 3B8
External interrupt 2 18 12 ICR02 3B4
External interrupt 3 19 13 ICR03 3B0
External interrupt 4 20 14 ICR04 3AC
External interrupt 5 21 15 ICR05 3A8
External interrupt 6 22 16 ICR06 3A4
External interrupt 7 23 17 ICR07 3A0
Reload timer 0 24 18 ICR08 39C
Reload timer 1 25 19 ICR09 398
Reload timer 2 26 1A ICR10 394
UART0(Reception completed) 27 1B ICR11 390
UART0 (Transmission completed) 28 1C ICR12 38C
UART1 (Reception completed) 29 1D ICR13 388
UART1 (Transmission completed) 30 1E ICR14 384
UART2 (Reception completed) 31 1F ICR15 380
UART2 (Transmission completed) 32 20 ICR16 37C

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

000FFFBC
000FFFB8
000FFFB4
000FFFB0
000FFFAC
000FFFA8
000FFFA4
000FFFA0
000FFF9C

000FFF98

000FFF94

000FFF90
000FFF8C

000FFF88

000FFF84

000FFF80
000FFF7C

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

34

(Continued)

MB91230 Series

Interrupt source

Interrupt level Offset

10 16

UART3 (Reception completed) 33 21 ICR17 378
UART3 (Transmission completed) 34 22 ICR18 374
A/D ch0 35 23 ICR19 370
A/D ch1 36 24 ICR20 36C
External interrupt8 37 25 ICR21 368
External interrupt9 38 26 ICR22 364
External interrupt 10 39 27 ICR23 360
External interrupt 11 40 28 ICR24 35C
External interrupt 12 41 29 ICR25 358
External interrupt 13 42 2A ICR26 354
External interrupt 14 43 2B ICR27 350
External interrupt 15 44 2C ICR28 34C
Real-time clock 45 2D ICR29 348

Interrupt number

Main clock oscillation
stabilization wait timer

46 2E ICR30 344

Timebase timer 47 2F ICR31 340

TBR default

address

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

000FFF78
000FFF74
000FFF70

000FFF6C

000FFF68
000FFF64
000FFF60

000FFF5C

000FFF58
000FFF54
000FFF50

000FFF4C

000FFF48
000FFF44
000FFF40

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

Reload timer 3 48 30 ICR32 33C
Watch timer 49 31 ICR33 338
UD Counter 0 50 32 ICR34 334
UD Counter 1 51 33 ICR35 330
PPG 0/1 52 34 ICR36 32C
PPG 2/3 53 35 ICR37 328
PPG 4/5 54 36 ICR38 324
Free-run timer 0 55 37 ICR39 320
Free-run timer 1 56 38 ICR40 31C
ICU 0 (capture) 57 39 ICR41 318
ICU 1 (capture) 58 3A ICR42 314
OCU 0 (match) 59 3B ICR43 310
OCU 1 (match) 60 3C ICR44 30C
OCU 2 (match) 61 3D ICR45 308
OCU 3 (match) 62 3E ICR46 304
Delay interrupt source bit 63 3F ICR47 300
System reserved (Used by REALOS) 64 40 ⎯ 2FC
System reserved (Used by REALOS) 65 41 ⎯ 2F8

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

000FFF3C

000FFF38
000FFF34
000FFF30

000FFF2C

000FFF28
000FFF24
000FFF20

000FFF1C

000FFF18
000FFF14
000FFF10

000FFF0C

000FFF08
000FFF04

000FFF00
000FFEFC
000FFEF8

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

System reserved 66 42 ⎯ 2F4

H

000FFEF4

H

(Continued)

35

MB91230 Series

(Continued)

Interrupt source

Interrupt number

10 16

Interrupt level Offset

TBR default

address

System reserved 67 43 ⎯ 2F0
System reserved 68 44 ⎯ 2EC
System reserved 69 45 ⎯ 2E8
System reserved 70 46 ⎯ 2E4
System reserved 71 47 ⎯ 2E0
System reserved 72 48 ⎯ 2DC
System reserved 73 49 ⎯ 2D8
System reserved 74 4A ⎯ 2D4
System reserved 75 4B ⎯ 2D0
System reserved 76 4C ⎯ 2CC
System reserved 77 4D ⎯ 2C8
System reserved 78 4E ⎯ 2C4
System reserved 79 4F ⎯ 2C0

Used by INT instruction

80
to

255

50
to

FF

⎯

2BC

to

000

H

H

H

H

H

H

H

H

H

H

H

H

H

H

000FFEF0

000FFEEC

000FFEE8
000FFEE4

000FFEE0
000FFEDC
000FFED8
000FFED4
000FFED0
000FFECC
000FFEC8
000FFEC4
000FFEC0
000FFEBC

H

H

H

H

H

H

H

H

H

H

H

H

H

H

to

H

000FFC00

H

36

MB91230 Series

PIN STATUS IN EACH CPU STATE

■

Terms used as the status of pins mean as follows.

• Input enabled
Indicates that the input function can be used.

• Input 0 fixed
Indicates that the input level has been internally fix ed to be “0” to pre vent leakage when the input is released.

• Output Hi-Z
Means the placing of a pin in a high impedance state by prev enting the transistor for driving the pin from driving.

• Output is maintained
Indicates the output in the output state existing immediately before this mode is established. If the device
enters this mode with an internal output peripheral operating or while serving as an output port, the output is
performed by the internal peripheral or the port output is maintained, respectively.

• State existing immediately before is maintained
When the device serves for output or input immediately before entering this mode, the device maintains the
output or is ready for the input, respectively.

37

MB91230 Series

• Pin Status List

Specified function

Pin

no.

1

2

3

4

5

Pin

name

P26/
SCK2

P27/
SIN3

P30/
SOT3

P31/
SCK3

P32/
AIN0

Port

name

P26 ⎯⎯SCK2 P26

P27 SIN3 ⎯⎯P27

P30 ⎯ SOT3 ⎯ P30

P31 ⎯⎯SCK3 P31

P32 AIN0 ⎯⎯P32

name

Input Output

Input/

Output

At initializing

Function

name

initializa-

Reset

tion

At sleep

mode

At Stop mode

Remarks

HIZ = 0 HIZ = 1

Pull-up
options
can be
selected

Pull-up
options
can be
selected

Pull-up
options
can be
selected

10

11

6

7

8

9

P33/
BIN0

P34/
ZIN0

P35/
AIN1

P36/
BIN1

P37/
ZIN1

P40/
PPG0

P33 BIN0 ⎯⎯P33

P34 ZIN0 ⎯⎯P34

P35 AIN1 ⎯⎯P35

P36 BIN1 ⎯⎯P36

P37 ZIN1 ⎯⎯P37

P40 ⎯

PPG
0

⎯ P40

Output
Hi-Z/
Input
enabled

Retention
of the
immediately
prior state

Retention
of the
immediately
prior state

Output
Hi-Z/
Input 0
fixed

Pull-up
options
can be
selected

Pull-up
options
can be
selected

Pull-up
options
can be
selected

Pull-up
options
can be
selected

Pull-up
options
can be
selected

38

12

P41/
PPG1

P41 ⎯

PPG
1

⎯ P41

(Continued)

MB91230 Series

Pin
no.

Pin

name

Port

name

Specified function

name

Input Output

Input/

Output

At initializing

Function

name

initialization

Reset

At sleep

mode

At Stop mode

HIZ = 0 HIZ = 1

13 X0A ⎯⎯⎯⎯ ⎯ ⎯ ⎯ ⎯ ⎯
14 X1A ⎯⎯⎯⎯ ⎯ ⎯ ⎯ ⎯ ⎯
15 V
16 V
17 V

18

19

20

21

22

23

3B ⎯⎯⎯⎯ ⎯ ⎯ ⎯ ⎯ ⎯

CC

SS

3 ⎯⎯⎯⎯ ⎯ ⎯ ⎯ ⎯ ⎯

CC

P42/
PPG2

P43/
PPG3

P44/
TOT0

P45/
TOT1

P46/
TOT2

P47/
CKOT

⎯⎯⎯⎯ ⎯ ⎯ ⎯ ⎯ ⎯

P42 ⎯ PPG2 ⎯ P42

P43 ⎯ PPG3 ⎯ P43

P44 ⎯ TOT0 ⎯ P44

P45 ⎯ TOT1 ⎯ P45

Retention
of the
immediately
prior state

Output
Hi-Z/
Input 0
fixed

P46 ⎯ TOT2 ⎯ P46

P47 ⎯ CKOT ⎯ P47

Remarks

P50/

24

25

26

INT8
P51/

INT9
P52/

INT10

P50 INT8 ⎯⎯P50

P51 INT9 ⎯⎯P51

P52 INT10 ⎯⎯P52

P53/

27

INT11/

P53 INT11 PPG4 ⎯ P53

PPG4
P54/

28

INT12/

P54 INT12 PPG5 ⎯ P54

PPG5

29

30

P55/
INT13/
TIN2

P56/
INT14/
TIN1

P55

P56

INT13
TIN2

INT14
TIN1

⎯⎯P55

⎯⎯P56

Note : P : Port selected, F : Specified function selected

Output
Hi-Z/
Input
enabled

Retention
of the
immediately
prior state

P :

Retention
of the
immediately
prior state

F :

Input
enabled

P :

Output
Hi-Z

F :

Input
enabled

(Continued)

39

MB91230 Series

Pin
no.

31

32

33

34

35

Pin

name

P57/
INT15/
TIN0/
ADTG0

PF3/
TOT3

PF4/
TIN3/
ADTG1

PD0/
DA0

PD1/
DA1

Specified function

Port

name

name

Input Output

Input/

Output

Function

name

INT15

P57

TIN0

⎯⎯P57

ADTG0

PF3 ⎯ TOT3 ⎯ PF3

PF4

TIN3
ADTG1

⎯⎯PF4

PD0 ⎯ DA0 ⎯ PD0

PD1 ⎯ DA1 ⎯ PD1

At initializing

Reset

initialization

Output
Hi-Z/
Input
enabled

At sleep

mode

Retention
of the
immediately
prior state

At Stop mode

HIZ = 0 HIZ = 1

P :

Retention
of the
immediately
prior state

F :

Input
enabled

Retention
of the
immediately
prior state

Re-

marks

P :
Output
Hi-Z

F :
Input 0
enabled

Output
Hi-Z/
Input 0
fixed

36 AV

CC

⎯⎯⎯⎯⎯ ⎯ ⎯ ⎯ ⎯

37 AVRH ⎯⎯⎯⎯⎯ ⎯ ⎯ ⎯ ⎯
38 AV

PC0/

39

AN0
PC1/

40

AN1
PC2/

41

AN2
PC3/

42

AN3
PC4/

43

AN4
PC5/

44

AN5
PC6/

45

AN6
PC7/

46

AN7

SS

⎯⎯⎯⎯⎯ ⎯ ⎯ ⎯ ⎯

PC0 AN0 ⎯⎯PC0

PC1 AN1 ⎯⎯PC1

Output
Hi-Z/
Input
enabled

Retention
of the
immediately
prior state

Retention
of the
immediately
prior state

Output
Hi-Z/
Input 0
fixed

PC2 AN2 ⎯⎯PC2

PC3 AN3 ⎯⎯PC3

PC4 AN4 ⎯⎯PC4

PC5 AN5 ⎯⎯PC5

Output
Hi-Z/
Input
enabled

Retention
of the
immediately
prior state

Retention
of the
immediately
prior state

Output
Hi-Z/
Input 0
fixed

PC6 AN6 ⎯⎯PC6

PC7 AN7 ⎯⎯PC7

Note : P : Port selected, F : Specified function selected

(Continued)

40

MB91230 Series

Pin
no.

47 V
48 V

49

50

51

52

53

54

55

56

57

58

Specified function

Pin

name

SS

CC

P80/
SEG0

P81/
SEG1

P82/
SEG2

P83/
SEG3

P84/
SEG4

P85/
SEG5

P86/
SEG6

P87/
SEG7

P90/
SEG8

P91/
SEG9

Port

name

Input Output

⎯⎯⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯

3IO ⎯⎯⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯

P80 ⎯ SEG0 ⎯ P80

P81 ⎯ SEG1 ⎯ P81

P82 ⎯ SEG2 ⎯ P82

P83 ⎯ SEG3 ⎯ P83

P84 ⎯ SEG4 ⎯ P84

P85 ⎯ SEG5 ⎯ P85

P86 ⎯ SEG6 ⎯ P86

P87 ⎯ SEG7 ⎯ P87

P90 ⎯ SEG8 ⎯ P90

P91 ⎯ SEG9 ⎯ P91

name

Input/

Output

At initializing

Function

name

initialization

Output
Hi-Z/
Input
enabled

Reset

At sleep

mode

Retention
of the
immediately
prior state

At Stop mode

HIZ = 0HIZ = 1

P :

Output
Hi-Z/

Retention
of the
immediately
prior state

Input 0
fixed

F :

Retention
of the
immediately
prior state

Re-

marks

P92/

59

60

61

62

63

SEG10
P93/

SEG11
P94/

SEG12
P95/

SEG13
P96/

SEG14

P92 ⎯ SEG10 ⎯ P92

P93 ⎯ SEG11 ⎯ P93

P94 ⎯ SEG12 ⎯ P94

P95 ⎯ SEG13 ⎯ P95

P96 ⎯ SEG14 ⎯ P96

Note : P : Port selected, F : Specified function selected

(Continued)

41

MB91230 Series

Pin
no.

64

65

66

67

68

69

70

71

72

Pin

name

P97/
SEG15

PA0/
SEG16

PA1/
SEG17

PA2/
SEG18

PA3/
SEG19

PA4/
SEG20

PA5/
SEG21

PA6/
SEG22

PA7/
SEG23

Specified function

Port

name

Input Output

name

Input/

Output

Function

name

P97 ⎯ SEG15 ⎯ P97

PA0 ⎯ SEG16 ⎯ PA0

PA1 ⎯ SEG17 ⎯ PA1

PA2 ⎯ SEG18 ⎯ PA2

PA3 ⎯ SEG19 ⎯ PA3

PA4 ⎯ SEG20 ⎯ PA4

PA5 ⎯ SEG21 ⎯ PA5

PA6 ⎯ SEG22 ⎯ PA6

PA7 ⎯ SEG23 ⎯ PA7

At initializing

Reset

initialization

Output
Hi-Z/
Input
enabled

At sleep

mode

Retention
of the
immediately
prior state

At Stop mode

HIZ = 0HIZ = 1

P :

Output
Hi-Z/

Retention

Input 0 fixed
of the
immediately
prior state

F :

Retention

of the

immediately

prior state

Re-

marks

PB0/

73

74
75 V

76 V
77

78

SEG24
PB1/

SEG25

CC

SS

PB2/
SEG26

PB3/
SEG27

PB0 ⎯ SEG24 ⎯ PB0

PB1 ⎯ SEG25

⎯ PB1

⎯⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
⎯⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯

PB2 ⎯ SEG26 ⎯ PB2

PB3 ⎯ SEG27 ⎯ PB3

Output
Hi-Z/
Input
enabled

79

P64/
SEG28

P64 ⎯ SEG28 ⎯ P64

Note : P : Port selected, F : Specified function selected

Retention
of the
immediately
prior state

Retention
of the
immediately
prior state

P :

Output
Hi-Z/
Input 0
fixed

F :

Retention
of the
immediately
prior state

open­drain
pin,

=

I

OL

20 mA

(Continued)

42

MB91230 Series

Pin
no.

80

81

82

83

84

Pin

name

P65/
SEG29

P66/
SEG30

P67/
SEG31

P70/
COM0

P71/
COM1

Specified function

Port

name

Input Output

name

Input/

Output

Function

name

P65 ⎯ SEG29 ⎯ P65

P66 ⎯ SEG30 ⎯ P66

P67 ⎯ SEG31 ⎯ P67

P70 ⎯ COM0 ⎯ P70

P71 ⎯ COM1 ⎯ P71

At initializing

Reset

initialization

Output
Hi-Z/
Input
enabled

At sleep

mode

Retention
of the
immediately
prior state

At Stop mode

HIZ = 0 HIZ = 1

P :

Output

Hi-Z/

Retention

Input 0 fixed

of the
immediately
prior state

F :

Retention

of the

immediately

prior state

Re-

marks

open­drain
pin,
I

=

OL

20 mA
open-

drain
pin,
I

=

OL

20 mA
open-

drain
pin,
I

=

OL

20 mA

P72/

85

86

COM2
P73/

COM3

P72 ⎯ COM2 ⎯ P72

P73 ⎯ COM3 ⎯ P73

87 MD2 ⎯⎯⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
88 MD1 ⎯⎯⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
89 MD0 ⎯⎯⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
90 INIT

⎯⎯⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯

91 V0 ⎯⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
92 V1 ⎯⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
93 V2 ⎯⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
94 V3 ⎯⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯

Note : P : Port selected, F : Specified function selected

(Continued)

43

MB91230 Series

Pin
no.

95

96

97

98

99

100

101

102

103

104

105 V

Pin

name

P00/
SIN0

P01/
SOT0

P02/
SCK0

P03/
SIN1

P04/
SOT1

P05/
SCK1

P06/
IC0

P07/
IC1

P10/
INT0

P11/
INT1

CC

Port

name

Specified function

name

Input Output

Input/

Output

At initializing

Function

name

initialization

Reset

At sleep

mode

At Stop mode

HIZ = 0 HIZ = 1

P00 SIN0 ⎯⎯P00

P01 ⎯ SOT0 ⎯ P01

P02 ⎯⎯SCK0 P02

P03 SIN1 ⎯⎯P03

P04 ⎯ SOT1 ⎯ P04

P05 ⎯⎯SCK1 P05

P06 IC0 ⎯⎯P06

Output
Hi-Z/
Input
enabled

Retention
of the
immediately
prior state

Retention
of the
immediately
prior state

Output
Hi-Z/
Input 0
fixed

P07 IC1 ⎯⎯P07

P :

P10 INT0 ⎯⎯P10

P11 INT1 ⎯⎯P11

Retention
of the
immediately
prior state

F : Input

P : Output

Hi-Z

F : Input

enabled

enabled

⎯⎯⎯⎯ ⎯ ⎯ ⎯ ⎯ ⎯

Remarks

Pull-up
options
can be
selected

Pull-up
options
can be
selected

106 V

SS

⎯⎯⎯⎯ ⎯ ⎯ ⎯ ⎯ ⎯

107 X1 ⎯⎯⎯⎯ ⎯ ⎯ ⎯ ⎯ ⎯
108 X0 ⎯⎯⎯⎯ ⎯ ⎯ ⎯ ⎯ ⎯

Note : P : Port selected, F : Specified function selected

44

(Continued)

(Continued)

Pin

Pin

no.

name

P12/

109

INT2

P13/

110

INT3

P14/

111

INT4

P15/

112

INT5

P16/

113

INT6

P17/

114

INT7

P20/

115

CKI0/
OP0

Specified function

Port

name

name

Input Output

Input/

Output

Function

name

P12 INT2 ⎯⎯P12

P13 INT3 ⎯⎯P13

P14 INT4 ⎯⎯P14

P15 INT5 ⎯⎯P15

P16 INT6 ⎯⎯P16

P17 INT7 ⎯⎯P17

P20 CKI0 OP0 ⎯ P20

At initializing

Reset

initialization

Output
Hi-Z/
Input
enabled

At sleep

mode

Retention
of the
immediately
prior state

MB91230 Series

At Stop mode

Remarks

HIZ = 0 HIZ = 1

Pull-up
options
can be
selected

Pull-up
options
can be
selected

P :

Retention
of the
immediately
prior state

F :

Input
enabled

P :

Output
Hi-Z

F :

Input
enabled

Pull-up
options
can be
selected

Pull-up
options
can be
selected

Pull-up
options
can be
selected

Pull-up
options
can be
selected

P21/

116

CKI1/

P21 CKI1 OP1 ⎯ P21

OP1
P22/

117

PWI0/

P22 PWI0 OP2 ⎯ P22

OP2
P23/

118

PWI1/

P23 PWI1 OP3 ⎯ P23

OP3
P24/

119

120

SIN2
P25/

SOT2

P24 SIN2 ⎯⎯P24

P25 ⎯ SOT2 ⎯ P25

Note : P : Port selected, F : Specified function selected

Retention
of the
immediately
prior state

Output
Hi-Z/
Input 0
fixed

45

MB91230 Series

ELECTRICAL CHARACTERISTICS

■

1. Absolute Maximum Ratings

MB91V230, MB91F233A

Parameter Symbol

Rating

Unit Remarks

Min Max

V

Power supply voltage*

V

V

CC

Analog power supply voltage* AV
Input voltage* V
Input voltage* (open-drain) V
Analog pin input voltage* V
Output voltage* V

CC

3V

CC

3IO V

CC

I

IND

IA

O

V

−0.5 V

SS

−0.5 V

SS

−0.5 V

SS

V

−0.5 V

SS

V

−0.5 V

SS

V

−0.5 V

SS

V

−0.5 AV

SS

V

−0.5 V

SS

+ 6.0 V

SS

+ 4.0 V

SS

+ 4.0 V

SS

+ 4.0 V

SS

+ 0.5 V

CC

+ 0.5 V

CC

+ 0.5 V

CC

+ 0.5 V

CC

Operating ambient temperature Ta −40 + 85 °C
Storage temperature Tstg −55 + 125 °C

= AVSS = 0.0 V.

* : This parameter is based on V

SS

MB91F233L, MB91233L

Rating

Parameter Symbol

Unit Remarks

Min Max

V

Power supply voltage*

V

V

CC

Analog power supply voltage* AV

CC

3V

CC

3IO V

CC

V

−0.5 V

SS

−0.5 V

SS

−0.5 V

SS

V

−0.5 V

SS

+ 4.0 V

SS

+ 4.0 V

SS

+ 4.0 V

SS

+ 4.0 V

SS

Input voltage* V
Input voltage* (open-drain) V
Analog pin input voltage* V
Output voltage* V

I

IND

IA

O

V

−0.5 V

SS

V

−0.5 V

SS

V

−0.5 AV

SS

V

−0.5 V

SS

+ 0.5 V

CC

+ 0.5 V

CC

+ 0.5 V

CC

+ 0.5 V

CC

Operating ambient temperature Ta −40 + 85 °C
Storage temperature Tstg −55 + 125 °C

= AVSS = 0.0 V.

* : This parameter is based on V

SS

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

46

MB91230 Series

2. Recommended Operating Conditions

MB91V230, MB91F233A

Parameter Symbol

Min Max

Operating ambient temperature Ta −40 + 85 °C

Value

Unit Remarks

(V

= AVSS = 0.0 V)

SS

Power supply voltage

V

CC

3 3.00 3.60 V *4

V

CC

3B

CC

V

4.00 5.25 V *1

3.00 3.60 V

2.20 3.60 V *2

3IO 3.00 3.60 V

CC

V

Analog power supply voltage AV

CC

3.00 3.60 V

LCD reference voltage V3 ⎯ 5.25 V *3

MB91F233L, MB91233L

(V

= AVSS = 0.0 V)

SS

Value

Parameter Symbol

Unit Remarks

Min Max

Operating ambient temperature Ta −40 + 85 °C

Power supply voltage

V

CC

V

33.00 3.60V*4

CC

3B

CC

V

3.00 3.60 V *1

3.00 3.60 V

2.20 3.60 V *2

V

3IO 3.00 3.60 V

CC

Analog power supply voltage AV

CC

3.00 3.60 V

LCD reference voltage V3 ⎯ 3.60 V *3

*1 : The standard power-supply voltage varies with the model of product.
*2 : Only for backup. Set V
*3 : V3 must not exceed V
*4 : For the relationships between V

3 = AVCC = VCC3IO.

CC

.

CC

3 and operating frequencies, see section “4. A C Characteristics (3) Operation

CC

Assurance Range”.
For the MB91V230, please inquire separately.

Note : For normal use, set V

3 = VCC3B = AVCC = VCC3IO.

CC

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

47

MB91230 Series

3. DC Characteristics

MB91V230, MB91F233A

(V

= 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C)

CC

Parameter Symbol Pin name Conditions

FLASH model normal
operation,
Ta = +25 °C,
F

= 33 MHz,

CP

F

= 16.5 MHz

I

CC

CPP

FLASH model normal
operation,
Ta = +25 °C,
F

= 33 MHz,

CP

F

= 33 MHz

CPP

Power supply
current

I

CCT

VCC3

RTC mode,
Ta = +25 °C,
F

= 32 kHz

CP

Value

Unit Remarks

Min Typ Max

⎯ 65 75 mA

⎯ 73 83 mA

⎯ 20 50 µA

Watch timer,
RTC, LCDC

3 = VCC3B =

V

CC

2.4 V

"H" level input
voltage

“L” level input
voltage

"H" level output
voltage

"L" level output
voltage

I

I

V

V

CCH

CCS

V

V

IH

IL

OH

OL

STOP mode,
Ta = +25 °C,
F

= 0 kHz

CP

SLEEP mode
F

= 33 MHz,

CP

F

= 16.5 MHz

CPP

SLEEP mode
F

= 33 MHz,

CP

F

= 33 MHz

CPP

⎯⎯

X0A V

3B = 2.2 V to 3.6 V

CC

⎯⎯V

X0A V

⎯ I
⎯ I

P64 to P67 I

3B = 2.2 V to 3.6 V V

CC

= −4 mA

OH

= 4 mA

OL

= 20 mA

OL

⎯ 550µA

⎯ 21 25 mA

⎯ 30 35 mA

×

V

CC

0.8

V

CC

B ×

3

⎯ V

⎯ V

CC

3B V

CC

0.8
V

SS

SS

V

CC

−0.5

SS

V

⎯

⎯

⎯ V

⎯ 0.4 V

CC

× 0.2

V

SS

+ 0.4

CC

V

When external
clock is used

V

When external

V

clock is used

V

Input leakage
current

Open-drain output
leakage current

48

I

IL

⎯⎯−5 ⎯ 5 µA

Ileak ⎯⎯−10 ⎯ 10 µA

(Continued)

MB91230 Series

(Continued)

(V

= 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C)

CC

Parameter Symbol Pin name Conditions

Min Typ Max

Value

Unit Remarks

LCD internal
division resistance

COM0 to COM3
output impedance

SEG00 to SEG31
output impedance

LCDC leakage
current

R

R

R

I

LCD

VCOM

VSEG

LCDC

V0 - V1,
V1 - V2,

V2 - V3

COM0 to

COM3

SEG00 to

SEG31

V0 to V3,

COM0 to

COM3,

SEG00 to

SEG31

⎯ 50 100 200 kΩ

⎯⎯2.5 kΩ

V1 to V3 = 5.0 V

⎯⎯15 kΩ

⎯−5 ⎯ 5 µA

49

MB91230 Series

MB91F233L, MB91233L

(V

= VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C)

CC

Parameter Symbol

Power supply
current

"H" level input
voltage

"L" level input
voltage

"H" level output
voltage

I

I

I

I

I

V

V

V

CC

CC

CCT

CCH

CCS

IH

IL

OH

Pin

name

Vcc3

X0A V

X0A V

Conditions

Min Typ Max

FLASH model normal
operation,
Ta = +25 °C,
F

= 33 MHz,

CP

F

= 16.5 MHz

CPP

FLASH model normal
operation,
Ta = +25 °C,

= 33 MHz,

CP

F
F

= 33 MHz

CPP

ROM model normal
operation,
Ta = +25 °C,
F

= 33 MHz,

CP

F

= 16.5 MHz

CPP

ROM model normal
operation,
Ta = +25 °C,

= 33 MHz,

CP

F
F

= 33 MHz

CPP

RTC mode,
Ta = +25 °C,
F

= 32 kHz

CP

STOP mode,
Ta = +25 °C,
F

= 0 MHz

CP

SLEEP mode
F

= 33 MHz,

CP

F

= 16.5 MHz

CPP

SLEEP mode

= 33 MHz,

CP

F
F

= 33 MHz

CPP

⎯⎯

3B = 2.2 V to 3.6 V

CC

V

× 0.8

V

× 0.8

⎯⎯V

3B = 2.2 V to 3.6 V V

CC

⎯

= 3.3 V,

V

CC

I

= −2 mA

OH

V

−0.5

Value

Unit Remarks

⎯ 65 75 mA

⎯ 73 83 mA

⎯ 45 55 mA

⎯ 55 65 mA

⎯ 20 50 µA

⎯ 550µA

⎯ 21 25 mA

⎯ 30 35 mA

CC

CC

3B

SS

SS

CC

⎯ V

⎯ V

⎯

× 0.15

⎯

+ 0.4

⎯ V

CC

3B V

CC

V

CC

V

SS

CC

Watch timer,
RTC, LCDC

3 = VCC3B =

V

CC

2.4 V

V

When external
clock is used

V

When external

V

clock is used

V

50

(Continued)

(Continued)

(V

Parameter Symbol

"L" level output
voltage

Input leakage
current

Open-drain output
leakage current

LCD internal
division resistance

COM0 to COM3
output impedance

SEG00 to SEG31
output impedance

LCDC leakage
current

MB91230 Series

= VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C)

CC

Pin

name

OL

V

IL

I

⎯ I

P64 to 67 I

⎯⎯−5 ⎯ 5 µA

Conditions

= 2 mA

OL

= 10 mA

OL

Min Typ Max

V

Ileak ⎯⎯−10 ⎯ 10 µA

V0 - V1,

R

LCD

V1 - V2,

⎯ 50 100 200 kΩ

V2 - V3

R

R

VCOM

VSEG

COM0 to

COM3

SEG00 to

SEG31

V1 to V3 = 5.0 V

V0 to V3,

COM0 to

I

LCDC

COM3,

⎯−5 ⎯−5 µA

SEG00 to

SEG31

Value

SS

⎯ 0.4 V

Unit Remarks

⎯⎯2.5 kΩ

⎯⎯15 kΩ

51

MB91230 Series

X

3

4. AC Characteristics

(1) Main clock input standard

(MB91V230, MB91F233A : V

(MB91F233L, MB91233L : V

Parameter

= 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,

CC

Sym-

bol

Pin

name

Ta = −40 °C to +85 °C)

= VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,

CC

Ta = −40 °C to +85 °C)

Condi-

tions

Min Typ Max

Value

Unit Remarks

Input frequency F
Input clock cycle t

CYL

Input clock pulse width ⎯
Input clock rise time

and fall time
Internal operating

clock frequency
Internal operating

clock cycle time
Peripheral clock

frequency
Peripheral clock cycle

time

0

F

F

t

CYCP

0.8 × V

t
t

t

C

⎯ 3.6 4 4.2 MHz
⎯⎯250 ⎯ ns

P

WH/tCYL

PWL/t

CYL

40 ⎯ 60 %

⎯⎯⎯5 ns At external clock

CR
CF

CP

CP

CPP

X0

⎯⎯ ⎯⎯33.6 MHz

⎯⎯29.7 ⎯⎯ns

⎯⎯ ⎯⎯33.6 MHz

⎯⎯29.7 ⎯⎯ns

tCYL

CC3 0.8 × VCC3

SS + 0.4 VSS + 0.4

V

0.8 × V

Peripheral clock
is derived from
internal operat­ing clock divided
by 1/1 to 1/16.

CC

PWH PWL

tCF tCR

52

(2) Subclock input standard

X

B

(MB91V230, MB91F233A : V

(MB91F233L, MB91233L : V

Parameter

Input frequency F

Sym-

bol

CL

MB91230 Series

= 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,

CC

Ta = −40 °C to +85 °C)

= VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,

CC

Ta = −40 °C to +85 °C)

Pin

name

Condi-

tions

⎯

Min Typ Max

⎯ 32.768 ⎯

28.571 32.768 35.714

Value

Unit Remarks

kHz

At external

clock

Input clock cycle t

LCYL

Input clock pulse width ⎯
Input clock rise time

and fall time

0A

⎯

CC3B 0.8 × VCC3B

0.8 × V

X0A

⎯ 28.0 ⎯ 35.0 µs

P

WLH/tLCYL

P

WLL/tLCYL

t

CR/tLCYL

tCF/t

LCYL

tLCYL

PWLH PWLL

tCF tCR

45 ⎯ 55 %

⎯⎯ 5 %

0.8 × V

SS + 0.4 VSS + 0.4

V

At external

clock

CC3

53

MB91230 Series

4

3

3

3

3

3

2

2

2

2

2

1

(3) Operation Assurance Range

.0

.8

.6

F

CP = 33.6 MHz,VCC3 = 3.6 V

3 [V]

CC

.4

.2

.0

.8

.6

.4

.2

Internal power supply voltage V

.0

.8

F

CP = 8 MHz

FCP = 32 MHz,
V

PLL OFF

32 kHz5 10152025303540

PLL ON

F

CP = 28 MHz,VCC3 = 2.7 V

CC3 = 3.0 V

CP = 33.6 MHz,VCC3 = 3.3 V

F

CP = 33.6 MHz,VCC3 = 3.0 V

F

MB91F233A
MB91F233L

MB91233L

Internal operation frequency FCP [MHz]

54

(4) PLL oscillation stabilization time (LOCK UP time)

I

(MB91V230, MB91F233A : V

(MB91F233L, MB91233L : V

= 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,

CC

= VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,

CC

Value

Parameter Symbol

Min Max

MB91230 Series

Ta = −40 °C to + 85 °C)
Ta = −40 °C to + 85 °C)

Unit Remarks

PLL oscillation stabilization
(LOCK UP time)

t

LOCK

(5) Reset input standards

(MB91V230, MB91F233A : V

= 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,

CC

(MB91F233L, MB91233L : V

Parameter Symbol

INIT

input time

(at power-on)

INITX

INIT

input time

t

(other than at power-on)

*1 : When turning the power on, keep INIT
*2 : t

indicates cycle time of CPU operating clock.

CP

Time from when the PLL

500 ⎯µs

starts operating to when its
oscillation becomes stable

Ta = −40 °C to + 85 °C)

= VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,

CC

Ta = −40 °C to + 85 °C)

Pin

name

Condi-

tions

Value

Unit Remarks

Min Max

⎯⎯ns *1

INIT

⎯

t

× 10 ⎯ ns *2

CP

input until the oscillation circuit provides stable oscillation.

t

INITX

NIT

V

IL

V

IL

55

MB91230 Series

(6)UART timing

(MB91V230, MB91F233A : V

(MB91F233L, MB91233L : V

Parameter Symbol Pin name Conditions

Serial clock cycle time t

= 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,

CC

SCYC

Ta = −40 °C to +85 °C)

= VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,

CC

Ta = −40 °C to +85 °C)

Value

Unit Remarks

Min Max

SCK0 to SCK3

t

* × 8 ⎯ ns

CYCP

SCK ↓ → SOT delay time t

SLOV

SCK0 to SCK3,

SOT0 to SOT3

Internal shift clock

Valid SIN → SCK ↑ t

SCK ↑ → Valid SIN hold time t
Serial clock “H” pulse width t

Serial clock “L” pulse width t
SCK ↓ → SOT delay time t

Valid SIN → SCK ↑ t

SCK ↑ → Valid SIN hold time t

* : t

represents the cycle time of peripheral operating clock.

CYCP

IVSH

SHIX

SHSL

SLSH

SLOV

IVSH

SHIX

SCK0 to SCK3,

SIN0 to SIN3

SCK0 to SCK3,

SIN0 to SIN3
SCK0 to SCK3
SCK0 to SCK3 t

SCK0 to SCK3,

SOT0 to SOT3

SCK0 to SCK3,

SIN0 to SIN3

SCK0 to SCK3,

SIN0 to SIN3

operation

External shift clock
operation

Note : The above specification applies to clock synchronous mode operation.

−80 80 ns

100 ⎯ ns

60 ⎯ ns

t

* × 4 ⎯ ns

CYCP

* × 4 ⎯ ns

CYCP

⎯ 150 ns

60 ⎯ ns

60 ⎯ ns

56

• Internal shift clock mode

S

S

S

S

CK0 to SCK3

OT0 to SOT3

SIN0 to SIN3

• External shift clock mode

MB91230 Series

t

SCYC

V

OH

V

OL

t

SLOV

V

OH

V

OL

t

IVSH

V

OH

V

OL

t

SHIX

V

OL

V

OH

V

OL

CK0 to SCK3

OT0 to SOT3

SIN0 to SIN3

VOL

tSLSH tSHSL

VOL

tSLOV

VOH
VOL

tIVSH tSHIX

VOH
VOL

VOH VOH

VOH
VOL

57

MB91230 Series

(7) Free-run timer clock, Reload timer event input, Up/down counter input, Input capture input,

Interrupt input timing

(MB91V230, MB91F233A : V

(MB91F233L, MB91233L : V

Parameter Symbol Pin name

Input pulse width

= 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,

CC

Ta = −40 °C to + 85 °C)

= VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,

CC

Ta = −40 °C to + 85 °C)

Condi-

tions

Value

Unit

Min Max

CKI0, CKI1

TIN0 to TIN3

t

TIWH

t

TIWL

IC0, IC1
AIN0, AIN1
BIN0, BIN1

⎯

t

× 2 ⎯ ns *

CYCP

ZIN0, ZIN1

Re-

marks

INT0 to INT15 t

* : t

indicates peripheral clock cycle time.

CYCP

VIL VIL

(8) A/D trigger, PWI (PWC) input timing

(MB91V230, MB91F233A : V

(MB91F233L, MB91233L : V

Parameter Symbol Pin name

A/D trigger input (falling) t
PWI (PWC) input (rising) t

* : t

indicates peripheral clock cycle time.

CYCP

TADTG

PWI

PWI0, PWI1 ⎯ t

× 3 ⎯ ns *

CYCP

tTIWH tTIWL

VIH VIH

= 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V,

CC

V

= AVSS = 0.0 V, Ta = −40 °C to + 85 °C)

SS

= VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V,

CC

V

= AVSS = 0.0 V, Ta = −40 °C to + 85 °C)

SS

Value

Unit Remarks

Min Max

× 2 ⎯ ns *
× 2 ⎯ ns *

ADTG0
ADTG1

Condi-

tions

⎯ t

CYCP

CYCP

58

tTADTG tPWI

VIH VIH

VIL VIL

MB91230 Series

5. Electrical Characteristics for the A/D Converter

(VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, AVRH = 3.0 V to 3.6 V, Ta = 0 °C to +85 °C)

Parameter

Min Typ Max

Resolution ⎯⎯10 bit
Total error*
Nonlinear error*
Differential linear error*
Zero transition voltage*
Full transition voltage*
Conversion time 1.69*

Power supply voltage
(analog+digital)

Reference power supply current

1

1

1

1

1

−5.0 ⎯+5.0 LSB

−3.5 ⎯+3.5 LSB

−2.5 ⎯+2.5 LSB

−2.0 +1.0 +6.0 LSB

AVRH−5.5 AVRH−1.0 AVRH+3.0 LSB

2

⎯ 3.6 ⎯ mA
⎯⎯ 5 µA

⎯ 470 ⎯µA

(between AVRH and AVRL)

⎯⎯10 µA At power-down*
Analog input capacitance ⎯ 40 ⎯ pF
Inter-channel disparity ⎯⎯ 4LSB

Value

Unit Remarks

AV
At AVRH = 3.3 V
At CPU sleep mode

⎯⎯µs

AVRH = 3.0 V,
At AVRL = 0.0 V*

= 3.3 V,

CC

3

4

*1 : Measured in the CPU sleep state
*2 : It depends on the clock cycle supplied to peripheral resources.
*3 : AVRL pin is only for FLGA package product. AVRL pin is connected to AV

inside the IC on LQFP package

SS

product.

*4 : The current when the CPU is in stop mode and the A/D converter is not operating.

59

MB91230 Series

1

5

2
1
1
1
1
1

8

•

About the external impedance of the analog input and its sampling time

• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sampling and hold capacitor is insufficient, adversely affecting
A/D conversion precision.

Analog input circuit model

•

Analog input

R

C

Comparator

During sampling : ON

RC
MB91233L
MB91F233A
MB91F233L

0.18 kΩ (Max) 63.0 pF (Max)

0.18 kΩ (Max) 39.0 pF (Max)

0.18 kΩ (Max) 39.0 pF (Max)

Note : The values are reference values.

• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance
and minimum sampling time and either adjust the resistor value and operating frequency or decrease the
external impedance so that the sampling time is longer than the minimum value.

The relationship between the external impedance and minimum sampling time

•

(External impedance = 0 kΩ to 100 kΩ)

MB91F233A

00
90
80
70
60
50
40
30
20
10

External impedance (kΩ)

0

0 5 10 15 20 25 30 3

MB91F233L

MB91233L

Minimum sampling time (µs)

(External impedance = 0 kΩ to 20 kΩ)

MB91F233A

0
8
6
4
2
0
8
6
4
2

External impedance (kΩ)

0

0123456

MB91F233L

MB91233L

Minimum sampling time (µs)

7

• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.

• About errors

As |AVRH − AV

| becomes smaller, values of relative errors grow larger.

SS

60

MB91230 Series

6. Electrical Characteristics for the D/A Converter

(VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = 0 °C to +85 °C)

Parameter

Min Typ Max

Resolution ⎯⎯ 8bit
Nonlinear error −2.0 ⎯+2.0 LSB When the output is unloaded
Differential linear error −1.0 ⎯+1.0 LSB When the output is unloaded

Value

Unit Remarks

⎯ 0.6 ⎯µs

When load capacitance

) = 20 pF

L

(C

Conversion speed

⎯ 3.0 ⎯µs

When load capacitance
(C

) = 100 pF

L

Output impedance 2.0 2.9 3.8 kΩ

10 µs conversion, when the
output is unloaded

When the input digital code is
fixed at 7A

or 85

H

H

Analog current

⎯ 40 ⎯µA

⎯⎯460* µA
⎯ 0.1 ⎯µA At power-down

* : The current consumption by D/A converter varies with input digital code.

The standard value indicates the current consumed when the digital code that maximizes the current consumption
is input.

7. Flash Memory Write/Erase Characteristics

Parameter Conditions

Sector erase time

Ta = + 25 °C,
Vcc = 5.0 V

Min Typ Max

Value

Unit Remarks

⎯ 115s

Excludes 00
prior erasure

programming

H

Chip erase time

Byte write time

Chip write time

Ta = + 25 °C,
Vcc = 5.0 V

Ta = + 25 °C,
Vcc = 5.0 V

Ta = + 25 °C,
Vcc = 5.0 V

⎯ 10 ⎯ s

⎯ 8 3,600 µs

⎯ 2.1 ⎯ s

Excludes 00

programming

H

prior erasure
Not including system-level

overhead time.
Not including system-level

overhead time.
Erase/write cycle ⎯ 10,000 ⎯⎯cycle
Flash data retention time Average Ta = + 85 °C20 ⎯⎯year *

* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature

measurements into normalized value at + 85 °C).

61

MB91230 Series

ORDERING INFORMATION

■

Part number Package Remarks

MB91V230CR-ES

401-pin ceramic PGA

(PGA-401C-A02)

MB91F233APFF-GE1

MB91F233LPFF-GE1

MB91F233LLGA-GE1

MB91233LPFF-G-xxx-BNDE1

MB91233LLGA-G-xxx-BNDE1

120-pin plastic LQFP

(FPT-120P-M05)

120-pin plastic LQFP

(FPT-120P-M05)

128-pin plastic FLGA

(LGA-128P-M01)

120-pin plastic LQFP

(FPT-120P-M05)

128-pin plastic FLGA

(LGA-128P-M01)

62

PACKAGE DIMENSIONS

■

401-pin Ceramic PGA

(PGA-401C-A02)

MB91230 Series

48.26 ± 0.55

(1.900 ± .022)

INDEX AREA

C

1994 FUJITSU LIMITED R401002SC-2-2

SQ

1.20 ± 0.25

(.047 ± .010)

5.27 (.207)
MAX

2.54 (.100) TYP 0.40 ± 0.10
(.016 ± .004)

45.72 (1.800)
REF

3.40 ± 0.40

(.134 ± .016)

Dimensions in mm (inches) .
Note : The values in parentheses are reference values.

DIA

1.02 (.040) C TYP
(4 PLCS)

1.00 (.039) DIA TYP
(4 PLCS)

EXTRA INDEX PIN

(Continued)

63

MB91230 Series

120-pin Plastic LQFP

(FPT-120P-M05)

120

LEAD No.

0.40(.016)

Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.

16.00±0.20(.630±.008)SQ

*

14.00±0.10(.551±.004)SQ

6190

6091

0.08(.003)

INDEX

31

130

0.16±0.03

(.006±.001)

0.07(.003)

M

"A"

0.145±0.055
(.006±.002)

Details of "A" part

+0.20
–0.10

1.50

+.008
–.004

.059

0~8

˚

0.50±0.20

(.020±.008)

0.60±0.15

(.024±.006)

(Mounting height)

0.10±0.10

(.004±.004)

(Stand off)

0.25(.010)

C

2003 FUJITSU LIMITED F120006S-c-4-5

Dimensions in mm (inches) .
Note : The values in parentheses are reference values.

(Continued)

64

(Continued)

128-pin plastic FLGA

(LGA-128P-M01)

9.00±0.10(.354±.004)SQ

8.30(.327)
REF

7.15(.282)
REF

0.65(.026)
TYP

MB91230 Series

8.30(.327)
REF

7.15(.282)
REF

0.65(.026)
TYP

12
11
10
9
8
7
6
5
4

(0.50)

3

((.020))

2
1

INDEX AREA

0.08(.003)

C

2004 FUJITSU LIMITED L128001S-c-1-1

1.00(.040)MAX
(Seated Height)

A

BCDEFGHJKLM

3-ø0.50

(3-ø.020)

ø0.35±0.05

128-

(128-ø.014±.002)

(0.50)

((.020))

ø0.08(ø.003)

Index

M

Dimensions in mm (inches) .
Note : The values in parentheses are reference values.

65

MB91230 Series

The information for microcontroller supports is shown in the following homepage.

http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

FUJITSU LIMITED

All Rights Reserved.

The contents of this document are subject to change without notice.
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representatives before ordering.
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circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
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assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
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Fujitsu assumes no liability for any infringement of the intellectual
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and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
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and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
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reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.

F0510

© 2005 FUJITSU LIMITED Printed in Japan