Fujitsu MB91150 Series Hardware Manual
FR30
32-BIT MICROCONTROLLER
MB91150 Series
HARDWARE MANUAL
FUJITSU LIMITED
PREFACE
■ Objectives and Intended Reader
The MB91150 Series, hereafter referred to as MB91150, is a member of the "32-bit single-chip
microcontroller FR30 Series" family and has a CPU based on a new RISC architecture at its
core. This single-chip microcontroller contains peripheral I/O resources suited for audio
equipment and MD drives that require low power consumption.
This manual is for engineers who develop products incorporating the MB91150. It also
describes the functions and operation of the MB91150. Read this manual thoroughly. For details
on each instruction, see the Instructions Manual.
■ Trademarks
FR is an abbreviation of FUJITSU RISC controller and a product of FUJITSU LIMITED.
Embedded Algorithm
■ License
Purchase of FUJITSU I
use these components in the I
Standard Specification as defined by Philips.
TM
is a trademark of Advanced Micro Device Corporation.
2
C components conveys a license under the Philips I2C Patent Right to
2
C system, provided that the system conforms to the I2C
i
■ Structure of This Manual
This manual contains 21 chapters and one appendix.
CHAPTER 1 "OVERVIEW OF THE MB91150"
This chapter provides basic items that are required to fully understand the MB91150, such
as a description of MB91150 features, block diagrams, and an outline of functions.
CHAPTER 2 "HANDLING THE DEVICE"
This chapter provides details on handling the MB91150.
CHAPTER 3 "MEMORY SPACE, CPU AND CONTROL UNIT"
This chapter describes basic items that are required to understand the FR Series CPU core
functions, its architecture, specifications, and instructions.
CHAPTER 4 "BUS INTERFACE"
This chapter describes the bus interface and bus operation.
CHAPTER 5 "I/O PORTS"
This chapter describes the I/O ports and provides the block diagrams of individual ports. It
also describes the structure and functions of registers.
CHAPTER 6 "8/16-BIT UP/DOWN COUNTER/TIMER"
This chapter describes the 8-bit and 16-bit up/down counter/timer and provides their block
diagrams. It also describes the structures and functions of registers and the operations of the
8-bit and 16-bit up/down counter/timer.
CHAPTER 7 "16-BIT RELOAD TIMER"
This chapter describes the 16-bit reload timer. It also describes the operations of the 16-bit
reload timer, block diagram, and the structures and functions of the timer registers.
CHAPTER 8 "PPG TIMER"
This chapter describes the PPG timer. It also describes the operations of the PPG timer,
block diagram, and the structures and functions of the timer registers.
CHAPTER 9 "MULTIFUNCTIONAL TIMER"
This chapter describes the multifunctional timer. It also describes the operations of the
multifunctional timer, block diagram, and the structures and functions of the timer registers.
CHAPTER 10 "EXTERNAL INTERRUPT CONTROL BLOCK"
This chapter describes the external interrupt control block. It also describes the operation of
the external interrupt control block, and the structures and functions of the related registers.
CHAPTER 11 "DELAYED INTERRUPT MODULE"
This chapter describes the delayed interrupt module. It also describes the operation of the
delayed interrupt module, and the structures and functions of related registers.
CHAPTER 12 "INTERRUPT CONTROLLER"
This chapter describes the interrupt controller and provides its block diagram. It also
describes the structures and functions of registers and the operation of the interrupt
controller.
CHAPTER 13 "8/10-BIT A/D CONVERTER"
This chapter describes the 8-bit D/A converter and provides its block diagram. It also
describes pins, structures and functions of registers, interrupts, device operation, and the A/
D conversion data protection function. The chapter also provides notes on using the 8/10-bit
A/D converter.
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CHAPTER 14 "8-BIT D/A CONVERTER"
This chapter describes the 8-bit D/A converter. It also describes the operation of the
converter, block diagram, and the structures and functions of the converter registers.
CHAPTER 15 "UART"
This chapter describes the UART and provides its block diagram. It also describes pins,
structures and functions of registers, interrupts, timing, baud rates, and device operation.
The chapter also provides notes on using the UART.
CHAPTER 16 "I
This chapter describes the I
register structures and functions and I
2
C INTERFACE"
2
C interface and provides its block diagram. It also describes
2
C interface operation.
CHAPTER 17 "DMAC"
This chapter describes the DMAC and provides its block diagram. It also describes registers,
operation, DMA transfer sources, and DMAC timing. The chapter also provides notes on
using the DMAC.
CHAPTER 18 "BIT SEARCH MODULE"
This chapter describes the bit search module. It also describes the structures and functions
of bit search module registers, and the processing for saving and restoring.
CHAPTER 19 "PERIPHERAL STOP CONTROL"
This chapter describes peripheral stop control and structures and functions of the registers.
CHAPTER 20 "CALENDAR MACROS"
This chapter describes the calendar macros, structures and functions of registers, and the
operation of the calendar macro.
CHAPTER 21 "FLASH MEMORY"
This chapter describes the flash memory, structures and functions of the registers, device
operation, and the automation algorithm. It also provides detailed information on flash
memory writing and erasing.
APPENDIX
The appendix contains I/O maps and information on the interrupt vectors, pin status for
various CPU states, details regarding the little-endian area, and references for programming.
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• The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presented
solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device;
Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you
develop equipment incorporating the device based on such information, you must assume any responsibility
arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of
the use of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be
construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or
any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party' s intellectual
property right or other right by using such information. Fujitsu assumes no liability for any infringement of the
intellectual property rights or other rights of third parties which would result from the use of information contained
herein.
• The products described in this document are designed, developed and manufactured as contemplated for general
use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but
are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers
that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to
death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control
in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in
connection with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy,
fire protection, and prevention of over-current levels and other abnormal operating conditions.
• If any products described in this document represent goods or technologies subject to certain restrictions on
export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese
government will be required for export of those products from Japan.
©2003 FUJITSU LIMITED Printed in Japan
iv
READING THIS MANUAL
■ Details Regarding the Manual Format
An explanation of the most important terms in this manual is given in the table below.
Term Meaning
I-BUS 16-bit bus for internal instructions. The FR Series employs internal Harvard
architecture; there are independent buses for instructions and data. A bus
converter is connected to the I-BUS.
D-BUS Internal 32-bit data bus. An internal resource is connected to the D-BUS.
C-BUS Internal multiplex bus. The C-BUS is connected to both the I-BUS and D-Bus
through a switch. An external interface module is connected to the C-BUS. On
external data buses, data and instructions are multiplexed.
R-BUS Internal 16-bit data bus. The R-Bus is connected to the D-BUS via an adapter.
Various I/O devices, a clock generator, and an interrupt controller are connected
to the R-BUS. The R-BUS has a bandwidth of 16 bits over which addresses and
data are multiplexed; CPU access time of these resources is several cycles.
E-unit Arithmetic execution unit
φ System clock. It provides the clock signals output to each of the built-in
resources connected to the R-BUS from the clock generator. The maximum
clock speed (cycle) is identical to the original clock oscillation. The clock cycle
can be divided by 1, 1/2, 1/4, and 1/8 (or 1/2, 1/4, 1/8, and 1/16) depending on
the setting of the PCK1 and PCK0 bits of the GCR register in the clock
generator.
θ System clock. Clock used by the CPU and resources connected to a bus other
than the R-BUS. The maximum clock speed (cycle) is identical to the original
clock oscillation. The clock cycle can be divided by 1, 1/2, 1/4, and 1/8 (or 1/2, 1/
4, 1/8, and 1/16) depending on the setting of the CCK1 and CCK0 bits of the
GCR register in the clock generator.
v
vi
CONTENTS
CHAPTER 1 OVERVIEW OF THE MB91150 ..................................................................... 1
1.1 MB91150 Features ................................................................................................................................ 2
1.2 Block Diagrams ...................................................................................................................................... 5
1.3 Package Dimensions ............................................................................................................................. 7
1.4 Pin Assignment ...................................................................................................................................... 9
1.5 Pin Functions ....................................................................................................................................... 12
1.6 I/O Circuit Types .................................................................................................................................. 20
CHAPTER 2 HANDLING THE DEVICE ........................................................................... 23
2.1 Notes on Handling Devices ................................................................................................................. 24
2.2 Notes on Using Devices ...................................................................................................................... 26
2.3 Power-On ............................................................................................................................................. 27
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT ......................................... 29
3.1 Memory Space ..................................................................................................................................... 30
3.2 CPU Architecture ................................................................................................................................. 33
3.3 Programming Model ............................................................................................................................ 36
3.4 Data Structure ...................................................................................................................................... 44
3.5 Word Alignment ................................................................................................................................... 45
3.6 Special Memory Areas ......................................................................................................................... 46
3.7 Overview of Instructions ...................................................................................................................... 47
3.7.1 Operations with Delay Slots ........................................................................................................... 49
3.7.2 Branch Instructions without a Delay Slot ........................................................................................ 52
3.8 EIT (Exception, Interrupt, and Trap) .................................................................................................... 53
3.8.1 Interrupt Level ................................................................................................................................. 54
3.8.2 Interrupt Stack Operation ............................................................................................................... 55
3.8.3 EIT Vector Table ............................................................................................................................. 56
3.8.4 Multiple EIT Processing .................................................................................................................. 58
3.8.5 EIT Operation ................................................................................................................................. 60
3.9 Reset Sequence .................................................................................................................................. 64
3.10 Operation Mode ................................................................................................................................... 65
3.11 Clock Generator (Low-Power Consumption Mechanism) .................................................................... 67
3.11.1 Reset Source Register (RSRR) and Watchdog Cycle Control Register (WTCR) .......................... 69
3.11.2 Standby Control Register (STCR) .................................................................................................. 71
3.11.3 Time-base Timer Clear Register (CTBR) ....................................................................................... 72
3.11.4 Gear Control Register (GCR) ......................................................................................................... 73
3.11.5 Watchdog Reset Generation Delay Register (WPR) ...................................................................... 75
3.11.6 DMA Request Suppression Register (PDRR) ................................................................................ 76
3.11.7 PLL Control Register (PCTR) ......................................................................................................... 77
3.11.8 Watchdog Function ......................................................................................................................... 78
3.11.9 Gear Function ................................................................................................................................. 80
3.11.10 Retaining a Reset Source ............................................................................................................... 82
3.11.11 Example of Setting the PLL Clock .................................................................................................. 84
3.12 Low-Power Consumption Mode ........................................................................................................... 87
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3.12.1 Stop Status .................................................................................................................................... 89
3.12.2 Sleep Status .................................................................................................................................. 92
3.12.3 Status Transition of the Low-power Consumption Mode .............................................................. 95
CHAPTER 4 BUS INTERFACE ....................................................................................... 97
4.1 Outline of Bus Interface ...................................................................................................................... 98
4.2 Block Diagram of the Bus Interface .................................................................................................. 100
4.3 Registers of the Bus Interface ........................................................................................................... 101
4.3.1 Area Select Registers (ASR) and Area Mask Registers (AMR) ................................................... 102
4.3.2 Area Mode Register 0 (AMD0) ..................................................................................................... 104
4.3.3 Area Mode Register 1 (AMD1) ..................................................................................................... 106
4.3.4 Area Mode Register 32 (AMD32) ................................................................................................. 107
4.3.5 Area Mode Register 4 (AMD4) ..................................................................................................... 108
4.3.6 Area Mode Register 5 (AMD5) ..................................................................................................... 109
4.3.7 External Pin Control Register 0 (EPCR0) .................................................................................... 110
4.3.8 External Pin Control Register 1 (EPCR1) .................................................................................... 112
4.3.9 Little-endian Register (LER) ........................................................................................................ 113
4.4 Bus Operation ................................................................................................................................... 114
4.4.1 Relationship Between Data Bus Width and Control Signals ........................................................ 115
4.4.2 Bus Access in Big-endian Mode .................................................................................................. 116
4.4.3 Bus Access in Little-endian Mode ................................................................................................ 122
4.4.4 Comparison of External Access in Big-endian and Little-endian Mode ....................................... 126
4.5 Bus Timing ........................................................................................................................................ 131
4.5.1 Basic Read Cycle ........................................................................................................................ 132
4.5.2 Basic Write Cycle ......................................................................................................................... 134
4.5.3 Read Cycle in Each Mode ........................................................................................................... 136
4.5.4 Write Cycle in Each Mode ........................................................................................................... 138
4.5.5 Mixed Read/Write Cycles ............................................................................................................. 140
4.5.6 Automatic Wait Cycle ................................................................................................................... 141
4.5.7 External Wait Cycle ..................................................................................................................... 142
4.5.8 External Bus Request .................................................................................................................. 143
4.6 Internal Clock Multiply Operation (Clock Doubler) ............................................................................ 144
4.7 Program Examples for the External Bus ........................................................................................... 146
CHAPTER 5 I/O PORTS ................................................................................................ 149
5.1 Overview of I/O Ports ....................................................................................................................... 150
5.2 Block Diagram of Basic I/O Port ....................................................................................................... 151
5.3 Block Diagram of I/O Ports (Including the Pull-up Resistor) ............................................................. 152
5.4 Block Diagram of I/O ports (Including the Open-drain Output and the Pull-up Resistor) .................. 153
5.5 Block Diagram of I/O Port (With Open-Drain Output Function) ........................................................ 155
5.6 Port Data Register (PDR) ................................................................................................................. 156
5.7 Data Direction Register (DDR) .......................................................................................................... 157
5.8 Pull-up Control Register (PCR) ......................................................................................................... 159
5.9 Open-Drain Control Register (ODCR) .............................................................................................. 160
5.10 Analog Input Control Register (AICR) ............................................................................................... 161
CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER ................................................... 163
6.1 Overview of 8/16-Bit Up/Down Counter/Timer .................................................................................. 164
viii
6.2 Block Diagram of the 8/16-bit Up/Down Counter/Timer ..................................................................... 166
6.3 List of Registers of the 8/16-Bit Up/Down Counter/Timer .................................................................. 168
6.3.1 Counter Control Register H/L (CCRH/L) ...................................................................................... 169
6.3.2 Counter Control Register H/L ch1 (CCR H/L Ch1) ....................................................................... 173
6.3.3 Counter status register 0/1 (CSR0/1) ........................................................................................... 174
6.3.4 Up/down count register 0/1 (UDCR 0/1) ....................................................................................... 176
6.3.5 Reload/compare Register 0/1 (RCR 0/1) ...................................................................................... 177
6.4 Selection of Counting Mode ............................................................................................................... 178
6.5 Reload and Compare Functions ........................................................................................................ 181
6.6 Writing data to the up/down count register (UDCR) .......................................................................... 185
CHAPTER 7 16-BIT RELOAD TIMER ........................................................................... 187
7.1 Overview of 16-bit Reload Timer ....................................................................................................... 188
7.2 Block diagram of a 16-bit reload timer ............................................................................................... 189
7.3 Registers of 16-bit Reload Timer ....................................................................................................... 190
7.3.1 Control status register (TMCSR) .................................................................................................. 191
7.3.2 16-bit Timer Register (TMR) and 16-bit Reload Register (TMRLR) ............................................. 193
7.4 Internal Clock Operation .................................................................................................................... 194
7.5 Underflow operation ........................................................................................................................... 195
7.6 Counter Operation States .................................................................................................................. 197
CHAPTER 8 PPG TIMER ............................................................................................... 199
8.1 Overview of PPG Timer ..................................................................................................................... 200
8.2 Block Diagram of PPG Timer ............................................................................................................. 201
8.3 Registers of PPG Timer ..................................................................................................................... 203
8.3.1 Control status registers (PCNH, PCNL) ....................................................................................... 205
8.3.2 PWM cycle set register (PCSR) ................................................................................................... 209
8.3.3 PWM duty set register (PDUT) ..................................................................................................... 210
8.3.4 PWM timer register (PTWR) ......................................................................................................... 211
8.3.5 General control register 1 (GCN1) ................................................................................................ 212
8.3.6 General control register 2 (GCN2) ................................................................................................ 215
8.4 PWM Operation ................................................................................................................................. 216
8.5 One-shot Operation ........................................................................................................................... 218
8.6 PWM Timer Interrupt Source and Timing Chart ................................................................................ 220
8.7 Activating Multiple Channels by Using the General Control Register (GCN) .................................... 222
CHAPTER 9 MULTIFUNCTIONAL TIMER .................................................................... 225
9.1 Overview of Multifunctional Timer ...................................................................................................... 226
9.2 Block Diagram of the Multifunctional Timer ...................................................................................... 228
9.3 Registers of Multifunctional Timer ..................................................................................................... 229
9.3.1 Registers of 16-bit Free-run Timer ............................................................................................... 230
9.3.2 Registers of the Output Compare ................................................................................................. 234
9.3.3 Registers of Input Capture ............................................................................................................ 237
9.4 Operations of Multifunctional Timer ................................................................................................... 239
9.4.1 Operation of 16-bit Free-run Timer ............................................................................................... 240
9.4.2 Operation of 16-bit Output Compare ............................................................................................ 242
9.4.3 Operation of 16-bit Input Capture ................................................................................................. 245
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CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK ......................................... 247
10.1 Overview of External Interrupt .......................................................................................................... 248
10.2 External Interrupt Registers .............................................................................................................. 249
10.2.1 Enable Interrupt Register (ENIRn) ............................................................................................... 250
10.2.2 External Interrupt Request Register (EIRRn) ............................................................................... 251
10.2.3 External Interrupt Level Setting Register (ELVR: External Level Register) ................................. 252
10.3 External Interrupt Operation .............................................................................................................. 253
10.4 External Interrupt Request Level ...................................................................................................... 254
CHAPTER 11 DELAYED INTERRUPT MODULE ........................................................... 255
11.1 Overview of Delayed Interrupt Module .............................................................................................. 256
11.2 Delayed Interrupt Control Register (DICR) ....................................................................................... 257
11.3 Operation of Delayed Interrupt Module ............................................................................................. 258
CHAPTER 12 INTERRUPT CONTROLLER .................................................................... 259
12.1 Overview of Interrupt Controller ........................................................................................................ 260
12.2 Block Diagram of the Interrupt Controller .......................................................................................... 261
12.3 List of Interrupt Controller Registers ................................................................................................. 262
12.3.1 Interrupt Control Register (ICR) ................................................................................................... 264
12.3.2 Hold-Request Cancellation-Request Level-Set Register (HRCL) ................................................ 266
12.4 Priority Evaluation ............................................................................................................................. 267
12.5 Return from Standby (Stop or Sleep) Mode ...................................................................................... 269
12.6 Hold-Request Cancellation Request ................................................................................................. 270
12.7 Example of Using Hold-Request Cancellation-Request Function (HRCR) ....................................... 271
CHAPTER 13 8/10-BIT A/D CONVERTER ...................................................................... 275
13.1 Overview of the 8/10-bit A/D Converter ............................................................................................ 276
13.2 8/10-bit A/D Converter Block Diagram .............................................................................................. 277
13.3 8/10-bit A/D Converter Pins .............................................................................................................. 279
13.4 8/10-bit A/D Converter Registers ...................................................................................................... 281
13.4.1 A/D Control Status Register 1 (ADCS1) ...................................................................................... 282
13.4.2 A/D Control Status Register 0 (ADCS0) ...................................................................................... 285
13.4.3 A/D Data Register (ADCR) .......................................................................................................... 287
13.5 8/10-bit A/D Converter Interrupt ........................................................................................................ 289
13.6 Operation of the 8/10-bit A/D Converter ........................................................................................... 290
13.7 A/D Converted Data Preservation Function ...................................................................................... 292
13.8 Notes on Using the 8/10-bit A/D Converter ....................................................................................... 293
CHAPTER 14 8-BIT D/A CONVERTER ........................................................................... 295
14.1 Overview of the 8-bit D/A Converter ................................................................................................. 296
14.2 8-bit D/A Converter Block Diagram ................................................................................................... 297
14.3 8-bit D/A Converter Registers ........................................................................................................... 298
14.3.1 D/A Control Registers (DACR0, DACR1, DACR2) ...................................................................... 299
14.3.2 D/A Data Registers (DADR2, DADR1, DADR0) .......................................................................... 300
14.4 8-bit D/A Converter Operation .......................................................................................................... 301
CHAPTER 15 UART ........................................................................................................ 303
15.1 Overview of the UART ...................................................................................................................... 304
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15.2 UART Block Diagram ......................................................................................................................... 306
15.3 UART Pins ......................................................................................................................................... 308
15.4 UART Registers ................................................................................................................................. 311
15.4.1 Control register (SCR0-3) ............................................................................................................. 312
15.4.2 Mode register (SMR0-3) ............................................................................................................... 314
15.4.3 Status register (SSR0-3) .............................................................................................................. 316
15.4.4 Input-data register (SIDR0-3), output-data register (SODR0-3) ................................................... 318
15.4.5 Communication prescaler control register (CDCR) ...................................................................... 320
15.5 Interrupts ........................................................................................................................................... 322
15.6 Receive-Interrupt Generation and Flag Set Timing ........................................................................... 324
15.7 Send-Interrupt Generation and Flag Set Timing ................................................................................ 325
15.8 Baud Rate .......................................................................................................................................... 326
15.8.1 Baud Rate Based on the Dedicated Baud-Rate Generator .......................................................... 328
15.8.2 Baud Rate Based on the Internal Timer (16-bit Reload Timer 0) ................................................. 331
15.8.3 Baud Rate Based on the External clock ....................................................................................... 333
15.9 UART Operations .............................................................................................................................. 334
15.9.1 Operation in asynchronous mode (operation modes 0 to 1) ........................................................ 336
15.9.2 Operation in synchronous mode (operation mode 2) ................................................................... 339
15.9.3 Bidirectional communication function (normal mode) ................................................................... 341
15.9.4 Master/slave-type communication function (multiprocessor mode) .............................................. 343
15.10 Notes on Using UART ....................................................................................................................... 345
CHAPTER 16 I2C INTERFACE ........................................................................................ 347
16.1 Overview of I2C Interface ................................................................................................................... 348
16.2 Block Diagram of I
16.3 Registers of I
16.3.1 Bus Control Register (IBCR) ........................................................................................................ 351
16.3.2 Bus Status Register (IBSR) .......................................................................................................... 354
16.3.3 Address Register (IADR)/Data Register (IDAR) ........................................................................... 356
16.3.4 Clock Control Register (ICCR) ..................................................................................................... 357
16.4 Operation of I
2
C Interface .......................................................................................................... 349
2
C Interface .................................................................................................................. 350
2
C Interface .................................................................................................................. 359
CHAPTER 17 DMA CONTROLLER ................................................................................. 361
17.1 Overview of the DMA Controller Overview ........................................................................................ 362
17.2 Block Diagram of the DMA Controller ................................................................................................ 363
17.3 Registers of the DMA Controller ........................................................................................................ 364
17.3.1 DMAC parameter descriptor pointer (DPDP) ............................................................................... 365
17.3.2 MAC control status register (DACSR) .......................................................................................... 366
17.3.3 DMAC pin control register (DATCR) ............................................................................................. 368
17.3.4 Register of the descriptor in RAM ................................................................................................. 370
17.4 Transfer Modes Supported by the DMA Controller ............................................................................ 373
17.4.1 Step Transfer (Single/Block Transfer) .......................................................................................... 376
17.4.2 Continuos Transfer ....................................................................................................................... 377
17.4.3 Burst Transfer ............................................................................................................................... 378
17.4.4 Differences Because of DREQ Sense Mode ................................................................................ 379
17.5 Transfer-Acceptance Signal Output and Transfer-End Signal Output ............................................... 381
17.6 Notes on the DMA Controller ............................................................................................................. 382
17.7 Timing Charts for the DMA Controller ................................................................................................ 384
xi
17.7.1 Timing charts for the descriptor access section ........................................................................... 385
17.7.2 Timing charts for the data transfer section ................................................................................... 387
17.7.3 Timing charts for transfer termination in continuous transfer mode ............................................. 389
17.7.4 Timing charts for the transfer termination operation .................................................................... 391
CHAPTER 18 BIT-SEARCH MODULE ............................................................................ 393
18.1 Overview of the Bit-Search Module .................................................................................................. 394
18.2 Registers of the Bit-Search Module .................................................................................................. 395
18.3 Operation of the Bit-Search Module .................................................................................................. 397
CHAPTER 19 PERIPHERAL STOP CONTROL .............................................................. 399
19.1 Overview of Peripheral Stop Control ................................................................................................. 400
19.2 Peripheral Stop Control Registers .................................................................................................... 401
CHAPTER 20 CALENDAR MACROS ............................................................................. 405
20.1 Overview of Calendar Macros ........................................................................................................... 406
20.2 Calendar Macro Registers ................................................................................................................ 407
20.3 Calendar Macro Operation ................................................................................................................ 411
CHAPTER 21 FLASH MEMORY ..................................................................................... 413
21.1 Overview of Flash Memory ............................................................................................................... 414
21.2 Flash Memory Registers ................................................................................................................... 418
21.3 Flash Memory Operation .................................................................................................................. 421
21.4 Automatic Algorithm of Flash Memory .............................................................................................. 423
21.5 Checking the Automatic Algorithm Execution Status ........................................................................ 427
21.6 Writing and Erasing Flash Memory ................................................................................................... 432
21.6.1 Putting flash memory into read/reset status ................................................................................. 433
21.6.2 Writing data to flash memory ....................................................................................................... 434
21.6.3 Erasing data ................................................................................................................................. 436
21.6.4 Temporarily Stopping and Restarting Sector Erase ..................................................................... 438
APPENDIX .......................................................................................................................... 439
APPENDIX A I/O Map ............................................................................................................................... 440
APPENDIX B Interrupt Vectors ................................................................................................................... 448
APPENDIX C Pin Status in Each CPU State .............................................................................................. 452
APPENDIX D Notes on Using the Little-Endian Area ................................................................................. 459
D.1 C Compiler (fcc911) ....................................................................................................................... 460
D.2 Assembler (fasm911) ..................................................................................................................... 463
D.3 Linker (flnk911) ............................................................................................................................... 464
D.4 Debuggers (sim911, eml911, and mon911) ................................................................................... 465
APPENDIX E Instruction Lists .................................................................................................................... 466
INDEX ...................................................................................................................................487
xii
CHAPTER 1 OVERVIEW OF THE MB91150
This chapter provides basic information required to fully understand the MB91150,
such as a description of MB91150 features, block diagrams, and an outline of
functions.
1.1 "MB91150 Features"
1.2 "Comprehensive Block Diagram of MB91150"
1.3 "Exterior Dimensions"
1.4 "Pin Assignment Drawing"
1.5 "Pin Functions"
1.6 "I/O Circuit Types"
1
CHAPTER 1 OVERVIEW OF THE MB91150
1.1 MB91150 Features
The MB91150 is a single-chip microcontroller with peripheral I/O resources suited for
controlling devices such as audio equipment and MD drives that require operation
with low-power consumption. The core of the MB91150 is a 32-bit RISC CPU (FR30
Series).
■ MB91150 features
❍ CPU
• 32-bit RISC (FR30), load/store architecture, 5-stage pipeline
• 32-bit general-purpose register x 16
• 16-bit fixed-length instructions (basic instruction), one instruction per cycle
• Instructions for memory-to-memory transfer, bit processing, parallel shift, etc.
The instructions are suited for embedded-type usage.
• Instructions for entry/exit functions, multiple load/store instructions for the register contents,
instructions for high-level languages.
• Register interlock function allowing simpler assembler code
• Branch instruction with a delay slot allowing a decrease in overhead for branch processing
• Built-in multiplier, supported on the instruction level
• Signed 32-bit multiplication: 5 cycles
• Signed 16-bit multiplication: 3 cycles
• Interrupt (PC and PS saving): 6 cycles, 16 priority levels
❍ Bus interface
• 24-bit address output, 8-bit and 16-bit data I/O
• Basic bus cycle: 2 clock cycles
• Interface for supporting various memory types
• Unused data and address pins can be used as I/O pins.
• Support of little endian mode
❍ Internal ROM
• MB91F155A, MB91FV150
• FLASH product, EVA-FLASH product: 510 KB
• MB91155
• Mask product: 510 KB
• MB91154
• Mask product: 384 KB
2
CHAPTER 1 OVERVIEW OF THE MB91150
❍ Internal RAM
Mask product, FLASH product, EVA-FLASH product: 2 KB
❍ Internal data RAM
• MB91FV150, MB91F155A, MB91155
• EVA-FLASH product, FLASH product, Mask product: 32 KB
• MB91154
• Mask product: 20 KB
❍ DMA controller (DMAC)
• DMAC of the descriptor type according to which transfer parameters are allocated in main
storage
• Capable of transferring up to eight internal and external sources
• External source: 3 channels
❍ Bit search module
The bit search module makes a one-cycle search for the location of the first I/O bit change
starting with the MSB of a word.
❍ Timer
• 16-bit OCU x 8 channels, ICU x 4 channels, free-run timer x 1 channel
• 8-bit or 16-bit up/down timer/counter (8-bit x 2 channels or 16-bit x 1 channel)
• The AIN and BIN pins are shared with internal interrupts.
• 16-bit PPG timer x 6 channels. The cycle and duty of an output pulse can be changed to an
arbitrary value.
• 16-bit reload timer x 4 channels
❍ D/A converter
8 bits x 3 channels
❍ A/D converter (successive approximation type)
• 10 bits x 8 channels
• Successive approximation type (conversion time: 5.0 µs@33 MHz)
• Singe and scan conversions can be selected, and single, continuous, and stop conversion
modes can be set.
• Hardware-driven or software-driven conversion function
3
CHAPTER 1 OVERVIEW OF THE MB91150
❍ Serial I/O
• UART x 4 channels. Each UART can perform clock-synchronized serial transfer with the
LSB/MSB switching function.
• Serial data output and serial clock output can be selected by open-drain or push-pull
software.
• Built-in 16-bit timer (U-Timer) as a dedicated baud rate generator, which can generate any
baud rate
2
❍ I
C bus interface
• 1-channel master/slave transmission/reception
• Arbitration function and clock synchronization function
• (As long as the customer uses this product in an I
Standard Specifications prepared by Philips, the customer is granted a license of the I
patent of Philips.)
❍ Clock switching function
The ratio of the operating clock to the base clock can independently be set with the gear
function to 1:1. 1:2, 1:4, or 1:8 for the CPU and for each peripheral device.
2
C system conforming to the I2C
2
C
❍ Clock function (calendar macro)
• Built-in 32 kHz clock function
• The 32 kHz oscillation clock function can operate in stop mode as well.
• (32-kHz oscillation does not stop in stop mode.)
❍ Interrupt controller
• External interrupt input (up to 16 channels)
• The leading edge, trailing edge, H level, or L level can be set.
• Internal interrupt source
• Resource interrupt, delayed interrupt
❍ Other features
• Reset sources
• Power-on reset, watchdog timer, software reset, and external reset
• Low-power consumption mode
• Sleep mode and stop mode
• Packages
• PGA-299 (MB91FV150)
• LQFP-144 [MB91F155A, MB91155, MB91154]
• CMOS technology (0.35 µm)
• Power supply
• 3.15 V to 3.6 V
4
CHAPTER 1 OVERVIEW OF THE MB91150
1ch
1.2 Block Diagrams
This section provides MB91150 block diagrams separately for individual packages.
■ Block diagram for MB91FV150, MB91F155A and MB91155
Figure 1.2-1 "Block diagram (MB91FV150, MB91F155A and MB91155)" is a block diagram for
the MB91FV150, MB91F155A and MB91155.
Figure 1.2-1 Block diagram (MB91FV150, MB91F155A and MB91155)
M
………
OSC
(2)
O
D
E
(4)
P
O
R
T
3
/
2
(16)
P
O
R
T
6
/
5
/
4
(24)
P
O
R
T
8
(7)
P
O
R
T
L
(8)
P
O
R
T
D
(8)
P
O
R
T
C
(8)
FR30 CPU Core
I-Bus
I-Bus
External
Bus CTL
RAM
2KB
ROM
510KB
Clock
Control
Interrupt
Controller
8bit
Up/Down
2
h
External
I2C Interface
Interrupt
16ch
Counter
1ch
D-Bus
D-Bus
C-Bus
Calendar
Data RAM
32KB
DMAC 8ch
Bit Search
D-Bus R-Bus
UART 4ch
UTIMER 4ch
16bit
Reload Timer
4ch
16bit
Free RUN Timer
16bit PPG
16bit
Input Capture
16bit
Output Compare
10bit 8input
A/D converter
8bit 3output
D/A converter
I2C Interface
6ch
4ch
8ch
1ch
OSC
(2)
P
O
R
T
E
(8)
P
O
R
T
G
(6)
P
O
R
T
H
(6)
P
O
R
T
I
(6)
P
O
R
T
J
(2)
P
O
R
T
K
(8)
P
O
R
T
F
(5)
D
A
(3)
X0A
X1A
PE7/OC7
PE6/OC6
PE5/OC5
PE4/OC4
PE3/OC3
PE2/OC2
PE1/OC1
PE0/OC0
PG5/PPG5
PG4/PPG4
PG3/PPG3
PG2/PPG2
PG1/PPG1
PG0/PPG0
PH0/SIN0
PH1/SOT0
PH2/SCK0/T00
PH3/SIN1
PH4/SOT1
PH5/SCK1/T01
PI0/SIN2
PI1/SOT2
PI2/SCK2/T02
PI3/SIN3
PI4/SOT3
PI5/SCK3/T03
PJ0/SCL
PJ1/SDA
PK0/AN0
PK1/AN1
PK2/AN2
PK3/AN3
PK4/AN4
PK5/AN5
PK6/AN6
PK7/AN7
PF4
PF3/IN3
PF2/IN2
PF1/IN1
PF0/IN0
DA2
DA1
DA0
Clock
Output
Compare
PPG
UART
TOX:
Reload
Timer
I2C
A/D
Input
Capture
A/D
DMAC
Up/Down
Counter
External
nterrupt
DATA
Address
Bus
Control
DMAC
Clock
MD0
MD1
MD2
RST
P37/D31(IO)
………
P30/D24
P27/D23
P20/D16
P67/A23(O)
P60/A16
P57/A15
……
P50/A8
P47/A7
P40/A0
P86/CLK(O)
P85/WR1(O)
P84/WR0
P83/RD(O)
P82/BRQ(I)
P81/BGRNT(O)
P80/RDY(I)
PL7/DACK2
PL6/DREQ2
PL5/DEOP1
PL4/DACK1
PL3/DREQ1
PL2/DEOP0(O)
PL1/DACK0(O)
PL0/DREQ0(I)
X0 (I)
X1 (I)
PD7/INT15/ATG(I)
PD6/INT14/DEOP2
PD5/INT13/ZIN1
PD4/INT12/ZIN0
PD3/INT11/BIN1
PD2/INT10/AIN1
PD1/INT9/BIN0(I)
PD0/INT8/AIN0(I)
PC7/INT7/CS3
PC6/INT6/CS2
PC5/INT5/CS1
PC4/INT4/CS0
PC3/INT3
PC2/INT2
PC1/INT1
PC0/INT0(I)
5
CHAPTER 1 OVERVIEW OF THE MB91150
4ch
e
■ Block diagram for MB91154
Figure 1.2-2 "Block diagram (MB91154)" is a block diagram for the MB91154.
Figure 1.2-2 Block diagram (MB91154)
M
…
…
…
OSC
(2)
O
D
E
(4)
P
O
R
T
3
/
2
(16)
P
O
R
T
6
/
5
/
4
(24)
P
O
R
T
8
(7)
P
O
R
T
L
(8)
P
O
R
T
D
(8)
P
O
R
T
C
(8)
I-Bus
I-Bus
RAM
2KB
ROM
384KB
Clock
Control
Interrupt
Controller
8bit
I2C Interface
16ch
A/D
DMAC
Up/Down
Counter
External
Interrupt
DATA
Address
Bus
Control
DMAC
Clock
MD0
MD1
MD2
RST
P37/D31(IO)
…
P30/D24
P27/D23
…
P20/D16
P67/A23(O)
………
P60/A16
P57/A15
P50/A8
P47/A7
P40/A0
P86/CLK(O)
P85/WR1(O)
P84/WR0
P83/RD(O)
P82/BRQ(I)
P81/BGRNT(O)
P80/RDY(I)
PL7/DACK2
PL6/DREQ2
PL5/DEOP1
PL4/DACK1
PL3/DREQ1
PL2/DEOP0(O)
PL1/DACK0(O)
PL0/DREQ0(I)
X0 (I)
X1 (I)
PD7/INT15/ATG(I)
PD6/INT14/DEOP2
PD5/INT13/ZIN1
PD4/INT12/ZIN0
PD3/INT11/BIN1
PD2/INT10/AIN1
PD1/INT9/BIN0(I)
PD0/INT8/AIN0(I)
PC7/INT7/CS3
PC6/INT6/CS2
PC5/INT5/CS1
PC4/INT4/CS0
PC3/INT3
PC2/INT2
PC1/INT1
PC0/INT0(I)
FR30 CPU Core
D-Bus
External
Bus CTL
Up/Down
Counter
2ch
External
Interrupt
1ch
D-Bus
C-Bus
Calendar
Data RAM
DMAC 8ch
Bit Search
D-Bus R-Bus
UART 4ch
UTIMER 4ch
16bit
Reload Timer
16bit
Free RUN Timer
1ch
16bit PPG
16bit
Input Capture
16bit
Output Compare
10bit 8input
A/D converter
8bit 3output
D/A converter
I2C Interface
6ch
4ch
8ch
1ch
OSC
(2)
P
O
R
T
E
(8)
P
O
R
T
G
(6)
P
O
R
T
H
(6)
P
O
R
T
I
(6)
P
O
R
T
J
(2)
P
O
R
T
K
(8)
P
O
R
T
F
(5)
D
A
(3)
X0A
X1A
PE7/OC7
PE6/OC6
PE5/OC5
PE4/OC4
PE3/OC3
PE2/OC2
PE1/OC1
PE0/OC0
PG5/PPG5
PG4/PPG4
PG3/PPG3
PG2/PPG2
PG1/PPG1
PG0/PPG0
PH0/SIN0
PH1/SOT0
PH2/SCK0/T00
PH3/SIN1
PH4/SOT1
PH5/SCK1/T01
PI0/SIN2
PI1/SOT2
PI2/SCK2/T02
PI3/SIN3
PI4/SOT3
PI5/SCK3/T03
PJ0/SCL
PJ1/SDA
PK0/AN0
PK1/AN1
PK2/AN2
PK3/AN3
PK4/AN4
PK5/AN5
PK6/AN6
PK7/AN7
PF4
PF3/IN3
PF2/IN2
PF1/IN1
PF0/IN0
DA2
DA1
DA0
Clock
Output
Compar
PPG
UART
TOX:
Reload
Timer
I2C
A/D
Input
Capture
6
1.3 Package Dimensions
Two types of MB91150 packages are provided.
■ Package dimensions of PGA-299C-A01 (MB91FV150 Only)
Figure 1.3-1 Package dimensions of PGA-299C-A01
299-pin ceramic PGA Lead pitch 2.54mm(100mil)
Sealing method Metal seal
CHAPTER 1 OVERVIEW OF THE MB91150
Pin matrix 20
(PGA-299C-A01)
299-pin ceramic PGA
(PGA-299C-A01)
INDEX AREA
2.41 ± 0.10
(.095 ± .004)
1.65 ± 0.10
(.065 ± .004)
30.48 ± 0.31
(1.200 ± .012)
52.32 ± 0.56
(2.060 ± .022)
SQ
35.56 ± 0.41
(1.400 ± .016)
3.94 ± 0.10
(.155 ± .004)
5.59 (.220) MAX
+ 0.13
0.46
+ .005
(.018 )
2.54 (.100) MAX
48.26 (19.00)
REF
2.54 ± 0.25
(.100 ± .010)
1.27 ± 0.25
(.050 ± .010)
+ 0.41
3.40
+ .016
(.134 )
1.27 (.050) DIA TYP
(4 PLCS)
INDEX AREA
C
1994 FUJITSU LIMITED R299001SC-2-2
Dimensions in mm (inches).
7
CHAPTER 1 OVERVIEW OF THE MB91150
■ Package dimensions of FPT-144P-M08 (MB91F155A, MB91155 and MB91154)
Figure 1.3-2 Package dimensions of FPT-144P-M08
144-pin plastic LQFP Lead pitch 0.50 mm
(FPT-144P-M08)
144-pin plastic LQFP
(FPT-144P-M08)
22.00±0.20(.866±.008)SQ
*
20.00±0.10(.787±.004)SQ
109
Package width ×
package length
20.0 × 20.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
1.70 mm MAX
Weight 1.20g
Code
(Reference)
Note 1)*:Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
0.145±0.055
73108
72
(.006±.002)
P-LFQFP144-20×20-0.50
INDEX
144
1 36
LEAD No.
C
2003 FUJITSU LIMITED F144019S-c-4-6
0.50(.020)
0.22±0.05
(.009±.002)
0.08(.003)
0.08(.003)
Details of "A" part
+0.20
1.50
–0.10
(Mounting height)
+.008
.059
–.004
0.10±0.10
0˚~8˚
37
M
"A"
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
(.004±.004)
(Stand off)
0.25(.010)
8
CHAPTER 1 OVERVIEW OF THE MB91150
1.4 Pin Assignment
This section shows the MB91150 pin assignment for each type of package.
■ Pin assignment of MB91FV150 (PGA-299C-A01)
Figure 1.4-1 "MB91FV150 (PGA-299C-A01) pin assignment" shows the MB91FV150 (PGA299C-A01) pin assignment. Table 1.4-1 "Correspondence between pin numbers and pin names
(MB91FV150 (PGA-299C-A01)) (Device: MB91FV150, Package: PGA-299C-A01)" lists the
correspondences between pin numbers and pin names.
Figure 1.4-1 MB91FV150 (PGA-299C-A01) pin assignment
3
2
5
8
25
27
32
34
22
29
37
50
53
296299
292
298
4
10
13
6
16 11
15 12
19
18
23
24
26
33
3839
40 41 4243
444546 47 48
51
54 565758
55
60 61
270
274 275
277 278
293
280
283
286
289
284
287
291
297
285
290
295
300
288
294
1
7
9
14
17
2021
28
3031
35 36
64
264
265
267
266
262
263
261
259
260
268
276
279
281
282
269
271
272
273
PGA-299C-A01
(Bottom View)
254
258
256
255
253
247
251
249
246
244
257
248
242
241
238
252
243
239
236
232
245
250
240
237
235
226231
222
227
220
216
214
208
206
198
197
193
186
185
178
180
170 171
164
167
233
234
228229
223
217
213
210211
204
196
191192
188
181
174
168
230
225
215
212
209
205
201
194
190
189
183
176
173
224
221
218219
207
202
199
195
203
200
187
179
172
184
182
59
49
52
62
65
68 69
71
75
80
74
66
63
67
72
73
76
78 79
84
87
83
95
70
82
77
86
81
85
89
90
93
100 102
88
91
92
98
107
94
96
99
101
97
103
105
106
108
104
110
116
117
109
111
115
113
114
112
125 118
123
122
121
119
133
131
129
126
139
136
135
130
120
145
141
138
134
124
159
153
147
142
137
127128
165
162
157
161
156
151
148
154 155
140
144
132
143
169
166
163
160
150
146
177
175
158
152
149
9
CHAPTER 1 OVERVIEW OF THE MB91150
Table 1.4-1 Correspondence between pin numbers and pin names (MB91FV150 (PGA-299C-A01))
(Device: MB91FV150, Package: PGA-299C-A01)
No. Pin name No. Pin name No. Pin name No. Pin name No. Pin name No. Pin name
1 P20/D16 51 P81/BGRNT
2V
SS
3OPEN 53V
52 P82/BRQ 102 PK2/AN2 152 V
CC
4 P21/D17 54 P83/RD
5V
CC
55 P84/WR0 105 PK4/AN4 155 V
6 P22/D18 56 P85/WR1
7 P23/D19 57 P86/CLK 107 PK6/AN6 157 PE0/OC0 207 IHIT0 257 TDT33
8V
SS
58 PL0/DREQ0 108 PK7/AN7 158 V
9 P24/D20 59 PL1/DACK0 109 DAVC 159 PE1/OC1 209 OPEN 259 OPEN
10 P25/D21 60 PL2/DEOP0 110 DAVS 160 PE2/OC2 210 OPEN 260 OPEN
11 P26/D22 61 PL3/DREQ1 111 DA0 161 PE3/OC3 211 V
12 P27/D23 62 PL4/DACK1 112 V
13 P30/D24 63 PL5/DEOP1 113 DA1 163 PE5/OC5 213 MOD30 263 TDT38
14 P31/D25 64 PL6/DREQ2 114 DA2 164 PE6/OC6 214 MOD29 264 TDT39
15 P32/D26 65 PL7/DACK2 115 PH0/SIN0 165 PE7/OC7 215 MOD28 265 TDT40
16 P33/D27 66 OPEN 116 PH1/SOT0 166 V
17 P34/D28 67 OPEN 117 PH2/SCK0/T00 167 PF0/IN0 217 MOD26 267 TDT42
18 P35/D29 68 V
CC
19 P36/D30 69 OPEN 119 PI1/SOT1 169 PF2/IN2 219 MOD25 269 V
20 P37/D31 70 OPEN 120 PI2/SCK1/T01 170 PF3/IN3 220 MOD24 270 OPEN
21 P40/A00 71 V
22 V
CC
72 OPEN 122 PI4/SOT2 172 V
SS
23 P41/A01 73 OPEN 123 PI5/SCK2/T02 173 PG0/PPG0 223 MOD22 273 OPEN
24 P42/A02 74 V
CC
25 P43/A03 75 OPEN 125 V
26 P44/A04 76 MD0 126 PI4/SOT3 176 PG3/PPG3 226 MOD20 276 TDT49
27 P45/A05 77 MD1 127 PI5/SCK3/T03 177 PG4/PPG4 227 MOD19 277 TDT50
28 P46/A06 78 MD2 128 V
29 V
SS
30 P47/A07 80 V
79 V
CC
SS
31 P50/A08 81 X0 131 OPEN 181 OPEN 231 MOD16 281 OPEN
32 P51/A09 82 X1 132 OPEN 182 OPEN 232 MOD15 282 OPEN
33 P52/A10 83 V
CC
34 P53/A11 84 RST
35 P54/A12 85 OPEN 135 V
36 P55/A13 86 ICLK 136 PC0/INT0 186 OPEN 236 MOD12 286 V
37 V
CC
87 ICS0 137 PC1/INT1 187 V
38 P56/A14 88 ICS1 138 PC2/INT2 188 OPEN 238 MOD10 288 OPEN
39 P57/A15 89 ICS2 139 PC3/INT3 189 OPEN 239 MOD9 289 OPEN
40 P60/A16 90 ICD0 140 PC4/INT4/CS0 190 OPEN 240 V
41 P61/A17 91 ICD1 141 PC5/INT5/CS1 191 MCLK 241 MOD8 291 OPEN
42 P62/A18 92 ICD2 142 PC6/INT6/CS2 192 MRST
43 P63/A19 93 ICD3 143 V
44 P64/A20 94 BREAK 144 PC7/INT7/CS3 194 DHIT5 244 MOD5 294 OPEN
45 P65/A21 95 AV
CC
46 P66/A22 96 AVRH 146 V
47 P67/A23 97 V
SS
48 P80/RDY 98 AVRL 148 PD2/INT10/AIN1 198 DHIT1 248 MOD2 298 OPEN
49 V
50 V
CC
SS
99 AV
SS
100 PK0/AN0 150 PD3/INT11/BIN1 200 V
101 PK1/AN1 151 PD4/INT12/ZIN0 201 OPEN 251 OPEN
103 PK3/AN3 153 PD5/INT13/ZIN1 203 V
SS
202 OPEN 252 OPEN
CC
253 OPEN
104 OPEN 154 PD6/INT14/DEOP2 204 IHIT3 254 VCC5
CC
205 IHIT2 255 TDT31
106 PK5/AN5 156 PD7/INT15/ATG 206 IHIT1 256 TDT32
SS
SS
162 PE4/OC4 212 MOD31 262 V
CC
118 PI0/SIN1 168 PF1/IN1 218 V
121 PI3/SIN2 171 PF4 221 V
CC
124 PJ0/SIN3 174 PG1/PPG1 224 V
CC
SS
129 OPEN 179 V
175 PG2/PPG2 225 MOD21 275 VCC5
178 PG5/PPG5 228 MOD18 278 V
SS
130 OPEN 180 OPEN 230 V
133 PJ0/SCL 183 OPEN 233 V
208 OPEN 258 TDT34
CC
261 OPEN
SS
216 MOD27 266 TDT41
SS
CC
268 OPEN
3
CC
271 OPEN
222 MOD23 272 OPEN
SS
274 OPEN
SS
229 MOD17 279 OPEN
CC
SS
280 OPEN
283 OPEN
134 PJ1/SDA 184 OPEN 234 MOD14 284 OPEN
SS
185 OPEN 235 MOD13 285 OPEN
CC
CC
237 MOD11 287 OPEN
CC
290 OPEN
242 MOD7 292 OPEN
CC
193 V
CC
243 MOD6 293 V
CC
145 PD0/INT8/AIN0 195 DHIT4 245 MOD4 295 OPEN
SS
147 PD1/INT9/BIN0 197 DHIT2 247 V
149 V
CC
196 DHIT3 246 MOD3 296 V
SS
297 OPEN
199 DHIT0 249 MOD1 299 V
SS
250 MOD0 300 OPEN
SS
CC
10
CHAPTER 1 OVERVIEW OF THE MB91150
6
5
5PD6/DEOP2/
5/
G5
■ Pin assignments of MB91F155A, MB91155, MB91154 (FPT-144P-M08) and MB91F155A (FPT-144P-M01)
Figure 1.4-2 "Pin assignments of MB91F155A, MB91155, MB91154 (FPT-144P-M08) and
MB91F155A (FPT-144P-M01)" shows the MB91F155A, MB91155, MB91154 (FPT-144P-M08)
and MB91F155A (FPT-144P-M01) pin assignments.
Figure 1.4-2 Pin assignments of MB91F155A, MB91155, MB91154 (FPT-144P-M08) and
MB91F155A (FPT-144P-M01)
VSSX1A
X0A
TEST
VCCPK7/AN7
PK6/AN6
PK5/AN5
PK4/AN4
PK3/AN3
PK2/AN2
PK1/AN1
PK0/AN0
AVSSAVRL
AVRH
AVCCDAVC
DAVS
DA0
DA1
DA2
VCCPL7/DACK2
PL6/DREQ2
PL5/DEOP1
PL4/DACK1
PL3/DREQ1
PL2/DEOP0
PL1/DACK0
PL0/DREQ0
PH0/SIN0
PH1/SOT0
PH2/SCK0/TO0
PH3/SIN1
PH4/SOT1
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
P20/D16 1 108
P21/D17 2 107
P22/D18 3 106
P23/D19 4 105
P24/D20 5 104
P25/D21 6 103
P26/D22 7 102
P27/D23 8 101
V
P30/D24 10 99
P31/D25 11 98
P32/D26 12 97
P33/D27 13 96
P34/D28 14 95
P35/D29 15 94
P36/D30 16 93
P37/D31 17 92
P40/A00 18 91
P41/A01 19 90
P42/A02 20 89
P43/A03 21 88 PF2/IN2
P44/A04 22 87 PF1/IN1
P45/A05 23 86 PF0/IN0
P46/A06 24 85 PE7/OC7
P47/A07 25 84 PE6/OC6
V
V
P50/A08 28 81 PE3/OC3
P51/A09 29 80 PE2/OC2
P52/A10 30 79 PE1/OC1
P53/A11 31 78 PE0/OC0
P54/A12 32 77 V
P55/A13 33 7
P56/A14 34 7
P57/A15 35 74 P D
P60/A16 36 7
9 100
SS
Top View
FPT-144P-M08
26 83 PE5/OC5
SS
27 82 PE4/OC4
CC
3738394041424344454647484950515253545556575859606162636465666768697071
FPT-144P-M01
109
72
PH5/SCK1/TO1
PI0/SIN2
PI1/SOT2
PI2/SCK2/TO2
PI3/SIN3
PI4/SOT3
PI5/SCK3/TO3
V
SS
PJ0/SCL
PJ1/SDA
V
SS
V
CC
PG5/PPG5
PG4/PPG4
PG3/PPG3
PG2/PPG2
PG1/PPG1
PG0/PPG0
PF4
PF3/IN3
CC
PD7/ATG/INT1
ZIN1/INT13/TR
PD4
ZIN
INT12TR4
INT14
P61/A17
P62/A18
P63/A19
P64/A20
P65/A21
P66/A22
SS
V
P67/A23
P80/RDY
P81/BGRNT
P83/RD
P82/BRQ
P84/WR0
P86/CLK
P85/WR1
MD2
MD1
MD0
RST
SS
CC
X1
X0
V
V
PC0/INT0
PC1/INT1
PC2/INT2
PC3/INT3
PC4/INT4/CS0
CC
V
PC5/INT5/CS1
PC6/INT6/CS2
PC7/INT7/CS3
PD0/AIN0/INT8/TRG0
PD1/BIN0/INT9/TRG1
PD2/AIN1/INT10/TRG2
PD3/BIN1/INT11/TRG3
11
CHAPTER 1 OVERVIEW OF THE MB91150
1.5 Pin Functions
Table 1.5-1 "Functions of the MB91150 pins" lists the functions of the MB91150 pins.
■ Functions of the MB91150 pins
Table 1.5-1 Functions of the MB91150 pins
Pin No. Pin name Circuit type Function description
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
28
29
30
31
32
33
34
35
P20/D16
P21/D17
P22/D18
P23/D19
P24/D20
P25/D21
P26/D22
P27/D23
P30/D24
P31/D25
P32/D26
P33/D27
P34/D28
P35/D29
P36/D30
P37/D31
P40/A00
P41/A01
P42/A02
P43/A03
P44/A04
P45/A05
P46/A06
P47/A07
P50/A08
P51/A09
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
C External data bus bits 16 to 23
Effective only in external bus 16-bit mode.
Can be used as a port in single chip or external bus 8bit mode.
C External data bus bits 24 to 31
Can be used as a port in single chip mode.
F External address bus bits 0 to 15
Effective in external bus mode.
Can be used as a port in single chip mode.
12
CHAPTER 1 OVERVIEW OF THE MB91150
Table 1.5-1 Functions of the MB91150 pins (Continued)
Pin No. Pin name Circuit type Function description
36
37
38
39
40
41
42
43
P60/A16
P61/A17
P62/A18
P63/A19
P64/A20
P65/A21
P66/A22
P67/A23
O External address bus bits 16 to 23
Can be used as a port when the address bus is not
used.
45 P80/RDY C External RDY input
Effective when external RDYU input is enabled.
"0" is input if the bus cycle in progress fails to be
complete.
Can be used as a port when external RDY input is not
used.
46 P81/BGRNT
F External bus open acceptance output
Effective when external bus open acceptance output is
enabled.
Outputs L when the external bus is opened.
Can be used as a port when external bus open
acceptance output is disabled.
47 P82/BRQ C External bus open request input
Effective when external bus open request input is
enabled.
Input "1" to open the external bus.
Can be used as a port when external bus open
request input is disabled.
48 P83/RD
F External bus read strobe output
Effective when external bus read strobe output is
enabled.
Can be used as a port when external bus read strobe
output is disabled.
49 P84/WR0
F External bus write strobe output
Effective in external bus mode.
Can be used as a port in single chip mode.
50 P85/WR1
F External bus write strobe output
Effective when MB91150 is in external bus mode and
bus width is 16 bits.
Can be used as a port when MB91150 is in single chip
mode or 8-bit external bus mode.
51 P86/CLK F System clock output
Outputs a clock signal that is equal to the operating
frequency of the external bus. Can be used as a port
when the system clock is not used.
52
53
54
55 RST
MD2
MD1
MD0
G Connect these pins directly to V
These pins set the basic MCU operation mode.
Mode pins
B External reset input
or VSS.
CC
13
CHAPTER 1 OVERVIEW OF THE MB91150
Table 1.5-1 Functions of the MB91150 pins (Continued)
Pin No. Pin name Circuit type Function description
57
58
60
61
62
63
64
65
66
67
X1
X0
PC0/INT0
PC1/INT1
PC2/INT2
PC3/INT3
PC4/INT4/CS0
PC5/INT5/CS1
PC6/INT6/CS2
PC7/INT7/CS3
A High-speed clock oscillation pins (16.5 MHz)
H External interrupt request inputs 0 to 3
These inputs are always in use while the
corresponding external interrupts are enabled. Stop
port output in advance unless the resulting processing
is intentional.
This port can be used to release the standby status
because its input is enabled even during standby.
Can be used as a port when the pin is not used for
external interrupt request input.
H Used for both chip select outputs and external interrupt
request inputs 4 to 7
Can be used for external interrupt request input or as a
port when chip select output is disabled.
These inputs are always in use while the
corresponding external interrupts are enabled. Stop
port output in advance unless the resulting processing
is intentional.
This port can be used to release the standby status
because its input is enabled even during standby.
Can be used as a port when the pin is not used for
external interrupt request input and chip select output.
69
70
71
72
73
74
75 PD6/DEOP2/INT14 H External interrupt request input 14
PD0/AIN0/INT8/TRG0
PD1/BIN0/INT9/TRG1
PD2/AIN1/INT10/TRG2
PD3/BIN1/INT11/TRG3
PD4/ZIN0/INT12/TRG4
PD5/ZIN1/INT13/TRG5
H External interrupt request inputs 8 to 13
These inputs are always in use while the
corresponding external interrupts are enabled. Stop
port output in advance unless the resulting processing
is intentional.
[AIN, BIN] Up/down timer input
[TRG] PPG external trigger input
These inputs are always in use while they are enabled.
Stop port output in advance unless the resulting
processing is intentional.
Can be used as a timer when the pin is not used for
external interrupt request input, up/down timer input,
and PPG external trigger input.
This input is always in use while the corresponding
external interrupt is enabled. Stop port output in
advance unless the resulting processing is intentional.
[DEOP2] DMA external transfer end output
Effective when DMAC external transfer end output
specification is enabled.
Can be used as a port when the pin is not used for
external interrupt request input or DMA external
transfer end output.
14
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