FUJITSU MB90V460, MB90F462, MB90462, MB90467 DATA SHEET
查询MB90460供应商
FUJITSU SEMICONDUCTOR
DATA SHEET
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90460 Series
MB90462/467/F462/V460
DESCRIPTION
■■■■
The MB90460 series is a line of general-purpose, Fujitsu 16-bit microcontrollers designed for process control
applications which require high-speed real-time processing, such as consumer products.
While inheriting the AT architecture of the F
MB90460 series incorporates additional instructions for high-level languages, supports extended addressing
modes, and contains enhanced multiplication and division instructions as well as a substantial collection of
improved bit manipulation instructions. In addition, the MB90460 has an on-chip 32-bit accumulator which enab les
processing of long-word data.
The peripheral resources integrated in the MB90460 series include : an 8/10-bit A/D converter, UARTs (SCI) 0
to 1, 16-bit PPG timer, a multi-functional timer (16-bit free-run timer, input capture units (ICUs) 0 to 3, output
compare units (OCUs) 0 and 5, 16-bit PPG timer, a waveform generator) , a multi-pulse generator (16-bit PPG
timer, 16-bit reload timer, waveform sequencer) , PWC 0 to 1, 16-bit reload timer and DTP/external interrupt.
2
MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
* : F
2MC*
family, the instruction set for the F2MC-16LX CPU core of the
DS07-13714-1E
FEATURES
■■■■
• Minimum execution time : 62.5 ns/4 MHz oscillation (Uses PLL clock multiplication) maximum multiplier = 4
• Maximum memory space
16 Mbyte
Linear/bank access
PACKAGES
■■■■
64-pin plastic QFP 64-pin plastic LQFP 64-pin plastic SH-DIP
(FPT-64P-M06) (FPT-64P-M09) (DIP-64P-M01)
(Continued)
MB90460 Series
(Continued)
• Instruction set optimized for controller applications
Supported data types : bit, byte, word, and long-word types
Standard addressing modes : 23 types
32-bit accumulator enhancing high-precision operations
Signed multiplication/division and extended RETI instructions
• Enhanced high level language (C) and multi-tasking support instructions
Use of a system stack pointer
Symmetrical instruction set and barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced execution speed : 4 byte instruction queue
• Enhanced interrupt function
Up to eight programmable priority levels
External interrupt inputs : 8 lines
• Automatic data transmission function independent of CPU operation
Up to 16 channels for the extended intelligent I/O service
DTP request inputs : 8 lines
• Internal ROM
FLASH : 64 Kbyte (with flash security)
MASKROM : 64 Kbyte
• Internal RAM
EVA : 8 Kbyte
FLASH : 2 Kbyte
MASKROM : 2 Kbyte
• General-purpose ports
Up to 51 channels (Input pull-up resistor settable for : 16 channels)
• A/D Converter (RC) : 8 ch
8/10-bit resolution selectable
Conversion time : 6.13 µs (Min) , 16 MHz operation
• UART : 2 channels
• 16 bit PPG : 3 channels
Mode switching function provided (PWM mode or one-shot mode)
Can be worked with a multi-functional timer, a multi-pulse generator or individually
• 16 bit reload timer : 2 channels
Can be worked with multi-pulse generator or individually
• 16-bit PWC timer : 2 channels
• A multi-functional timer
Input capture : 4 channels
Output compare with selectable buffer : 6 channels
Free-run timer with up or up/down mode selection and selectable buffer : 1 channel
16-bit PPG : 1 channel
A waveform generator : (16-bit timer : 3 channels, 3-phase waveform or dead time)
• A multi-pulse generator
16-bit PPG : 1 channel
16-bit reload timer : 1 channel
Waveform sequencer : (16-bit timer with buffer and compare clear function)
• Time-base counter/watchdog timer : 18-bit
2
• Low-power consumption mode :
Sleep mode
Stop mode
CPU intermittent operation mode
• Package :
QFP-64 (FPT-64P-M09 : 0.65 mm pitch)
QFP-64 (FPT-64P-M06 : 1.00 mm pitch)
SDIP-64 (DIP-64P-M01 : 1.78 mm pitch)
•CMOS technology
MB90460 Series
3
MB90460 Series
PRODUCT LINEUP
■■■■
Part number
Item
Classification
ROM size 64 KBytes
RAM size 8 KBytes 2 KBytes
Number of Instruction : 351
Minimum execution time : 62.5 ns / 4 MHz (PLL × 4)
CPU function
I/O port I/O port (CMOS) : 51
PWC
UART
16-bit reload timer
16-bit PPG timer
Multi-functional
timer
(for AC/DC
motor control)
Multi-pulse
generator
(for DC motor control)
8/10-bit A/D
converter
DTP/External
interrupt
Lower power
consumption
Addressing mode : 23
Data bit length : 1, 8, 16 bits
Maximum memory space : 16 MBytes
Pulse width counter timer : 2 channels
Timer function (select the counter timer from three internal clocks)
Various Pulse width measuring function (H pulse width, L pulse width, rising edge to falling edge period, falling edge to rising edge period, rising edge to rising edge period and
falling edge to falling edge period)
UART : 2 channels
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized transmission (with start and stop bits) can
be selectively used
Transmission can be one-to-one (bi-directional commuication) or one-to-n (MasterSlave communication)
Reload timer : 2 channels
Reload mode, single-shot mode or event count mode selectable
Can be worked with a multi-pulse generator or individually
PPG timer : 3 channels PPG timer : 2ch
PWM mode or single-shot mode selectable
Can be worked with multi-functional timer / multi-pulse generator or individually
16-bit free-running timer with up or up/down mode selection and buffer : 1 channel
16-bit output compare : 6 channels
16-bit input capture : 4 channels
16-bit PPG timer : 1 channel
Waveform generator (16-bit timer : 3 channels, 3-phase waveform or dead time)
16-bit PPG timer : 1 channel
16-bit reload timer operation (toggle output, one shot output selectable)
Event counter function : 1 channel built-in
A waveform sequencer (includes 16-bit timer with buffer and compare clear function)
8/10-bit resolution (8 channels)
Conversion time : Less than 6.13 µS (16 MHz internal clock)
8 independent channels
Selectable causes : Rising edge, falling edge, “L” level or “H” level
Stop mode / Sleep mode / CPU intermittent operation mode
MB90V460 MB90F462 MB90462 MB90467
Development/evaluation
product
Mass-produced
products
(Flash ROM)
Mass-produced products
(Mask ROM)
Pulse width counter
timer : 1ch
(Continued)
4
(Continued)
Item
Package PGA256
Part number
MB90460 Series
MB90V460 MB90F462 MB90462 MB90467
LQFP-64 (FPT-64P-M09 : 0.65 mm pitch)
QFP-64 (FPT-64P-M06 : 1.00 mm pitch)
SDIP-64 (DIP-64P-M01 : 1.78 mm pitch)
Power supply voltage for
operation*
Process CMOS
* : V aries with conditions such as the operating frequency (See section “■ ELECTRICAL CHARA CTERISTICS”) .
Assurance for the MB90V460 is giv en only for operation with a tool at a power supply voltage of 4.5 V to 5.5 V,
an operating temperature of 0 to +25 °C, and an operating frequency of 1 MHz to 16 MHz.
PACKAGE AND CORRESPONDING PRODUCTS
■■■■
Package MB90V460 MB90F462 MB90462 MB90467
PGA256
FPT-64P-M09
FTP-64P-M06
DIP-64P-M01
: Available, : Not available
Note : For more information about each package, see section “■ PACKAGE DIMENSIONS”.
DIFFERENCES AMONG PRODUCTS
■■■■
Memory Size
×
×
×
×
4.5 V to 5.5 V *
×××
In evaluation with an evaluation product, note the difference between the evaluation product and the product
actually used. The following items must be taken into consideration.
• The MB90V460 does not have an internal ROM, ho wev er, operations equivalent to chips with an internal ROM
can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the
development tool.
• In the MB90V460, images from FF4000
mapped to bank FF only. (This setting can be changed by configuring the development tool.)
• In the MB90462/F462/467, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to
FF3FFF
H are mapped to bank FF only.
H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH are
5
MB90460 Series
PIN ASSIGNMENT
■■■■
(TOP VIEW)
P44/SNI1*
P45/SNI2*
P46/PPG2
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AV
AVR
AV
P60/SIN1
P61/SOT1
P62/SCK1
P63/INT7
MD0
CC
SS
2
P42/SCK0
P41/SOT0
P43/SNI0*
2
P40/SIN0
P37/PPG0
P36/PPG1*
/RTO5 (Z)
/RTO4 (W)
/RTO3 (Y)
/RTO2 (V)
1
P33*
1
P32*
/RTO1 (X)
1
P31*
1
1
VCC
P35*
P34*
C
64636261605958575655545352
2
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
/RTO0 (U)
P30*
V
SS
P27/IN3
P26/IN2
P25/IN1
P24/IN0
P23/PWO1
P22/PWI1
P21/TO1
P20/TIN1
P17/FRCK
P16/INT6/TO0
P15/INT5/TIN0
P14/INT4
P13/INT3
P12/INT2/DTTI1*
P11/INT1
P10/INT0/DTTI0
P07/PWO0*
2
2
20212223242526272829303132
*1 : Heavy current pins
*2 : MB90V460, MB90F462, MB90462 only.
They do not exist on MB90467, because there are not PWC (ch 0) , 16-bit PPG (ch 1) and waveform
sequencer.
6
RST
X0
MD2
X1
MD1
(FPT-64P-M06)
SS
V
2
2
/OPT0*
/OPT1*
1
1
P00*
P01*
2
2
/OPT2*
/OPT3*
1
1
P02*
P03*
2
2
/OPT4*
/OPT5*
1
1
P04*
P05*
2
P06/PWI0*
(Continued)
(TOP VIEW)
MB90460 Series
P45/SNI2*
P46/PPG2
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AV
AVR
AV
P60/SIN1
P61/SOT1
P62/SCK1
CC
SS
2
2
P43/SNI0*
P42/SCK0
P44/SNI1*
P41/SOT0
646362616059585756555453525150
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
171819202122232425262728293031
2
P40/SIN0
P37/PPG0
P36/PPG1*
C
/RTO5 (Z)
1
VCCP35*
/RTO4 (W)
/RTO3 (Y)
1
1
P34*
P33*
/RTO2 (V)
1
1
P32*
/RTO1 (X)
/RTO0 (U)
1
P31*
P30*
SS
V
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
P27/IN3
P26/IN2
P25/IN1
P24/IN0
P23/PWO1
P22/PWI1
P21/TO1
P20/TIN1
P17/FRCK
P16/INT6/TO0
P15/INT5/TIN0
P14/INT4
P13/INT3
P12/INT2/DTTI1*
P11/INT1
P10/INT0/DTTI0
2
2
2
2
2
2
/OPT3*
/OPT4*
1
1
P03*
P04*
2
/OPT5*
1
P06/PWI0
P05*
P07/PWO0
RST
MD0
P63/INT7
MD1
MD2
X0
X1
SS
V
/OPT0*
/OPT1*
1
1
P00*
P01*
/OPT2*
1
P02*
(FPT-64P-M09)
*1 : Heavy current pins
*2 : MB90V460, MB90F462, MB90462 only.
They do not exist on MB90467, because there are not PWC (ch 0) , 16-bit PPG (ch 1) and waveform
sequencer.
(Continued)
7
MB90460 Series
(Continued)
(TOP VIEW)
P36/PPG1*
P37/PPG0
P40/SIN0
P41/SOT0
P42/SCK0
P43/SNI0*
P44/SNI1*
P45/SNI2*
P46/PPG2
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AV
AVR
AVSS
P60/SIN1
P61/SOT1
P62/SCK1
P63/INT7
MD0
RST
MD1
MD2
V
CC
X0
X1
SS
C
2
1
2
3
4
5
2
2
2
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V
CC
P35*1/RTO5 (Z)
P34*1/RTO4 (W)
1
P33*
/RTO3 (Y)
P32*1/RTO2 (V)
1
P31*
/RTO1 (X)
P30*1/RTO0 (U)
VSS
P27/IN3
P26/IN2
P25/IN1
P24/IN0
P23/PWO1
P22/PWI1
P21/TO1
P20/TIN1
P17/FRCK
P16/INT6/TO0
P15/INT5/TIN0
P14/INT4
P13/INT3
P12/INT2/DTTI1*
P11/INT1
P10/INT0/DTTI0
P07/PWO0*
P06/PWI0*
P05*1/OPT5*
P04*1/OPT4*
P03*1/OPT3*
P02*1/OPT2*
P01*1/OPT1*
P00*1/OPT0*
2
2
2
2
2
2
2
2
2
*1 : Heavy current pins
*2 : MB90V460, MB90F462, MB90462 only.
They do not exist on MB90467, because there are not PWC (ch 0) , 16-bit PPG (ch 1) and waveform
sequencer.
8
(DIP-64P-M01)
PIN DESCRIPTION
■■■■
MB90460 Series
Pin No.
QFP-
M06*
2
LQFP-
M09*
1
SDIP*
Pin
name
3
I/O
circuit
23, 24 22, 23 30, 31 X0, X1 A Oscillation input pins.
20 19 27 RST
P00 to
26 to 3125 to 3033 to
38
OPT0 to
OPT5
P05
*
B External reset input pin.
General-purpose I/O ports.
Output terminals OPT0 to 5 of the waveform sequencer.
D
These pins output the waveforms specified at the output data
4
registers of the waveform sequencer circuit. Output is generated
when OPE0 to 5 of OPCR is enabled.
32 31 39
33 32 40
34 33 41
P06
PWI0
P07
PWO0
P10
INT0
DTTI0
4
*
4
*
General-purpose I/O ports.
E
PWC 0 signal input pin.
General-purpose I/O ports.
E
PWC 0 signal output pin.
General-purpose I/O ports.
Can be used as interrupt request input channels 0. Input is en-
C
abled when 1 is set in EN0 in standby mode.
RTO0 to 5 pins for fixed-level input. This function is enabled
when the waveform generator enables its input bits.
Function
4
*
4
*
4
*
35 34 42
36 35 43
37 to 3836 to 3744 to
45
39 38 46
P11
INT1
P12
INT2
DTTI1
P13 to
P14
4
*
General-purpose I/O ports.
C
Can be used as interrupt request input channels 1. Input is enabled when 1 is set in EN1 in standby mode.
General-purpose I/O ports.
Can be used as interrupt request input channels 2. Input is en-
C
abled when 1 is set in EN2 in standby mode.
OPT0 to 5 pins for fixed-level input. This function is enabled
when the waveform sequencer enables its input bit.
General-purpose I/O ports.
C
INT3 to
INT4
P15
INT5
Can be used as interrupt request input channels 3 to 4.
Input is enabled when 1 is set in EN3 to EN4 in standby mode.
General-purpose I/O ports.
Can be used as interrupt request input channel 5. Input is en-
C
abled when 1 is set in EN5 in standby mode.
TIN0 External clock input pin for reload timer 0.
4
*
(Continued)
9
MB90460 Series
Pin No.
2
LQFP-
M09*
1
SDIP*
QFP-
M06*
40 39 47
41 40 48
42 41 49
43 42 50
44 43 51
45 44 52
46 to 4945 to 4853 to
56
51 to 5650 to 5558 to
63
Pin
name
3
P16
INT6
I/O
circuit
C
Function
General-purpose I/O ports.
Can be used as interrupt request input channels 6. Input is en-
abled when 1 is set in EN6 in standby mode.
TO0 Event output pin for reload timer 0.
P17
General-purpose I/O ports.
C
FRCK External clock input pin for free-running timer.
P20
General-purpose I/O ports.
F
TIN1 External clock input pin for reload timer 1.
P21
General-purpose I/O ports.
F
TO1 Event output pin for reload timer 1.
P22
General-purpose I/O ports.
F
PWI1 PWC 1 signal input pin.
P23
General-purpose I/O ports.
F
PWO1 PWC 1 signal output pin.
P24 to
P27
IN0 to
IN3
General-purpose I/O ports.
Trigger input pins for input capture channels 0 to 3.
F
When input capture channels 0 to 3 are used for input operation,
these pins are enabled as required and must not be used for any
other I/P.
P30 to
P35
RTO0 (U)
to
RTO5 (Z)
General-purpose I/O ports.
Waveform generator output pins. These pins output the wave-
G
forms specified at the waveform generator. Output is generated
when waveform generator output is enabled. (U) to (Z) show the
coils that control 3-phase motor.
59 58 2
60 59 3
61 60 4
62 61 5
10
P36
PPG1
P37
PPG0
P40
SIN0
P41
SOT0
General-purpose I/O ports.
H
4
*
Output pins for PPG channels 1. This function is enabled when
PPG channels 1 enable output.
4
*
General-purpose I/O ports.
H
Output pins for PPG channels 0. This function is enabled when
PPG channels 0 enable output.
General-purpose I/O ports.
Serial data input pin for UART channel 0. While UART channel
F
0 is operating for input, the input of this pin is used as required
and must not be used for any other input.
General-purpose I/O ports.
F
Serial data output pin for UART channel 0. This function is enabled when UART channel 0 enables data output.
(Continued)
Pin No.
QFP-
2
M06*
LQFP-
M09*
1
SDIP*
MB90460 Series
(Continued)
Pin
name
3
I/O
circuit
Function
63 62 6
64 63 7
1648
219
3210
4 to 11 3 to 10
11 to
18
P42
SCK0
P43
SNI0
*
P44
SNI1
*
P45
SNI2
*
P46
PPG2
P50 to
P57
AN0 to
AN7
General-purpose I/O ports.
F
Serial clock I/O pin for UART channel 0. This function is enabled
when UART channel 0 enables clock output.
General-purpose I/O ports.
Trigger input pins for position detection of the waveform se-
4
F
quencer. When this pin is used for input operation, it is enabled
as required and must not be used for any other I/P.
4
*
General-purpose I/O ports.
Trigger input pins for position detection of the Multi-pulse gener-
4
F
ator. When this pin is used for input operation, it is enabled as
required and must not be used for any other I/P.
*
4
General-purpose I/O ports.
Trigger input pins for position detection of the Multi-pulse gener-
4
F
ator. When this pin is used for input operation, it is enabled as
required and must not be used for any other I/P.
*
4
General-purpose I/O ports.
F
Output pins for PPG channel 2. This function is enabled when
PPG channel 2 enables output.
General-purpose I/O ports.
I
A/D converter analog input pins. This function is enabled when
the analog input specification is enabled. (ADER) .
12 11 19 AV
CC VCC power input pin for analog circuits.
Reference voltage (+) input pin for the A/D converter. This volt-
13 12 20 AVR
age must not exceed V
fixed to AV
SS.
CC and AVCC. Reference voltage (−) is
14 13 21 AVSS VSS power input pin for analog circuits.
P60
15 14 22
SIN1
General-purpose I/O ports.
Serial data input pin for UART channel 1. While UART channel
F
1 is operating for input, the input of this pin is used as required
and must not be used for any other in-put.
P61
16 15 23
SOT1
General-purpose I/O ports.
F
Serial data output pin for UART channel 1. This function is enabled when UART channel 1 enables data output.
(Continued)
11
MB90460 Series
(Continued)
QFP-
M06*
Pin No.
2
LQFP-
M09*
1
SDIP*
Pin
name
3
I/O
circuit
Function
P62
17 16 24
SCK1
P63
18 17 25
INT7
19 18 26 MD0 J
21, 22 20, 21 28, 29
25, 50 24, 49 32, 57 V
57 56 64 V
MD1,
MD2
SS Power (0 V) input pin.
CC Power (5 V) input pin.
58 57 1 C
General-purpose I/O port.
F
Serial clock I/O pin for UART channel 1. This function is enabled
when UART channel 1 enables clock output.
General-purpose I/O port.
F
Usable as interrupt request input channel 7. Input is enabled
when 1 is set in EN7 in standby mode.
Input pin for operation mode specification. Connect this pin directly to V
Input pin for operation mode specification. Connect this pin di-
J
rectly to VCC or VSS.
CC or VSS.
Capacity pin for power stabilization. Please connect to an approximately 0.1 µF ceramic capacitor.
*1 : FPT-64P-M09
*2 : FPT-64P-M06
*3 : DIP-64P-M01
*4 : MB90V460, MB90F462, MB90462 only.
They do not exist on MB90467, because there are not PWC (ch 0) , 16-bit PPG (ch 1) and w avef orm sequencer.
12
MB90460 Series
I/O CIRCUIT TYPE
■■■■
Classification Type Remarks
X1
N-ch P-ch
X0
A
B
R
R
C
P-ch
P-ch
N-ch
Pull up control
P-ch
N-ch
Standby mode control
Pout
Nout
Xout
Main clock (main clock crystal
oscillator)
• At an oscillation feedback
resistor of approximately
1 MΩ
• Hysteresis input
• Pull-up resistor
approximately 50 kΩ
• CMOS output
• Hysteresis input
• Selectable pull-up resistor
approximately 50 kΩ
•I
OL = 4 mA
• Standby control available
Hysteresis input
Standby mode control
• CMOS output
R
P-ch
D
Pull up control
P-ch
N-ch
Pout
Nout
CMOS input
Standby mode control
• CMOS input
• Selectable pull-up resistor
approximately 50 kΩ
• Standby control available
•I
OL = 12 mA
(Continued)
13
MB90460 Series
Classification Type Remarks
• CMOS output
R
P-ch
E
P-ch
N-ch
Pull up control
P-ch
N-ch
Pout
Nout
CMOS input
Standby mode control
Pout
Nout
F
• CMOS input
• Selectable pull-up resistor
approximately 50 kΩ
• Standby control available
•I
OL = 4 mA
• CMOS output
• Hysteresis input
• Standby control available
OL = 4 mA
•I
Hysteresis input
Standby mode control
• CMOS output
P-ch
N-ch
Pout
Nout
• CMOS input
• Standby control available
OL = 12 mA
•I
G
CMOS input
Standby mode control
• CMOS output
P-ch
N-ch
Pout
Nout
• CMOS input
• Standby control available
OL = 4 mA
•I
H
CMOS input
14
Standby mode control
(Continued)
MB90460 Series
(Continued)
Classification Type Remarks
• CMOS output
P-ch
N-ch
Pout
Nout
I
CMOS input
Analog input control
Analog input
J
• CMOS input
• Analog input
•I
OL = 4 mA
• Hysteresis input
15
MB90460 Series
HANDLING DEVICES
■■■■
1. Preventing Latchup
CMOS ICs may cause latchup in the following situations :
• When a voltage higher than V
• When a voltage exceeding the rating is applied between VCC and VSS.
• When AV
CC power is supplied prior to the VCC voltage.
If latchup occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the
device. Use meticulous care not to let it occur.
For the same reason, also be careful not to let the analog power-supply v oltage e xceed the digital pow er-supply
voltage.
2. Handling unused input pins
Unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage. Unused
input pins should be pulled up or pulled down through at least 2 kΩ resistance.
Unused input/output pins may be left open in the output state, b ut if such pins are in the input state the y should
be handled in the same way as input pins.
3. Use of the external clock
CC or lower than VSS is applied to input or output pins.
When the device uses an e xternal clock, drive only the X0 pin while leaving the X1 pin open (See the illustr ation
below) .
MB90460 series
X0
Open
X1
4. Power Supply Pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to
avoid abnormal operations including latch-up. However, connect the pins exter nal power and ground lines to
lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in
the ground level, and to conform to the total current rating.
Make sure to connect V
It is recommended to provide a bypass capacitor of around 0.1 µF between V
CC and VSS pins via the lowest impedance to power lines.
CC and VSS pins near the device.
5. Crystal Oscillator Circuit
Noise around X0 or X1 pins may cause abnormal operations. Make sure to provide bypass capacitors via the
shortest distance from X0, X1 pins, cr ystal oscillator (or ceramic resonator) and ground lines, and make sure,
to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with the ground
area for stabilizing the operation.
6. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVSS, AVR) and analog inputs (AN0 to AN7) after
turning-on the digital power supply (V
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage of A VR dose not exceed A V
is acceptable) .
16
CC) .
CC (turning on/off the analog and digital power supplies simultaneously
MB90460 Series
7. Connection of Unused Pins of A/D Converter
Connect unused pin of A/D converter to AVCC = VCC, AVSS = AVR = VSS.
8. N.C. Pin
The N.C. (internally connected) pin must be opened for use.
9. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50
µs or more.
10. Initialization
In the device, there are internal registers which are initialized only by a pow er-on reset. T o initialize these registers,
please turn on the power again.
11. Return from standby state
If the power-supply voltage goes below the standby RAM holding voltage in the standby state, the device may
fail to return from the standby state. In this case, reset the de vice via the external reset pin to return to the normal
state.
17
MB90460 Series
BLOCK DIAGRAM
■■■■
P11/INT1
P13/INT3 to
P14/INT4
P40/SIN0
P41/SOT0
P42/SCK0
P36/PPG1
P15/INT5/TIN0
P16/INT6/TO0
P43/SNI0∗2 to
P45/SNI2
P00/OPT0
P01/OPT1
P02/OPT2
P03/OPT3
P04/OPT4
P05/OPT5
P12/INT2/DTTI1
P06/PWI0
P07/PWO0
P46/PPG2
X0
X1
RST
∗2
∗2
∗2
∗2
∗2
∗2
∗2
∗2
∗2
∗2
∗2
Clock control
circuit
Reset circuit
(Watch-dog timer)
Interrupt controller
2
3
8
DTP/External interrupt
UART
(Ch0)
Multi-pulse Generator
16-bit PPG
16-bit reload timer
3
Waveform
sequencer
16-bit PPG
(Ch1)
(Ch0)
PWC
(Ch0)
(Ch2)
F2MC-16LX series core
∗2
∗1
∗1
∗1
CPU
MC-16LX Bus
2
F
Timebase timer
Delayed interrupt generator
Multi-functional Timer
16-bit PPG
(Ch0)
16-bit input capture
(Ch0/1/2/3)
16-bit free-run
timer
16-bit output
compare
(Ch0 to 5)
Waveform
generator
16-bit reload timer
(Ch1)
(Ch1)
UART
(Ch1)
CMOS I/O port 1, 2, 3, 6
Other pins
SS × 2, VCC × 1, MD0-2, C
V
44
PWC
P37/PPG0
P24/IN0 to
P27/IN3
P17/FRCK
P30/RTO0 (U)
P31/RTO1 (X)
P32/RTO2 (V)
P33/RTO3 (Y)
P34/RTO4 (W)
P35/RTO5 (Z)
P10/INT0/DTTI0
P20/TIN1
P21/TO1
P22/PWI1
P23/PWO1
P60/SIN1
P61/SOT1
P62/SCK1
P63/INT7
CMOS I/O port 0, 1, 3, 4
RAM
ROM
ROM correction
ROM mirroring
CMOS I/O port 5
A/D converter
(8/10 bit)
8
Note : P00 to P07 (8 channels) : With registers that can be used
as input pull-up resistors
P10 to P17 (8 channels) : With registers that can be used as input pull-up resistors
*1: Only MB90V460, MB90F462 and MB90462 have PWC (ch 0) , 16-bit PPG (ch 1) and w aveform sequencer .
They do not exist on MB90467.
*2: The multi-pulse generator function can be used only by MB90V460, MB90F462 and MB90462.
This function can not be used by MB90467.
18
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AV
CC
AVR
AV
SS
MEMORY MAP
■■■■
Address #1
Address #2
FFFFFFH
FC0000
010000H
MB90460 Series
ROM area
H
ROM area
(FF bank image)
: Internal access memory
: Access not allowed
004000H
003FE0H
Address #3
000100H
0000C0H
000000H
Peripheral area
RAM
Register
area
Peripheral area
In Single chip mode
the mirror function
is supported
Parts No. Address#1 Address#2 Address#3
MB90462/467 FF0000
H 004000H 000900H
MB90F462 FF0000H 004000H 000900H
MB90V460 (FF0000H) 004000H 002100H
Note : The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C
compiler small model. The lower 16-bit is assigned to the same address, enabling ref erence of the tab le on
the ROM without stating “far”. F o r e xample, if an attempt has been made to access 00C000
of the ROM at FFC000
H are accessed actually. Since the ROM area of the FF bank exceeds 48 Kbytes, the
whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000
therefore, as if it were the image f or 004000
be stored in the area of FF4000
H to FFFFFFH.
H to 00FFFFH. Thus, it is recommended that the ROM data table
H , the contents
H to FFFFFFH looks,
19
MB90460 Series
I/O MAP
■■■■
Address
000000
Abbrevia-
tion
H PDR0 Port 0 data register R/W R/W Port 0 XXXXXXXXB
Register
Byte
access
Word
access
Resource
name
Initial value
000001H PDR1 Port 1 data register R/W R/W Port 1 XXXXXXXXB
000002H PDR2 Port 2 data register R/W R/W Port 2 XXXXXXXXB
000003H PDR3 Port 3 data register R/W R/W Port 3 XXXXXXXXB
000004H PDR4 Port 4 data register R/W R/W Port 4 -XXXXXXXB
000005H PDR5 Port 5 data register R/W R/W Port 5 XXXXXXXXB
000006H PDR6 Port 6 data register R/W R/W Port 6 ----XXXXB
000007H Prohibited area
000008
H PWCSL0
R/W R/W
00000000B
PWC control status register CH0
000009H PWCSH0 R/W R/W 00000000B
00000AH
PWC0 PWC data buffer register CH0 R/W
PWC timer
(CH0)
XXXXXXXX
00000BH XXXXXXXXB
00000CH DIV0 Divide ratio control register CH0 R/W R/W ------00B
00000DH
to 0F
H
000010
H DDR0 Port 0 direction register R/W R/W Port 0 00000000B
Prohibited area
B
000011H DDR1 Port 1 direction register R/W R/W Port 1 00000000B
000012H DDR2 Port 2 direction register R/W R/W Port 2 00000000B
000013H DDR3 Port 3 direction register R/W R/W Port 3 00000000B
000014H DDR4 Port 4 direction register R/W R/W Port 4 -0000000B
000015H DDR5 Port 5 direction register R/W R/W Port 5 00000000B
000016H DDR6 Port 6 direction register R/W R/W Port 6 ----0000B
000017H ADER Analog input enable register R/W R/W Port 5, A/D 11111111B
000018H Prohibited area
000019
H CDCR0 Clock division control register 0 R/W R/W
Communication
prescaler 0
0---0000B
00001AH Prohibited area
00001BH CDCR1 Clock division control register 1 R/W R/W
Communication
prescaler 1
0---0000B
00001CH RDR0 Port 0 pull-up resistor setting register R/W R/W Port 0 00000000B
00001DH RDR1 Port 1 pull-up resistor setting register R/W R/W Port 1 00000000B
00001EH
to 1F
H
Prohibited area
(Continued)
20
MB90460 Series
Address
000020
Abbrevia-
tion
H SMR0 Serial mode register 0 R/W R/W
Register
Byte
access
Word
access
Resource
name
Initial value
00000000B
000021H SCR0 Serial control register 0 R/W R/W 00000100B
000022H
SIDR0 /
SODR0
Input data register 0 /
output data register 0
R/W R/W XXXXXXXXB
UART0
000023H SSR0 Serial status register 0 R/W R/W 00001000B
000024H SMR1 Serial mode register 1 R/W R/W
00000000B
000025H SCR1 Serial control register 1 R/W R/W 00000100B
000026H
SIDR1 /
SODR1
Input data register 1 /
output data register 1
R/W R/W XXXXXXXXB
UART1
000027H SSR1 Status register 1 R/W R/W 00001000B
000028H PWCSL1
R/W R/W
00000000B
PWC control status register CH1
000029H PWCSH1 R/W R/W 00000000B
00002AH
PWC1 PWC data buffer register CH1 R/W
PWC timer
(CH1)
XXXXXXXX
00002BH XXXXXXXXB
00002CH DIV1 Divide ratio control register CH1 R/W R/W ------00B
00002DH
to 2F
H
Prohibited area
B
000030
H ENIR Interrupt / DTP enable register R/W R/W
00000000B
000031H EIRR Interrupt / DTP cause register R/W R/W XXXXXXXXB
000032H ELVRL
000033H ELVRH
Request level setting register
(Lower Byte)
Request level setting register
(Higher Byte)
R/W R/W 00000000B
R/W R/W 00000000B
000034H ADCS0 A/D control status register 0 R/W R/W
000035H ADCS1 A/D control status register 1 R/W R/W 00000000B
000036H ADCR0 A/D data register 0 R R XXXXXXXXB
DTP/external
interrupt
00000000B
8/10-bit A/D
converter
000037H ADCR1 A/D data register 1 R/W R/W 00000-XXB
000038H
11111111
B
PDCR0 PPG0 down counter register R
000039H 11111111B
00003AH
00003BH XXXXXXXXB
PCSR0 PPG0 period setting register W
16-bit
XXXXXXXX
PPG timer
00003CH
PDUT0 PPG0 duty setting register W
(CH0)
XXXXXXXX
00003DH XXXXXXXXB
00003EH PCNTL0
R/W R/W --000000B
PPG0 control status register
00003FH PCNTH0 R/W R/W 00000000B
(Continued)
B
B
21
MB90460 Series
Address
000040
Abbrevia-
H
tion
Register
Byte
access
Word
access
Resource
name
Initial value
11111111
B
PDCR1 PPG1 down counter register R
000041H 11111111B
000042H
000043H XXXXXXXXB
PCSR1 PPG1 period setting register W
16-bit
XXXXXXXX
PPG timer
000044H
PDUT1 PPG1 duty setting register W
(CH1)
XXXXXXXX
000045H XXXXXXXXB
000046H PCNTL1
R/W R/W --000000B
PPG1 control status register
000047H PCNTH1 R/W R/W 00000000B
000048H
11111111
B
PDCR2 PPG2 down counter register R
000049H 11111111B
00004AH
00004BH XXXXXXXXB
PCSR2 PPG2 period setting register W
16-bit
XXXXXXXX
PPG timer
00004CH
PDUT2 PPG2 duty setting register W
(CH2)
XXXXXXXX
00004DH XXXXXXXXB
00004EH PCNTL2
R/W R/W --000000B
PPG2 control status register
00004FH PCNTH2 R/W R/W 00000000B
B
B
B
B
000050H
XXXXXXXX
TMRR0 16-bit timer register 0 R/W
000051H XXXXXXXXB
000052H
XXXXXXXX
TMRR1 16-bit timer register 1 R/W
000053H XXXXXXXXB
000054H
TMRR2 16-bit timer register 2 R/W
000055H XXXXXXXXB
Waveform
generator
XXXXXXXX
000056H DTCR0 16-bit timer control register 0 R/W R/W 00000000B
000057H DTCR1 16-bit timer control register 1 R/W R/W 00000000B
000058H DTCR2 16-bit timer control register 2 R/W R/W 00000000B
000059H SIGCR Waveform control register R/W R/W 00000000B
00005AH
00005BH 11111111B
00005CH
00005DH 00000000B
CPCLRB /
CPCLR
Compare clear buffer register /
Compare clear register (lower)
R/W
TCDT Timer data register (lower) R/W
16-bit
free-running
timer
11111111
00000000
00005EH TCCSL Timer control status register (lower) R/W R/W 00000000B
00005FH TCCSH Timer control status register (upper) R/W R/W -0000000B
(Continued)
B
B
B
B
B
22
MB90460 Series
Address
000060
Abbrevia-
H
tion
Register
Byte
access
Word
access
Resource
name
Initial value
XXXXXXXX
IPCP0 Input capture data register CH0 R
000061H XXXXXXXXB
000062H
XXXXXXXX
IPCP1 Input capture data register CH1 R
000063H XXXXXXXXB
000064H
XXXXXXXX
IPCP2 Input capture data register CH2 R
000065H XXXXXXXXB
000066H
IPCP3 Input capture data register CH3 R
000067H XXXXXXXXB
000068H PICSL01
000069H PICSH01
00006AH ICSL23
00006BH ICSH23
00006CH
to 6E
H
PPG output control / Input capture
control status register 01 (lower)
PPG output control / Input capture
control status register 01 (upper)
Input capture control status register
23 (lower)
Input capture control status register
23 (upper)
Prohibited area
R/W R/W 00000000B
R/W R/W 00000000B
R/W R/W 00000000B
R R ------00B
16-bit
input capture
(CH0 to CH3)
XXXXXXXX
B
B
B
B
00006F
000070H
000071H XXXXXXXXB
000072H
000073H XXXXXXXXB
000074H
000075H XXXXXXXXB
000076H
000077H XXXXXXXXB
000078H
000079H XXXXXXXXB
00007AH
00007BH XXXXXXXXB
H ROMM
OCCPB0/
OCCP0
OCCPB1/
OCCP1
OCCPB2/
OCCP2
OCCPB3/
OCCP3
OCCPB4/
OCCP4
OCCPB5/
OCCP5
ROM mirroring function selection
register
Output compare buffer register /
output compare register 0
Output compare buffer register /
output compare register 1
Output compare buffer register /
output compare register 2
Output compare buffer register /
output compare register 3
Output compare buffer register /
output compare register 4
Output compare buffer register /
output compare register 5
WW
R/W
R/W
R/W
R/W
R/W
R/W
ROM mirroring
function
Output compare
(CH0 to CH5)
-------1B
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
(Continued)
B
B
B
B
B
B
23
MB90460 Series
Address
00007C
Abbrevia-
tion
H OCS0 Compare control register 0 R/W R/W
Register
Byte
access
Word
access
Resource
name
Initial value
00000000B
00007DH OCS1 Compare control register 1 R/W R/W -0000000B
00007EH OCS2 Compare control register 2 R/W R/W 00000000B
00007FH OCS3 Compare control register 3 R/W R/W -0000000B
Output compare
(CH0 to CH5)
000080H OCS4 Compare control register 4 R/W R/W 00000000B
000081H OCS5 Compare control register 5 R/W R/W -0000000B
000082H TMCSRL0
000083H TMCSRH0
Timer control status register CH0
(lower)
Timer control status register CH0
(upper)
R/W R/W
00000000B
16-bit
R/W R/W ----0000B
reload timer
(CH0)
000084H
000085H XXXXXXXXB
000086H TMCSRL1
000087H TMCSRH1
000088H
000089H XXXXXXXXB
TMR0 /
TMRD0
TMR1 /
TMRD1
16 bit timer register CH0 /
16-bit reload register CH0
Timer control status register CH1
(lower)
Timer control status register CH1
(upper)
16 bit timer register CH1 /
16-bit reload register CH1
R/W
R/W R/W
R/W R/W ----0000B
16-bit reload
timer (CH1)
R/W
XXXXXXXX
00000000B
XXXXXXXX
B
B
00008AH OPCLR Output control lower register R/W R/W
00000000B
00008BH OPCUR Output control upper register R/W R/W 00000000B
00008CH IPCLR Input control lower register R/W R/W 00000000B
00008DH IPCUR Input control upper register R/W R/W 00000000B
Waveform
sequencer
00008EH TCSR Timer control status register R/W R/W 00000000B
00008FH NCCR Noise cancellation control register R/W R/W 00000000B
000090H
to 9D
H
00009E
H PACSR
00009FH DIRR
0000A0H LPMCR
Program address detect control
status register
Delayed interrupt cause /
clear register
Low-power consumption mode
register
0000A1H CKSCR Clock selection register R/W R/W 11111100B
0000A2H
to A7
H
Prohibited area
R/W R/W Rom correction 00000000B
R/W R/W
R/W R/W
Prohibited area
Delayed
interrupt
Low-power
consumption
control register
-------0B
00011000B
0000A8H WDTC Watchdog control register R/W R/W Watchdog timer X-XXX111B
0000A9H TBTC Timebase timer control register R/W R/W Timebase timer 1--00100B
(Continued)
24
MB90460 Series
Address
0000AA
to AD
H
0000AE
Abbrevia-
tion
H
H FMCS
Register
Prohibited area
Flash memory control status
register
Byte
access
access
R/W R/W
Word
Resource
name
Flash memory
interface circuit
Initial value
00010000B
0000AFH Prohibited area
0000B0H ICR00 Interrupt control register 00 R/W R/W
00000111B
0000B1H ICR01 Interrupt control register 01 R/W R/W 00000111B
0000B2H ICR02 Interrupt control register 02 R/W R/W 00000111B
0000B3H ICR03 Interrupt control register 03 R/W R/W 00000111B
0000B4H ICR04 Interrupt control register 04 R/W R/W 00000111B
0000B5H ICR05 Interrupt control register 05 R/W R/W 00000111B
0000B6H ICR06 Interrupt control register 06 R/W R/W 00000111B
0000B7H ICR07 Interrupt control register 07 R/W R/W 00000111B
0000B8H ICR08 Interrupt control register 08 R/W R/W 00000111B
Interrupt
controller
0000B9H ICR09 Interrupt control register 09 R/W R/W 00000111B
0000BAH ICR10 Interrupt control register 10 R/W R/W 00000111B
0000BBH ICR11 Interrupt control register 11 R/W R/W 00000111B
0000BCH ICR12 Interrupt control register 12 R/W R/W 00000111B
0000BDH ICR13 Interrupt control register 13 R/W R/W 00000111B
0000BEH ICR14 Interrupt control register 14 R/W R/W 00000111B
0000BFH ICR15 Interrupt control register 15 R/W R/W 00000111B
0000C0H
to FF
H
001FF0
H PADR0L
001FF1H PADR0M
001FF2H PADR0H
Program address detection
register 0 (Lower Byte)
Program address detection
register 0 (Middle Byte)
Program address detection
register 0 (Higher Byte)
External area
R/W R/W
R/W R/W XXXXXXXXB
R/W R/W XXXXXXXXB
XXXXXXXXB
Rom correction
001FF3H PADR1L
001FF4H PADR1M
001FF5H PADR1H
Program address detection
register 1 (Lower Byte)
Program address detection
register 1 (Middle Byte)
Program address detection
register 1 (Higher Byte)
R/W R/W XXXXXXXXB
R/W R/W XXXXXXXXB
R/W R/W XXXXXXXXB
(Continued)
25
MB90460 Series
(Continued)
Address
Abbrevia-
tion
Register
Byte
access
Word
access
Resource
name
Initial value
003FE0
H
00000000
OPDBR0 Output data buffer register 0 R/W
003FE1H 00000000B
003FE2H
00000000
OPDBR1 Output data buffer register 1 R/W
003FE3H 00000000B
003FE4H
00000000
OPDBR2 Output data buffer register 2 R/W
003FE5H 00000000B
003FE6H
00000000
OPDBR3 Output data buffer register 3 R/W
003FE7H 00000000B
003F78H
00000000
OPDBR4 Output data buffer register 4 R/W
003FE9H 00000000B
003FEAH
00000000
OPDBR5 Output data buffer register 5 R/W
003FEBH 00000000B
003FECH
00000000
OPEBR6 Output data buffer register 6 R/W
003FEDH 00000000B
003FEEH
OPEBR7 Output data buffer register 7 R/W
003FEFH 00000000B
Waveform
sequencer
003FF0H
00000000
00000000
OPEBR8 Output data buffer register 8 R/W
003FF1H 00000000B
B
B
B
B
B
B
B
B
B
003FF2H
00000000
B
OPEBR9 Output data buffer register 9 R/W
003FF3H 00000000B
003FF4H
00000000
B
OPEBRA Output data buffer register A R/W
003FF5H 00000000B
003FF6H
00000000
B
OPEBRB Output data buffer register B R/W
003FF7H 00000000B
003FF8H
XXXXXXXX
OPDR Output data register R
003FF9H 0000XXXXB
003FFAH
XXXXXXXX
CPCR Compare clear register R/W
003FFBH XXXXXXXXB
003FFCH
00000000
B
TMBR Timer buffer register R
003FFDH 00000000B
003FFEH
to
003FFF
H
Prohibited area
B
B
26
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