The MB90495-series with FULL-CAN interface and FLASH ROM is especially designed for automotive and industrial applications.
Its main feature is the on-chip CAN Interface, which conforms to V2.0 Part A and Part B, while supporting a very flexible message
buffer scheme, including 8 message buffers, and so offering more functions than a normal full CAN approach.
With the new 0.5 mm CMOS technology, Fujitsu now also offers on-chip FLASH-ROM program memory. An internal voltage
booster removes the necessity for a second programming voltage. An on-chip voltage regulator provides 3V to the internal MCU
core. This creates a major advantage in terms of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 62.5 nsec instruction cycle time from an external 4 MHz clock. A
32kHz Subsystem clock has been included for power saving modes and real time measurement.
There are 2 on-chip UART’s, which also provide synchronous communication modes. Furthermore the MCU features an 8 channel ADC, 8 channel External interrupt controller, two 16 bit PPG channels, 4 channel Input Capture Unit and a 16-bit free running
I/O-timer.
MB90495 Series Data Sheet (Advance Information)1 / 40FME EMDC June 19, 2000
•PPG (Programmable Pulse Generator) 16bit * 2ch; Can be configured as 8bit * 4ch
•Optimised instruction set for controller applications
(bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety
of pointers)
•4-byte instruction execution queue
•Signed multiply (16bit*16bit) and divide (32bit/16bit) instructions available
•Program Patch Function
•Fast Interrupt processing
•16-bit reload timer: 2 channels
•Low Power Consumption - Several different Lo-Power modes: (Sleep, Stop, Watch,...)
•Package:QFP-64; 12mm x 12mm body, 0.65mm pin pitch
•QFP-64; 20mm x 18mm body, 1.0mm pin pitch
MB90495 Series Data Sheet (Advance Information)2 / 40FMG EMDC June 19, 2000
MB90495 Series
3. PRODUCT LINEUP
The following table provides an overview of the MB90495 Series
0.5 mm CMOS with on-chip voltage regulator
for internal power supply + Flash memory Onchip charge pump for programming voltage
F2MC-16LX CPU
Mask ROM 64 Kbytes
0.5 mm CMOS with on-chip voltage regulator for
internal power supply
5 V +/- 10%
- 40 to 85 °C
QFP64
MB90495 Series Data Sheet (Advance Information)3 / 40FME EMDC June 19, 2000
MB90495 Series
4. BLOCK DIAGRAM
X0,X1
RSTX
X0A, X1A
SOT1
SCK1
SIN1
SOT 0
SCK0
SIN0
Clock
Controller
Watch
Timer
Time Base
Timer
RAM
2K
ROM/Flash
64K
Prescaler
UART 1
(SCI)
Prescaler
UART 0
(SCI)
16LX
CPU
FMC-16 Bus
IO Timer
Input
Capture
4ch
16-bit
PPG
2ch
CAN
External
Interrupt
FRCK
IN[3:0]
PPG[3:0]
RX
TX
INT[7:0]
16bit Reload
AVCC
AVSS
AN[7:0]
AVR
ADTG
MB90495 Series Data Sheet (Advance Information)4 / 40FMG EMDC June 19, 2000
10-bit ADC
8ch
Timer
2ch
TIN[1:0]
TOT[1:0]
5. PIN ASSIGNMENT
P30/ALE/SOUT0
VSS
P31/RDX/SCK0
P32/WRLX/SIN0
P33/WRHX
P34/HRQ
P35/HAKX
VCC
P36/FRCK/RDY
P37/ADTG/CLK
P40/SIN1
P41/SCK1
P42/SOUT1
P43/TX
P44/RX
P27/INT7/A23
48
49
50
51
52
53
54
55
56
57
C
58
59
60
61
62
63
64
123456789
P26/INT6/A22
P25/INT5/A21
P24/INT4/A20
P23/TOUT1/A19
P22/TIN1/A18
P21/TOUT0/A17
P20/TIN0/A16
P17/PPG3/AD15
P16/PPG2/AD14
P15/PPG1/AD13
P14/PPG0/AD12
P13/IN3/AD11
P12//IN2/AD10
P11/IN1/AD09
474645444342414039383736353433
QFP-64
Package code (mold)
FPT-64P-M09
10111213141516
P10/IN0/AD08
P07/AD07
32
P06/AD06
31
P05/AD05
30
P04/AD04
29
P03/AD03
28
P02/AD02
27
P01/AD01
26
P00/AD00
25
VSS
24
X1
23
X0
22
MD2
21
MD1
20
RSTX
19
MD0
18
P63/INT3
17
MB90495 Series
P31/RDX/SCK0
P32/WRLX/SIN0
P33/WRHX
P34/HRQ
P35/HAKX
VCC
P36/FRCK/RDY
P37/ADTG/CLK
P40/SIN1
P41/SCK1
P42/SOUT1
P43/TX
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P61/INT1
P62/INT2
P57/AN7
Figure 5.1 FPT-64P-M09
P30/ALE/SOUT0
VSS
P27/INT7/A23
P26/INT6/A22
P25/INT5/A21
P24/INT4/A20
P23/TOUT1/A19
P22/TIN1/A18
P21/TOUT0/A17
P20/TIN0/A16
474645444342414039383736353433
515049
52
53
54
55
56
57
C
58
59
60
61
62
63
64
48
QFP-64
Package code (mold)
FPT-64P-M06
123456789
X0A
X1A
AVR
AVSS
AVCC
P60/INT0
P17/PPG3/AD15
P16/PPG2/AD14
P15/PPG1/AD13
P14/PPG0/AD12
P13/IN3/AD11
P12//IN2/AD10
P11/IN1/AD09
101112131415161718
P10/IN0/AD08
P07/AD07
32
P06/AD06
31
P05/AD05
30
P04/AD04
29
P03/AD03
28
P02/AD02
27
P01/AD01
26
P00/AD00
25
VSS
24
X1
23
X0
22
MD2
21
MD1
20
RSTX
19
P44/RX
P61/INT1
P50/AN0
P51/AN1
P62/INT2
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
AVR
AVSS
P60/INT0
MD0
P63/INT3
X0A
X1A
Figure 5.2 FPT-64P-M06
MB90495 Series Data Sheet (Advance Information)5 / 40FME EMDC June 19, 2000
MB90495 Series
6. PIN DESCRIPTION
6.1 Pin Function
Pin No.
M06M09
21
32
4 to 113 to 10
1211AVCC
1312AVR
1413AVSS
1514
1615X0AALow frequency oscillation input
1716X1AALow frequency oscillation output
1817
1918MD0CHCMOSMode input
2019RSTXBLCMOSReset input
2120MD1CHCMOSMode input
2221MD2FHCMOSMode input
2322X0AHigh frequency oscillation input
2423X1AHigh frequency oscillation output
2524VSSPower ground
26 to 33 25 to 32
34 to 37 33 to 36
38 to 41 37 to 40
4241
4342
4443
Pin Name
P61
INT1External Interrupt input 1
P62
INT2External interrupt 2
P50 to P57
AN0 to AN7Inputs for A/D Converter
P60
INT0External interrupt input 0
P63
INT3External interrupt 3
P00 to P07
AD00 to AD07Addresss Data Bus
P10 to P13
IN0 to IN3Inputs for Input Captures
AD08 to AD11Address Data Bus
P14 to P17
PPG0 to PPG3
AD12 to AD15Address Data Bus
P20
TIN0Input for 16-bit Reload Timer 0
A16Address Bus
P21
TOT0Output for 16-bit Reload Timer 0
A17Address Bus
P22
TIN1Input for 16-bit Reload Timer 1
A18Address Bus
Circuit
Type
ActiveLevelat RST PriorityFunction
DH
DH
EHCMOSHigh-ZPort
DH
DH
GH
GH
GH
GH
GH
GH
CMOS/
TTL
CMOS/
TTL
CMOS/
TTL
CMOS/
TTL
CMOS/
TTL
CMOS/
TTL
CMOS/
TTL
CMOS/
TTL
CMOS/
TTL
CMOS/
TTL
High-ZPort
High-ZPort
High-ZPort
High-ZPort
High-ZPort
High-ZPort
High-ZPort
High-ZPort
High-ZPort
High-ZPort
General pupose IO
General pupose IO
General pupose IO
Dedicated power supply for A/D Converter
Reference Volgate inupt for A/D Converter
Dedicated power ground for A/D Converter
General pupose IO
General purpose IO
General purpose IO
General pupose IO
General pupose IO
Outputs for Programable Pulse Gener-
ators
General pupose IO
General pupose IO
General pupose IO
MB90495 Series Data Sheet (Advance Information)6 / 40FMG EMDC June 19, 2000
MB90495 Series
Pin No.
M06M09
4544
46 to 49 45 to 48
5049VSS Ground
5150
5251
5352
5453
5554
5655
5756VCCPower supply
5857C
5958
6059
6160
6261
6362
6463
164
Pin Name
P23
TOT1Output for 16-bit Reload Timer 1
A19Address Bus
P24 to P25
INT4 to INT 7Inputs for External Interrupt
A20 to A23Address Bus
P30
SOT0Output for UART 0
ALEAddress Latch Enable output
P31
SCK0Input/Output for UART 0
RDXRead Enable output
P32
SIN0Input for UART 0
WRLXWrite Enable Low-byte output
P33
WRHXWrite Enable High-byte output
P34
HRQHalt Request input
P35
HAKXHalt Acknowledge output
P36
FRCKInupt for IO Timer
RDYReady input
P37
ADTGTrigger inupt for A/D Converter
CLKClock output
P40
SIN1Input for UART 1
P41
SCK1Input/Output for UART 1
P42
SOT1Output for UART 1
P43
TxCAN Transmit pin
P44
RxCAN receive pin
Circuit
Type
ActiveLevelat RST PriorityFunction
GH
GH
GH
GH
GH
GH
GH
GH
GH
DHCMOSHigh-ZPort
GH
GH
GH
GH
GH
CMOS/
TTL
CMOS/
TTL
CMOS/
TTL
CMOS/
TTL
CMOS/
TTL
CMOS/
TTL
CMOS/
TTL
CMOS/
TTL
CMOS/
TTL
CMOS/
TTL
CMOS/
TTL
CMOS/
TTL
CMOS/
TTL
CMOS/
TTL
High-ZPort
High-ZPort
High-ZPort
High-ZPort
High-ZPort
High-ZPort
High-ZPort
High-ZPort
High-ZPort
High-ZPort
High-ZPort
High-ZPort
High-ZPort
High-ZPort
General pupose IO
General pupose IO
General pupose IO
General pupose IO
General pupose IO
General pupose IO
General pupose IO
General pupose IO
Pin for capacitor for the internal power
supply.
General pupose IO
General pupose IO
General pupose IO
General pupose IO
General pupose IO
General pupose IO
General pupose IO
MB90495 Series Data Sheet (Advance Information)7 / 40FME EMDC June 19, 2000
MB90495 Series
0
1
0
1
6.2 I/O Circuit Types
CircuitDrawingComment
X1
X1A
A
B
X0
X0A
Standby Control Signal
HYS
C
HYS
D
HYS
Standby Control Signal
E
HYS
Standby Control Signal
Analog
HYS
F
G
HYS
Standby Control Signal
TTL
MB90495 Series Data Sheet (Advance Information)8 / 40FMG EMDC June 19, 2000
7. HANDLING DEVICES
(1) Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions:
A voltage higher than Vcc or lower than Vss is applied to an input or output pin.
A voltage higher than the rated voltage is applied between Vcc and Vss.
The AVcc power supply is applied before the Vcc voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the
device.
(2) Handling unused input pins
Do not leave unused input pins open, as doing so may cause misoperation of the device. Use a
pull-up or pull-down resistor.
(3) Using external clock
To use external clock, drive the X0 and X1 pins in reverse phase.
Below is a diagram of how to use external clock.
MB90495 Series
MB90495 Series
X0
X1
Figure 7.1 Using external clock
(4) Power supply pins (Vcc/Vss)
Ensure that all Vcc-level power supply pins are at the same potential. In addition, ensure the same
for all Vss-level power supply pins. (See the figure below.) If there are more than one Vcc or Vss
system, the device may operate incorrectly even within the guaranteed operating range. Note that
this product may not have as many power pins as pictured in the figure.
MB90495 Series Data Sheet (Advance Information)9 / 40FME EMDC June 19, 2000
MB90495 Series
Vcc
Vss
Vss
Vcc
Vss
Vcc
MB90495
Series
Vss
Vcc
Vss
Vcc
Figure 7.2 Power pin connections
(5) Pull-up/down resistors
The MB90495 Series does not support internal pull-up/down resistors. Use external components
where needed.
MB90495 Series Data Sheet (Advance Information)10 / 40FMG EMDC June 19, 2000
8. ADDRESS SPACE
MB90V495MB90F497MB90497
FFFFFFH
ROM FFFLASH ROM FFROM FF
FF0000H
FEFFFFH
ROM FENo Acess
FE0000H
FDFFFFH
ROM FD
FD0000H
FCFFFFH
ROM FC
FC0000H
FBFFFFH
ROM FB
FB0000H
FAFFFFH
ROM FA
FA0000H
MB90495 Series
External bus accessExternal bus access
010000H
00FFFFH
FF ROM mirrorFF ROM mirrorFF ROM mirror
004000H
003FFFH
Extended I/OExtended I/OExtended I/O
003800H
External bus accessExternal bus access
0018FFH
0010FFH
000900H
RAM mirror
Do not use
RAM
1
RAM mirror
Do not use.
0008FFH
RAMRAM
000100H
0000BFH
I/OI/OI/O
000000H
1. The RAMcontentsof0000H- 08FFHis mirrored to0900H- 10FFH. The RAMmirrorareashouldnot be
accessed for proper operation.
MB90495 Series Data Sheet (Advance Information)11 / 40FME EMDC June 19, 2000
MB90495 Series
9. REGISTER MAP
AddressRegisterAbbreviationPeripheralAccess Initial value
00 HPort 0 data registerPDR0Port 0R/WXXXXXXXX
01 HPort 1 data registerPDR1Port 1R/WXXXXXXXX
02 HPort 2 data registerPDR2Port 2R/WXXXXXXXX
03 HPort 3 data registerPDR3Port 3R/WXXXXXXXX
04 HPort 4 data registerPDR4Port 4R/WXXXXXXXX
05 HPort 5 data registerPDR5Port 5R/WXXXXXXXX
06 HPort 6 data registerPDR6Port 6R/WXXXXXXXX
07-0F HReserved
10 HPort 0 direction registerDDR0Port 0R/W00000000
11 HPort 1 direction registerDDR1Port 1R/W00000000
12 HPort 2 direction registerDDR2Port 2R/W00000000
13 HPort 3 direction registerDDR3Port 3R/W00000000
14 HPort 4 direction registerDDR4Port 4R/W00000000
15 HPort 5 direction registerDDR5Port 5R/W00000000
16 HPort 6 direction registerDDR6Port 6R/W00000000
17-1A HReserved
1B HAnalog Input EnableADERPort 5, A/DR/W11111111
1C - 1F HReserved
20 HSerial Mode Register 1SMR0
21 HSerial Control Register 1SCR0R/W00000100
22 HInput/Output Data Register 1SIDR0/SODR0R/WXXXXXXXX
23 HSerial Status Register 1SSR0R/W00001_00
24 HUART 0 Prescaler Control RegisterCDCR0R/W0___1111
25 HUART 0 edge selectSES0R/W_______1
26 HSerial Mode Control Register 1SMC1
27 HSerial Control RegisterSRC1R/W00000X00
28 HInput/Output Data Register 1SIDR1/SODR1R/WXXXXXXXX
29 HSerial Status Register 1SMC1R/WXXXXX000
2A HReserved
2B HUART 1 Prescaler Control RegisterCDCR0Prescaler UART 1R/W0___0000
70-7F HReserved
80-8F HReserved for CAN 1 Interface . Refer to “CAN Controller”
90-9D HReserved
9E HROM Correction Control StatusPACSRROM CorrectionR/W11000000
9F HDelayed Interrupt/releaseDIRRDelayed InterruptR/W_______0
A0 HLow-power ModeLPMCRLow Power ControllerR/W00011000
A1 HClock SelectorCKSCRLow Power ControllerR/W11111100
A2-A4 HReserved
A5 HAutomatic ready function select reg.ARSRWExterA6 HExternal address output control reg.HACRW00000000
A7 HBus control signal select registerECSRW0000000_
A8 HWatchdog ControlWDTCWatchdog TimerR/WXXXXX111
A9 HTime Base Timer ControlTBTCTime Base TimerR/W1__0X100
AA-AD HReserved
AE H
AF HReserved
Flash Control Status
(Flash only, otherwise reserved)
FMCSFlash MemoryR/W000X0000
16-bit Programable Pulse
Generator 2/3
Input Captue 0/1
Input Capture 0/1/2/3
I/O Timer
Input Captue 2/3
16-bit Reload Timer 0
16-bit Reload Timer 1
R/W0_00X__1
RXXXXXXXX
R/WXX000000
R/W00000000
RXXXXXXXX
R/W00000X00
R/W00000X00
0011__00
nal
Mem-
ory
Access
MB90495 Series Data Sheet (Advance Information)13 / 40FME EMDC June 19, 2000
MB90495 Series
AddressRegisterAbbreviationPeripheralAccess Initial value
B0 HInterrupt control register 00ICR00
B1 HInterrupt control register 01ICR01R/W11000111
B2 HInterrupt control register 02ICR02R/W11000111
B3 HInterrupt control register 03ICR03R/W11000111
B4 HInterrupt control register 04ICR04R/W11000111
B5 HInterrupt control register 05ICR05R/W11000111
B6 HInterrupt control register 06ICR06R/W11000111
B7 HInterrupt control register 07ICR07R/W11000111
B8 HInterrupt control register 08ICR08R/W11000111
B9 HInterrupt control register 09ICR09R/W11000111
BA HInterrupt control register 10ICR10R/W11000111
BB HInterrupt control register 11ICR11R/W11000111
BC HInterrupt control register 12ICR12R/W11000111
BD HInterrupt control register 13ICR13R/W11000111
BE HInterrupt control register 14ICR14R/W11000111
BF HInterrupt control register 15ICR15R/W11000111
MB90495 Series Data Sheet (Advance Information)19 / 40FME EMDC June 19, 2000
MB90495 Series
12. ELECTRICAL CHARACTERISTICS
12.1 Absolute Maximum Ratings
ParameterSymbol
VCCVSS – 0.3VSS + 6.0V
Rated Value
Min.Max.
(VSS = AVSS = 0 V)
UnitsRemarks
Power supply voltage
Input voltageVIVSS – 0.3VSS + 6.0V*2
Output voltageVOVSS – 0.3VSS + 6.0V*2
"L" level max. output currentIOL—15mA
"L" level avg. output currentIOLAV—4mAAverage value over a period of 100ms
"L" level max. overall output currentIOL—100mA
"L" level avg. overall output currentIOLAV—50mAAverage value over a period of 100ms
"H" level max. output currentIOH—–15mA
"H" level avg. output currentIOHAV—–4mAAverage value over a period of 100ms
"H" level max. overall output currentIOH—-100mA
"H" level avg. overall output currentIOHAV—-50mAAverage value over a period of 100ms
Power consumptionPD—300mW
Operating temperatureTA–40+85°C
Storage temperatureTSTG–55+150°C
MB90495 Series Data Sheet (Advance Information)22 / 40FMG EMDC June 19, 2000
14. AC CHARACTERISTICS
14.1 Clock Timing
ParameterSymbolPin
fCX0, X13—16MHz
Oscillation frequency
fCLX0A, X1A—32.768—kHz
(TA = –40 to +85°C, VCC = 5.0 V 10%, VSS = AVSS = 0 V)
Rated Value
Min.Typ.Max.
MB90495 Series
UnitsRemarks
Oscillation cycle time
Frequency deviation with
PLL *
Input clock pulse width
Input clock rise and fall
time
Machine clock frequency
Machine clock cycle time
*: Frequency deviation indicates the maximum frequency difference from the target frequency when using a multiplied clock.
|a|
∆f =× 100%
fO
tHCYLX0, X162.5—333ns
tLCYLX0A, X1A—30.5—µs
∆f———5%
PWH, PWLX010——ns
PWLH,PWLLX0A—15.2—µs
tCR, tCFX0——5nsWhen using external clock
fCP—1.5—16MHzWhen using main clock
fLCP——8.192—kHzWhen using sub-clock
tCP—62.5—666nsWhen using main clock
tLCP——122.1—µsWhen using sub-clock
+a
Central frequency f
O
–a
Duty ratio is about 30 to
70%.
tHCYL
0.8 VCC
X0
X0A
PWH
PWLH
tCF
tLCYL
tCF
PWL
tCR
PWLL
tCR
0.2 VCC
0.8 VCC
0.2 VCC
MB90495 Series Data Sheet (Advance Information)23 / 40FME EMDC June 19, 2000
MB90495 Series
5.5
4.5
Guaranteed operation range for MB90F497, MB90497
Power supply voltage VCC (V)
Machine clock
fCP (MHz)
Guaranteed PLL operation
3.3
3.0
1.53812
Machine clock fCP (MHz)
Guaranteed operation range
16
12
9
8
x 4x 3x 2
16
x 1
x 1/2
(PLL off)
4
34816
Oscillation clock fC (MHz)
Ocsillation clock frequency and Machine clock frequency
Figure 14.1 Clock Timing
AC characteristics are set to the measured reference voltage values below.
• Input signal waveform
Hysteresis Input Pin
0.8 VCC
0.2 VCC
• Output signal waveform
Output Pin
2.4 V
0.8 V
Figure 14.2 Measured Reference Voltages
MB90495 Series Data Sheet (Advance Information)24 / 40FMG EMDC June 19, 2000
14.2 Clock Output Timing
(TA = –40 to +85°C, VCC = 5.0 V 10%, VSS = AVSS = 0.0 V)
ParameterSymbolPinTest Condition
Cycle timetCYC
CLKVCC = 5 V ±10%
CLK ↑ ⇒ CLK ↓tCHCL20—ns
tCYC
tCHCL
Rated Value
Min.Max.
62.5—ns
MB90495 Series
UnitsRemarks
CLK
2.4 V
2.4 V
0.8 V
Figure 14.3 Measured CLK timing
MB90495 Series Data Sheet (Advance Information)25 / 40FME EMDC June 19, 2000
MB90495 Series
14.3 Reset Input
(TA = –40 to +85°C, VCC = 5.0 V 10%, VSS = AVSS = 0.0 V)
0.2 VCC
Rated Value
Min.Max.
tRSTL, tHSTL
UnitsRemarks
0.2 VCC
ParameterSymbolPin
Reset input timetRSTLRST16 tCP—ns
“tcp” represents one cycle time of the machine clock.
Any reset can not fully initialize the Flash Memory if it is performing the automatic algorithm.
RST
Figure 14.4 Measured RST timing
MB90495 Series Data Sheet (Advance Information)26 / 40FMG EMDC June 19, 2000
MB90495 Series
14.4 Power On Reset
(TA = –40 to +85°C, VCC = 5.0 V 10%, VSS = AVSS = 0.0 V)
ParameterSymbolPinTest Condition
Power on rise timetRVCC
—
Power off timetOFFVCC50—msDue to repetitive operation
tR
3.5 V
VCC
Rated Value
Min.Max.
0.0530ms
0.2 V
UnitsRemarks
tOFF
0.2 V0.2 V
If you change the power supply voltage too rapidly, a power on reset may occur. We recommend that
you startup smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. Perform while not using the PLL clock. However, if voltage drops
are within 1 mV/sec, you can operate while using the PLL clock.
VCC
3V
Holds RAM data
VSS
We recommend a rise of
50 mV/ms maximum.
Figure 14.5 Power On Reset Timing
MB90495 Series Data Sheet (Advance Information)27 / 40FME EMDC June 19, 2000
MB90495 Series
14.5 External Bus Timing (Read)
ParameterSymbolPinTest Condition
ALE pulse widthtLHLLALE
ALE,
Valid address ⇒ ALE ↓ timetAVLL
A23 - A16,
AD15 - AD00
(TA = –40 to +85°C, VCC = 4.5 to 5.5 V, VSS = 0 V)
MB90495 Series Data Sheet (Advance Information)30 / 40FMG EMDC June 19, 2000
MB90495 Series
14.7 External Bus Ready Input Timing
(TA = –40 to +85°C, VCC = 4.5 to 5.5 V, VSS = 0 V)
ParameterSymbolPinTest Condition
RDY setup timetRYHSRDY
—
RDY hold timetRYHHRDY0—ns
Note: If the RDY setup time is insufficient, use the auto-ready function.
Rated Value
Min.Max.
45—ns
UnitsRemarks
CLK
ALE
RD/WR
RDY
no WAIT is used.
RDY
When WAIT is used
tRYHS
0.8 VCC
0.2 VCC
Figure 14.8 Ready Input Timing
2.4 V
tRYHH
0.8 VCC
MB90495 Series Data Sheet (Advance Information)31 / 40FME EMDC June 19, 2000
MB90495 Series
14.8 External Bus Hold Timing
(TA = –40 to +85°C, VCC = 4.5 to 5.5 V, VSS = 0 V)
ParameterSymbolPinTest Condition
Pin floating ⇒ HAK ↓timetXHALHAK
—
HAK ↑ time ⇒ Pin valid timetHAHVHAKtCP2 tCPns
Note: There is more than 1 cycle from when HRQ reads in until the HAK is changed.
Rated Value
Min.Max.
30tCPns
UnitsRemarks
HAK
Each pin
2.4V
0.8V
tXHAL
2.4V2.4V
0.8V
High impedance
tHAHV
0.8V
Figure 14.9 Hold Timing
MB90495 Series Data Sheet (Advance Information)32 / 40FMG EMDC June 19, 2000
MB90495 Series
14.9 UART1 Timing
(TA = –40 to +85°C, VCC = 4.5 to 5.5 V, VSS = 0 V)
ParameterSymbolPin SymbolTest Condition
Serial clock cycle timetSCYCSCK1
SCK ↓ ⇒ SOT delay timetSLOVSCK1, SOT1–8080ns
Valid SIN ⇒ SCK ↑tIVSHSCK1, SIN1100—ns
SCK ↑ ⇒ Valid SIN hold timetSHIXSCK1, SIN160—ns
Zero reading voltageVOTAN0 to AN7AVSS – 3.5AVSS +0.5AVSS + 4.5LSB
Full scale reading voltageVFSTAN0 to AN7AVR – 6.5AVR –1.5AVR + 1.5LSB
Conversion time———176tCP—ns
Sampling time———64tCP—ns
Analog port input currentIAINAN0 to AN7——10µA
Analog input voltage rangeVAINAN0 to AN7AVSS—AVRV
Reference voltage range—AVRAVSS + 2.7—AVCCV
IAAVCC—5—mA
Power supply current
IAHAVCC——5µA*1
IRAVR200400600µA
Reference voltage current
IRHAVR——5µA*1
Offset between input channels—AN0 to AN7——4LSB
*1: When not operating A/D converter, this is the current (VCC = AVCC = AVR = 5.0 V) when the CPU is stopped.
Terminology:
Conversion error :Absolute maximum conversion deviation with respect to the theoretical conversion line.
Nonlinearlity :Relative maximum conversion deviation with respect to the theoretical conversion line connecting to
the device-unique zero reading voltage and full-scale reading voltage.
Differential non-linearlity :Maximum conversion deviation in any two adjacent reading voltages with respect to the theoretical
LSB conversion step.
Zero-reading voltage :Input voltage which results in the minimum conversion value.
Full-scale reading voltage :Input voltage which results in the maximum coversion value.
1 LSB =
AVR/1024
Notes:
1. The accuracy gets worse as AVR - AVSS becomes smaller.
2. Analog input external circuit output impedance should use the following conditions:
External circuit output impedance less than 15 kΩ
3. If the external circuit output impedance is too high, there may be insufficient time for sampling of the analog voltage.
Converter
C1
Analog input
C0
Figure 14.15 Analog Input pin
MB90495 Series Data Sheet (Advance Information)38 / 40FMG EMDC June 19, 2000
15. PACKAGE DIMENSIONS
MB90495 Series
14.00±0.20(.551±.008)SQ
12.00±0.10(.472±.004)SQ
49
1 PIN INDEX
64
LEAD No.
0.65(.0256)TYP0.30±0.10
116
(.012±.004)
0.10(.004)
C
1994 FUJITSU LIMITED F64018S-1C-2
0.13(.005)
3348
32
17
"A"
M
+0.20
–0.10
1.50
+.008
.059
–.004
9.7513.00
(.384)
REF
+0.05
–0.02
0.127
+.002
–.001
.005
(Mounting height)
(.512)
NOM
Details of "A" part
0 10°
0.10±0.10
(.004±.004)
0.50±0.20
(.020±.008)
(STAND OFF)
Figure 15.1 Package Code: FPT-64P-M09
MB90495 Series Data Sheet (Advance Information)39 / 40FME EMDC June 19, 2000
MB90495 Series
51
64
LEAD No.
24.70±0.40(.972±.016)
20.00±0.20(.787±.008)
INDEX
"A"
1
1.00(.0394)0.40±0.10
0.10(.004)
18.00(.709)REF
22.30±0.40(.878±.016)
(.016±.004)TYP
0.20(.008)
33
(.551±.008)
19
"B"
3252
14.00±0.20
20
M
Details of "A" part
18.70±0.40
(.736±.016)
0.25(.010)
0.30(.012)
0.18(.007)MAX
0.63(.025)MAX
3.35(.132)MAX
(Mounting height)
0.05(.002)MIN
(STAND OFF)
12.00(.472)
REF
0.15±0.05(.006±.002)
Details of "B" part
16.30±0.40
(.642±.016)
0 10°
1.20±0.20
(.047±.008)
C
1994 FUJITSU LIMITED F64013S-3C-2
Figure 15.2 Package Code FPT-64P-M06
MB90495 Series Data Sheet (Advance Information)40 / 40FMG EMDC June 19, 2000
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