FUJITSU MB90497, MB90F497 DATA SHEET

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FUJITSU SEMICONDUCTOR

Advance Information

Data Sheet (Advance Information)

16-bit Proprietary Microcontroller

CMOS

F2MC-16LX MB90495 Series

MB90497/F497

1. OUTLINE

The MB90495-series with FULL-CAN interface and FLASH ROM is especially designed for automotive and industrial applications.
Its main feature is the on-chip CAN Interface, which conforms to V2.0 Part A and Part B, while supporting a very flexible message
buffer scheme, including 8 message buffers, and so offering more functions than a normal full CAN approach.

With the new 0.5 mm CMOS technology, Fujitsu now also offers on-chip FLASH-ROM program memory. An internal voltage
booster removes the necessity for a second programming voltage. An on-chip voltage regulator provides 3V to the internal MCU
core. This creates a major advantage in terms of EMI and power consumption.

The internal PLL clock frequency multiplier provides an internal 62.5 nsec instruction cycle time from an external 4 MHz clock. A
32kHz Subsystem clock has been included for power saving modes and real time measurement.

There are 2 on-chip UART’s, which also provide synchronous communication modes. Furthermore the MCU features an 8 chan­nel ADC, 8 channel External interrupt controller, two 16 bit PPG channels, 4 channel Input Capture Unit and a 16-bit free running
I/O-timer.

MB90495 Series Data Sheet (Advance Information) 1 / 40 FME EMDC June 19, 2000

MB90495 Series

2. FEATURES

• 16-bit core CPU; 4MHz external clock (16 MHz internal, 62.5 ns instruction cycle time)

• 32kHz Subsystem Clock

• 0.5 mm CMOS Technology

• Internal voltage regulator supports 3V MCU core, offering low EMI and low power consump­tion figures

• 64 KB FLASH ROM; supports automatic programming, 10.000 erase cycles, 10 year data
retention time and no second programming voltage required

• 2 KB static RAM

• FULL-CAN interface; conforming to Version 2.0 Part A and Part B, flexible message buffering
(mailbox and FIFO buffering can be mixed)

• 2 UART’s; both offering synchronous communication modes.

• Powerful interrupt functions (8 programmable priority levels; 8 external interrupts)

• I/O Timer

• A/D Converter: 8 channel analogue inputs (Resolution 10 bits or 8 bits)

• ICU (Input capture) 16bit * 4ch

• PPG (Programmable Pulse Generator) 16bit * 2ch; Can be configured as 8bit * 4ch

• Optimised instruction set for controller applications
(bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety
of pointers)

• 4-byte instruction execution queue

• Signed multiply (16bit*16bit) and divide (32bit/16bit) instructions available

• Program Patch Function

• Fast Interrupt processing

• 16-bit reload timer: 2 channels

• Low Power Consumption - Several different Lo-Power modes: (Sleep, Stop, Watch,...)

• Package: QFP-64; 12mm x 12mm body, 0.65mm pin pitch

• QFP-64; 20mm x 18mm body, 1.0mm pin pitch

MB90495 Series Data Sheet (Advance Information) 2 / 40 FMG EMDC June 19, 2000

MB90495 Series

3. PRODUCT LINEUP

The following table provides an overview of the MB90495 Series

Features MB90F497 MB90497

CPU

System clock

ROM

RAM 2 Kbytes 2 Kbytes

Technology

Operating
voltage range

Temperature
range

Package

On-chip PLL clock multiplier (x1, x2, x3, x4, 1/2 when PLL stop)
Minimum instruction execution time: 62.5 ns (4 MHz osc. PLL x4)

Boot-block
Flash memory 64 Kbytes

0.5 mm CMOS with on-chip voltage regulator
for internal power supply + Flash memory On­chip charge pump for programming voltage

F2MC-16LX CPU

Mask ROM 64 Kbytes

0.5 mm CMOS with on-chip voltage regulator for
internal power supply

5 V +/- 10%

- 40 to 85 °C

QFP64

MB90495 Series Data Sheet (Advance Information) 3 / 40 FME EMDC June 19, 2000

MB90495 Series

4. BLOCK DIAGRAM

X0,X1
RSTX
X0A, X1A

SOT1
SCK1
SIN1

SOT 0
SCK0

SIN0

Clock

Controller

Watch

Timer

Time Base

Timer

RAM

2K

ROM/Flash

64K

Prescaler

UART 1
(SCI)

Prescaler

UART 0
(SCI)

16LX

CPU

FMC-16 Bus

IO Timer

Input

Capture

4ch

16-bit

PPG

2ch

CAN

External

Interrupt

FRCK

IN[3:0]

PPG[3:0]

RX

TX

INT[7:0]

16bit Reload

AVCC
AVSS
AN[7:0]
AVR
ADTG

MB90495 Series Data Sheet (Advance Information) 4 / 40 FMG EMDC June 19, 2000

10-bit ADC

8ch

Timer

2ch

TIN[1:0]

TOT[1:0]

5. PIN ASSIGNMENT

P30/ALE/SOUT0

VSS

P31/RDX/SCK0

P32/WRLX/SIN0

P33/WRHX

P34/HRQ

P35/HAKX

VCC

P36/FRCK/RDY
P37/ADTG/CLK

P40/SIN1

P41/SCK1

P42/SOUT1

P43/TX
P44/RX

P27/INT7/A23

48

49
50
51
52
53
54
55
56
57

C

58
59
60
61
62
63
64

123456789

P26/INT6/A22

P25/INT5/A21

P24/INT4/A20

P23/TOUT1/A19

P22/TIN1/A18

P21/TOUT0/A17

P20/TIN0/A16

P17/PPG3/AD15

P16/PPG2/AD14

P15/PPG1/AD13

P14/PPG0/AD12

P13/IN3/AD11

P12//IN2/AD10

P11/IN1/AD09

474645444342414039383736353433

QFP-64

Package code (mold)

FPT-64P-M09

10111213141516

P10/IN0/AD08

P07/AD07

32

P06/AD06

31

P05/AD05

30

P04/AD04

29

P03/AD03

28

P02/AD02

27

P01/AD01

26

P00/AD00

25

VSS

24

X1

23

X0

22

MD2

21

MD1

20

RSTX

19

MD0

18

P63/INT3

17

MB90495 Series

P31/RDX/SCK0

P32/WRLX/SIN0

P33/WRHX

P34/HRQ

P35/HAKX

VCC

P36/FRCK/RDY

P37/ADTG/CLK

P40/SIN1

P41/SCK1

P42/SOUT1

P43/TX

P50/AN0

P51/AN1

P52/AN2

P53/AN3

P54/AN4

P55/AN5

P56/AN6

P61/INT1

P62/INT2

P57/AN7

Figure 5.1 FPT-64P-M09

P30/ALE/SOUT0

VSS

P27/INT7/A23

P26/INT6/A22

P25/INT5/A21

P24/INT4/A20

P23/TOUT1/A19

P22/TIN1/A18

P21/TOUT0/A17

P20/TIN0/A16

474645444342414039383736353433

515049

52
53
54
55
56
57

C

58
59
60
61
62
63
64

48

QFP-64

Package code (mold)

FPT-64P-M06

123456789

X0A

X1A

AVR

AVSS

AVCC

P60/INT0

P17/PPG3/AD15

P16/PPG2/AD14

P15/PPG1/AD13

P14/PPG0/AD12

P13/IN3/AD11

P12//IN2/AD10

P11/IN1/AD09

101112131415161718

P10/IN0/AD08

P07/AD07

32

P06/AD06

31

P05/AD05

30

P04/AD04

29

P03/AD03

28

P02/AD02

27

P01/AD01

26

P00/AD00

25

VSS

24

X1

23

X0

22

MD2

21

MD1

20

RSTX

19

P44/RX

P61/INT1

P50/AN0

P51/AN1

P62/INT2

P52/AN2

P53/AN3

P54/AN4

P55/AN5

P56/AN6

P57/AN7

AVCC

AVR

AVSS

P60/INT0

MD0

P63/INT3

X0A

X1A

Figure 5.2 FPT-64P-M06

MB90495 Series Data Sheet (Advance Information) 5 / 40 FME EMDC June 19, 2000

MB90495 Series

6. PIN DESCRIPTION

6.1 Pin Function

Pin No.

M06 M09

21

32

4 to 11 3 to 10

12 11 AVCC

13 12 AVR

14 13 AVSS

15 14

16 15 X0A A Low frequency oscillation input
17 16 X1A A Low frequency oscillation output

18 17

19 18 MD0 C H CMOS Mode input
20 19 RSTX B L CMOS Reset input
21 20 MD1 C H CMOS Mode input
22 21 MD2 F H CMOS Mode input
23 22 X0 A High frequency oscillation input
24 23 X1 A High frequency oscillation output
25 24 VSS Power ground

26 to 33 25 to 32

34 to 37 33 to 36

38 to 41 37 to 40

42 41

43 42

44 43

Pin Name

P61

INT1 External Interrupt input 1

P62

INT2 External interrupt 2

P50 to P57

AN0 to AN7 Inputs for A/D Converter

P60

INT0 External interrupt input 0

P63

INT3 External interrupt 3

P00 to P07

AD00 to AD07 Addresss Data Bus

P10 to P13

IN0 to IN3 Inputs for Input Captures

AD08 to AD11 Address Data Bus

P14 to P17

PPG0 to PPG3

AD12 to AD15 Address Data Bus

P20

TIN0 Input for 16-bit Reload Timer 0

A16 Address Bus
P21

TOT0 Output for 16-bit Reload Timer 0

A17 Address Bus
P22

TIN1 Input for 16-bit Reload Timer 1

A18 Address Bus

Circuit

Type

Active Level at RST Priority Function

DH

DH

E H CMOS High-Z Port

DH

DH

GH

GH

GH

GH

GH

GH

CMOS/

TTL

CMOS/

TTL

CMOS/

TTL

CMOS/

TTL

CMOS/

TTL

CMOS/

TTL

CMOS/

TTL

CMOS/

TTL

CMOS/

TTL

CMOS/

TTL

High-Z Port

High-Z Port

High-Z Port

High-Z Port

High-Z Port

High-Z Port

High-Z Port

High-Z Port

High-Z Port

High-Z Port

General pupose IO

General pupose IO

General pupose IO

Dedicated power supply for A/D Con­verter

Reference Volgate inupt for A/D Con­verter

Dedicated power ground for A/D Con­verter

General pupose IO

General purpose IO

General purpose IO

General pupose IO

General pupose IO
Outputs for Programable Pulse Gener-

ators

General pupose IO

General pupose IO

General pupose IO

MB90495 Series Data Sheet (Advance Information) 6 / 40 FMG EMDC June 19, 2000

MB90495 Series

Pin No.

M06 M09

45 44

46 to 49 45 to 48

50 49 VSS Ground

51 50

52 51

53 52

54 53

55 54

56 55

57 56 VCC Power supply
58 57 C

59 58

60 59

61 60

62 61

63 62

64 63

164

Pin Name

P23

TOT1 Output for 16-bit Reload Timer 1

A19 Address Bus

P24 to P25

INT4 to INT 7 Inputs for External Interrupt

A20 to A23 Address Bus

P30

SOT0 Output for UART 0

ALE Address Latch Enable output

P31

SCK0 Input/Output for UART 0

RDX Read Enable output

P32

SIN0 Input for UART 0

WRLX Write Enable Low-byte output

P33

WRHX Write Enable High-byte output

P34

HRQ Halt Request input

P35

HAKX Halt Acknowledge output

P36

FRCK Inupt for IO Timer

RDY Ready input

P37

ADTG Trigger inupt for A/D Converter

CLK Clock output

P40

SIN1 Input for UART 1

P41

SCK1 Input/Output for UART 1

P42

SOT1 Output for UART 1

P43

Tx CAN Transmit pin

P44

Rx CAN receive pin

Circuit

Type

Active Level at RST Priority Function

GH

GH

GH

GH

GH

GH

GH

GH

GH

D H CMOS High-Z Port

GH

GH

GH

GH

GH

CMOS/

TTL

CMOS/

TTL

CMOS/

TTL

CMOS/

TTL

CMOS/

TTL

CMOS/

TTL

CMOS/

TTL

CMOS/

TTL

CMOS/

TTL

CMOS/

TTL

CMOS/

TTL

CMOS/

TTL

CMOS/

TTL

CMOS/

TTL

High-Z Port

High-Z Port

High-Z Port

High-Z Port

High-Z Port

High-Z Port

High-Z Port

High-Z Port

High-Z Port

High-Z Port

High-Z Port

High-Z Port

High-Z Port

High-Z Port

General pupose IO

General pupose IO

General pupose IO

General pupose IO

General pupose IO

General pupose IO

General pupose IO

General pupose IO

Pin for capacitor for the internal power
supply.

General pupose IO

General pupose IO

General pupose IO

General pupose IO

General pupose IO

General pupose IO

General pupose IO

MB90495 Series Data Sheet (Advance Information) 7 / 40 FME EMDC June 19, 2000

MB90495 Series

0

1

0

1

6.2 I/O Circuit Types

Circuit Drawing Comment

X1

X1A

A

B

X0

X0A

Standby Control Signal

HYS

C

HYS

D

HYS

Standby Control Signal

E

HYS
Standby Control Signal

Analog

HYS

F

G

HYS

Standby Control Signal

TTL

MB90495 Series Data Sheet (Advance Information) 8 / 40 FMG EMDC June 19, 2000

7. HANDLING DEVICES

(1) Preventing latch-up

CMOS IC chips may suffer latch-up under the following conditions:

A voltage higher than Vcc or lower than Vss is applied to an input or output pin.
A voltage higher than the rated voltage is applied between Vcc and Vss.
The AVcc power supply is applied before the Vcc voltage.

Latch-up may increase the power supply current drastically, causing thermal damage to the
device.

(2) Handling unused input pins

Do not leave unused input pins open, as doing so may cause misoperation of the device. Use a
pull-up or pull-down resistor.

(3) Using external clock

To use external clock, drive the X0 and X1 pins in reverse phase.
Below is a diagram of how to use external clock.

MB90495 Series

MB90495 Series

X0

X1

Figure 7.1 Using external clock

(4) Power supply pins (Vcc/Vss)

Ensure that all Vcc-level power supply pins are at the same potential. In addition, ensure the same
for all Vss-level power supply pins. (See the figure below.) If there are more than one Vcc or Vss
system, the device may operate incorrectly even within the guaranteed operating range. Note that
this product may not have as many power pins as pictured in the figure.

MB90495 Series Data Sheet (Advance Information) 9 / 40 FME EMDC June 19, 2000

MB90495 Series

Vcc
Vss

Vss

Vcc

Vss

Vcc

MB90495

Series

Vss

Vcc

Vss

Vcc

Figure 7.2 Power pin connections

(5) Pull-up/down resistors

The MB90495 Series does not support internal pull-up/down resistors. Use external components
where needed.

MB90495 Series Data Sheet (Advance Information) 10 / 40 FMG EMDC June 19, 2000

8. ADDRESS SPACE

MB90V495 MB90F497 MB90497

FFFFFFH

ROM FF FLASH ROM FF ROM FF

FF0000H
FEFFFFH

ROM FE No Acess

FE0000H
FDFFFFH

ROM FD

FD0000H
FCFFFFH

ROM FC

FC0000H
FBFFFFH

ROM FB

FB0000H
FAFFFFH

ROM FA

FA0000H

MB90495 Series

External bus access External bus access

010000H
00FFFFH

FF ROM mirror FF ROM mirror FF ROM mirror

004000H
003FFFH

Extended I/O Extended I/O Extended I/O

003800H

External bus access External bus access

0018FFH
0010FFH

000900H

RAM mirror

Do not use

RAM

1

RAM mirror
Do not use.

0008FFH

RAM RAM

000100H

0000BFH

I/O I/O I/O

000000H

1. The RAMcontentsof0000H- 08FFHis mirrored to0900H- 10FFH. The RAMmirrorareashouldnot be
accessed for proper operation.

MB90495 Series Data Sheet (Advance Information) 11 / 40 FME EMDC June 19, 2000

MB90495 Series

9. REGISTER MAP

Address Register Abbreviation Peripheral Access Initial value

00 H Port 0 data register PDR0 Port 0 R/W XXXXXXXX
01 H Port 1 data register PDR1 Port 1 R/W XXXXXXXX
02 H Port 2 data register PDR2 Port 2 R/W XXXXXXXX
03 H Port 3 data register PDR3 Port 3 R/W XXXXXXXX
04 H Port 4 data register PDR4 Port 4 R/W XXXXXXXX
05 H Port 5 data register PDR5 Port 5 R/W XXXXXXXX
06 H Port 6 data register PDR6 Port 6 R/W XXXXXXXX

07-0F H Reserved

10 H Port 0 direction register DDR0 Port 0 R/W 00000000
11 H Port 1 direction register DDR1 Port 1 R/W 00000000
12 H Port 2 direction register DDR2 Port 2 R/W 00000000
13 H Port 3 direction register DDR3 Port 3 R/W 00000000
14 H Port 4 direction register DDR4 Port 4 R/W 00000000
15 H Port 5 direction register DDR5 Port 5 R/W 00000000
16 H Port 6 direction register DDR6 Port 6 R/W 00000000

17-1A H Reserved

1B H Analog Input Enable ADER Port 5, A/D R/W 11111111

1C - 1F H Reserved

20 H Serial Mode Register 1 SMR0
21 H Serial Control Register 1 SCR0 R/W 00000100
22 H Input/Output Data Register 1 SIDR0/SODR0 R/W XXXXXXXX
23 H Serial Status Register 1 SSR0 R/W 00001_00
24 H UART 0 Prescaler Control Register CDCR0 R/W 0___1111
25 H UART 0 edge select SES0 R/W _______1
26 H Serial Mode Control Register 1 SMC1
27 H Serial Control Register SRC1 R/W 00000X00

28 H Input/Output Data Register 1 SIDR1/SODR1 R/W XXXXXXXX

29 H Serial Status Register 1 SMC1 R/W XXXXX000
2A H Reserved
2B H UART 1 Prescaler Control Register CDCR0 Prescaler UART 1 R/W 0___0000

2C - 2F H Reserved

30 H External Interrupt Enable ENIR
31 H External Interrupt Request EIRR R/W XXXXXXXX
32 H External Interrupt Level ELVR R/W 00000000
33 H External Interrupt Level ELVR R/W 00000000

34 H A/D Control Status 0 ADCS0

34 H A/D Control Status 1 ADCS1 R/W 00000100

36 H A/D Data 0 ADCR0 R XXXXXXXX

37 H A/D Data 1 ADCR1 R/W 00000_XX

38-3FH Reserved

40 H PPG0 operation mode control register PPGC0

41 H PPG1 operation mode control register PPGC1 R/W 0_00X001

42 H PPG0 and PPG1 clock select register PPG01 R/W 000000__

16-bit Programable Pulse

UART0

UART1

External Interrupt

A/D Converter

Generator 0/1

R/W 00000000

R/W 00XXXX00

R/W 00000000

R/W 00000000

R/W 0_00X__1

MB90495 Series Data Sheet (Advance Information) 12 / 40 FMG EMDC June 19, 2000