F2MC-16LX MB90495G Series
MB90497G/F497G/F498G/V495G
DESCRIPTION
■
The MB90495G Series is a general-purpose, high-performance 16-bit microcontroller. It was designed f or devices
like consumer electronics, which require high-speed, real-time process control. This series features an on-chip
full-CAN interface.
In addition to being backwards compatible with the F
panded to add support for high-level language instructions, e xpanded addressing mode, and enhanced multiply/
divide and bit processing instructions. A 32-bit accumulator is also provided, making it possible to process long
word (32-bit) data.
2
MC* family architecture, the instruction set has been ex-
DS07-13713-3E
The MB90495G Series peripheral resources include on chip 8/10-bit A/D converter, UART (SCI) 0/1, 8/16-bit
PPG timer, 16-bit I/O timer (16-bit free-run timer, input capture 0, 1, 2, 3 (ICU) ) , and CAN controller.
2
* : F
MC is abbreviation for Fujitsu Flexible Microcontroller. F2MC is a registered trademark of Fujitsu Limited.
FEATURES
■
• Models that support +125 °C
•Clock
•Built-in PLL clock multiplier circuit
•Choose 1/2 oscillation clock or ×1 to ×4 multiplied oscillation clock (f or a 4-MHz oscillation cloc k, 4 to 16 MHz)
machine (PLL) clock
(Continued)
PACKAGES
■
64-pin plastic QFP64-pin plastic LQFP
(FPT-64P-M06) (FPT-64P-M09)
MB90495G Series
(Continued)
•Select subclock behavior (8.192 kHz)
•Minimum instruction execution time : 62.5 ns (operating with 4-MHz oscillation clock and × 4 PLL clock)
• 16-MByte CPU memory space
•24-bit internal addressing
•External access possible through selection of 8/16-bit bus width (external bus mode)
• Optimum instruction set for controller applications
•Wealth of data types (Bit, Byte, Word, Long Word)
•Wealth of addressing modes (23 different modes)
•Enhanced signed multiply-divide instructions and RETI instruction functions
Number of channels : 2 (two 8-bit channels can be used)
Two 8-bit or one 16-bit channel PPG operation possible
Free interval, free duty pulse output possible
Count clock : 62.5 ns to 1 µs (with 16-MHz machine clock)
(Continued)
(Continued)
Part Number
Parameter
Delayed interrupt generation
module
DTP/external interrupt circuit
8/10-bit A/D converter
UART0 (SCI)
UART1 (SCI)
CAN
MB90495G Series
MB90F497GMB90497GMB90F498GMB90V495G
Module for delayed interrupt generation switching tasks
Used in real-time OS
Number of inputs : 8
Starting by rising edge, falling edge, “H” level input, or “L” level input, external
interrupts or extended intelligent I/O service (EI
Number of channels : 8
Resolution : set 10-bit or 8-bit
Conversion time : 6.13 µs (with 16-MHz machine clock, including sampling time)
Continuous conversion of multiple linked channels possible
(up to 8 channels can be set)
One-shot conversion mode : converts selected channel only once
Continuous conversion mode : converts selected channel continuously
Stop conversion mode : converts selected channel and suspends operation
repeatedly
Number of channels : 1
Clock-synchronous forwarding : 62.5 Kbps to 2 Mbps
Clock-asynchronous forwarding : 1,202 bps to 62,500 bps
Transmission can be performed by two-way serial transmission or by master/
slave connection
Number of channels : 1
Clock-synchronous forwarding : 62.5 Kbps to 2 Mbps
Clock-asynchronous forwarding : 9,615 bps to 500 Kbps
Transmission can be performed by two-way serial transmission or by master/
slave connection
Compliant with CAN specification versions 2.0A and 2.0B
Send/receive message buffers : 8
Forwarding bit rate : 10 Kbps to 1 Mbps (with 16-MHz machine clock)
2
OS) can be used
PACKAGES AND CORRESPONDING PRODUCTS
■
PackageMB90F497GMB90497GMB90F498G
FPT-64P-M06
FPT-64P-M09
: available × : not available
Note : See “Package Dimensions” for details.
PRODUCT COMPARISON
■
Memory Size
When evaluating with e valuation chips and other means, tak e careful note of the different between the e valuation
chip and the chip actually used. Take particular note of the following.
• While the MB90V495G does not feature an on-chip ROM, the dedicated development tool can be used to
achieve operation equivalent to a product with built-in ROM. Therefore, the ROM size is configured by the
development tool.
• On the MB90V495G, the FF4000
FF3FFF
• On the MB90F497G/F498G/497G, the FF4000
to FF3FFFH is visible only in the FF bank.
H is only visible in the FE and FF banks (configurable on development tool) .
H to FFFFFFH image is only visible in the 00 bank, and the FE0000H to
H to FFFFFFH image is visible in the 00 bank, and the FF0000H
5
MB90495G Series
PIN ASSIGNMENTS
■
• FPT-64P-M06
SS
P27/INT7/A23
P30/SOT0/ALE
V
(TOP VIEW)
P26/INT6/A22
P25/INT5/A21
P24/INT4/A20
P23/TOT1/A19
P22/TIN1/A18
P21/TOT0/A17
P20/TIN0/A16
P17/PPG3/AD15
P16/PPG2/AD14
P15/PPG1/AD13
P14/PPG0/AD12
P13/IN3/AD11
P12/IN2/AD10
P11/IN1/AD09
P10/IN0/AD08
P07/AD07
P31/SCK0/RD
P32/SIN0/WRL
P33/WRH
P34/HRQ
P35/HAK
V
CC
P36/FRCK/RDY
P37/ADTG/CLK
P40/SIN1
P41/SCK1
P42/SOT1
P43/TX
51
52
58
C
64
1
P44/RX
P50/AN0
P51/AN1
P61/INT1
P62/INT2
P52/AN2
P53/AN3
P54/AN4
P55/AN5
42
10
CC
AV
P56/AN6
P57/AN7
AVR
SS
AV
P60/INT0
X0A
X1A
P63/INT3
33
32
26
20
19
MD0
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
V
General-purpose I/O port
Only enabled in single-chip mode.
D
AD00 to
AD07
P10 to P13
IN0 to IN3
AD08 to
AD11
I/O pin for the lower 8-bit of the external address data bus.
Only enabled during external bus mode.
General-purpose I/O port. Only enabled in single-chip mode.
Functions as trigger input pin for input capture channels 0 to 3. Set this to
D
input port.
I/O pin for upper 4-bit of external address data bus.
Only enabled during external bus mode.
(Continued)
8
(Continued)
Pin No.
M06M09
38 to 4137 to
40
Pin Name
P14 to P17
PPG0 to
PPG3
Circuit
Type
D
MB90495G Series
Description
General-purpose I/O port.
Only enabled in single-chip mode.
Functions as output pin of PPG timer 01, 23. Only valid if output configuration is enabled.
4241
4342
AD12 to
AD15
P20
TIN0
A16
P21
TOT0
A17
P22
I/O pin for upper 4-bit of external address data bus.
Only enabled during external bus mode.
General-purpose I/O port.
When the bits of high address control register (HACR) are set to “1” in external bus mode, these pins function as general purpose I/O ports.
Functions as event input pin of TIN0 reload timer 0.
D
Set this to input port.
Output pin of external address bus (A16) .
Only valid when the bits of high address control register (HACR) are set
to “0” in external bus mode.
General-purpose I/O port.
When the bits of high address control register (HACR) are set to “1” in external bus mode, these pins function as general purpose I/O ports.
Functions as event output pin of TOT0 reload timer 0.
D
Only valid if output configuration enabled.
Output pin of external address bus (A17) .
Only valid when the bits of high address control register (HACR) are set
to “0” in external bus mode.
General-purpose I/O port.
When the bits of high address control register (HACR) are set to “1” in external bus mode, these pins function as general purpose I/O ports.
4443
4544
TIN1
A18
P23
TOT1
A19
Functions as event input pin of TIN1 reload timer 1.
D
Set this to input port.
Output pin of external address bus (A18) .
Only valid when the bits of high address control register (HACR) are set
to “0” in external bus mode.
General-purpose I/O port.
When the bits of high address control register (HACR) are set to “1” in external bus mode, these pins function as general purpose I/O ports.
Functions as event output pin for TOT1 reload timer 1.
D
Only valid if output configuration enabled.
Output pin for external address bus (A19) .
Only valid when the bits of high address control register (HACR) are set
to “0” in external bus mode.
(Continued)
9
MB90495G Series
(Continued)
Pin No.
M06M09
46 to 4945 to
48
Pin Name
P24 to P27
INT4 to INT7
A20 to A23
Circuit
Type
D
Description
General-purpose I/O port.
When the bits of high address control register (HACR) are set to “1” in external bus mode, these pins function as general purpose I/O ports.
Functions as external interrupt input pin. Set this to input port.
Output pin for external address bus (A20 to A23) .
Only valid when the bits of high address control register (HACR) are set
to “0” in external bus mode.
5049V
P30
5150
5251
5352
5453
SOT0
ALE
P31
SCK0
P32
SIN0
WRL
P33
WRH
SSPower supply (0 V) input pin.
General-purpose I/O port.
Only enabled in single-chip mode.
UART0 serial data output pin.
D
Only valid if UART0 serial data output configuration is enabled.
Address latch authorization output pin.
Only enabled during external bus mode.
General-purpose I/O port.
Only enabled in single-chip mode.
UART0 serial clock I/O pin.
D
Only valid if UART0 serial clock I/O configuration is enabled.
RD
Lead strobe output pin.
Only enabled during external bus mode.
General-purpose I/O port.
UART0 serial data input pin.
D
Set this to input port.
Write strobe output pin for lower 8-bit of data bus.
Only valid if WRL
General-purpose I/O port.
D
Write strobe output pin for upper 8-bit of data bus.
Only valid if external bus mode/16-bit bus mode/WRH
pin output is enabled, in external bus mode.
pin output enabled.
5554
5655
5756V
5857C
10
P34
HRQ
P35
HAK
CCPower supply (5 V) input pin.
General-purpose I/O port.
D
Hold request input pin.
Only valid if hold input is enabled, in external bus mode.
General-purpose I/O port.
D
Hold addressing output pin.
Only valid if hold input is enabled, in external bus mode.
Capacity pin for power stabilization.
Please connect to an approximately 0.1 µF ceramic capacitor.
(Continued)
(Continued)
Pin No.
M06M09
Pin Name
P36
Circuit
Type
MB90495G Series
Description
General-purpose I/O port.
5958
6059
6160
6261
6362
6463
164
FRCK
RDY
P37
ADTGFunctions as A/D converter external trigger input pin. Set this to input port.
CLK
P40
SIN1
P41
SCK1
P42
SOT1
P43
TX
P44
RX
Functions as an external clock input pin for a FRCK 16-bit free-run timer.
D
Set this to input port.
External ready input pin.
Only valid if external ready input is enabled, in external bus mode.
General-purpose I/O port.
D
External clock output pin.
Only valid if external clock output is enabled, in external bus mode.
General-purpose I/O port.
D
UART1 serial data input pin.
Set this to input port.
General-purpose I/O port.
D
UART1 serial clock I/O pin.
Only valid if UART1 clock I/O configuration is enabled.
General-purpose I/O port.
D
UART1 serial data output pin.
Only valid if UART1 serial data output configuration is enabled.
General-purpose I/O port.
D
CAN transmission output pin.
Only valid if output configuration enabled.
General-purpose I/O port.
D
CAN reception input pin.
Set this to input port.
11
MB90495G Series
I/O CIRCUIT TYPE
■
TypeCircuitRemarks
X1
Clock input
X1A
• High speed oscillation feedback
resistor : 1 MΩ approx.
• Make sure you do not exceed the maximum rated values (in order to prevent latch-up) .
• CMOS IC chips may suffer latch-up if a voltage higher than V
output pin with other than mid or high current resistance; or voltage exceeding the r ating is applied across VCC
and V
SS.
• Latch-ups can dramatically increase the power supply current, causing thermal breakdown of the device.
Make sure that you do not exceed the maximum rated value of your device, in order to prevent a latch-up.
• When turning the analog power supply on or off, make sure that the analog power v oltage (AV
analog input voltages do not exceed the digital voltage (VCC) .
• Handling Unused Pins
Leaving unused input pins open may cause malfunctions and latch-ups, per manently damaging the device.
Prevent this by connecting it to a pull-up or pull-down resistor of no less than 2 kΩ. Leave unused output pins
open in output mode, or if in input mode, handle them in the same as input pins.
• Notes on Using External Clock
When using the external clock, drive pin X0 only, and leave pin X1 unconnected. See below for an example of
external clock use.
CC or lower than VSS is applied to an input or
CC, A VR) and
Example External Clock Use
X0
Open
X1
MB90495G Series
• Notes on Not Using Subclock
If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the
X1A pin open.
•Power Supply Pins
• If your product has multiple V
CC or VSS pins, pins of the same potential are internally connected in the device
in order to avoid abnormal operation, including latch-up . Howe ver, you should mak e sure to connect the pins’
external power and ground lines, in order to low er unneeded emissions, prevent abnormal operation of strobe
signals due to a rise in ground levels, and maintain total output current within rated levels.
• T ak e care to connect the V
CC and VSS pins of MB90495G Series devices to power lines via the low est possible
impedance.
• It is recommended that you connect a bypass capacitor of approximately 0.1 µF between V
CC and VSS near
MB90495G Series device pins.
• Crystal Oscillator Circuit
• Noise in the vicinity of X0 and X1 pins could cause abnormal operations in MB90495G Series devices. Make
sure to provide bypass capacitors via the shortest possible distance from X0 and X1 pins, crystal oscillators
(or ceramic resonators) , and ground lines. In addition, design your printed circuit boards so as to keep X0
and X1 wiring from crossing other wiring, if at all possible.
• It is strongly recommended that you provide printed circuit board artwork surrounding X0 and X1 pins within
a grand area, as this should stabilize operation.
14
MB90495G Series
• A/D Converter Power-up and Analog Input Initiation Sequence
• Make sure to power up the A/D con verter and analog input (pins AN0 to AN7) after turning on digital power
(V
CC) .
• Turn off digital power after turning off the A/D converter power supply and analog inputs. In this case, make
sure that the voltage of AVR does not exceed AV
simultaneously) .
• Connecting Unused A/D Converter Pins
CC (it is permissible to turn off analog and digital power
If you are not using the A/D converter, set unused pins to AV
CC= AVR = VCC, AVSS= VSS.
• Notes for Powering Up
Ensure that the voltage step-up time (between 0.2 V and 2.7 V) at power-up is no less than 50 µs, in order to
prevent malfunction in the built-in step-down circuit.
• Initialization
The device contains built-in registers which are only initialized by a power-on reset. Cycle the power supply to
initialize these registers.
• Stabilizing the Power Supply
Make sure that the V
CC power supply voltage is stable. Even at the rated operating VCC power supply voltage,
large, sudden changes in the voltage could cause malfunctions. As a standard for stable power supply, keep
V
CC ripples (peak-to-peak value) at commercial power frequencies (50 Hz to 60 Hz) to no more than 10% of the
power supply voltage, and momentary surges caused by switching the power supply and other events to more
than 0.1 V/ms.
• If Output from Ports 0/1 Becomes Undefined
After power is turned on, if the RST
on reset) , ports 0 and 1 output will be undefined. If the RST
pin is set to “H” during step-down circuit stabilization standby (during power-
pin is set to “L”, ports 0 and 1 will go into a high
impedance state. Take careful note of the timing of events outlined in figures 1 and 2.
15
MB90495G Series
•
Figure 1 - Timing Chart of Undefined Output from Ports 0/1 (with RST
Time in standby for oscillation to stabilize
VCC (power supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operating clock A) signal
KB (internal operating clock B) signal
PORT (port output) signal
Time in standby for stepdown circuit to stabilize
Time of undefined output
1
*
pin set to “H
*1 : Step-down circuit stabilization standby time : 217/oscillation clock frequency
(with 16-MHz oscillation clock frequency, about 8.19 ms)
*2 : Oscillation stabilization standby time : 2
18
/oscillation clock frequency
(with 16-MHz oscillation clock frequency, about 16.36 ms)
”)
2
*
•
Figure 2 - Timing Chart of High Impedance State for Ports 0/1 (when RST
Time in standby for oscillation to stabilize
VCC (power supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operation clock A) signal
KB (internal operating clock B) signal
PORT (port output) signal
Step-down circuit
stabilization standby time
High impedance
1
*
*1 : Step-down circuit stabilization standby time : 217/oscillation clock frequency
(with 16-MHz oscillation clock frequency, about 8.19 ms)
*2 : Oscillation stabilization standby time : 2
18
/oscillation clock frequency
(with 16-MHz oscillation clock frequency, about 16.38 ms)
pin is “L
2
*
”)
16
MB90495G Series
• Caution on Operations during PLL Clock Mode
If the PLL clock mode is selected in the microcontroller , it may attempt to continue the operation using the freerunning frequency of the automatic oscillating circuit in the PLL circuitry even if the oscillator is out of place or
the clock input is stopped. Performance of this operation, however, cannot be guaranteed.
++++
• Support for
125
°°°°
C
If used exceeding T
A=+105 °C, be sure to contact us for reliability limitations.
17
MB90495G Series
BLOCK DIAGRAM
■
X0, X1
RST
X0A, X1A
SOT1
SCK1
SIN1
SOT0
SCK0
SIN0
Clock
control circuit
Watch timer
Time-base timer
RAM
ROM/FLASH
Prescaler
UART1
Prescaler
UART0
CPU
2
F
MC-16LX
Core
16 bit
free-run timer
Input
capture
(4 ch)
16-bit
PPG timer
(2 ch)
Internal data bus
CAN
DTP/external
interrupt circuit
16 bits
reload timer
(2 ch)
FRCK
IN0 to IN3
PPG0 to PPG3
RX
TX
INT0 to INT7
TIN0, TIN1
TOT0, TOT1
18
AV
CC
AVSS
AN0 to AN7
AVR
ADTG
8/10 bit
A/D converter
(8 ch)
External bus
AD00 to AD15
A16 to A23
ALE
RD
WRL
WRH
HRQ
HAK
RDY
CLK
MB90495G Series
MEMORY MAP
■
The memory access modes of the MB90495G Series can be set to single chip mode, internal ROM - exter n al
bus mode, and external ROM - external bus mode.
1.Memory Allocation of the MB90495G
The MB90495G Series has 24-bit internal address bus and 24-bit external address bus output, enabling it to
access up to 16 Mbytes of external access memory . The enable/disab le time of the ROM mirror function is shown
graphically in the memory map.
Note : When the internal ROM is operational, the ROM data in the upper address of bank 00 of the F2MC-16LX is
visible in an image. This is called the ROM mirror function, and tak es advantage of the small C compiler model.
With the F
2
MC-16LX, the lower 16-bit address of bank FF and the lower 16-bit address of bank 00 are set
identical to one another. This allo ws the ROM-internal table to be ref erenced without specifying a far pointer .
For e xample, sa y the address “00C000
H” is accessed. In actuality, the “FFC000H ” address inside ROM will
be accessed. Howev er, as the ROM space in bank FF exceeds 48 Kb ytes, the entire space cannot be viewed
on bank 00’s image. And so, since “FF4000
“00FFFF
H” image, save the ROM data table in the “FF4000H” to “FFFFFFH” space.
H” to “FFFFFFH” ROM data will be visible on the “004000H” to
19
MB90495G Series
I/O MAP
■
Address
000000
Register
Abbreviation
HPDR0Port 0 data registerR/WPort 0XXXXXXXXB
Register NameAccessResource NameInitial Value
000001HPDR1Port 1 data registerR/WPort 1XXXXXXXXB
000002HPDR2Port 2 data registerR/WPort 2XXXXXXXXB
000003HPDR3Port 3 data registerR/WPort 3XXXXXXXXB
000004HPDR4Port 4 data registerR/WPort 4XXXXXXXXB
000005HPDR5Port 5 data registerR/WPort 5XXXXXXXXB
000006HPDR6Port 6 data registerR/WPort 6XXXXXXXXB
000007H