FUJITSU MB90495G DATA SHEET

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FUJITSU SEMICONDUCTOR

DATA SHEET

16-bit Proprietary Microcontroller

CMOS

F2MC-16LX MB90495G Series MB90497G/F497G/F498G/V495G

DESCRIPTION

■

The MB90495G Series is a general-purpose, high-performance 16-bit microcontroller. It was designed f or devices like consumer electronics, which require high-speed, real-time process control. This series features an on-chip full-CAN interface.

In addition to being backwards compatible with the F panded to add support for high-level language instructions, e xpanded addressing mode, and enhanced multiply/ divide and bit processing instructions. A 32-bit accumulator is also provided, making it possible to process long word (32-bit) data.

MC* family architecture, the instruction set has been ex-

DS07-13713-3E

The MB90495G Series peripheral resources include on chip 8/10-bit A/D converter, UART (SCI) 0/1, 8/16-bit PPG timer, 16-bit I/O timer (16-bit free-run timer, input capture 0, 1, 2, 3 (ICU) ) , and CAN controller.

* : F

MC is abbreviation for Fujitsu Flexible Microcontroller. F2MC is a registered trademark of Fujitsu Limited.

FEATURES

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• Models that support +125 °C

•Clock

•Built-in PLL clock multiplier circuit

•Choose 1/2 oscillation clock or ×1 to ×4 multiplied oscillation clock (f or a 4-MHz oscillation cloc k, 4 to 16 MHz) machine (PLL) clock

(Continued)

PACKAGES

■

64-pin plastic QFP 64-pin plastic LQFP

(FPT-64P-M06) (FPT-64P-M09)

MB90495G Series

(Continued)

•Select subclock behavior (8.192 kHz)

•Minimum instruction execution time : 62.5 ns (operating with 4-MHz oscillation clock and × 4 PLL clock)

• 16-MByte CPU memory space

•24-bit internal addressing

•External access possible through selection of 8/16-bit bus width (external bus mode)

• Optimum instruction set for controller applications

•Wealth of data types (Bit, Byte, Word, Long Word)

•Wealth of addressing modes (23 different modes)

•Enhanced signed multiply-divide instructions and RETI instruction functions

•Enhanced high-precision arithmetic employing 32-bit accumulator

• Instruction set supports high-level programming language (C) and multitasking

•Employs system stack pointer

•Enhanced indirect instructions with all pointer types

•Barrel shift instructions

• Improved execution speed

•4-byte instruction queue

• Powerful interrupt feature

•Powerful 8-level, 34-condition interrupt feature

• CPU-independent automated data forwarding

•Extended intelligent I/O service feature (EI

• Low-power consumption (Standby) Mode

•Sleep mode (CPU operation clock stopped)

•Time-base timer mode (oscillation clock and subclock, time-base timer and watch timer only operational)

•Watch mode (subclock and watch timer only operational)

•Stop mode (oscillation clock and subclock stopped)

•CPU intermittent operation mode

• Process

•CMOS technology

• I/O Ports

•Generic I/O ports (CMOS output) : 49

•Timer

•Time-base timer, watch timer, watchdog timer : 1 channel

•8/16-bit PPG timer : four 8-bit channels, or two 16-bit channels

•16-bit reload timer : 2 channels

•16-bit I/O timer

•16-bit free-run timer : 1 channel

•16-bit input capture (ICU) : 4 channels

Generates interrupt requests by latching onto the count value of the 16-bit free-run timer with pin input edge detection

OS) : maximum 16 channels

(Continued)

MB90495G Series

(Continued)

•

CAN Controller

•CAN specifications conform to versions 2.0A and 2.0B

•8 on-chip message buffers

•Forwarding rate 10 Kbps to 1 Mbps (with 16-MHz machine clock)

• UART0 (SCI) /UART1 (SCI) : 2 channels

•All with full duplex double buffer

•Use clock-asynchronous or clock-synchronous serial forwarding

• DTP/external interrupt : 8 channels

•A module for launching extended intelligent I/O service (EI external output

• Delayed interrupt generation module

•Generates interrupt requests for switching tasks

• 8/10-bit A/D converter : 8 channels

•Switch between 8-bit and 10-bit resolution

•Launch through external trigger input

•Conversion time : 6.13 µs (with 16-MHz machine clock, including sampling time)

1 channel

OS) and generating external interrupts through

• Program batch function

•2-address pointer ROM correction

• Clock output function

MB90495G Series

PRODUCT LINEUP

■

Part Number

Paarmeter

Feature Classification FLASH ROM Mask ROM FLASH ROM Product Evaluated ROM Size 64 Kbytes 128 Kbytes  RAM Size 2 Kbytes 6 Kbytes Process CMOS Package LQFP64 (width 0.65 mm) , QFP64 (width 1.0 mm) PGA256 Operating Power 4.5 V to 5.5 V Emulator power supply*  None

CPU Functions

Low-power consumption (Standby) Mode

I/O Ports General-purpose I/O ports (CMOS output) : 49

Time-base timer

Watchdog timer

MB90F497G MB90497G MB90F498G MB90V495G

Number of instructions Instruction bit length Instruction length Data bit length

Minimum execution time : 62.5 ns (with 16-MHz machine clock) Interrupt processing time : minimum 1.5 µs (with 16-MHz machine clock) Sleep mode/watch mode/time-base timer mode/stop mode / CPU intermittent

mode

18-bit free-run counter Interrupt interval : 1.024 ms, 4.096 ms, 16.834 ms, 131.072 ms (with 4-MHz oscillation clock)

Reset generation intervals : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (with 4-MHz oscillation clock)

: 351 : 8-bit, 16-bit : 1 to 7 bytes : 1 bit, 8-bit, 16-bit

16-bit free-run timer

16-bit I/O Timer

Input capture

16-bit reload timer

Watch timer

8/16-bit PPG timer

* : The S2 dipswitch setting when using the MB2145-507 emulation baud. For details, see the MB2145-507

hardware manual (2.7 Emulator Power Pin) .

Number of channels : 1 Interrupts from overflow generation

Number of channels : 4 Maintenance of free-run timer value through pin input (rising, falling or both edges)

Number of channels : 2 16-bit reload timer operation Count clock interval : 0.25 µs, 0.5 µs, 2.0 µs (with 16-MHz machine clock) External event count enabled

15-bit free-run counter Interrupt intervals : 31.25 ms, 62.5 ms, 12 ms, 250 ms, 500 ms, 1.0 s, 2.0 s (with 8.192-kHz subclock)

Number of channels : 2 (two 8-bit channels can be used) Two 8-bit or one 16-bit channel PPG operation possible Free interval, free duty pulse output possible Count clock : 62.5 ns to 1 µs (with 16-MHz machine clock)

(Continued)

Part Number

Parameter

Delayed interrupt generation module

DTP/external interrupt circuit

8/10-bit A/D converter

UART0 (SCI)

UART1 (SCI)

CAN

MB90495G Series

MB90F497G MB90497G MB90F498G MB90V495G

Module for delayed interrupt generation switching tasks Used in real-time OS

Number of inputs : 8 Starting by rising edge, falling edge, “H” level input, or “L” level input, external interrupts or extended intelligent I/O service (EI

Number of channels : 8 Resolution : set 10-bit or 8-bit Conversion time : 6.13 µs (with 16-MHz machine clock, including sampling time) Continuous conversion of multiple linked channels possible (up to 8 channels can be set) One-shot conversion mode : converts selected channel only once Continuous conversion mode : converts selected channel continuously Stop conversion mode : converts selected channel and suspends operation repeatedly

Number of channels : 1 Clock-synchronous forwarding : 62.5 Kbps to 2 Mbps Clock-asynchronous forwarding : 1,202 bps to 62,500 bps Transmission can be performed by two-way serial transmission or by master/ slave connection

Number of channels : 1 Clock-synchronous forwarding : 62.5 Kbps to 2 Mbps Clock-asynchronous forwarding : 9,615 bps to 500 Kbps Transmission can be performed by two-way serial transmission or by master/ slave connection

Compliant with CAN specification versions 2.0A and 2.0B Send/receive message buffers : 8 Forwarding bit rate : 10 Kbps to 1 Mbps (with 16-MHz machine clock)

OS) can be used

PACKAGES AND CORRESPONDING PRODUCTS

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Package MB90F497G MB90497G MB90F498G

FPT-64P-M06 FPT-64P-M09

: available × : not available

Note : See “Package Dimensions” for details.

PRODUCT COMPARISON

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Memory Size

When evaluating with e valuation chips and other means, tak e careful note of the different between the e valuation chip and the chip actually used. Take particular note of the following.

• While the MB90V495G does not feature an on-chip ROM, the dedicated development tool can be used to achieve operation equivalent to a product with built-in ROM. Therefore, the ROM size is configured by the development tool.

• On the MB90V495G, the FF4000 FF3FFF

• On the MB90F497G/F498G/497G, the FF4000 to FF3FFFH is visible only in the FF bank.

H is only visible in the FE and FF banks (configurable on development tool) .

H to FFFFFFH image is only visible in the 00 bank, and the FE0000H to

H to FFFFFFH image is visible in the 00 bank, and the FF0000H

MB90495G Series

PIN ASSIGNMENTS

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• FPT-64P-M06

P27/INT7/A23

P30/SOT0/ALE

(TOP VIEW)

P26/INT6/A22

P25/INT5/A21

P24/INT4/A20

P23/TOT1/A19

P22/TIN1/A18

P21/TOT0/A17

P20/TIN0/A16

P17/PPG3/AD15

P16/PPG2/AD14

P15/PPG1/AD13

P14/PPG0/AD12

P13/IN3/AD11

P12/IN2/AD10

P11/IN1/AD09

P10/IN0/AD08

P07/AD07

P31/SCK0/RD

P32/SIN0/WRL

P33/WRH

P34/HRQ

P35/HAK

P36/FRCK/RDY P37/ADTG/CLK

P40/SIN1 P41/SCK1 P42/SOT1

P43/TX

P44/RX

P50/AN0

P51/AN1

P61/INT1

P62/INT2

P52/AN2

P53/AN3

P54/AN4

P55/AN5

P56/AN6

P57/AN7

AVR

P60/INT0

X0A

X1A

P63/INT3

MD0

P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 V

X1 X0 MD2 MD1 RST

(FPT-64P-M06)

• FPT-64P-M09

(TOP VIEW)

P27/INT7/A23

P26/INT6/A22

P25/INT5/A21

P24/INT4/A20

P23/TOT1/A19

P22/TIN1/A18

P21/TOT0/A17

P20/TIN0/A16

P17/PPG3/AD15

P16/PPG2/AD14

MB90495G Series

P15/PPG1/AD13

P14/PPG0/AD12

P13/IN3/AD11

P12/IN2/AD10

P11/IN1/AD09

P10/IN0/AD08

P30/SOT0/ALE

P31/SCK0/RD

P32/SIN0/WRL

P33/WRH

P34/HRQ

P35/HAK

P36/FRCK/RDY P37/ADTG/CLK

P40/SIN1 P41/SCK1 P42/SOT1

P43/TX P44/RX

P50/AN0

P51/AN1

P52/AN2

P61/INT1

P62/INT2

P53/AN3

P54/AN4

P55/AN5

P56/AN6

AVR

P57/AN7

P60/INT0

X0A

X1A

P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00

V X1 X0 MD2 MD1 RST MD0 P63/INT3

(FPT-64P-M09)

MB90495G Series

PIN DESCRIPTION

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Pin No.

Pin Name

M06 M09

P61

INT1 Functions as external interrupt input pin. Set this to input port.

P62

INT2 Functions as external interrupt input pin. Set this to input port.

P50 to P57

4 to 11 3 to 10

AN0 to

AN7

12 11 AV

CC  VCC power input pin of A/D converter.

13 12 AVR  14 13 AV

SS  VSS power input pin of A/D converter.

P60

15 14

INT0 Functions as external interrupt input pin. Set this to input port.

16 15 X0A A

17 16 X1A A

Circuit

Type

Description

General-purpose I/O port

General-purpose I/O port Functions as analog input port of A/D converter. This is enabled if analog

input configuration is permitted.

Reference voltage (+) input pin for the A/D converter.This voltage must not exceed V

CC and AVCC. Reference voltage (−) is fixed to AVSS.

General-purpose I/O port

Low-speed oscillation pin. Perform pull-down processing if not connected to an oscillator.

Low-speed oscillation pin. Set to open if not connected to an oscillator.

18 17

P63

General-purpose I/O port

INT3 Functions as external interrupt input pin. Set this to input port. 19 18 MD0 C Input pin for specifying operation mode. 20 19 RST

B External reset input pin. 21 20 MD1 C Input pin for specifying operation mode. 22 21 MD2 F Input pin for specifying operation mode. 23 22 X0 A High-speed oscillation pin. 24 23 X1 A High-speed oscillation pin. 25 24 V

26 to 3325 to

34 to 3733 to

SS  Power supply (0 V) input pin.

P00 to P07

General-purpose I/O port Only enabled in single-chip mode.

AD00 to

AD07

P10 to P13

IN0 to IN3

AD08 to

AD11

I/O pin for the lower 8-bit of the external address data bus. Only enabled during external bus mode.

General-purpose I/O port. Only enabled in single-chip mode. Functions as trigger input pin for input capture channels 0 to 3. Set this to

input port. I/O pin for upper 4-bit of external address data bus.

Only enabled during external bus mode.

(Continued)

Pin No.

M06 M09

38 to 4137 to

Pin Name

P14 to P17

PPG0 to

PPG3

Circuit

Type

MB90495G Series

Description

General-purpose I/O port. Only enabled in single-chip mode.

Functions as output pin of PPG timer 01, 23. Only valid if output configuration is enabled.

42 41

43 42

AD12 to

AD15

P20

TIN0

A16

P21

TOT0

A17

P22

I/O pin for upper 4-bit of external address data bus. Only enabled during external bus mode.

General-purpose I/O port. When the bits of high address control register (HACR) are set to “1” in external bus mode, these pins function as general purpose I/O ports.

Functions as event input pin of TIN0 reload timer 0.

Set this to input port. Output pin of external address bus (A16) .

Only valid when the bits of high address control register (HACR) are set to “0” in external bus mode.

General-purpose I/O port. When the bits of high address control register (HACR) are set to “1” in external bus mode, these pins function as general purpose I/O ports.

Functions as event output pin of TOT0 reload timer 0.

Only valid if output configuration enabled. Output pin of external address bus (A17) .

Only valid when the bits of high address control register (HACR) are set to “0” in external bus mode.

General-purpose I/O port. When the bits of high address control register (HACR) are set to “1” in external bus mode, these pins function as general purpose I/O ports.

44 43

45 44

TIN1

A18

P23

TOT1

A19

Functions as event input pin of TIN1 reload timer 1.

Set this to input port. Output pin of external address bus (A18) .

Only valid when the bits of high address control register (HACR) are set to “0” in external bus mode.

General-purpose I/O port. When the bits of high address control register (HACR) are set to “1” in external bus mode, these pins function as general purpose I/O ports.

Functions as event output pin for TOT1 reload timer 1.

Only valid if output configuration enabled. Output pin for external address bus (A19) .

Only valid when the bits of high address control register (HACR) are set to “0” in external bus mode.

(Continued)

MB90495G Series

(Continued)

Pin No.

M06 M09

46 to 4945 to

Pin Name

P24 to P27

INT4 to INT7

A20 to A23

Circuit

Type

Description

General-purpose I/O port. When the bits of high address control register (HACR) are set to “1” in external bus mode, these pins function as general purpose I/O ports.

Functions as external interrupt input pin. Set this to input port. Output pin for external address bus (A20 to A23) .

Only valid when the bits of high address control register (HACR) are set to “0” in external bus mode.

50 49 V

P30

51 50

52 51

53 52

54 53

SOT0

ALE

P31

SCK0

P32

SIN0

WRL

P33

WRH

SS  Power supply (0 V) input pin.

General-purpose I/O port. Only enabled in single-chip mode.

UART0 serial data output pin.

Only valid if UART0 serial data output configuration is enabled. Address latch authorization output pin.

Only enabled during external bus mode. General-purpose I/O port.

Only enabled in single-chip mode. UART0 serial clock I/O pin.

Only valid if UART0 serial clock I/O configuration is enabled.

Lead strobe output pin. Only enabled during external bus mode.

General-purpose I/O port. UART0 serial data input pin.

Set this to input port. Write strobe output pin for lower 8-bit of data bus.

Only valid if WRL General-purpose I/O port.

Write strobe output pin for upper 8-bit of data bus. Only valid if external bus mode/16-bit bus mode/WRH

pin output is enabled, in external bus mode.

pin output enabled.

55 54

56 55

57 56 V 58 57 C 

P34

HRQ

P35

HAK

CC  Power supply (5 V) input pin.

General-purpose I/O port.

Hold request input pin. Only valid if hold input is enabled, in external bus mode.

General-purpose I/O port.

Hold addressing output pin. Only valid if hold input is enabled, in external bus mode.

Capacity pin for power stabilization. Please connect to an approximately 0.1 µF ceramic capacitor.

(Continued)

Pin No.

M06 M09

Pin Name

P36

Circuit

Type

MB90495G Series

Description

General-purpose I/O port.

59 58

60 59

61 60

62 61

63 62

64 63

164

FRCK

RDY

P37

ADTG Functions as A/D converter external trigger input pin. Set this to input port.

CLK

P40

SIN1

P41

SCK1

P42

SOT1

P43

P44

Functions as an external clock input pin for a FRCK 16-bit free-run timer.

Set this to input port. External ready input pin.

Only valid if external ready input is enabled, in external bus mode. General-purpose I/O port.

External clock output pin. Only valid if external clock output is enabled, in external bus mode.

General-purpose I/O port.

UART1 serial data input pin. Set this to input port.

General-purpose I/O port.

UART1 serial clock I/O pin. Only valid if UART1 clock I/O configuration is enabled.

General-purpose I/O port.

UART1 serial data output pin. Only valid if UART1 serial data output configuration is enabled.

General-purpose I/O port.

CAN transmission output pin. Only valid if output configuration enabled.

General-purpose I/O port.

CAN reception input pin. Set this to input port.

MB90495G Series

I/O CIRCUIT TYPE

■

Type Circuit Remarks

Clock input

X1A

• High speed oscillation feedback resistor : 1 MΩ approx.

• Low speed oscillation feedback resistor : 10 MΩ approx.

X0A

Standby control signal

• Hysteresis input with pull-up

VCC

Hysteresis input

• Pull-up Resistor : 50 kΩ approx.

• Hysteresis input

Hysteresis input

• CMOS hysteresis input

Pch

Digital output

IOL = 4 mA

Standby control

Nch

Digital output

Hysteresis input

• CMOS level output

• Standby control available

Pch

Digital output

• CMOS level output

• Doubles as analog input pin

• Standby control available

• CMOS hysteresis input

IOL = 4 mA

Nch

Standby control Analog input

Digital output

Hysteresis input

(Continued)

MB90495G Series

(Continued)

Type Circuit Remarks

Hysteresis input

• Pull-down Resistor : 50 kΩ approx. (except FLASH device)

• Hysteresis input with pull-down

MB90495G Series

HANDLING DEVICES

■

• Make sure you do not exceed the maximum rated values (in order to prevent latch-up) .

• CMOS IC chips may suffer latch-up if a voltage higher than V output pin with other than mid or high current resistance; or voltage exceeding the r ating is applied across VCC and V

SS.

• Latch-ups can dramatically increase the power supply current, causing thermal breakdown of the device.

Make sure that you do not exceed the maximum rated value of your device, in order to prevent a latch-up.

• When turning the analog power supply on or off, make sure that the analog power v oltage (AV

analog input voltages do not exceed the digital voltage (VCC) .

• Handling Unused Pins

Leaving unused input pins open may cause malfunctions and latch-ups, per manently damaging the device. Prevent this by connecting it to a pull-up or pull-down resistor of no less than 2 kΩ. Leave unused output pins open in output mode, or if in input mode, handle them in the same as input pins.

• Notes on Using External Clock

When using the external clock, drive pin X0 only, and leave pin X1 unconnected. See below for an example of external clock use.

CC or lower than VSS is applied to an input or

CC, A VR) and

Example External Clock Use

Open

MB90495G Series

• Notes on Not Using Subclock

If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the X1A pin open.

•Power Supply Pins

• If your product has multiple V

CC or VSS pins, pins of the same potential are internally connected in the device

in order to avoid abnormal operation, including latch-up . Howe ver, you should mak e sure to connect the pins’ external power and ground lines, in order to low er unneeded emissions, prevent abnormal operation of strobe signals due to a rise in ground levels, and maintain total output current within rated levels.

• T ak e care to connect the V

CC and VSS pins of MB90495G Series devices to power lines via the low est possible

impedance.

• It is recommended that you connect a bypass capacitor of approximately 0.1 µF between V

CC and VSS near

MB90495G Series device pins.

• Crystal Oscillator Circuit

• Noise in the vicinity of X0 and X1 pins could cause abnormal operations in MB90495G Series devices. Make

sure to provide bypass capacitors via the shortest possible distance from X0 and X1 pins, crystal oscillators (or ceramic resonators) , and ground lines. In addition, design your printed circuit boards so as to keep X0 and X1 wiring from crossing other wiring, if at all possible.

• It is strongly recommended that you provide printed circuit board artwork surrounding X0 and X1 pins within

a grand area, as this should stabilize operation.

MB90495G Series

• A/D Converter Power-up and Analog Input Initiation Sequence

• Make sure to power up the A/D con verter and analog input (pins AN0 to AN7) after turning on digital power

CC) .

• Turn off digital power after turning off the A/D converter power supply and analog inputs. In this case, make

sure that the voltage of AVR does not exceed AV simultaneously) .

• Connecting Unused A/D Converter Pins

CC (it is permissible to turn off analog and digital power

If you are not using the A/D converter, set unused pins to AV

CC = AVR = VCC, AVSS = VSS.

• Notes for Powering Up

Ensure that the voltage step-up time (between 0.2 V and 2.7 V) at power-up is no less than 50 µs, in order to prevent malfunction in the built-in step-down circuit.

• Initialization

The device contains built-in registers which are only initialized by a power-on reset. Cycle the power supply to initialize these registers.

• Stabilizing the Power Supply

Make sure that the V

CC power supply voltage is stable. Even at the rated operating VCC power supply voltage,

large, sudden changes in the voltage could cause malfunctions. As a standard for stable power supply, keep V

CC ripples (peak-to-peak value) at commercial power frequencies (50 Hz to 60 Hz) to no more than 10% of the

power supply voltage, and momentary surges caused by switching the power supply and other events to more than 0.1 V/ms.

• If Output from Ports 0/1 Becomes Undefined

After power is turned on, if the RST on reset) , ports 0 and 1 output will be undefined. If the RST

pin is set to “H” during step-down circuit stabilization standby (during power-

pin is set to “L”, ports 0 and 1 will go into a high

impedance state. Take careful note of the timing of events outlined in figures 1 and 2.

MB90495G Series

•

Figure 1 - Timing Chart of Undefined Output from Ports 0/1 (with RST

Time in standby for oscillation to stabilize

VCC (power supply pin)

PONR (power-on reset) signal

RST (external asynchronous reset) signal

RST (internal reset) signal

Oscillation clock signal

KA (internal operating clock A) signal KB (internal operating clock B) signal

PORT (port output) signal

Time in standby for stepdown circuit to stabilize

Time of undefined output

pin set to “H

*1 : Step-down circuit stabilization standby time : 217/oscillation clock frequency

(with 16-MHz oscillation clock frequency, about 8.19 ms)

*2 : Oscillation stabilization standby time : 2

/oscillation clock frequency

(with 16-MHz oscillation clock frequency, about 16.36 ms)

”)

•

Figure 2 - Timing Chart of High Impedance State for Ports 0/1 (when RST

Time in standby for oscillation to stabilize

VCC (power supply pin)

PONR (power-on reset) signal

RST (external asynchronous reset) signal

RST (internal reset) signal

Oscillation clock signal

KA (internal operation clock A) signal KB (internal operating clock B) signal

PORT (port output) signal

Step-down circuit

stabilization standby time

High impedance

*1 : Step-down circuit stabilization standby time : 217/oscillation clock frequency

(with 16-MHz oscillation clock frequency, about 8.19 ms)

*2 : Oscillation stabilization standby time : 2

/oscillation clock frequency

(with 16-MHz oscillation clock frequency, about 16.38 ms)

pin is “L

”)

MB90495G Series

• Caution on Operations during PLL Clock Mode

If the PLL clock mode is selected in the microcontroller , it may attempt to continue the operation using the freerunning frequency of the automatic oscillating circuit in the PLL circuitry even if the oscillator is out of place or the clock input is stopped. Performance of this operation, however, cannot be guaranteed.

++++

• Support for

125

°°°°

If used exceeding T

A = +105 °C, be sure to contact us for reliability limitations.

MB90495G Series

BLOCK DIAGRAM

■

X0, X1

RST

X0A, X1A

SOT1 SCK1

SIN1

SOT0 SCK0

SIN0

Clock

control circuit

Watch timer

Time-base timer

RAM

ROM/FLASH

Prescaler

UART1

Prescaler

UART0

CPU

MC-16LX

Core

16 bit

free-run timer

Input

capture

(4 ch)

16-bit

PPG timer

(2 ch)

Internal data bus

CAN

DTP/external

interrupt circuit

16 bits

reload timer

(2 ch)

FRCK

IN0 to IN3

PPG0 to PPG3

RX TX

INT0 to INT7

TIN0, TIN1 TOT0, TOT1

AVSS

AN0 to AN7

AVR

ADTG

8/10 bit

A/D converter

(8 ch)

External bus

AD00 to AD15 A16 to A23 ALE RD WRL WRH HRQ HAK RDY CLK

MB90495G Series

MEMORY MAP

■

The memory access modes of the MB90495G Series can be set to single chip mode, internal ROM - exter n al bus mode, and external ROM - external bus mode.

1. Memory Allocation of the MB90495G

The MB90495G Series has 24-bit internal address bus and 24-bit external address bus output, enabling it to access up to 16 Mbytes of external access memory . The enable/disab le time of the ROM mirror function is shown graphically in the memory map.

2. Memory Map

000000H 0000C0H 000100H

Address #1 002000H

003800

003900H

Address #2

010000H

Address #3

FFFFFFH

Single chip mode

(ROM mirror function available)

Periphery Periphery Periphery

RAM space

Extention

IO space

ROM space

(image of

bank FF)

ROM space

Internal access memory External access memory Access prohibited

Internal ROM

External bus mode

RAM space

Extention

IO space

ROM space

(image of

bank FF)

ROM space

External ROM

External bus mode

RAM space

Extention IO space

Product

Address #1

MB90V495G 001900

H 004000H (FC0000H)

Address #2 Address #3

MB90F497G 000900H 004000H FF0000H

MB90497G 000900H 004000H FF0000H

MB90F498G 000900H 004000H FE0000H

* : Addresses #1 and #3 are product-specific.

Note : When the internal ROM is operational, the ROM data in the upper address of bank 00 of the F2MC-16LX is

visible in an image. This is called the ROM mirror function, and tak es advantage of the small C compiler model. With the F

MC-16LX, the lower 16-bit address of bank FF and the lower 16-bit address of bank 00 are set identical to one another. This allo ws the ROM-internal table to be ref erenced without specifying a far pointer . For e xample, sa y the address “00C000

H” is accessed. In actuality, the “FFC000H ” address inside ROM will

be accessed. Howev er, as the ROM space in bank FF exceeds 48 Kb ytes, the entire space cannot be viewed on bank 00’s image. And so, since “FF4000 “00FFFF

H” image, save the ROM data table in the “FF4000H” to “FFFFFFH” space.

H” to “FFFFFFH” ROM data will be visible on the “004000H” to

MB90495G Series

I/O MAP

■

Address

000000

Abbreviation

H PDR0 Port 0 data register R/W Port 0 XXXXXXXXB

000001H PDR1 Port 1 data register R/W Port 1 XXXXXXXXB 000002H PDR2 Port 2 data register R/W Port 2 XXXXXXXXB 000003H PDR3 Port 3 data register R/W Port 3 XXXXXXXXB 000004H PDR4 Port 4 data register R/W Port 4 XXXXXXXXB 000005H PDR5 Port 5 data register R/W Port 5 XXXXXXXXB 000006H PDR6 Port 6 data register R/W Port 6 XXXXXXXXB 000007H

00000F 000010

H DDR0 Port 0 direction register R/W Port 0 0 0 0 0 0 0 0 0B

(system-reserved area) *

000011H DDR1 Port 1 direction register R/W Port 1 0 0 0 0 0 0 0 0B 000012H DDR2 Port 2 direction register R/W Port 2 0 0 0 0 0 0 0 0B 000013H DDR3 Port 3 direction register R/W Port 3 0 0 0 0 0 0 0 0B 000014H DDR4 Port 4 direction register R/W Port 4 XXX 0 0 0 0 0B 000015H DDR5 Port 5 direction register R/W Port 5 0 0 0 0 0 0 0 0B 000016H DDR6 Port 6 direction register R/W Port 6 XXXX 0 0 0 0B 000017H

00001A 00001B

H ADER Analog input enable register R/W

(system-reserved area) *

8/10-bit

A/D converter

1 1 1 1 1 1 1 1B

00001CH

00001F

000020

H SMR0 Serial mode register 0 R/W

(system-reserved area) *

0 0 0 0 0 0 0 0B

000021H SCR0 Serial control register 0 R/W 0 0 0 0 0 1 0 0B 000022H

SIDR0/

SODR0

Serial input data register 0/ Serial output data register 0

R/W XXXXXXXXB

UART0

000023H SSR0 Serial status register 0 R/W 0 0 0 0 1 X 0 0B 000024H CDCR0

Communication prescaler control register 0

R/W 0 XXX 1 1 1 1B

000025H SES0 Serial edge selection register 0 R/W XXXXXXX 0B 000026H SMR1 Serial mode register 1 R/W 000027H SCR1 Serial control register 1 R/W 0 0 0 0 0 1 0 0B

000028H

SIDR1/

SODR1

Serial input data register 1/ Serial output data register 1

R/W XXXXXXXXB

UART1

0 0 0 0 0 0 0 0B

(Continued)

Address

000029

Abbreviation

H SSR1 Serial status register 1 R/W UART1 0 0 0 0 1 0 0 0B

00002AH (system-reserved area) *

MB90495G Series

00002B

H CDCR1

Communication prescaler control register 1

R/W UART1 0 XXX 0 0 0 0B

00002CH

00002F

000030H ENIR DTP/external interrupt enable register R/W 000031H EIRR

DTP/external interrupt condition register

(system-reserved area) *

R/W XXXXXXXXB

0 0 0 0 0 0 0 0B

DTP/external

interrupt

000032H

R/W 0 0 0 0 0 0 0 0

ELVR Detection level configuration register

000033H R/W 0 0 0 0 0 0 0 0B 000034H

R/W

0 0 0 0 0 0 0 0

ADCS A/D control status register

000035H R/W 0 0 0 0 0 0 0 0B 000036H

R XXXXXXXX

8/10-bit

A/D converter

ADCR A/D data register

000037H R/W 0 0 1 0 1 XXXB 000038H

00003F

000040

H PPGC0 PPG0 operation mode control register R/W

000041H PPGC1 PPG1 operation mode control register R/W 0 X 0 0 0 0 0 1B

(system-reserved area) *

0 X 0 0 0 XX 1B

8/16-bit

PPG timer 0/1

000042H PPG01 PPG0/1 count clock selection register R/W 0 0 0 0 0 0 XXB

000043H (system-reserved area) * 000044H PPGC2 PPG2 operation mode control register R/W 000045H PPGC3 PPG3 operation mode control register R/W 0 X 0 0 0 0 0 1B

8/16-bit

PPG timer 2/3

0 X 0 0 0 XX 1B

000046H PPG23 PPG2/3 count clock selection register R/W 0 0 0 0 0 0 XXB 000047H

00004F

000050

(system-reserved area) *

XXXXXXXX

IPCP0 Input capture data register 0 R

000051H XXXXXXXXB 000052H

XXXXXXXX

IPCP1 Input capture data register 1 R

000053H XXXXXXXXB

16-bit I/O timer

000054H ICS01

0 0 0 0 0 0 0 0B

Input capture control status register R/W

000055H ICS23 0 0 0 0 0 0 0 0B 000056H

0 0 0 0 0 0 0 0

TCDT Timer counter data register R/W

000057H 0 0 0 0 0 0 0 0B

(Continued)

MB90495G Series

(Continued)

Address

000058 000059H 0 XXXXXXXB

Abbreviation

TCCS Timer counter control status register R/W

0 0 0 0 0 0 0 0

00005AH

IPCP2 Input capture data register 2 R

16-bit I/O timer

XXXXXXXX 00005BH XXXXXXXXB 00005CH

XXXXXXXX

IPCP3 Input capture data register 3 R

00005DH XXXXXXXXB 00005EH

000065 000066H

TMCSR0

(system-reserved area) *

R/W

16-bit reload timer 0

0 0 0 0 0 0 0 0

000067H R/W XXXX0 0 0 0B

Timer control status register

000068H

TMCSR1

R/W

16-bit reload timer 1

0 0 0 0 0 0 0 0

000069H R/W XXXX0 0 0 0B

00006AH

00006E 00006F

H ROMM ROM mirror function selection register W

(system-reserved area) *

ROM mirror function

selection module

XXXXXXX 1B

000070H

00007F

(system-reserved area) *

000080H BVALR Message buffer valid register R/W CAN controller 0 0 0 0 0 0 0 0B

000081H (system-reserved area) * 000082

H TREQR Send request register R/W CAN controller 0 0 0 0 0 0 0 0B

000083H (system-reserved area) * 000084

H TCANR Send cancel register W CAN controller 0 0 0 0 0 0 0 0B

000085H (system-reserved area) * 000086H TCR Send complete register R/W CAN controller 0 0 0 0 0 0 0 0B 000087H (system-reserved area) * 000088

H RCR Reception complete register R/W CAN controller 0 0 0 0 0 0 0 0B

000089H (system-reserved area) *

00008A

H RRTRR Reception RTR register R/W CAN controller 0 0 0 0 0 0 0 0B

00008BH (system-reserved area) * 00008C

H ROVRR Reception overrun register R/W CAN controller 0 0 0 0 0 0 0 0B

00008DH (system-reserved area) * 00008E

H RIER

Reception complete interrupt enable register

R/W CAN controller 0 0 0 0 0 0 0 0B

(Continued)

Address

00008F

00009D 00009E

H PACSR Address detection control register R/W

Abbreviation

MB90495G Series

(system-reserved area) *

ROM correction

function

0 0 0 0 0 0 0 0B

00009FH DIRR

0000A0H LPMCR

Delayed interrupt request generate/ cancel register

Low power consumption mode control register

R/W

Delayed interrupt

generation module

Low-power

consumption modes

XXXXXXX 0B

0 0 0 1 1 0 0 0B

0000A1H CKSCR Clock selection register R/W Clock 1 1 1 1 1 1 0 0B 0000A2H

0000A4 0000A5

H ARSR Auto ready function selection register W

(system-reserved area) *

0 0 1 1 XX 0 0B

0000A6H HACR High address control register W 0 0 0 0 0 0 0 0B

External access

0000A7H ECSR Bus control signal selection register W

0 0 0 0 0 0 0 X

0 0 0 0 1 0 0 X 0000A8H WDTC Watchdog timer control register R/W Watchdog timer XXXXX 1 1 1B 0000A9H TBTC Time-base timer control register R/W Time-base timer 1 XX 0 0 1 0 0B

0000AAH WTC Watch timer control register R/W Watch timer 1 0 0 0 1 0 0 0B 0000ABH

0000AD 0000AE

H FMCS Flash memory control status register R/W

(system-reserved area) *

512-Kbit

flash memory

0 0 0 X 0 0 0 0B 0000AFH (system-reserved area) *

0000B0

H ICR00 Interrupt control register 00 R/W

0 0 0 0 0 1 1 1B 0000B1H ICR01 Interrupt control register 01 R/W 0 0 0 0 0 1 1 1B 0000B2H ICR02 Interrupt control register 02 R/W 0 0 0 0 0 1 1 1B 0000B3H ICR03 Interrupt control register 03 R/W 0 0 0 0 0 1 1 1B 0000B4H ICR04 Interrupt control register 04 R/W 0 0 0 0 0 1 1 1B 0000B5H ICR05 Interrupt control register 05 R/W 0 0 0 0 0 1 1 1B

Interrupt controller 0000B6H ICR06 Interrupt control register 06 R/W 0 0 0 0 0 1 1 1B 0000B7H ICR07 Interrupt control register 07 R/W 0 0 0 0 0 1 1 1B 0000B8H ICR08 Interrupt control register 08 R/W 0 0 0 0 0 1 1 1B 0000B9H ICR09 Interrupt control register 09 R/W 0 0 0 0 0 1 1 1B

0000BAH ICR10 Interrupt control register 10 R/W 0 0 0 0 0 1 1 1B

(Continued)

MB90495G Series

(Continued)

Address

0000BB 0000BCH ICR12 Interrupt control register 12 R/W 0 0 0 0 0 1 1 1B 0000BDH ICR13 Interrupt control register 13 R/W 0 0 0 0 0 1 1 1B 0000BEH ICR14 Interrupt control register 14 R/W 0 0 0 0 0 1 1 1B

0000BFH ICR15 Interrupt control register 15 R/W 0 0 0 0 0 1 1 1B 0000C0H

0000FF 001FF0

001FF1H

001FF2H

001FF3H

001FF4H

001FF5H

003900H 003901H XXXXXXXXB 003902H 003903H XXXXXXXXB 003904H

00390F

003910 003911H PRLH0 PPG0 reload register H R/W XXXXXXXXB 003912H PRLL1 PPG1 reload register L R/W XXXXXXXXB 003913H PRLH1 PPG1 reload register H R/W XXXXXXXXB 003914H PRLL2 PPG2 reload register L R/W XXXXXXXXB 003915H PRLH2 PPG2 reload register H R/W XXXXXXXXB 003916H PRLL3 PPG3 reload register L R/W XXXXXXXXB 003917H PRLH3 PPG3 reload register H R/W XXXXXXXXB 003918H

003BFF

003C00

003C0F

Abbreviation

H ICR11 Interrupt control register 11 R/W

(system-reserved area) *

PADR0

PADR1

TMR0/

TMRLR0

TMR1/

TMRLR1

H PRLL0 PPG0 reload register L R/W

Detection address configuration register 0 (lower)

Detection address configuration register 0 (mid)

Detection address configuration register 0 (upper)

Detection address configuration register 1 (lower)

Detection address configuration register 1 (mid)

Detection address configuration register 1 (upper)

16-bit timer register 0/ 16-bit reload register 0

16-bit timer register 1/

-bit reload register 1

(system-reserved area) *

R/W

R/W XXXXXXXX

R/W 16-bit reload timer 0

R/W 16-bit reload timer 1

(system-reserved area) *

RAM (general-purpose RAM)

0 0 0 0 0 1 1 1B

Interrupt controller

XXXXXXXX

ROM correction

function

XXXXXXXX

XXXXXXXXB

8/16-bit PPG timer

(Continued)

Address

003C10

003C13

003C14H

003C17

Abbreviation

IDR0 ID register 0 R/W

IDR1 ID register 1 R/W

MB90495G Series

XXXXXXXX XXXXXXXX

003C18H

003C1B

003C1CH

003C1F

003C20H

003C23 003C24H

003C27 003C28H

003C2B

003C2CH

003C2F

003C30H 003C31H

003C32H 003C33H

IDR2 ID register 2 R/W

IDR3 ID register 3 R/W

IDR4 ID register 4 R/W

IDR5 ID register 5 R/W

IDR6 ID register 6 R/W

IDR7 ID register 7 R/W

DLCR0 DLC register 0 R/W

DLCR1 DLC register 1 R/W

CAN controller

XXXXXXXX

XXXXXXXX XXXXXXXX

XXXXXXXX XXXXXXXXB

XXXXXXXXB XXXXXXXXB

XXXXXXXXB

003C34H 003C35H

003C36H 003C37H

003C38H 003C39H

003C3AH 003C3BH

003C3CH 003C3DH

003C3EH 003C3FH

003C40H

003C47

DLCR2 DLC register 2 R/W

DLCR3 DLC register 3 R/W

DLCR4 DLC register 4 R/W

DLCR5 DLC register 5 R/W

DLCR6 DLC register 6 R/W

DLCR7 DLC register 7 R/W

DTR0 Data register 0 R/W

XXXXXXXXB XXXXXXXXB

XXXXXXXX

(Continued)

MB90495G Series

(Continued)

Address

003C48

003C4F

003C50H

003C57

Abbreviation

DTR1 Data register 1 R/W

DTR2 Data register 2 R/W

XXXXXXXX

XXXXXXXX XXXXXXXX

XXXXXXXX

003C58H

003C5F

003C60H

003C67 003C68H

003C6F

003C70H

003C77 003C78H

003C7F

DTR3 Data register 3 R/W

DTR4 Data register 4 R/W

DTR5 Data register 5 R/W

DTR6 Data register 6 R/W

DTR7 Data register 7 R/W

CAN controller

XXXXXXXX

XXXXXXXX XXXXXXXX

XXXXXXXX

003C80H

003CFF

003D00 003D01H

CSR Control status register R/W

(system-reserved area) *

CAN controller

0 XXXX 0 0 1B

0 0 XXX 0 0 0B

003D02H LEIR Display last event register R/W 0 0 0 XX 0 0 0B

003D03H (system-reserved area) * 003D04H

003D05H 003D06H

003D07H

RTEC Receive/transmit error counter R

BTR Bit timing register R/W

CAN controller

0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B

1 1 1 1 1 1 1 1B

X 1 1 1 1 1 1 1B 003D08H IDER IDE register R/W XXXXXXXXB 003D09H (system-reserved area) *

003D0A

H TRTRR Transmit RTR register R/W CAN controller 0 0 0 0 0 0 0 0B

003D0BH (system-reserved area) *

003D0CH RFWTR

Remote frame reception standby register

R/W CAN controller XXXXXXXXB

003D0DH (system-reserved area) *

003D0E

H TIER

Transmit complete interrupt enable register

R/W CAN controller 0 0 0 0 0 0 0 0B

(Continued)

Address

003D0F

H (system-reserved area) *

Abbreviation

MB90495G Series

003D10 003D11H

003D12H 003D13H

003D14 003D17

AMSR Acceptance mask selection register R/W CAN controller

(system-reserved area) *

AMR0 Acceptance mask register 0 R/W

CAN controller

003D18H

003D1B

AMR1 Acceptance mask register 1 R/W

003D1CH

003FFF

(system-reserved area) *

Explanation of reset values 0 : The reset value of this bit is 0. 1 : The reset value of this bit is 1. X : The reset value of this bit is undefined.

* : System-reserved area contains system-internal addresses, and cannot be used.

XXXXXXXXB XXXXXXXXB

XXXXXXXX

XXXXXXXX XXXXXXXX

XXXXXXXX

MB90495G Series

INTERRUPT CONDITIONS AND INTERRUPT VECTOR/REGISTER

■

Interrupt Condition

Compatible

Reset × #08 08 INT 9 instruction × #09 09 Exception processing × #10 0A

Interrupt Vector Interrupt Register

Number Address ICR Address

H FFFFDCH Highest H FFFFD8H  ↑ H FFFFD4H 

Can controller reception complete (RX) × #11 0BH FFFFD0H Can controller reception complete (TX)

/Node status transition (NS)

× #12 0C

H FFFFCCH

Reserved × #13 0DH FFFFC8H Reserved × #14 0EH FFFFC4H External interrupt (INT0/INT1) #15 0FH FFFFC0H Time-base timer × #16 10

H FFFFBCH

16-bit reload timer 0 #17 11H FFFFB8H 8/10-bit A/D converter #18 12

H FFFFB4H

16-bit free-run timer overflow #19 13H FFFFB0H External interrupt (INT2/INT3) #20 14

H FFFFACH

Reserved × #21 15H FFFFA8H PPG timer ch0, ch1 underflow × #22 16

H FFFFA4H

ICR00 0000B0H (*1)

ICR01 0000B1H

ICR02 0000B2H (*1)

ICR03 0000B3H (*1)

ICR04 0000B4H (*1)

ICR05 0000B5H (*2)

Priority

Input capture 0 load #23 17H FFFFA0H External interrupt (INT4/INT5) #24 18

H FFFF9CH

Input capture 1 load #25 19H FFFF98H PPG timer ch2, ch3 underflow × #26 1A

H FFFF94H

External interrupt (INT6/INT7) #27 1BH FFFF90H Watch timer #28 1C

H FFFF8CH

Reserved × #29 1DH FFFF88H Input capture 2 load

Input capture 3 load

× #30 1E

H FFFF84H

Reserved × #31 1FH FFFF80H Reserved × #32 20

H FFFF7CH

Reserved × #33 21H FFFF78H Reserved × #34 22

H FFFF74H

Reserved × #35 23H FFFF70H 16-bit reload timer 1 #36 24

H FFFF6CH

UART1 reception complete #37 25H FFFF68H UART1 transmission complete #38 26

H FFFF64H

ICR06 0000B6H (*1)

ICR07 0000B7H (*1)

ICR08 0000B8H (*1)

ICR09 0000B9H (*1)

ICR10 0000BAH (*1)

ICR11 0000BBH (*1)

ICR12 0000BCH (*1)

ICR13 0000BDH (*1)

(Continued)

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