Fujitsu MB86617A User Manual
LSI Specification MB86617A
i
IEEE1394 Serial Bus Controller
for DTV
MB86617A
LSI Specification
Rev. 1.0 August 16, 2001
Rev.1.0 Fujitsu VLSI
LSI Specification MB86617A
ii
Contents
CHAPTER 1 OVERVIEW ............................................................................................................................................................................1
CHAPTER 2 FEATURES ..............................................................................................................................................................................2
CHAPTER 3 CHIP BLOCK.........................................................................................................................................................................3
3.1. BLOCK DIAGRAM..................................................................................................................................................................................4
<NORMAL OPERATION MODE......................................................................................................................................................................4
< A SYNCHRONOUS TRANSMIT FIFO EXTENDED MODE ......................................................................................................................5
< A SYNCHRONOUS RECEIVE FIFO EXTENDED MODE.......................................................................................................................... 6
3.2. FUNCTION OF EACH BLOCK...................................................................................................................................................................7
<PHY LAYER CONTROL CIRCUIT.............................................................................................................................................................7
<LINK LAYER CONTROL CIRCUIT........................................................................................................................................................... 7
< TSP IC INTERFACE.................................................................................................................................................................................... 7
<CP IC INTERFACE......................................................................................................................................................................................7
< D ATA BRIDGE .............................................................................................................................................................................................7
CHAPTER 4 PIN ASSIGNMENT............................................................................................................................................................... 8
IN ASSIGNMENT
4.1. P
4.2.CORRESPONDING TABLE OF MB86617A PIN
4.3. O UTLINE DRAWING OF PACKAGE........................................................................................................................................................11
CHAPTER 5 PIN FUNCTION ................................................................................................................................................................... 12
5.1. IEEE1394 INTERFACE...........................................................................................................................................................................13
5.2. ISOCHRONOUS INTERFACE.................................................................................................................................................................... 14
5.4. MPU INTERFACE .................................................................................................................................................................................... 16
5.5. OTHER PINS ............................................................................................................................................................................................17
5.6. POWER/GND PIN...................................................................................................................................................................................18
.....................................................................................................................................................................................9
.....................................................................................................................................10
CHAPTER 6 INTERNAL REGISTER.................................................................................................................................................... 19
CHAPTER 7 INT ERNAL REGISTER FUNCT ION DESCRIPTION ........................................................................................... 25
7.1. M ODE -CONTROL REGISTER..................................................................................................................................................................27
7.2. FLAG & STATUS REGISTER .................................................................................................................................................................... 29
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LSI Specification MB86617A
iii
7.3. INSTRUCTION FETCH REGISTER
7.4. INTERRUPT-FACTOR INDICATE REGISTER/INTERRUPT-MASK SETTING REGISTER........................................................................ 32
7.5. RECEIVE A CKNOWLEDGE INDICATE REGISTER.................................................................................................................................33
7.6. A-BUFFER DATA PORT RECEIVE /TRANSMIT ...................................................................................................................................... 34
7.7. TSP TRANSMIT INFORMATION SETTING REGISTER [A] ................................................................................................................... 35
7.8. TSP TRANSMIT INFORMATION SETTING REGISTER [B] ................................................................................................................... 37
7.9. TRANSMIT OFFSET SETTING REGISTER [A] ....................................................................................................................................... 39
7.10. TRANSMIT OFFSET SETTING REGISTER [B] ..................................................................................................................................... 40
7.11. TSP RECEIVE INFORMATION SETTING REGISTER........................................................................................................................... 41
7.12. RECEIVE DSS PACKET HEADER INDICATE REGISTER [A]/TRANSMIT DSS PACKET HEADER SETTING REGISTER [A] .......44
7.13. RECE IVE DSS PACKET HEADER INDICATE REGISTER [B]/T RANSMIT DSS PACKET HEADER SETTING REGISTER [B] ........ 45
7.14. TSP STATUS REGISTER....................................................................................................................................................................... 46
...........................................................................................................................................................31
7.15. DATA BRIDGE TRANSMIT INFORMATION SETTING REGISTER 1 [A].............................................................................................48
7.16. DATA BRIDGE TRANSMIT INFORMATION SETTING REGISTER 2 [A].............................................................................................49
7.17. DATA BRIDGE TRANSMIT INFORMATION SETTING REGISTER 3 [B].............................................................................................50
ATA BRIDGE TRANSMIT INFORMATION SETTING REGISTER
7.18. D
ATA BRIDGE RECEIVE INFORMATION SETTING REGISTER
7.19. D
7.20. TRANSMIT PACKET LINK/SPLIT SETTING REGISTER
......................................................................................................................53
4 [B].............................................................................................51
.......................................................................................................... 52
7.21. LATE PACKET DECISION RANGE SETTING REGISTER [A] .............................................................................................................. 55
7.22. LATE PACKET DECISION RANGE SETTING REGISTER [B] .............................................................................................................. 56
7.23. RECEIVE ISOCHRONOUS PACKET HEADER INDICATE REGISTER 1 [A] ........................................................................................ 57
7.24. RECEIVE ISOC HRONOUS PACKET HEADER INDICATE REGISTER 2 [A] ........................................................................................ 58
7.25. RECEIVE ISOCHRONOUS PACKET HEADER INDICATE REGISTER 3 [B]......................................................................................... 59
7.26. RECEIVE ISOCHRONOUS PACKET HEADER INDICATE REGISTER 4 [B]......................................................................................... 60
7.27. FIFO RESET SETTING REGISTER....................................................................................................................................................... 61
7.28. DATA BRIDGE TRANSMIT /RECEIVE STATUS REGISTER [A] ........................................................................................................... 62
7.29. DATA BRIDGE TRANSMIT /RECEIVE STATUS REGISTER [B] ........................................................................................................... 65
7.30. ISOCHRONOUS CHANNEL M ONITOR REGISTER............................................................................................................................... 68
7.31. CYCLE-TIMER -MONITOR INDICATE REGISTER................................................................................................................................. 69
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LSI Specification MB86617A
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7.32. PING TIME MONITOR REGISTER
7.33. PHY/LINK REGISTER/ADDRESS SETTING REGISTER................................................................................................................... 71
7.34. PHY/LINK REGISTER ACCESS PORT ............................................................................................................................................... 72
7.35. REVISION INDICATE REGISTER .......................................................................................................................................................... 73
7.36. TRANSMIT CGMS/TSCH INDICATE REGISTER [A] ....................................................................................................................... 74
7.37. TRANSMIT CGMS/TSCH INDICATE REGISTER [B]........................................................................................................................75
7.38. TRANSMIT CGMS/TSCH INDICATE STATUS REGISTER ................................................................................................................ 76
7.39. TRANSMIT EMI/OE SETTING REGISTER.......................................................................................................................................... 78
CHAPTER 8 PHY /INK REGISTER FUNCTION DESCRIPTION................................................................................................80
8.1. PHY/LINK REGISTER T ABLE..............................................................................................................................................................81
8.2. PHYSICAL REGISTER #00 (READ).........................................................................................................................................................83
8.3. PHYSICAL REGISTER #01 (READ/WRITE) ............................................................................................................................................84
........................................................................................................................................................70
8.4. PHYSICAL REGISTER #02 (READ).........................................................................................................................................................85
8.5. PHYSICAL REGISTER #03 (READ).........................................................................................................................................................86
8.6. PHYSICAL REGISTER #04 (READ/WRITE) ............................................................................................................................................87
HYSICAL REGISTER
8.7. P
HYSICAL REGISTER
8.8. P
8.9. PHYSICAL REGISTER #0A, 0B, 0C (READ/WRITE)
READ/WRITE
#05 (
#07, 08, 09 (
) ............................................................................................................................................88
READ
) ...........................................................................................................................................90
............................................................................................................................91
8.10. PHYSICAL REGISTER #0D, 0E, 0F (READ/WRITE)...........................................................................................................................92
8.11. PHYSICAL REGISTER #10 (READ).......................................................................................................................................................93
8.12. PHYSICAL REGISTER #11, 12, 13 (READ) .........................................................................................................................................94
8.13. PHYSICAL REGISTER #14, 15, 16 (READ).........................................................................................................................................95
8.14. PHYSICAL REGISTER #17, 18, 19, 1A, 1B, 1C, 1D, 1E (READ/WRITE) ....................................................................................... 96
8.15. LINK REGISTER #00 (READ/WRITE)...................................................................................................................................................97
8.16. LINK REGISTER #01 (READ/WRITE)...................................................................................................................................................98
8.17. LINK REGISTER #02 (READ/WRITE)...................................................................................................................................................99
8.18. LINK REGISTER #03 (READ/WRITE).................................................................................................................................................100
CHAPTER 9 INSTRUCTIO N ................................................................................................................................................................ 101
9.1. INSTRUCTION C ODE TABLE..............................................................................................................................................................102
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LSI Specification MB86617A
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9.2. DESCRIPTION OF E ACH INSTRUCTION
............................................................................................................................................... 103
CHAPTER 10 INTERRUPT
.....................................................................................................................................................................106
10.1. I NTERRUPT-FACTOR INDICATOR REGISTER & INTERRUPT-MASK SETTING REGISTER.............................................................107
10.2. I NTERRUPT.......................................................................................................................................................................................... 108
10.3. DESCRIPTION OF INTERRUPT............................................................................................................................................................109
CHAPTER 11 OPERATION ...................................................................................................................................................................112
11.1. INITIALIZATION................................................................................................................................................................................ 113
11.2. SELF-ID PACKET RECEIVING .........................................................................................................................................................114
11.2.1 Self-ID Packet Receive at Bus Reset Process .............................................................................................................115
11.2.2 Self-ID Packet Receive after Transmitting Ping Packet Ping................................................................................ 118
11.3. ASYNCHRONOUS PACKET TRANSMITTING.................................................................................................................................120
11.4. ASYNCHRONOUS PACKET RECEIVING .........................................................................................................................................122
11.5. ISOCHRONOUS PACKET TRANSMITTING ..................................................................................................................................... 125
11.6. ISOCHRONOUS PACKET RECEIVING .............................................................................................................................................128
CHAPTER 12 SYSTEM CO NFIGURATION ...................................................................................................................................130
12.1. RECOMMENDED CONNECTION FOR 1934 PORT (FOR ONE PORT).......................................................................................... 131
12.2. RECOMMENDED CONNECTION FOR CABLE POWER SUPPLY ..................................................................................................132
12.3. RECOMMENDED CONNECTION FOR BUILD-IN PLL LOOP F ILTER.........................................................................................133
ONFIGURATION OF FEEDBACK CIRCUIT AT CRYSTAL OSCILLATOR
12.4. C
...................................................................................134
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
1
Chapter 1 Overview
This chapter explains the overview of MB86617A.
MB86617A is Fujitsu’s IEEE1394 serial bus controller based on both IEEE1394 Standard (IEEE Std. 1394-1995) and P1394.a
Standard Draft (rev.2.0).
This MB86617A has three ports for network under the 1394 cable environment, differential transceiver, and comparator, and the
transfer data rate supports S400.
MB86617A integrates PHY and LINK layers into single-chip, and plans for degression of component side product and saving power
consumption.
MB86617A has two exclusive ports (one is the combined use for receiving a message of interface for DV) for MPEG2 and DSS data
transfer, and performs isolating and packeting of Header and Data department with these two ports automatically. This function is
suited for maintaining continuum of transfer.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
2
Chapter 2 Features
This chapter explains the features of MB86617A.
> Compliant with IEEE1394 high performance serial bus standard and P1394.a standard draft
> Integrates PHY and LINK layers into single-chip
> 1394 port number : 3 ports
> Transfer Data Rate : S100, S200, S400
> On-chip PLL (corresponding to Crystal Oscillator) : generate internal clock
> 4K Byte X 2 channels Isochronous transmit and receive data buffer
> 256Byte Asynchronous exclusive buffer for transmit/receive
> Auto isolating and packeting for received header and data of packet
> Two exclusive ports for Isochronous transfer (8 bit bus)
> Loading interface with copy protection LSI (8 bits I/O)
> Generating and Checking Function for 32bit CRC
> 6-pin cable supported
> Power supply system : 3.3V size -D battery
> Package : LQFP-176 (FPT-176P-M03)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
3
Chapter 3 Chip Block
This chapter explains the MB86617A block diagram and the function of each block.
3.1. Block Diagram
3.2. Function of Each Block
Rev.1.0 Fujitsu VLSI
MB86617A
4
PHY/
CP IC
Interface
Asynch Transmit
Asynch Transmit
Asynch Transmit
LSI Specification
3.1. Block Diagram
MB86617A block diagram is shown below.
<< Normal Operation Mode
Host Interface
FIFO
(2KByte)
TSP IC Interface
FIFO
(2KByte)
Asynch Transmit
Exclusive FIFO
(256 byte)
Packet Process
Packet Process
Exclusive FIFO
(256 byte)
LINK
FIFO
(2KByte)
Layer
Control
Circuit
Data Bridge
FIFO
(2KByte)
Fig.3.1.1 Block Diagram - Normal Operation Mode -
1394 Interface (Port 0)
TPA0
XTPA0
TPB0
XTPB0
TPBIAS0
1394 Interface (Port 1)
TPA1
XTPA1
TPB1
XTPB1
TPBIAS1
1394 Interface (Port 2)
TPA2
XTPA2
TPB2
XTPB2
TPBIAS2
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
5
PHY/
CP IC
Interface
Asynch Transmit
Asynch Transmit
Asynch Transmit
Asynch Transmit
<< Asynchronous Transmit FIFO Extended Mode
Host Interface
FIFO
(2KByte)
TSP IC Interface
FIFO
(2KByte)
Exclusive FIFO
(256 byte)
Packet Process
Packet Process
Exclusive FIFO
(256 byte)
FIFO
(2KByte)
FIFO
(2KByte)
Fig.3.1.2 Block Diagram - Asynchronous Transmit FIFO Extended Mode -
1394 Interface (Port 0)
TPA0
XTPA0
TPB0
XTPB0
TPBIAS0
1394 Interface (Port 1)
TPA1
XTPA1
LINK
Layer
Control
Circuit
TPB1
XTPB1
TPBIAS1
Data Bridge
1394 Interface (Port 2)
TPA2
XTPA2
TPB2
XTPB2
TPBIAS2
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
6
PHY/
CP IC
Interface
Asynch Transmit
Asynch Transmit
Asynch Transmit
Asynch Transmit
<< Asynchronous Receive FIFO Extended Mode
Host Interface
FIFO
(2KByte)
TSP IC Interface
FIFO
(2KByte)
Exclusive FIFO
(256 byte)
Packet Process
Packet Process
Exclus ive FIFO
(256 byte)
(2KByte)
(2KByte)
Fig.3.1.3 Block Diagram - Asynchronous Receive FIFO Extended Mode -
FIFO
Data Bridge
FIFO
LINK
Layer
Control
Circuit
1394 Interface (Port 0)
TPA0
XTPA0
TPB0
XTPB0
TPBIAS0
1394 Interface (Port 1)
TPA1
XTPA1
TPB1
XTPB1
TPBIAS1
1394 Interface (Port 2)
TPA2
XTPA2
TPB2
XTPB2
TPBIAS2
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
7
3.2. Function of Each Block
This section explains the function of each block for MB86617A.
<< PHY Layer Control Circuit
This circuit is for the Physical layer of IEEE 1394 with the following functions .
> Asynchronous transfer is supported under cable environment.
> Maximum transfer data rate : 393.216Mbit/sec.
> with three ports for transceiver/receiver : transfer IEEE1394 packet
> with bus monitor, initial performance for occurring bus reset, speed signaling, arbitration, encode/decode : transfer/receive data
<< LINK Layer Control Circuit
This circuit generates standard packet for IEEE1394, controls transfer, and performs the following functions.
> Generates and checks 32 bit CRC for header and data of packet.
> Activates cycle master function with integrated 32 bit cycle timer register
<< TSP IC Interface
This TSP IC Interface has two exclusive ports with the following functions for transmitting/receiving TSP IC, MPEG2-TS and DSS
data, and receiving DV data.
> Adds time stamp to both MPEG2-TS and DSS data.
> Outputs received data just when the value of time stamp (SPH) and cycle timer is matched with each other.
> Integrated transmit/receive (dual purpose) FIFO for transferring Isochronous by 2K byte X 2 channels.
<< CP IC Interface
This interface adds the copy information to CP IC so as to correspond to copy protect.
<< Data Bridge
This Data Bridge packets MPEG2-TS, DSS, and DVC, and re-builds the receiving data.
At data transmission, this section adds Isochronous packet header and CIP header, and connects/separates source packet
When transmitting 2ch, it connects Isochronous packet.
At data receipt, it deletes Isochronous packet header and CIP header, restores by unit of source packet.
When receiving 2ch, it separates Isochronous packet and divide them to each FIFO.
> Integrated transmit/receive (dual purpose) FIFO for transferring Isochronous by 2K byte X 2 channels.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
8
Chapter 4 Pin Assignment
This chapter explains the pin assignment and table of pin function of MB86617A.
4.1. Pin Assignment
4.2. Corresponding Table of MB86617A Pin
4.3. Outline Drawing of Package
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
9
88
SELIOA
XRESET
SELTSPA
1
132
133
4.1. Pin Assignment
The following diagram shows the MB86617A pin assignment.
MODE1
MODE0
XCS
XWR(XDS)
XRD(R/XW)
ALE
XINT
DREQ
XDACK
VDD
VSS
D15
D14
D13
D12
D11
D10
D9
D8
VDD
VSS
AD7
AD6
AD5
AD4
AD3
AD2
AD1
D0
TEST1
TEST2
VSS
VDD
XO
AVSS
AVDD
FIL
RF
AVSS
AVDD
RO
CPS
TSDB7
TSDB6
TSDB5
TSCGMSB
TSVALB
140
DSSCLKB
TEST3
VSS
VDD
155
SELTSPB
SELIOB
TSDB0
IERRB
150
TSDB3
TSDB2
TSDB1
VDD
VSS
TSDB4
145
XILWRE
ICLK
XIV
160
TEST4
XFP
MB86617
TEST5
A4
170
A5
A6
TEST6
A7
165
VSS
VDD
TEST7
VDD
VSS
176
5
10
15
20
175
A1
A2
A3
FPT-176P-M03
25
30
XI
35
40
44
45
50
55
60
65
70
75
80
TSSYNCB
TSCLKB
VDD
VSS
135
85
DSSCLKA
130
125
120
115
110
105
100
95
90
89
IERRA
TSDA0
TSDA1
TSDA2
TSDA3
VSS
VDD
TSDA4
TSDA5
TSDA6
TSDA7
TSVALA
TSCGMSA
TSSYNCA
TSCLKA
VSS
VDD
VSS
VDD
VSS
VDD
VSS
AVDD
AVSS
TPB2
XTPB2
TPBIAS2
TPA2
XTPA2
AVSS
AVDD
AVDD
AVSS
TPB1
XTPB1
TPBIAS1
TPA1
XTPA1
AVSS
AVDD
AVDD
AVSS
TPB0
XTPB0
TPBIAS0
TPA0
XTPA0
AVSS
AVDD
VSS
VDD
PWR2
PWR1
LINKON
PWR3
PMODE
VDD
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
10
4.2. Corresponding Table of MB86617A Pin
The following table shows the corresponding items of MB86617A pin.
Pin
No.
1 I XRESET 45 - AVSS 89 133 O SELTSPA
2 I MODE1 46 - AVDD 90 134 I DSSCLKA
3 I MODE0 47 I/O XTPB2 91 135 - VDD
4 I XCS 48 I/O TPB2 92 136 - VSS
5 I XWR(XDS) 49 I/O XTPA2 93 137 I/O TSCLKB
6 I XRD(R/XW) 50 I/O TPA2 94 138 I TSSYNCB
7 I ALE 51 O TPBIAS2 95 139 I TSCGMSB
8 O XINT 52 - AVDD 96 - VDD 140 I/O TSVALB
9 O DREQ 53 - AVSS 97 - VSS 141 I/O TSDB7
10 I XDACK 54 - AVSS 98 142 I/O TSDB6
11 - VDD 55 - AVDD 99 143 I/O TSDB5
12 - VSS 56 I/O XTPB1 100 144 I/O TSDB4
13 I/O D15 57 I/O T PB1 101 145 - VDD
14 I/O D14 58 I/O XTPA1 102 146 - VSS
15 I/O D13 59 I/O TPA1 103 147 I/O TSDB3
16 I/O D12 60 O TPBIAS1 104 148 I/O TSDB2
17 I/O D11 61 - AVDD 105 - VDD 149 I/O TSDB1
18 I/O D10 62 - AVSS 106 - VSS 150 I/O TSDB0
19 I/O D9 63 - AVSS 107 151 O IERRB
20 I/O D8 64 - AVDD 108 152 O SELIOB
21 - VDD 65 I/O XTPB0 109 153 O SELTSPB
22 - VSS 66 I/O TPB0 110 154 I DSSCLKB
23 I/O AD7 67 I/O XTPA0 111 155 - VDD
24 I/O AD6 68 I/O TPA0 112 156 - VSS
25 I/O AD5 69 O TPBIAS0 113 157 I/O TEST3
26 I/O AD4 70 - AVDD 114 158 I/O TEST4
27 I/O AD3 71 - AVSS 115 - VDD 159 O XFP
28 I/O AD2 72 - VSS 116 - VSS 160 O XILWRE
29 I/O AD1 73 - VDD 117 I/O TSCLKA 161 I XIV
30 I/O D0 74 I PWR1 118 I/O TSSYNCA 162 I ICLK
31 I/O TEST1 75 I PWR2 119 I/O TSCGMSA 163 - VDD
32 I/O TEST2 76 I PWR3 120 I/O TSVALA 164 - VSS
33 - VSS 77 O LINKON 121 I/O TSDA7 165 I/O TEST5
34 I XI 78 I PMODE 122 I/O TSDA6 166 I/O TEST6
35 - VDD 79 123 I/O TSDA5 167 I A7
36 I/O XO 80 124 I/O TSDA4 168 I A6
37 - AVSS 81 125 - VDD 169 I A5
38 - AVDD 82 126 - VSS 170 I A4
39 O FIL 83 127 I/O TSDA3 171 I A3
40 O RF 84 128 I/O TSDA2 172 I A2
41 - AVSS 85 - VDD 129 I/O TSDA1 173 I A1
42 - AVDD 86 - VSS 130 I/O TSDA0 174 I/O TEST7
43 O RO 87 131 O IERRA 175 - VDD
44 I CPS 88 132 O SELIOA 176 - VSS
I/O Pin Name
Pin
No.
I/O Pin Name
Pin
No.
I/O Pin Name
Pin
No.
I/O Pin Name
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
11
4.3. Outline Drawing of Package
This section shows the outline drawing of MB86617A package (LQFP-176).
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
12
Chapter 5 Pin Function
This chapter explains the MB86617A pin function.
5.1. IEE E1394 Interface
5.2. Isochronous (TSP-IC,DV-IC) Interface
5.4. MPU Interface
5.5. Other Pins
5.6. Power/GND Pin
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
13
5.1. IEEE1394 Interface
This section explains the pin function of IEEE1394 interface.
Signal Name I/O Function
TPA0 I/O I/O pin of TPA + (plus) signal on cable port 0
XTPA0 I/O I/O pin of TPA - (minus) signal on cable port 0
TPB0 I/O I/O pin of TPB + (plus) signal on cable port 0
XTPB0 I/O I/O pin of TPB - (minus) signal on cable port 0
TPA1 I/O I/O pin of TPA + (plus) signal on cable port 1
XTPA1 I/O I/O pin of TPA - (minus) signal on cable port 1
TPB1 I/O I/O pin of TPB + (plus) signal on cable port 1
XTPB1 I/O I/O pin of TPB - (minus) signal on cable port 1
TPA2 I/O I/O pin of TPA + (plus) signal on cable port 2
XTPA2 I/O I/O pin of TPA - (minus) signal on cable port 2
TPB2 I/O I/O pin of TPB + (plus) signal on cable port 2
XTPB2 I/O I/O pin of TPB - (minus) signal on cable port 2
TPBIAS0 O Output pin of reference voltage for common voltage on cable port 0
TPBIAS1 O Output pi n of reference voltage for common voltage on cable port 1
TPBIAS2 O Output pin of reference voltage for common voltage on cable port 2
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
14
active.
5.2. Isochronous Interface
This section explains the pin function of Isochronous interface.
Signal Name I/O Function
TSVALIDA I/O
TSSYNCA I/O
TSCLKA I/O
TSDA7 - 0 I/O I/O pin for TS packet data (on Port A)
TSCGMSA I
SELIOA O
SELTSPA O Output pin for switching output device from port A
TSVALIDB I/O
TSSYNCB I/O
TSCLKB I/O
I.O pin for indicating effective data period of TS packet (on port A)
‘H’ active signal
Input/Output pin for indicating leading data of TS packet (on port A)
‘H’ active signal
On transmitting: sync clock input pin for input data of TS packet
On receiving : sync clock output pin for output data of TS packet
(switchable either 6.144MHz or 3.072MHz)
Serial input pin for CGMS and TSCH information (on port A)
Effective for 8 clocks since TSSYNCA input signal rising
Output pin for switching I/O on port A
Outputs ‘L’ at transmitting and ‘H’at receiving
I.O pin for indicating effective data period of TS packet (on port B)
‘H’ active signal
Input/Output pin for indicating leading data of TS packet (on port B)
‘H’ active signal
On transmitting: sync clock input pin for input data of TS packet
On receiving : sync clock output pin for output data of TS packet
(switchable either 6.144MHz or 3.072MHz)
TSDB7 - 0 I/O I/O pin for TS packet data (on port B)
TSCGMSB I
SELIOB O
SELTSPB O Output pin for switching output device from port B
ICLK I Clock input pin from DV-IC
XILWRE O
XIV I
XFP O
Serial input pin for CGMS and TSCH information (on port B)
Effective for 8 clocks si nce TSSYNCA input signal rising
Output pin for switching I/O on port B
Outputs ‘L’ at transmitting and ‘H’at receiving
Output pin for signal to be allowed accessing to Isochronous-FIFO
Asserted by completing reception of data for one source packet
‘L’ active signal
Input signal for enable signal of Isochronous data
Output Isochronous- FIFO data to data output pin while this signal in
Switch data synchronizing with rise edge of ICLK
Output pin of time stamp trigger signal
‘L’ active signal
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
15
IERRA O
IERRB O
Output pin for noticing error of receive data (on port A)
‘H’ active signal
Output pin for noticing error of receive data (on port B)
‘H’ active signal
DSSCLKA I
DSSCLKB I
Clock input pin for DSS data (27MHz)
Clock input pin for DSS data (27MHz)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
16
5.4. MPU Interface
This section explains the pin function of MPU interface.
Signal Name I/O Function
A7 – 1 I
D15 - 8,0
AD7 – 1
XCS I Chip enable input pin for this device
XRD(R/W) I
XWR(XDS) I
ALE I
DREQ O Output pin of DMA transfer requiring signal for DMAC
XDACK I Input pin of DMA allowance signal from DMAC
XINT O Output pin for interruption request
I/O
Address input pin for selecting internal register
Available only when selecting non-multi mode
When selecting multiplex mode, set this signal in fixed ‘L’
Data I/O pin
Corresponding to address input signal when selecting multiplex mode
80 system mode: read out strobe input pin for this device
68 system mode: input pin for controlling read out/write for this device
80 system mode: strobe input pin for writing into this device
68 system mode: input pin of XDS signal to be output with data bus in available
Input pin of ALE signal to be output with its address in available when selecting
multiplex mode
When selecting non -multiplex mode, set this signal in fixed ‘L’
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
17
5.5. Other Pins
This section explains the pin function like internal PLL.
Signal Name I/O Function
XRESET I
MODE1
I
MODE0
XO I/O
XI I
RF O
FIL O Exterior type filter circuit connecting pin for internal PLL
RO O Connect to GND through 5.1kΩ register.
CPS I
PMODE I
Input signal for resetting signal
When operating with cable supply power, set this pin to ‘L’.
This pin is used for setting operating mode of MPU.
This device is operated as follows depending on the setting of MODE1 and MODE0
pins;
‘00’ input: TX1940 mode
‘01’ input: MB90F574 mode
‘10’ input: 80 system non-multiplex mode
‘11’ input: 68 system non-multiplex mode
Exterior type crystal connecting pin for oscillator circuit (24.576MHz)
Connect to GND through 5.1kΩ register.
Power supply input pin from IEEE1394 cable
Detect cable supply power 0 to 33V (requiring of lowering/div iding voltage)
Criterion pin for inputting power
‘L’ input : operate with power supplying through IEEE1394 cable
‘H’ input: operate with system power
Setting pin got POWER_CLASS of Self-ID packet to be transmitted when operating
PWR3 - 1 I
LINKON O
TEST1 - 7 I/O This pin is for test. Use this pin as open one.
with supply power through cable.
Note) The POWER_CLASS of the Self_ID packet to be sent when operating
under the system power does not use this pin, but follows the setting of
Pwr bit (Bit2 to 0) of Physical Register#4.
Output pin for detecting Link-on packet receive
Output ‘H’ when receiving Link-on packet under operating with supply power
through IEEE1394 cable. When PMODE becomes ‘H’, ‘L’ is output. With the
PMODE in ‘H’, the output of this pin is not changed.
If not using this pin, set this pin as open one.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
18
5.6. Power/GND Pin
This section explains the power/GND pin.
Signal Name I/O Function
VDD - 3.3V digital power pin
VSS - Digital ground pin
AVDD - 3.3V analog power pin
AVSS - Analog ground pin
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
19
Chapter 6 Internal Register
This chapter explains the MB86617A internal register.
Note that the access of internal register is applied only 16 bits access.
Address
(HEX)
00 mode-control mode-control
02 (reserved) flag & status
04 Instruction-fetch Instruction-fetch
06 Interrupt-mask setting [A] Interrupt indicate [A]
08 Interrupt-mask setting [B] Interrupt indicate [B]
0A (reserved) Receive Acknowledge
WRITE READ
Register Name Register Name
0C A-buffer data port transmit A-buffer data port receive
0E (reserved) (reserved)
10 TSP transmit information setting [A] TSP transmit information setting [A]
12 TSP transmit information setting [B] TSP transmit information setting [B]
14 transmit offset setting [A] (upper) transmit offset setting [A] (upper)
16 transmit offset setting [A] (lower) transmit offset setting [A] (lower)
18 transmit offset setting [B] (upper) transmit offset setting [B] (upper)
1A transmit offset setting [B] (lower) transmit offset setting [B] (lower)
1C TSP receive information setting TSP receive information setting
1E
transmit DSS packet header setting [A]
(most significant)
receive DSS packet header setting [A]
(most significant)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
20
Address
(HEX)
20 transmit DSS packet header setting [A] (upper) receive DSS packet header setting [A] (upper)
22 transmit DSS packet header setting [A] (medium) receive DSS packet header setting [A] (medium)
24 transmit DSS packet header setting [A] (lower) receive DSS packet header setting [A] (lower)
26
28
2A transmit DSS packet header setting [B] (upper) receive DSS packet header setting [B] (upper)
2C transmit DSS packet header setting [B] (medium) receive DSS packet header setting [B] (medium)
2E transmit DSS packet header setting [B] (lower) receive DSS packet header setting [B] (lower)
30
32 (reserved) TSP status
34 data bridge transmit information setting 1 [A] data bridge transmit information setting 1 [A]
transmit DSS packet header setting [A]
transmit DSS packet header setting [B]
transmit DSS packet header setting [B]
WRITE READ
Register Name Register Name
receive DSS packet header setting [A]
(least significant)
receive DSS packet header setting [B]
(most significant)
receive DSS packet header setting [B]
(least significant)
(least significant)
(most significant)
(least significant)
36 data bridge transmit information setting 2 [A] data bridge transmit information setting 2 [A]
38 data bridge transmit information setting 3 [B] data bridge transmit information setting 3 [B]
3A data bridge transmit information setting 4 [B] data bridge transmit information setting 4 [B]
3C data bridge receive information setting data bridge receive information setting
3E transmit packet concatenate/split setting transmit packet concatenate/split setting
40 Late packet criterion range setting [A] Late packet criterion range setting [A]
42 Late packet criterion range setting [B] Late packet criterion range setting [B]
44 (reserved) receive Isochronous packet header indicate 1 [A]
46 (reserved) receive Isochronous packet header indicate 2 [A]
48 (reserved) receive Isochronous packet header indicate 3 [B]
4A (reserved) receive Isochronous packet header indicate 4 [B]
4C FIFO reset FIFO reset
4E (reserved) data bridge transmit/receive status [A]
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
21
Address
(HEX)
50 (reserved) data bridge transmit/receive status [B]
52 (reserved) Isochronous channel monitor 1
54 (reserved) Isochronous channel monitor 2
56 (reserved) Isochronous channel monitor 3
58 (reserved) Isochronous channel monitor 4
5A (reserved) cycle-time-monitor (upper)
5C (reserved) cycle-time-monitor (lower)
5E (reserved) Ping time monitor
60 PHY/LINK register address setting PHY/LINK register address setting
62 PHY/LINK register access port PHY/LINK register access port
64 (reserved) Revision indicate register (upper)
WRITE READ
Register Name Register Name
66 (reserved) Revision indicate register (lower)
68 (reserved) (reserved)
6A (reserved) (reserved)
6C (reserved) (reserved)
6E (reserved) (reserved)
70 (reserved) (reserved)
72 (reserved) (reserved)
74 (reserved) (reserved)
76 (reserved) (reserved)
78 (reserved) (reserved)
7A (reserved) (reserved)
7C (reserved) (reserved)
7E (reserved) (reserved)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
22
Address
(HEX)
80 (reserved) transmit CGMS/TSCH indicate [A]
82 (reserved) transmit CGMS/TSCH indicate [B]
84 transmit CGMS/TSCH indicate status transmit CGMS/TSCH indicate status
86 transmit EMI/OE setting transmit EMI/OE setting
88 (reserved) (reserved)
8A (reserved) (reserved)
8C (reserved) (reserved)
8E (reserved) (reserved)
90 (reserved) (reserved)
92 (reserved) (reserved)
94 (reserved) (reserved)
WRITE READ
Register Name Register Name
96 (reserved) (reserved)
98 (reserved) (reserved)
9A (reserved) (reserved)
9C (reserved) (reserved)
9E (reserved) (reserved)
A0 (reserved) (reserved)
A2 (reserved) (reserved)
A4 (reserved) (reserved)
A6 (reserved) (reserved)
A8 (reserved) (reserved)
AA (reserved) (reserved)
AC (reserved) (reserved)
AE (reserved) (reserved)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
23
Address
(HEX)
B 0 (reserved) (reserved)
B 2 (reserved) (reserved)
B 4 (reserved) (reserved)
B 6 (reserved) (reserved)
B 8 (reserved) (reserved)
BA (reserved) (reserved)
BC (reserved) (reserved)
BE (reserved) (reserved)
C 0 (reserved) (reserved)
C 2 (reserved) (reserved)
C 4 (reserved) (reserved)
WRITE READ
Register Name Register Name
C 6 (reserved) (reserved)
C 8 (reserved) (reserved)
CA (reserved) (reserved)
CC (reserved) (reserved)
CE (reserved) (reserved)
D0 (reserved) (reserved)
D2 (reserved) (reserved)
D4 (reserved) (reserved)
D6 (reserved) (reserved)
D8 (reserved) (reserved)
DA (reserved) (reserved)
DC (reserved) (reserved)
DE (reserved) (reserved)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
24
Address
(HEX)
E0 (reserved) (reserved)
E2 (reserved) (reserved)
E4 (reserved) (reserved)
E6 (reserved) (reserved)
E8 (reserved) (reserved)
EA (reserved) (reserved)
EC (reserved) (reserved)
EE (reserved) (reserved)
F0 (reserved) (reserved)
F2 (reserved) (reserved)
F4 (reserved) (reserved)
WRITE READ
Register Name Register Name
F6 (reserved) (reserved)
F8 (reserved) (reserved)
F A (reserved) (reserved)
FC (reserved) (reserved)
FE (reserved) (reserved)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
25
Chapter 7 Internal Register Function Description
This chapter explains the details of the internal register of MB86617A.
7.1. mode-control Register
7.2. flag & status Register
7.3. instruction fetch Register
7.4. interrupt-factor Indicate Register/interrupt-mask Setting Register
7.5. Receive Acknowledge Indicate Register
7.6. A-buffer Data Port Receive/Transmit
7.7. TSP Transmit Information Set ting Register [A]
7.8. TSP Transmit Information Setting Register [B]
7.9. Transmit Offset Setting Register [A]
7.10. Transmit Offset Setting Register [B]
7.11. TSP Receive Information Setting Register
7.12. Transmit DSS Packet Header Setting Register [A]
7.13. Transmit DSS Packet Header Setting Register [B]
7.14. TSP Status Register
7.15. Data Bridge Transmit Information Setting Register 1 [A]
7.16. Data Bridge Transmit Information Setting Register 2 [A]
7.17. Data Bridge Transmit Information Sett ing Register 3 [B]
7.18. Data Bridge Transmit Information Setting Register 4 [B]
7.19. Data Bridge Receive Information Setting Register
7.20. Transmit Packet Link/Split Setting Register
7.21. Late Packet Decision Range Setting Register [A]
7.22. Late Packet Decision Range Setting Register [B]
7.23. Receive Isochronous Packet Header Indicate Register 1 [A]
7.24. Receive Isochronous Packet Header Indicate Register 2 [A]
Rev.1.0 Fujitsu VLSI
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