LSI Specification MB86617A
i
IEEE1394 Serial Bus Controller
for DTV
MB86617A
LSI Specification
Rev. 1.0 August 16, 2001
Rev.1.0 Fujitsu VLSI
LSI Specification MB86617A
ii
Contents
CHAPTER 1 OVERVIEW ............................................................................................................................................................................1
CHAPTER 2 FEATURES ..............................................................................................................................................................................2
CHAPTER 3 CHIP BLOCK.........................................................................................................................................................................3
3.1. BLOCK DIAGRAM..................................................................................................................................................................................4
<NORMAL OPERATION MODE......................................................................................................................................................................4
< A SYNCHRONOUS TRANSMIT FIFO EXTENDED MODE ......................................................................................................................5
< A SYNCHRONOUS RECEIVE FIFO EXTENDED MODE.......................................................................................................................... 6
3.2. FUNCTION OF EACH BLOCK...................................................................................................................................................................7
<PHY LAYER CONTROL CIRCUIT.............................................................................................................................................................7
<LINK LAYER CONTROL CIRCUIT........................................................................................................................................................... 7
< TSP IC INTERFACE.................................................................................................................................................................................... 7
<CP IC INTERFACE......................................................................................................................................................................................7
< D ATA BRIDGE .............................................................................................................................................................................................7
CHAPTER 4 PIN ASSIGNMENT............................................................................................................................................................... 8
IN ASSIGNMENT
4.1. P
4.2.CORRESPONDING TABLE OF MB86617A PIN
4.3. O UTLINE DRAWING OF PACKAGE........................................................................................................................................................11
CHAPTER 5 PIN FUNCTION ................................................................................................................................................................... 12
5.1. IEEE1394 INTERFACE...........................................................................................................................................................................13
5.2. ISOCHRONOUS INTERFACE.................................................................................................................................................................... 14
5.4. MPU INTERFACE .................................................................................................................................................................................... 16
5.5. OTHER PINS ............................................................................................................................................................................................17
5.6. POWER/GND PIN...................................................................................................................................................................................18
.....................................................................................................................................................................................9
.....................................................................................................................................10
CHAPTER 6 INTERNAL REGISTER.................................................................................................................................................... 19
CHAPTER 7 INT ERNAL REGISTER FUNCT ION DESCRIPTION ........................................................................................... 25
7.1. M ODE -CONTROL REGISTER..................................................................................................................................................................27
7.2. FLAG & STATUS REGISTER .................................................................................................................................................................... 29
Rev.1.0 Fujitsu VLSI
LSI Specification MB86617A
iii
7.3. INSTRUCTION FETCH REGISTER
7.4. INTERRUPT-FACTOR INDICATE REGISTER/INTERRUPT-MASK SETTING REGISTER........................................................................ 32
7.5. RECEIVE A CKNOWLEDGE INDICATE REGISTER.................................................................................................................................33
7.6. A-BUFFER DATA PORT RECEIVE /TRANSMIT ...................................................................................................................................... 34
7.7. TSP TRANSMIT INFORMATION SETTING REGISTER [A] ................................................................................................................... 35
7.8. TSP TRANSMIT INFORMATION SETTING REGISTER [B] ................................................................................................................... 37
7.9. TRANSMIT OFFSET SETTING REGISTER [A] ....................................................................................................................................... 39
7.10. TRANSMIT OFFSET SETTING REGISTER [B] ..................................................................................................................................... 40
7.11. TSP RECEIVE INFORMATION SETTING REGISTER........................................................................................................................... 41
7.12. RECEIVE DSS PACKET HEADER INDICATE REGISTER [A]/TRANSMIT DSS PACKET HEADER SETTING REGISTER [A] .......44
7.13. RECE IVE DSS PACKET HEADER INDICATE REGISTER [B]/T RANSMIT DSS PACKET HEADER SETTING REGISTER [B] ........ 45
7.14. TSP STATUS REGISTER....................................................................................................................................................................... 46
...........................................................................................................................................................31
7.15. DATA BRIDGE TRANSMIT INFORMATION SETTING REGISTER 1 [A].............................................................................................48
7.16. DATA BRIDGE TRANSMIT INFORMATION SETTING REGISTER 2 [A].............................................................................................49
7.17. DATA BRIDGE TRANSMIT INFORMATION SETTING REGISTER 3 [B].............................................................................................50
ATA BRIDGE TRANSMIT INFORMATION SETTING REGISTER
7.18. D
ATA BRIDGE RECEIVE INFORMATION SETTING REGISTER
7.19. D
7.20. TRANSMIT PACKET LINK/SPLIT SETTING REGISTER
......................................................................................................................53
4 [B].............................................................................................51
.......................................................................................................... 52
7.21. LATE PACKET DECISION RANGE SETTING REGISTER [A] .............................................................................................................. 55
7.22. LATE PACKET DECISION RANGE SETTING REGISTER [B] .............................................................................................................. 56
7.23. RECEIVE ISOCHRONOUS PACKET HEADER INDICATE REGISTER 1 [A] ........................................................................................ 57
7.24. RECEIVE ISOC HRONOUS PACKET HEADER INDICATE REGISTER 2 [A] ........................................................................................ 58
7.25. RECEIVE ISOCHRONOUS PACKET HEADER INDICATE REGISTER 3 [B]......................................................................................... 59
7.26. RECEIVE ISOCHRONOUS PACKET HEADER INDICATE REGISTER 4 [B]......................................................................................... 60
7.27. FIFO RESET SETTING REGISTER....................................................................................................................................................... 61
7.28. DATA BRIDGE TRANSMIT /RECEIVE STATUS REGISTER [A] ........................................................................................................... 62
7.29. DATA BRIDGE TRANSMIT /RECEIVE STATUS REGISTER [B] ........................................................................................................... 65
7.30. ISOCHRONOUS CHANNEL M ONITOR REGISTER............................................................................................................................... 68
7.31. CYCLE-TIMER -MONITOR INDICATE REGISTER................................................................................................................................. 69
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LSI Specification MB86617A
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7.32. PING TIME MONITOR REGISTER
7.33. PHY/LINK REGISTER/ADDRESS SETTING REGISTER................................................................................................................... 71
7.34. PHY/LINK REGISTER ACCESS PORT ............................................................................................................................................... 72
7.35. REVISION INDICATE REGISTER .......................................................................................................................................................... 73
7.36. TRANSMIT CGMS/TSCH INDICATE REGISTER [A] ....................................................................................................................... 74
7.37. TRANSMIT CGMS/TSCH INDICATE REGISTER [B]........................................................................................................................75
7.38. TRANSMIT CGMS/TSCH INDICATE STATUS REGISTER ................................................................................................................ 76
7.39. TRANSMIT EMI/OE SETTING REGISTER.......................................................................................................................................... 78
CHAPTER 8 PHY /INK REGISTER FUNCTION DESCRIPTION................................................................................................80
8.1. PHY/LINK REGISTER T ABLE..............................................................................................................................................................81
8.2. PHYSICAL REGISTER #00 (READ).........................................................................................................................................................83
8.3. PHYSICAL REGISTER #01 (READ/WRITE) ............................................................................................................................................84
........................................................................................................................................................70
8.4. PHYSICAL REGISTER #02 (READ).........................................................................................................................................................85
8.5. PHYSICAL REGISTER #03 (READ).........................................................................................................................................................86
8.6. PHYSICAL REGISTER #04 (READ/WRITE) ............................................................................................................................................87
HYSICAL REGISTER
8.7. P
HYSICAL REGISTER
8.8. P
8.9. PHYSICAL REGISTER #0A, 0B, 0C (READ/WRITE)
READ/WRITE
#05 (
#07, 08, 09 (
) ............................................................................................................................................88
READ
) ...........................................................................................................................................90
............................................................................................................................91
8.10. PHYSICAL REGISTER #0D, 0E, 0F (READ/WRITE)...........................................................................................................................92
8.11. PHYSICAL REGISTER #10 (READ).......................................................................................................................................................93
8.12. PHYSICAL REGISTER #11, 12, 13 (READ) .........................................................................................................................................94
8.13. PHYSICAL REGISTER #14, 15, 16 (READ).........................................................................................................................................95
8.14. PHYSICAL REGISTER #17, 18, 19, 1A, 1B, 1C, 1D, 1E (READ/WRITE) ....................................................................................... 96
8.15. LINK REGISTER #00 (READ/WRITE)...................................................................................................................................................97
8.16. LINK REGISTER #01 (READ/WRITE)...................................................................................................................................................98
8.17. LINK REGISTER #02 (READ/WRITE)...................................................................................................................................................99
8.18. LINK REGISTER #03 (READ/WRITE).................................................................................................................................................100
CHAPTER 9 INSTRUCTIO N ................................................................................................................................................................ 101
9.1. INSTRUCTION C ODE TABLE..............................................................................................................................................................102
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LSI Specification MB86617A
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9.2. DESCRIPTION OF E ACH INSTRUCTION
............................................................................................................................................... 103
CHAPTER 10 INTERRUPT
.....................................................................................................................................................................106
10.1. I NTERRUPT-FACTOR INDICATOR REGISTER & INTERRUPT-MASK SETTING REGISTER.............................................................107
10.2. I NTERRUPT.......................................................................................................................................................................................... 108
10.3. DESCRIPTION OF INTERRUPT............................................................................................................................................................109
CHAPTER 11 OPERATION ...................................................................................................................................................................112
11.1. INITIALIZATION................................................................................................................................................................................ 113
11.2. SELF-ID PACKET RECEIVING .........................................................................................................................................................114
11.2.1 Self-ID Packet Receive at Bus Reset Process .............................................................................................................115
11.2.2 Self-ID Packet Receive after Transmitting Ping Packet Ping................................................................................ 118
11.3. ASYNCHRONOUS PACKET TRANSMITTING.................................................................................................................................120
11.4. ASYNCHRONOUS PACKET RECEIVING .........................................................................................................................................122
11.5. ISOCHRONOUS PACKET TRANSMITTING ..................................................................................................................................... 125
11.6. ISOCHRONOUS PACKET RECEIVING .............................................................................................................................................128
CHAPTER 12 SYSTEM CO NFIGURATION ...................................................................................................................................130
12.1. RECOMMENDED CONNECTION FOR 1934 PORT (FOR ONE PORT).......................................................................................... 131
12.2. RECOMMENDED CONNECTION FOR CABLE POWER SUPPLY ..................................................................................................132
12.3. RECOMMENDED CONNECTION FOR BUILD-IN PLL LOOP F ILTER.........................................................................................133
ONFIGURATION OF FEEDBACK CIRCUIT AT CRYSTAL OSCILLATOR
12.4. C
...................................................................................134
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
1
Chapter 1 Overview
This chapter explains the overview of MB86617A.
MB86617A is Fujitsu’s IEEE1394 serial bus controller based on both IEEE1394 Standard (IEEE Std. 1394-1995) and P1394.a
Standard Draft (rev.2.0).
This MB86617A has three ports for network under the 1394 cable environment, differential transceiver, and comparator, and the
transfer data rate supports S400.
MB86617A integrates PHY and LINK layers into single-chip, and plans for degression of component side product and saving power
consumption.
MB86617A has two exclusive ports (one is the combined use for receiving a message of interface for DV) for MPEG2 and DSS data
transfer, and performs isolating and packeting of Header and Data department with these two ports automatically. This function is
suited for maintaining continuum of transfer.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
2
Chapter 2 Features
This chapter explains the features of MB86617A.
> Compliant with IEEE1394 high performance serial bus standard and P1394.a standard draft
> Integrates PHY and LINK layers into single-chip
> 1394 port number : 3 ports
> Transfer Data Rate : S100, S200, S400
> On-chip PLL (corresponding to Crystal Oscillator) : generate internal clock
> 4K Byte X 2 channels Isochronous transmit and receive data buffer
> 256Byte Asynchronous exclusive buffer for transmit/receive
> Auto isolating and packeting for received header and data of packet
> Two exclusive ports for Isochronous transfer (8 bit bus)
> Loading interface with copy protection LSI (8 bits I/O)
> Generating and Checking Function for 32bit CRC
> 6-pin cable supported
> Power supply system : 3.3V size -D battery
> Package : LQFP-176 (FPT-176P-M03)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
3
Chapter 3 Chip Block
This chapter explains the MB86617A block diagram and the function of each block.
3.1. Block Diagram
3.2. Function of Each Block
Rev.1.0 Fujitsu VLSI
MB86617A
4
PHY/
CP IC
Interface
Asynch Transmit
Asynch Transmit
Asynch Transmit
LSI Specification
3.1. Block Diagram
MB86617A block diagram is shown below.
<< Normal Operation Mode
Host Interface
FIFO
(2KByte)
TSP IC Interface
FIFO
(2KByte)
Asynch Transmit
Exclusive FIFO
(256 byte)
Packet Process
Packet Process
Exclusive FIFO
(256 byte)
LINK
FIFO
(2KByte)
Layer
Control
Circuit
Data Bridge
FIFO
(2KByte)
Fig.3.1.1 Block Diagram - Normal Operation Mode -
1394 Interface (Port 0)
TPA0
XTPA0
TPB0
XTPB0
TPBIAS0
1394 Interface (Port 1)
TPA1
XTPA1
TPB1
XTPB1
TPBIAS1
1394 Interface (Port 2)
TPA2
XTPA2
TPB2
XTPB2
TPBIAS2
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
5
PHY/
CP IC
Interface
Asynch Transmit
Asynch Transmit
Asynch Transmit
Asynch Transmit
<< Asynchronous Transmit FIFO Extended Mode
Host Interface
FIFO
(2KByte)
TSP IC Interface
FIFO
(2KByte)
Exclusive FIFO
(256 byte)
Packet Process
Packet Process
Exclusive FIFO
(256 byte)
FIFO
(2KByte)
FIFO
(2KByte)
Fig.3.1.2 Block Diagram - Asynchronous Transmit FIFO Extended Mode -
1394 Interface (Port 0)
TPA0
XTPA0
TPB0
XTPB0
TPBIAS0
1394 Interface (Port 1)
TPA1
XTPA1
LINK
Layer
Control
Circuit
TPB1
XTPB1
TPBIAS1
Data Bridge
1394 Interface (Port 2)
TPA2
XTPA2
TPB2
XTPB2
TPBIAS2
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
6
PHY/
CP IC
Interface
Asynch Transmit
Asynch Transmit
Asynch Transmit
Asynch Transmit
<< Asynchronous Receive FIFO Extended Mode
Host Interface
FIFO
(2KByte)
TSP IC Interface
FIFO
(2KByte)
Exclusive FIFO
(256 byte)
Packet Process
Packet Process
Exclus ive FIFO
(256 byte)
(2KByte)
(2KByte)
Fig.3.1.3 Block Diagram - Asynchronous Receive FIFO Extended Mode -
FIFO
Data Bridge
FIFO
LINK
Layer
Control
Circuit
1394 Interface (Port 0)
TPA0
XTPA0
TPB0
XTPB0
TPBIAS0
1394 Interface (Port 1)
TPA1
XTPA1
TPB1
XTPB1
TPBIAS1
1394 Interface (Port 2)
TPA2
XTPA2
TPB2
XTPB2
TPBIAS2
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
7
3.2. Function of Each Block
This section explains the function of each block for MB86617A.
<< PHY Layer Control Circuit
This circuit is for the Physical layer of IEEE 1394 with the following functions .
> Asynchronous transfer is supported under cable environment.
> Maximum transfer data rate : 393.216Mbit/sec.
> with three ports for transceiver/receiver : transfer IEEE1394 packet
> with bus monitor, initial performance for occurring bus reset, speed signaling, arbitration, encode/decode : transfer/receive data
<< LINK Layer Control Circuit
This circuit generates standard packet for IEEE1394, controls transfer, and performs the following functions.
> Generates and checks 32 bit CRC for header and data of packet.
> Activates cycle master function with integrated 32 bit cycle timer register
<< TSP IC Interface
This TSP IC Interface has two exclusive ports with the following functions for transmitting/receiving TSP IC, MPEG2-TS and DSS
data, and receiving DV data.
> Adds time stamp to both MPEG2-TS and DSS data.
> Outputs received data just when the value of time stamp (SPH) and cycle timer is matched with each other.
> Integrated transmit/receive (dual purpose) FIFO for transferring Isochronous by 2K byte X 2 channels.
<< CP IC Interface
This interface adds the copy information to CP IC so as to correspond to copy protect.
<< Data Bridge
This Data Bridge packets MPEG2-TS, DSS, and DVC, and re-builds the receiving data.
At data transmission, this section adds Isochronous packet header and CIP header, and connects/separates source packet
When transmitting 2ch, it connects Isochronous packet.
At data receipt, it deletes Isochronous packet header and CIP header, restores by unit of source packet.
When receiving 2ch, it separates Isochronous packet and divide them to each FIFO.
> Integrated transmit/receive (dual purpose) FIFO for transferring Isochronous by 2K byte X 2 channels.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
8
Chapter 4 Pin Assignment
This chapter explains the pin assignment and table of pin function of MB86617A.
4.1. Pin Assignment
4.2. Corresponding Table of MB86617A Pin
4.3. Outline Drawing of Package
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
9
88
SELIOA
XRESET
SELTSPA
1
132
133
4.1. Pin Assignment
The following diagram shows the MB86617A pin assignment.
MODE1
MODE0
XCS
XWR(XDS)
XRD(R/XW)
ALE
XINT
DREQ
XDACK
VDD
VSS
D15
D14
D13
D12
D11
D10
D9
D8
VDD
VSS
AD7
AD6
AD5
AD4
AD3
AD2
AD1
D0
TEST1
TEST2
VSS
VDD
XO
AVSS
AVDD
FIL
RF
AVSS
AVDD
RO
CPS
TSDB7
TSDB6
TSDB5
TSCGMSB
TSVALB
140
DSSCLKB
TEST3
VSS
VDD
155
SELTSPB
SELIOB
TSDB0
IERRB
150
TSDB3
TSDB2
TSDB1
VDD
VSS
TSDB4
145
XILWRE
ICLK
XIV
160
TEST4
XFP
MB86617
TEST5
A4
170
A5
A6
TEST6
A7
165
VSS
VDD
TEST7
VDD
VSS
176
5
10
15
20
175
A1
A2
A3
FPT-176P-M03
25
30
XI
35
40
44
45
50
55
60
65
70
75
80
TSSYNCB
TSCLKB
VDD
VSS
135
85
DSSCLKA
130
125
120
115
110
105
100
95
90
89
IERRA
TSDA0
TSDA1
TSDA2
TSDA3
VSS
VDD
TSDA4
TSDA5
TSDA6
TSDA7
TSVALA
TSCGMSA
TSSYNCA
TSCLKA
VSS
VDD
VSS
VDD
VSS
VDD
VSS
AVDD
AVSS
TPB2
XTPB2
TPBIAS2
TPA2
XTPA2
AVSS
AVDD
AVDD
AVSS
TPB1
XTPB1
TPBIAS1
TPA1
XTPA1
AVSS
AVDD
AVDD
AVSS
TPB0
XTPB0
TPBIAS0
TPA0
XTPA0
AVSS
AVDD
VSS
VDD
PWR2
PWR1
LINKON
PWR3
PMODE
VDD
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
10
4.2. Corresponding Table of MB86617A Pin
The following table shows the corresponding items of MB86617A pin.
Pin
No.
1 I XRESET 45 - AVSS 89 133 O SELTSPA
2 I MODE1 46 - AVDD 90 134 I DSSCLKA
3 I MODE0 47 I/O XTPB2 91 135 - VDD
4 I XCS 48 I/O TPB2 92 136 - VSS
5 I XWR(XDS) 49 I/O XTPA2 93 137 I/O TSCLKB
6 I XRD(R/XW) 50 I/O TPA2 94 138 I TSSYNCB
7 I ALE 51 O TPBIAS2 95 139 I TSCGMSB
8 O XINT 52 - AVDD 96 - VDD 140 I/O TSVALB
9 O DREQ 53 - AVSS 97 - VSS 141 I/O TSDB7
10 I XDACK 54 - AVSS 98 142 I/O TSDB6
11 - VDD 55 - AVDD 99 143 I/O TSDB5
12 - VSS 56 I/O XTPB1 100 144 I/O TSDB4
13 I/O D15 57 I/O T PB1 101 145 - VDD
14 I/O D14 58 I/O XTPA1 102 146 - VSS
15 I/O D13 59 I/O TPA1 103 147 I/O TSDB3
16 I/O D12 60 O TPBIAS1 104 148 I/O TSDB2
17 I/O D11 61 - AVDD 105 - VDD 149 I/O TSDB1
18 I/O D10 62 - AVSS 106 - VSS 150 I/O TSDB0
19 I/O D9 63 - AVSS 107 151 O IERRB
20 I/O D8 64 - AVDD 108 152 O SELIOB
21 - VDD 65 I/O XTPB0 109 153 O SELTSPB
22 - VSS 66 I/O TPB0 110 154 I DSSCLKB
23 I/O AD7 67 I/O XTPA0 111 155 - VDD
24 I/O AD6 68 I/O TPA0 112 156 - VSS
25 I/O AD5 69 O TPBIAS0 113 157 I/O TEST3
26 I/O AD4 70 - AVDD 114 158 I/O TEST4
27 I/O AD3 71 - AVSS 115 - VDD 159 O XFP
28 I/O AD2 72 - VSS 116 - VSS 160 O XILWRE
29 I/O AD1 73 - VDD 117 I/O TSCLKA 161 I XIV
30 I/O D0 74 I PWR1 118 I/O TSSYNCA 162 I ICLK
31 I/O TEST1 75 I PWR2 119 I/O TSCGMSA 163 - VDD
32 I/O TEST2 76 I PWR3 120 I/O TSVALA 164 - VSS
33 - VSS 77 O LINKON 121 I/O TSDA7 165 I/O TEST5
34 I XI 78 I PMODE 122 I/O TSDA6 166 I/O TEST6
35 - VDD 79 123 I/O TSDA5 167 I A7
36 I/O XO 80 124 I/O TSDA4 168 I A6
37 - AVSS 81 125 - VDD 169 I A5
38 - AVDD 82 126 - VSS 170 I A4
39 O FIL 83 127 I/O TSDA3 171 I A3
40 O RF 84 128 I/O TSDA2 172 I A2
41 - AVSS 85 - VDD 129 I/O TSDA1 173 I A1
42 - AVDD 86 - VSS 130 I/O TSDA0 174 I/O TEST7
43 O RO 87 131 O IERRA 175 - VDD
44 I CPS 88 132 O SELIOA 176 - VSS
I/O Pin Name
Pin
No.
I/O Pin Name
Pin
No.
I/O Pin Name
Pin
No.
I/O Pin Name
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
11
4.3. Outline Drawing of Package
This section shows the outline drawing of MB86617A package (LQFP-176).
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
12
Chapter 5 Pin Function
This chapter explains the MB86617A pin function.
5.1. IEE E1394 Interface
5.2. Isochronous (TSP-IC,DV-IC) Interface
5.4. MPU Interface
5.5. Other Pins
5.6. Power/GND Pin
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
13
5.1. IEEE1394 Interface
This section explains the pin function of IEEE1394 interface.
Signal Name I/O Function
TPA0 I/O I/O pin of TPA + (plus) signal on cable port 0
XTPA0 I/O I/O pin of TPA - (minus) signal on cable port 0
TPB0 I/O I/O pin of TPB + (plus) signal on cable port 0
XTPB0 I/O I/O pin of TPB - (minus) signal on cable port 0
TPA1 I/O I/O pin of TPA + (plus) signal on cable port 1
XTPA1 I/O I/O pin of TPA - (minus) signal on cable port 1
TPB1 I/O I/O pin of TPB + (plus) signal on cable port 1
XTPB1 I/O I/O pin of TPB - (minus) signal on cable port 1
TPA2 I/O I/O pin of TPA + (plus) signal on cable port 2
XTPA2 I/O I/O pin of TPA - (minus) signal on cable port 2
TPB2 I/O I/O pin of TPB + (plus) signal on cable port 2
XTPB2 I/O I/O pin of TPB - (minus) signal on cable port 2
TPBIAS0 O Output pin of reference voltage for common voltage on cable port 0
TPBIAS1 O Output pi n of reference voltage for common voltage on cable port 1
TPBIAS2 O Output pin of reference voltage for common voltage on cable port 2
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
14
active.
5.2. Isochronous Interface
This section explains the pin function of Isochronous interface.
Signal Name I/O Function
TSVALIDA I/O
TSSYNCA I/O
TSCLKA I/O
TSDA7 - 0 I/O I/O pin for TS packet data (on Port A)
TSCGMSA I
SELIOA O
SELTSPA O Output pin for switching output device from port A
TSVALIDB I/O
TSSYNCB I/O
TSCLKB I/O
I.O pin for indicating effective data period of TS packet (on port A)
‘H’ active signal
Input/Output pin for indicating leading data of TS packet (on port A)
‘H’ active signal
On transmitting: sync clock input pin for input data of TS packet
On receiving : sync clock output pin for output data of TS packet
(switchable either 6.144MHz or 3.072MHz)
Serial input pin for CGMS and TSCH information (on port A)
Effective for 8 clocks since TSSYNCA input signal rising
Output pin for switching I/O on port A
Outputs ‘L’ at transmitting and ‘H’at receiving
I.O pin for indicating effective data period of TS packet (on port B)
‘H’ active signal
Input/Output pin for indicating leading data of TS packet (on port B)
‘H’ active signal
On transmitting: sync clock input pin for input data of TS packet
On receiving : sync clock output pin for output data of TS packet
(switchable either 6.144MHz or 3.072MHz)
TSDB7 - 0 I/O I/O pin for TS packet data (on port B)
TSCGMSB I
SELIOB O
SELTSPB O Output pin for switching output device from port B
ICLK I Clock input pin from DV-IC
XILWRE O
XIV I
XFP O
Serial input pin for CGMS and TSCH information (on port B)
Effective for 8 clocks si nce TSSYNCA input signal rising
Output pin for switching I/O on port B
Outputs ‘L’ at transmitting and ‘H’at receiving
Output pin for signal to be allowed accessing to Isochronous-FIFO
Asserted by completing reception of data for one source packet
‘L’ active signal
Input signal for enable signal of Isochronous data
Output Isochronous- FIFO data to data output pin while this signal in
Switch data synchronizing with rise edge of ICLK
Output pin of time stamp trigger signal
‘L’ active signal
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
15
IERRA O
IERRB O
Output pin for noticing error of receive data (on port A)
‘H’ active signal
Output pin for noticing error of receive data (on port B)
‘H’ active signal
DSSCLKA I
DSSCLKB I
Clock input pin for DSS data (27MHz)
Clock input pin for DSS data (27MHz)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
16
5.4. MPU Interface
This section explains the pin function of MPU interface.
Signal Name I/O Function
A7 – 1 I
D15 - 8,0
AD7 – 1
XCS I Chip enable input pin for this device
XRD(R/W) I
XWR(XDS) I
ALE I
DREQ O Output pin of DMA transfer requiring signal for DMAC
XDACK I Input pin of DMA allowance signal from DMAC
XINT O Output pin for interruption request
I/O
Address input pin for selecting internal register
Available only when selecting non-multi mode
When selecting multiplex mode, set this signal in fixed ‘L’
Data I/O pin
Corresponding to address input signal when selecting multiplex mode
80 system mode: read out strobe input pin for this device
68 system mode: input pin for controlling read out/write for this device
80 system mode: strobe input pin for writing into this device
68 system mode: input pin of XDS signal to be output with data bus in available
Input pin of ALE signal to be output with its address in available when selecting
multiplex mode
When selecting non -multiplex mode, set this signal in fixed ‘L’
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
17
5.5. Other Pins
This section explains the pin function like internal PLL.
Signal Name I/O Function
XRESET I
MODE1
I
MODE0
XO I/O
XI I
RF O
FIL O Exterior type filter circuit connecting pin for internal PLL
RO O Connect to GND through 5.1kΩ register.
CPS I
PMODE I
Input signal for resetting signal
When operating with cable supply power, set this pin to ‘L’.
This pin is used for setting operating mode of MPU.
This device is operated as follows depending on the setting of MODE1 and MODE0
pins;
‘00’ input: TX1940 mode
‘01’ input: MB90F574 mode
‘10’ input: 80 system non-multiplex mode
‘11’ input: 68 system non-multiplex mode
Exterior type crystal connecting pin for oscillator circuit (24.576MHz)
Connect to GND through 5.1kΩ register.
Power supply input pin from IEEE1394 cable
Detect cable supply power 0 to 33V (requiring of lowering/div iding voltage)
Criterion pin for inputting power
‘L’ input : operate with power supplying through IEEE1394 cable
‘H’ input: operate with system power
Setting pin got POWER_CLASS of Self-ID packet to be transmitted when operating
PWR3 - 1 I
LINKON O
TEST1 - 7 I/O This pin is for test. Use this pin as open one.
with supply power through cable.
Note) The POWER_CLASS of the Self_ID packet to be sent when operating
under the system power does not use this pin, but follows the setting of
Pwr bit (Bit2 to 0) of Physical Register#4.
Output pin for detecting Link-on packet receive
Output ‘H’ when receiving Link-on packet under operating with supply power
through IEEE1394 cable. When PMODE becomes ‘H’, ‘L’ is output. With the
PMODE in ‘H’, the output of this pin is not changed.
If not using this pin, set this pin as open one.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
18
5.6. Power/GND Pin
This section explains the power/GND pin.
Signal Name I/O Function
VDD - 3.3V digital power pin
VSS - Digital ground pin
AVDD - 3.3V analog power pin
AVSS - Analog ground pin
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
19
Chapter 6 Internal Register
This chapter explains the MB86617A internal register.
Note that the access of internal register is applied only 16 bits access.
Address
(HEX)
00 mode-control mode-control
02 (reserved) flag & status
04 Instruction-fetch Instruction-fetch
06 Interrupt-mask setting [A] Interrupt indicate [A]
08 Interrupt-mask setting [B] Interrupt indicate [B]
0A (reserved) Receive Acknowledge
WRITE READ
Register Name Register Name
0C A-buffer data port transmit A-buffer data port receive
0E (reserved) (reserved)
10 TSP transmit information setting [A] TSP transmit information setting [A]
12 TSP transmit information setting [B] TSP transmit information setting [B]
14 transmit offset setting [A] (upper) transmit offset setting [A] (upper)
16 transmit offset setting [A] (lower) transmit offset setting [A] (lower)
18 transmit offset setting [B] (upper) transmit offset setting [B] (upper)
1A transmit offset setting [B] (lower) transmit offset setting [B] (lower)
1C TSP receive information setting TSP receive information setting
1E
transmit DSS packet header setting [A]
(most significant)
receive DSS packet header setting [A]
(most significant)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
20
Address
(HEX)
20 transmit DSS packet header setting [A] (upper) receive DSS packet header setting [A] (upper)
22 transmit DSS packet header setting [A] (medium) receive DSS packet header setting [A] (medium)
24 transmit DSS packet header setting [A] (lower) receive DSS packet header setting [A] (lower)
26
28
2A transmit DSS packet header setting [B] (upper) receive DSS packet header setting [B] (upper)
2C transmit DSS packet header setting [B] (medium) receive DSS packet header setting [B] (medium)
2E transmit DSS packet header setting [B] (lower) receive DSS packet header setting [B] (lower)
30
32 (reserved) TSP status
34 data bridge transmit information setting 1 [A] data bridge transmit information setting 1 [A]
transmit DSS packet header setting [A]
transmit DSS packet header setting [B]
transmit DSS packet header setting [B]
WRITE READ
Register Name Register Name
receive DSS packet header setting [A]
(least significant)
receive DSS packet header setting [B]
(most significant)
receive DSS packet header setting [B]
(least significant)
(least significant)
(most significant)
(least significant)
36 data bridge transmit information setting 2 [A] data bridge transmit information setting 2 [A]
38 data bridge transmit information setting 3 [B] data bridge transmit information setting 3 [B]
3A data bridge transmit information setting 4 [B] data bridge transmit information setting 4 [B]
3C data bridge receive information setting data bridge receive information setting
3E transmit packet concatenate/split setting transmit packet concatenate/split setting
40 Late packet criterion range setting [A] Late packet criterion range setting [A]
42 Late packet criterion range setting [B] Late packet criterion range setting [B]
44 (reserved) receive Isochronous packet header indicate 1 [A]
46 (reserved) receive Isochronous packet header indicate 2 [A]
48 (reserved) receive Isochronous packet header indicate 3 [B]
4A (reserved) receive Isochronous packet header indicate 4 [B]
4C FIFO reset FIFO reset
4E (reserved) data bridge transmit/receive status [A]
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
21
Address
(HEX)
50 (reserved) data bridge transmit/receive status [B]
52 (reserved) Isochronous channel monitor 1
54 (reserved) Isochronous channel monitor 2
56 (reserved) Isochronous channel monitor 3
58 (reserved) Isochronous channel monitor 4
5A (reserved) cycle-time-monitor (upper)
5C (reserved) cycle-time-monitor (lower)
5E (reserved) Ping time monitor
60 PHY/LINK register address setting PHY/LINK register address setting
62 PHY/LINK register access port PHY/LINK register access port
64 (reserved) Revision indicate register (upper)
WRITE READ
Register Name Register Name
66 (reserved) Revision indicate register (lower)
68 (reserved) (reserved)
6A (reserved) (reserved)
6C (reserved) (reserved)
6E (reserved) (reserved)
70 (reserved) (reserved)
72 (reserved) (reserved)
74 (reserved) (reserved)
76 (reserved) (reserved)
78 (reserved) (reserved)
7A (reserved) (reserved)
7C (reserved) (reserved)
7E (reserved) (reserved)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
22
Address
(HEX)
80 (reserved) transmit CGMS/TSCH indicate [A]
82 (reserved) transmit CGMS/TSCH indicate [B]
84 transmit CGMS/TSCH indicate status transmit CGMS/TSCH indicate status
86 transmit EMI/OE setting transmit EMI/OE setting
88 (reserved) (reserved)
8A (reserved) (reserved)
8C (reserved) (reserved)
8E (reserved) (reserved)
90 (reserved) (reserved)
92 (reserved) (reserved)
94 (reserved) (reserved)
WRITE READ
Register Name Register Name
96 (reserved) (reserved)
98 (reserved) (reserved)
9A (reserved) (reserved)
9C (reserved) (reserved)
9E (reserved) (reserved)
A0 (reserved) (reserved)
A2 (reserved) (reserved)
A4 (reserved) (reserved)
A6 (reserved) (reserved)
A8 (reserved) (reserved)
AA (reserved) (reserved)
AC (reserved) (reserved)
AE (reserved) (reserved)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
23
Address
(HEX)
B 0 (reserved) (reserved)
B 2 (reserved) (reserved)
B 4 (reserved) (reserved)
B 6 (reserved) (reserved)
B 8 (reserved) (reserved)
BA (reserved) (reserved)
BC (reserved) (reserved)
BE (reserved) (reserved)
C 0 (reserved) (reserved)
C 2 (reserved) (reserved)
C 4 (reserved) (reserved)
WRITE READ
Register Name Register Name
C 6 (reserved) (reserved)
C 8 (reserved) (reserved)
CA (reserved) (reserved)
CC (reserved) (reserved)
CE (reserved) (reserved)
D0 (reserved) (reserved)
D2 (reserved) (reserved)
D4 (reserved) (reserved)
D6 (reserved) (reserved)
D8 (reserved) (reserved)
DA (reserved) (reserved)
DC (reserved) (reserved)
DE (reserved) (reserved)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
24
Address
(HEX)
E0 (reserved) (reserved)
E2 (reserved) (reserved)
E4 (reserved) (reserved)
E6 (reserved) (reserved)
E8 (reserved) (reserved)
EA (reserved) (reserved)
EC (reserved) (reserved)
EE (reserved) (reserved)
F0 (reserved) (reserved)
F2 (reserved) (reserved)
F4 (reserved) (reserved)
WRITE READ
Register Name Register Name
F6 (reserved) (reserved)
F8 (reserved) (reserved)
F A (reserved) (reserved)
FC (reserved) (reserved)
FE (reserved) (reserved)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
25
Chapter 7 Internal Register Function Description
This chapter explains the details of the internal register of MB86617A.
7.1. mode-control Register
7.2. flag & status Register
7.3. instruction fetch Register
7.4. interrupt-factor Indicate Register/interrupt-mask Setting Register
7.5. Receive Acknowledge Indicate Register
7.6. A-buffer Data Port Receive/Transmit
7.7. TSP Transmit Information Set ting Register [A]
7.8. TSP Transmit Information Setting Register [B]
7.9. Transmit Offset Setting Register [A]
7.10. Transmit Offset Setting Register [B]
7.11. TSP Receive Information Setting Register
7.12. Transmit DSS Packet Header Setting Register [A]
7.13. Transmit DSS Packet Header Setting Register [B]
7.14. TSP Status Register
7.15. Data Bridge Transmit Information Setting Register 1 [A]
7.16. Data Bridge Transmit Information Setting Register 2 [A]
7.17. Data Bridge Transmit Information Sett ing Register 3 [B]
7.18. Data Bridge Transmit Information Setting Register 4 [B]
7.19. Data Bridge Receive Information Setting Register
7.20. Transmit Packet Link/Split Setting Register
7.21. Late Packet Decision Range Setting Register [A]
7.22. Late Packet Decision Range Setting Register [B]
7.23. Receive Isochronous Packet Header Indicate Register 1 [A]
7.24. Receive Isochronous Packet Header Indicate Register 2 [A]
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
26
7.25. Receive Isochronous Packet Header Indicate Register 3 [B]
7.26. Receive Isochronous Packet Header Indicate Register 4 [B]
7.27. FIFO Reset Setting Register
7.28. Data Bridge Transmit/Receive Status Register [A]
7.29. Data Bridge Transmit/Receive Status Register [B]
7.30. Isochronous channel monitor Register
7.31. cycle-timer-monitor Indicate Register
7.32. Ping time monitor Register
7.33. PHY/LINK Register/Address Setting Register
7.34. PHY/LINK Register/Access Port
7.35. Revision Indicate Register
7.36. Transmit CGMS/TSCH Indicate Register [A]
7.37. Transmit CGMS/TSCH Indicate Register [B]
7.38. Transmit CGMS/TSCH Indicate Status Register
7.39. Transmit EMI/OE Setting Register
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
27
TSSYNCA and TSSYNCB signals are asserted when the data is outputted from TSP
7.1. M ode-control Register
Mode-control register is the register that performs the relative setting of various operation mode of this LSI.
Bit
Bit
Bit
Bit
Bit
Bit
AD R /W
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
CPS
00h R/W - - - -
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ ‘1’ ‘1’ ‘1’
BIT Bit Name Action Value Function
Read - Always indicate ‘0’.
15 - 12 reserved
Write - Always write in ‘0’.
11 CPS soft reset
10 clk off
9
s-ID store
Note 1)
Read/
Write
Read/
Write
Read/
Write
clk
soft
off
reset
PHY/LINK is reset by writing ‘0’ after writing ‘1’ (not automatic clear)
Note:
-
1) Perform read modify write so as not to re-write other bit.
2) Write ‘0’ after 500 ns minimum passed after writing ‘1’.
0 Not stop clock for providing to TSP I/F, CP I/F and data bridge.
Stop clock for providing to TSP I/F, CP I/F and data bridge when PMODE input
1
terminal is in ‘H’.
0 Deletes Self-ID packet in spite of receiving it during bus reset.
In case of receiving Self-ID packet during bu s reset process, this bit stores 512 byte
1
at maximum accompanying with both Asynchronous receive FIFO and
Asynchronous transmit FIFO.
s -ID
store
Cp_
trhrou
gh
- - -
Iso-FI
FO no
clr
AsynFIFOs
el
send/re
c
TSP
stand -
by
CP
stand -
by
8 Cp_through
7 Sync_in
6 Sync_out
5 reserved
4
Iso-FIFO
no clr
Read/
Write
Read/
Write
Read/
Write
Read 0 Always indicate ‘0’.
Write 0 Always write in ‘0’.
Read/
Write
0 Enable CP-IC interface.(Needs external CP IC)
1 Disable CP-IC interface. CP -IC interface is internally by passed.
TSSYNCA and TSSYNCB signals are neccesary to detect the first byte of the input
0
data to TSP interface.
TSSYNCA and TSSYNCB signals are not neccesary to detect the first byte of the
1
input data to TSP interface.
TSSYNCA and TSSYNCB signals are not asserted when the data is outputted from
0
TSP interface.
1
interface.
0 Clears receive Isochronous-FIFO when bus reset occurred.
1 Does not clear Isochronous-FIFO when bus reset occurred.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
28
BIT Bit Name Action value Function
3
2 send/rec
1 TSP stand -by
Asyn-FIFO
sel
Read/
Write
Read/
Write
Read/
Write
0 Uses 2K byte FIFO on LINK I/F side of bridge for Isochronous transmit/receive.
1 Uses 2K byte FIFO on LINK I/F side of bridge for Asynchronous transmit/receive.
0 Uses 2K byte FIFO for Asynchronous transmit with Asyn-FIFO sel (bit3) ‘1’.
1 Uses 2K byte FIFO for Asynchronous receive with Asyn-FIFO sel (bit3) ‘1’.
0 Activates TSP -IC I/F terminal output.
1 Disables TSP -IC I/F terminal output, and brings it in high impedance status.
0 CP stand-by
Note 1) Refer to “Self-ID Packet Receive Operation” for the internal operation flow and read-out flow of with this bit set at ‘1’.
Read/
Write
0 Activates CP I/F terminal output.
0 Disables CP I/F terminal output, and brings it in high impedance status.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
29
7.2. flag & status Register
flag & status register indicates the status of this LSI and data access inquiries.
Bit
Bit
Bit
Bit
Bit
Bit
AD R/W
02h R
15
IPC
busy
14
tran
ready
13
tran
busy
12
ISO
cycle
11
A-Tx-
buff
empty
A-Rx-
empty
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
BIT Bit Name Action Value Function
0 Indicates that receipt of instruction is available.
15 IPC busy Read
1 Indicates that receipt of instruction is not available.
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
data
buff
- - - - -
sleep
req
recv
busy
cmstr INT
0
14 tran ready Read
13 tran busy Read
12 ISO cycle Read
11
10
A-Tx-buff
Empty
A-Rx-buff
Empty
Read
Read
Indicates that bus reset or forced sleep is being executed, and transmit/receive of
0
packet is unavailable.
Indicates that bus reset is completed and forced sleep is not being executed, and
1
transmit/receive of packet is available.
Indicates that packet transmit is not being executed or in the process of packet
0
receive addressed to this node.
Indicates that packet transmit is being executed or in the process of packet receive
1
addressed to this node.
0 Indicates that Isochronous cycle is not being executed.
Indicates that Isochronous cycle is being executed by transmit or receive of cycle
1
start packet.
0 Indicates that Asynchronous transmit specific buffer is not empty.
1 Indicates that Asynchronous transmit specific buffer is empty.
0 Indicates that Asynchronous receive specific buffer is not empty.
1 Indicates that Asynchronous receive specific buffer is empty.
9 – 5 reserved Read 0 Always indicate ‘0’.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
30
BIT Bit Name Action Value Function
0 Indicates that the device is not in forced sleep.
4 sleep Read
3 data req Read
2
1 cmstr Read
0 INT Read
Note 1) IEEE1394 block is in internal reset status until integrated PLL is locked after turning the power ON. PHY layer and Link
Note 2) In case that Asynchronous packet addressed to this node is received with this Bit indicate ‘1’, it transmits “ack busy X”.
recv busy
Note 2)
layer do not operate during this period.
Read
Indicates that the device is in forced sleep by accepting “Start sleep” (01h)
1
instruction.
0 Indicates that no data is stored in ASYNC receive specific buffer.
1 Indicates that data is stored in ASYNC receive specific buffer.
0 Indicates that packet receive is not in busy mode.
Indicates that packet receive is in busy mode due to receipt of Asynchronous
1
packet and self-ID packet.
0 Indicates that node is not the cycle master now.
1 Node is the cycle master now.
0 Interrupt indicate register does not have interrupt.
1 Interrupt indicate register has interrupt.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
31
7.3. instruction-fetch Register
instruction-fetch register is the register that writes in instructions for this LSI, and consists of the instruction code and operand.
Refer to “Chapter 9 Instruction ” for each instruction code and operand code.
AD R/W
04h R/W Instruction code operand
Initial Value “00 h” “00 h”
BIT Bit Name Action Value Function
Bit
Bit
15
14
Bit
13
Bit
12
Bit
11
Bit
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bi t 2 Bit 1 Bit
10
0
15 - 8
7 - 0 operand
Note) Before writing in instruction for this register, read out IPC busy Bit (bit15) of “7.2. flag & status Register”, and confirm that the
instruction
code
IPC busy value is ‘0’.
Read/
Write
Read/
Write
- Specify each instruction code.
Specify required operand for each instruction code.
Write ‘0’ into all bits for instructions without operand.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
32
7.4. interrupt-facto r Indicate Register/interrupt-mask Setting Register
interrupt-factor indicate register is the register that indicates interrupt reported by this LSI.
Refer to “Chapter 10 Interrupt ” for measure against and details of each Bit and interrupt factor.
interrupt-mask setting register is the register that controls mask of each interrupt factor generated by this LSI.
Bit
Bit
Bit
Bit
Bit
Bit
AD R/
06h
W interrupt-mask
08h
W interrupt-mask
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
BIT Bit Name Action Value Function
15
14
13
12
11
R Interrupt-factor
R Interrupt-factor
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
0 Indicate that interrupt factors are not generated.
interrupt-facto
r
15 - 0
interrupt-mask Write
Read
Indicate that interrupt factors are generated.
1
After reading out this register, clear to ‘0’ automatically.
0 Do not mask interrupt factors.
Mask interrupt factors.
1
Interrupt factors masked by setting of this register are neither stored in interrupt
indicate register nor assert INT signal.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
33
7.5. Receive Acknowledge Indicate Register
Receive Acknowledge indicate register is the register that indicates received Acknowledge packet addressed to itself.
Read out this register after interrupt report of “Asynchronous packet send”.
Bit
Bit
Bit
Bit
Bit
Bit
AD R/W
0Ah R - - - - - - - - Receive ack-code Receive ack-parity
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ “0 h” “0 h”
BIT Bit Name Action Value Function
15 - 8 reserved Read - Always indicate ‘0’.
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
7 - 4
3 - 0
Note) In case of not receiving Acknowledge within specified time, this register indicates “00h” and reports interrupt of “Acknowledge
missing”.
Receive
Acknowledge-co
de
Receive
Acknowledge-par
ity
Read -
Read -
Indicate code of received Acknowledge packet addressed to it.
(MSB: bit7, LSB: bit5)
Indicate parity of received Acknowledge packet addressed to it.
(MSB: bit3, LSB: bit0)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
34
7.6. A-buffer Data Port Receive/Transmit
This integrated register is the buffer access port for both ASYNC receive specific buffer and ASYNC transmit specific one.
Read data is able to be read out IEEE1394 packet data in the order received. (MSB: 1ST read)
Write data is transmitted as IEEE1394 packet data in the order written in. (MSB: 1ST write)
Bit
Bit
Bit
Bit
Bit
Bit
AD R/W
0C h
W ASYNC Transmit Specific Buffer Data
Initial Value Undefined
BIT Bit Name Action Value Function
15
14
13
12
11
R ASYNC Receive Specific Buffer Data
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
ASYNC Receive
Speci fic Buffer
15 - 0
Data
ASYNC Transmit
Specific Buffer
Data
Read -
Write -
Read out port of Asynchronous receive specific buffer.
(MSB: bit15, LSB: bit0)
Write in port of Asynchronous transmit specific buffer.
(MSB: bit15, LSB: bit0)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
35
7.7. TSP Transmit Informa tion Setting Register [A]
TSP transmit information setting register [A] is the register that makes settings for transmit packet processed by bridge -Ach.
Bit
Bit
Bit
Bit
Bit
Bit
AD R /W
10h R/ W
Initial Value ‘0’ ‘0’ ‘0’ “00 h” ‘0’ ‘0’ ‘0’ “00 b” ‘0’ ‘0’
BIT Bit Name Action Value Function
15 Tx start -A
15
Tx
start
-A
14
Tx
end
-A
13
Tx
select
-A
Read/
Write
12
11
0
1 Starts transmit processing with bridge-Ach.
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
Tx
input
set TS-ID-A
Automatically clears when transmit process is started with bridge-Ach after setting
at ‘1’.
form
-A
DSS
size-A
EMI
select
-A
set EMI -A
27M
count
-A
0
port
mask-
A
14 Tx end-A
13 Tx select -A
12 - 7 set TS-ID-A
6 Tx form-A
5
input DSS
size-A
Read/
Write
Read/
Write
Read/
Write
Read/
Write
Read/
Write
Automatically clears when transmit process is stopped by bridge-Ach after setting
0
at ‘1’.
1 Stops transmit process by bridge-Ach.
0 Outputs ‘L’ to SELTSPA output terminal.
1 Outputs ‘H’ to SELTSPA output terminal.
Set TSCH classification ID to be stored at FIFO of bridge-Ach.
(MSB: bit1 2, LSB: bit7)
0 Processes transmit data as MPEG2-TS.
1 Processes transmit data as DSS packet.
0 Processes transmit DSS packet as 140 byte.
1 Processes transmit DSS packet as 130 byte.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
36
BIT Bit Name Action Value Function
4 EMI select -A
Read/
Write
Selects CGMS information input from TSP -IC as EMI information to be output to
0
CP-IC.
Selects setting value of set EMI -A (bit3 to 2) as EMI information to be output to
1
CP-IC.
3 - 2 set EMI -A
1 27M count-A
0 port mask -A
Read/
Write
Read/
Write
Read/
Write
Set EMI information to be output to CP-IC.
-
Valid only when EMI select-A (bit4) is ‘1’.
(MSB: bit3, LSB: bit2)
Does not insert internal 27 MHz counter value to System clock count range of DSS
0
packet header.
Inserts internal 27 MHz counter value to System clock count range of DSS packet
1
header.
Does not mask port A input of TSP-IC interface.
0
Read in input data from port A at transmit.
Masks port A input of TSP- IC interface.
1
Does not read in input data from port A at transmit.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
37
7.8. TSP Transmit Information Setting Register [B]
TSP transmit information setting register [B] is the register that makes settings for transmit packet processed by bridge-Bch.
Bit
Bit
Bit
Bit
Bit
Bit
AD R /W
12h R/ W
Initial Value ‘0’ ‘0’ ‘0’ “00 h” ‘0’ ‘0’ ‘0’ “00 b” ‘0’ ‘0’
BIT Bit Name Action Value Function
15 Tx start -B
15
Tx
start
-B
14
Tx
end
-B
13
Tx
select
-B
Read/
Write
12
11
0
1 Starts transmit process with bridge-Bch.
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
Tx
input
set TS-ID-B
Automatically clears when transmit process is started with bridge -Bch after setting
at ‘1’.
form
-B
DSS
size-B
EMI
select
-B
set EMI -B
27M
count
-B
0
port
mask-
B
14 Tx end-B
13 Tx select -B
12 - 7 set TS-ID-B
6 Tx form-B
5
input DSS
size-B
Read/
Write
Read/
Write
Read/
Write
Read/
Write
Read/
Write
Automatically clears when transmit process is stopped by bridge- Bch after setting
0
at ‘1’.
1 Stops transmit process by bridge-Bch.
0 Outputs ‘L’ to SELTSPB output terminal.
1 Outputs ‘H’ to SELTSPB output terminal.
Set TSCH classification ID to be stored at FIFO of bridge-Bch.
(MSB: bit1 2, LSB: bit7)
0 Processes transmit data as MPEG2-TS packet.
1 Processes transmit data as DSS packet.
0 Processes transmit DSS packet as 140 byte.
1 Processes transmit DSS packet as 130 byte.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
38
BIT Bit Name Action Value Function
4 EMI select -B
Read/
Write
Selects CGMS information input from TSP -IC as EMI information to be output to
0
CP-IC.
Selects setting value of set EMI -A (bit3 to 2) as EMI information to be output to
1
CP-IC.
3 - 2 set EMI -B
1 27M count-B
0 port mask -B
Read/
Write
Read/
Write
Read/
Write
Set EMI information to be output to CP-IC.
-
Valid only when EMI select-A (bit4) is ‘1’.
(MSB: bit3, LSB: bit2)
Does not insert internal 27 MHz counter to System clock count range of DSS
0
packet header.
1 Inserts internal 27 MHz counter to System clock count range of DSS packet header.
Does not mask port B input of TSP-IC interface.
0
Reads in input data from port A at transmit.
Masks port B input of TSP-IC interface.
1
Does not read in input data from port A at transmit.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
39
7.9. Transmit Offset Setting Register [A]
Transmit offset sett ing register [A] is the register that sets offset value added to cycle-time-monitor value. Its aim is to generate source
packet header (Time -stamp) added to transmit packet processed by bridge -Ach. (Max. 32 ms)
Time-stamp value is generated on the basis of cycle -time-monitor value at input of first byte of source packet from TSP -IC.
Bit
Bit
Bit
Bit
Bit
Bit
AD R/W
14h R/W reserved transmit-offset-A (high)
16h R/W transmit-offset-A (low)
Initial Value “0000 h”
BIT Bit Name Action Value Function
15 - 4 (high) reserved
15
14
13
12
11
Read - Always indicate ‘0’.
Write - Always write in ‘0’.
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
3 - 0 (high)
15 - 12 (low)
11 - 0
transmit-offset
-A
Read/
Write
Set value to be added to cycle-count range of cycle-time-monitor.
Setting range is 0h to FFh. (unit=125µS).
-
Set value to be added to cycle-offset range of cycle-time-monitor.
Setting range is 0h to C00h. (unit=1/24.576 MHz).
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
40
7.10. Transmit Offset Setting Register [B]
Transmit off set setting register [B] is the register that sets offset value added to cycle-time-monitor value Its aim is to generate source
packet header (Time -stamp) added to transmit packet processed by bridge -Bch. (Max. 32 ms)
Time-stamp value is generated on the basis of cycle-time-monitor value at input of first byte of source packet from TSP -IC.
Bit
Bit
Bit
Bit
Bit
Bit
AD R/W
18h R/W reserved transmit-offset-B (high)
1Ah R/W transmit-offset-B (low)
Initial Value “0000 h”
BIT Bit Name Action Value Function
15 - 4 (high) reserved
15
14
13
12
11
Read - Always indicate ‘0’.
Write - Always write in ‘0’.
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
3 - 0 (high)
15 - 12 (low)
11 - 0
transmit-offset
-B
Read/
Write
Set value to be added to cycle-count range of cycle-time-monitor.
Setting range is 0h to FFh. (unit=125µS).
-
Set value to be added to cycle-offset range of cycle-time-monitor.
Setting range is 0h to C00h. (unit=1/24.576MHz).
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
41
7.11. TSP Receive Information Setting Register
TSP receive information setting register performs the setting for outputting received packet to TSP -IC
Bit
Bit
Bit
Bit
Bit
Bit
AD R /W
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
output
DV-
DSS-
1Ch R/ W TV2B TV1B - -
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
BIT Bit Name Action Value Function
15 TV2B
14 TV1B
13 - 12 reserved
Read/
Write
Read/
Write
Read - Always indicates ‘0’.
Write - Always write in ‘0’.
DSS
size-B
EN
0 Does not output packet received by bridge-Bch to port B of TSP -IC I/F.
1 Outputs packet received by bridge-Bch to port B of TSP -IC I/F.
0 Does not output packet received by bridge-Bch to port A of TSP-IC I/F.
1 Outputs packet received by bridge-Bch to port A of TSP-IC I/F.
EN
TS-E
TV2A TV1A - -
N
output
DSS
size-A
TCL
KSL
CMP
SEL
TSC
MP
Outputs DSS packet received by bridge -Bch, with DSS packet header attached, to
0
TSP-IC in unit of 140 byte.
11
10 DV-EN
9 DSS-EN
output DSS
size-B
Read/
Write
Read/
Write
Read/
Write
Outputs DSS packet received by bridge- Bch, without attachment of DSS packet
header, to TSP -IC in unit of 130 byte.
1
Removed DSS packet header is stored at receive DSS packet header indicate
register [B].
Deletes received data and reports FMT error when DV data is received.
0
ISO packet header and CIP header are indicated in register.
1 Allows receiving DV data.
Deletes received data and reports FMT error when DSS data is received.
0
ISO packet header and CIP header are indicated in register.
1 Allows receiving DSS data.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
42
BIT Bit Name Action Value Function
8 TS-EN
7 TV2A
6 TV1A
5 - 4 reserved
Read/
Write
Read/
Write
Read/
Write
Read - Always indicates ‘0’.
Write - Always write in ‘0’.
Deletes received data and reports FMT error when MPEG2-TS data is received.
0
ISO packet header and CIP header are indicated in register.
1 Allows receiving MPEG2-TS data.
0 Does not output the packet received by bridge-Ach to port B of TSP -IC I/F.
1 Outputs the packet received by bridge-Ach to port B of TSP-IC I/F.
0 Does not output the packet received by bridge-Ach to port A of TSP -IC I/F.
1 Outputs the packet received by bridge-Ach to port A of TSP-IC I/F.
Outputs DSS packet with DSS packet header received by bridge- Bch to TSP -IC in
0
unit of 140 byte.
3
2 TCLKSL
1 CMPSEL
0 TSCMP
Note 1) Do not set TV2B (bit15), TV1B (bit14), and DV1B (bit12) to ‘1’ simultaneously.
Note 2) Do not set TV2A (bit7), TV1A (bit6), and DV1A (bit4) to ‘1’ simultaneously.
Note 3) Do not set TV2B (bit15) and TV2A (bit7) to ‘1’ simultaneously.
Note 4) Do not set TV1B (bit14) and TV1A (bit6) to ‘1’ simultaneously.
Note 5) Do not set ‘1’ to TV2B (bit15), TV1B (bit14), TV2A (bit7) and TV1A(bit6) when TSCMP (bit0) is set to ‘1’.
Note 6) FMT error is reported when receiving data format other than DV-EN (bit10), DSS -EN (bit9) and TS-EN (bit8) regardless of
their settings.
output DSS
size-
Read/
Write
Read/
Write
Read/
Write
Read/
Write
Outputs DSS packet without DSS packet header received by bridge-Ach to TSP -IC
in unit of 130 byte.
1
Removed DSS packet header is stored at receive DSS packet header indicate register
[A].
0 Outputs received data to TSP-IC in synchronization with 6.144 MHz TSCLK.
1 Outputs received data to TSP-IC in synchronization with 3.072 MHz TSCLK.
0 Outputs to port A when TSCMP (bit0) is ‘1’.
1 Outputs to port B when TSCMP (bit0) is ‘1’.
0 Does not merge packet received by Ach and Bch.
1 Outputs to one TSP -IC after merging packets received by Ach and Bch.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
43
Register setting value and selection of output port are shown in the table below.
Receive
Status
Bit 15 Bit 14 Bit 7 Bit 6 Bit 1 Bit 0
TV2B TV1B TV2A TV1A
CMP
SEL
TS
CMP
TSP -IC I/F
Port A
TSP -IC I/F
Port B
1ch receive
2ch receive
0 0 0 1 0 0
0 0 1 0 0 0 -
0 1 0 0 0 0
1 0 0 0 0 0 -
1 0 0 1 0 0
0 1 1 0 0 0
0 0 0 0 0 1
0 0 0 0 1 1 -
Processing-Ach
Receive data
Processing-Bch
Receive data
Processing-Ach
Receive data
Processing-Bch
Receive data
Processing -Ach+Bc
Receive data
-
Processing-Ach
Receive data
-
Processing-Bch
Receive data
Processing-Bch
Receive data
Processing-Ach
Receive data
h
Processing-Ach+Bc
-
h
Receive data
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
44
7.12. Receive DSS Packet Header Indicate Register [A]/Transmit DSS Packet Header
Setting Register [A]
Receive DSS packet header indi cate register [A] indicates DSS packet header range of DSS packet received by bridge-Ach.
Transmit DSS packet header setting register [A] sets DSS packet header range of DSS packet received by bridge-Ach.
AD R/W
R
1Eh
W
R Rx-System clock count-A(low)
20h
W Tx-System clock count-A(low)
R reserved
22h
W reserved
R reserved
24h
W reserved
Bit
Bit
15
14
Rx-SI
F -A
Tx-SIF
-A
Bit
13
Bit
12
Bit
11
Bit
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
Rx-System clock count-A(high)
Tx-System clock count-A(high)
Rx-E
F -A
Tx-E
F -A
Reserved
reserved
0
R reserved
26h
W reserved
Initial Value “0000 h”
BIT Bit Name Active Value Function
Rx-SIF-A Read - Indicates SIF range of received DSS packet header.
15 (1Eh)
Tx-SIF-A Write - Write in SIF range of transmits DSS packet header.
14 - 0 (1Eh)
15 - 8(20h)
7(20h)
6 - 0(20h)
15 - 0(22h)
15 - 0(24h)
15 - 0(26h)
Rx-System
clock count-A
Tx-System
clock count-A
Rx-EF -A Read - Indicates EF range of received DSS packet header.
Tx-EF -A Write - Write in EF range of transmits DSS packet header.
reserved
Read -
Write -
Read - Indicates reserved range of received DSS packet header.
Write - Write in reserved range of transmit DSS packet header.
Indicate System clock count range of received DSS packet header.
(MSB: 1Eh-bit14 , LSB: 20h-bit8)
Write in System clock count range of transmit DSS packet header.
(MSB: 1Eh-bit14 , LSB: 20h-bit8)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
45
7.13. Receive DSS Packet Header Indicate Register [B]/Transmit DSS Packet Header
Setting Register [B]
Receive DSS packet header indicate register [B] indicates DSS packet header range of DSS packet received by bridge-Bch.
Transmit DSS packet header setting register [B] sets DSS packet header range of DSS packet received by bridge-Bch.
Bit
Bit
Bit
Bit
Bit
Bit
AD R/W
R
28h
W
R Rx-maximum bit rate-B (low)
2Ah
W Tx-maximum bit rate-B (low)
R reserved
2Ch
W reserved
15
Rx-SI
F -B
Tx-SIF
-B
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
Rx-System clock count-B (high)
Tx-System clock count-B (high)
Rx-E
F -B
Tx-E
F -B
reserved
reserved
0
R reserved
2Eh
W reserved
R reserved
30h
W reserved
Initial Value “0000 h”
BIT Bit Name Action Value Function
Rx-SIF-B Read - Indicates SIF range of receive DSS packet header.
15 (28h)
Tx-SIF-B Write - Write in SIF range of transmit DSS packet header.
14 - 0 (28h)
15 - 8(2Ah)
7(2Ah)
Rx-System
clock count-B
Tx-System
clock count-B
Rx-EF -B Read - Indicates EF range of received DSS packet header.
Read -
Write -
Indicate System clock count range of receive DSS packet header.
(MSB: 28h-bit14, LSB: 2Ah-bit8)
Write in System clock count range of transmit DSS packet header.
(MSB: 28h-bit14, LSB: 2Ah-bit8)
Tx-EF -B Write - Write in EF range of transmit DSS packet header.
6 - 0 (2Ah)
7 - 0 (2Ch)
15 - 0 (2Eh)
15 - 0 (30h)
reserved
Read - Indicates reserved range of receive DSS packet header.
Write - Write in reserved range of transmit DSS packet header.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
46
7.14. TSP Status Register
TSP status register indicates status of TSP -IC I/F.
Bit
Bit
Bit
Bit
Bit
Bit
AD R /W
32h R
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’
BIT Bit Name Action Value Function
15
CG
chg-B
14
TS
chg-B
13
no
47h-B
12
TSP
FIFOf
ull -B
11
TSP
Tx-len
FIFO
gth -err-
emp-B
0 Indicates that CGMS information input from port B of TSP IC I/F is not changed.
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
TSP
TSP
CG
TS
- -
B
chg-A
chg-A
no
47h-A
FIFO
full-A
FIFO
emp-A
Tx-len
gth-err-
A
- -
0
15 CG chg-B Read
14 TS chg-B Read
13 no 47h -B Read
12
11
TSP FIFO
full-B
TSP FIFO
emp-B
Read
Read
Indicates that CGMS information corresponding to TSCH classification ID of same
1
type input from port B of TSP IC I/F is changed.
Clears to ‘0’ by lead of this register.
0 Indicates that TS classification ID input from port B of TSP IC I/F is not changed.
Indicates that TSCH classification ID input from port B of TSP IC I/F is not
consistent with TSCH classification ID (10h- bit12 to 7 set TS-ID-A or 12h-bit12 to
1
7 set TS-ID-B) to be stored to FIFO.
Clears to ‘0’ by lead of this register.
Indicates that synchronization byte of received MPEG2-TS input from CP -IC by
0
bridge-Bch is 47h
Indicates that synchronization byte of received MPEG2 -TS input from CP -IC by
1
bridge-Bch is not 47h
Clears to ‘0’ by lead of this register.
0 Indicates that FIFO on TSP IC I/F side of bridge-Bch is not full.
1 Indicates that FIFO on TSP IC I/F side of bridge-Bch is full.
0 Indicates that FIFO on TSP IC I/F side of bridge-Bch is not empty.
1 Indicates that FIFO on TSP IC I/F side of bridge-Bch is empty.
0 Indicates that transmit data length input from TSP IC I/F is normal.
10
Tx-length-err-
B
Read
Indicates that transmit data length input from TSP IC I/F is not consistent with
specified format data length.
1
Deletes transmit data without writing into FIFO.
Clears to ‘0’ by lead of this register.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
47
BIT Bit Name Active Value Function
9~8 reserved Read - Always indicate ‘0’.
7 CG chg-A Read
0 Indicates that CGMS information input from port A of TSP IC I/F is not changed.
Indicates that CGMS information input from port A of TSP IC I/F is changed.
1
Clears to ‘0’ by lead of this register.
0 Indicates that TS classification ID input from port A of TSP IC I/F is not changed.
6 TS chg-A Read
5 no 47h -A Read
4
3
2
TSP FIFO
full-A
TSP FIFO
emp-A
Tx-length-err-
A
Read
Read
Read
Indicates that TSCH classification ID input from port B of TSP IC I/F is not
consistent with TSCH classification ID (10h- bit12 to 7 set TS-ID-A or 12h-bit12 to
1
7 set TS-ID-B) to be stored to FIFO.
Clears to ‘0’ by lead of this register.
Indicates that synchronization byte of received MPEG2-TS input from CP -IC by
0
bridge-Bch is 47h
Indicates that synchronization byte of received MPEG2 -TS input from CP -IC by
1
bridge-Bch is not 47h
Clears to ‘0’ by lead of this register.
0 Indicates that FIFO on TSP IC I/F side of bridge-Ach is not full.
1 Indicates that FIFO on TSP IC I/F side of bridge-Ach is full.
0 Indicates that FIFO on TSP IC I/F side of bridge-Ach is not empty.
1 Indicates that FIFO on TSP IC I/F side of bridge-Ach is empty.
0 Indicates transmit data length input from TSP IC I/F is normal.
Indicates transmit data length input from TSP IC I/F is not consistent with
specified format data length.
1
Deletes transmit data without writing into FIFO.
Clears to ‘0’ by lead of this register.
1 - 0 reserved Read - Always indicate ‘0’.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
48
7.15. Data Bridge Transmit Information Setting Register 1 [A]
Data bridge transmit information setting register 1 [A] is the register that sets CIP header range added to transmit packet processed by
bridge-Ach.
Bit
Bit
Bit
Bit
Bit
Bit
AD R /W
34h R/W Tx SID-A Tx DBS-A Tx FN-A
Initial Value “00 h” “00 h” “00 b”
BIT Bit Name Action Value Function
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
15 - 10 Tx SID-A
9 - 2 Tx DBS-A
1 - 0 Tx FN-A
Read/
Write
Read/
Write
Read/
Write
Write in SID range of transmit CIP header.
(MSB: bit1 5, LSB: bit10)
Write in DBS range of transmit CIP header.
(MSB: bit9, LSB: bit2)
MPEG2-TS at transmit: “00000110” b
DSS at transmit: “00001001” b
Write in FN range of transmit CIP header.
(MSB: bit1, LSB: bit0)
MPEG2-TS at transmit: “11” b
DSS at transmit: “10” b
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
49
7.16. Data Bridge Transmit Information Setting Register 2 [A]
Data bridge transmit information setting register 2 [A] is the register that sets CIP header range, transmit channel, and speed added to
transmit packet processed by bridge-Ach.
Bit
Bit
Bit
Bit
Bit
Bit
AD R /W
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bi t 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
36h R/W Tx FMT-A
Initial Value “00” h ‘0’ “00” h “00” b ‘0’
BIT Bit Name Action Value Function
15 - 10 Tx FMT -A
9 Tx TSF -A
8 - 3 Tx channel-A
2 - 1 Tx speed-A
Read/
Write
Read/
Write
Read/
Write
Read/
Write
-
- Write in TSF range of transmits CIP header.
-
-
Tx
TSF-
A
Write in FMT range of transmit CIP header.
(MSB: bit1 5, LSB: bit10)
MPEG2-TS at transmit: “100000” b
DSS at transmit: “100001” b
Write in channel range of transmit Isochronous packet header.
(MSB: bit8, LSB: bit 3)
Write in transmit packet speed.
(MSB: bit2, LSB: bit1)
s100 at transmit: “00” b
s200 at transmit: “01” b
s400 at transmit: “10” b
Tx channel-A Tx speed-A -
Read - Always indicates ‘0’.
0 reserved
Write - Always writes in ‘0’.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
50
7.17. Data Bridge Transmit Information Setting Register 3 [B]
Data bridge transmit information setting register 3 [B] is the register that sets CIP header range added to transmit packet processed by
bridge-Bch.
Bit
Bit
Bit
Bit
Bit
Bit
AD R /W
38h R/W Tx SID-B Tx DBS-B Tx FN-B
Initial Value “00 h” “00 h” “00 b”
BIT Bit Name Action Value Function
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
15 - 10 Tx SID-B
9 - 2 Tx DBS-B
1 - 0 Tx FN-B
Read/
Write
Read/
Write
Read/
Write
Write in SID range of transmit CIP header.
(MSB: bit1 5, LSB: bit10)
Write in DBS range of transmit CIP header.
(MSB: bit9, LSB: bit2)
MPEG2-TS at transmit: “00000110” b
DSS at transmit: “00001001” b
Write in FN range of transmit CIP header.
(MSB: bit1, LSB: bit 0)
MPEG2-TS at transmit: “11” b
DSS at transmit: “10” b
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
51
7.18. Data Bridge Transmit Information Setting Register 4 [B]
Data bridge transmit information setting register 4 [B] is the register that sets CIP header range, transmit channel and speed added to transmit
packet processed by bridge -Bch.
Bit
Bit
Bit
Bit
Bit
Bit
AD R /W
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
3Ah R/W Tx FMT -B
Initial Value “00” h ‘0’ “00” h “00” b ‘0’
BIT Bit Name Action Value Function
15 - 10 Tx FMT -B
9 Tx TSF -B
8 - 3 Tx channel-B
2 - 1 Tx speed-B
Read/
Write
Read/
Write
Read/
Write
Read/
Write
-
- Write in TSF range of transmit CIP header.
-
-
Tx
TSF-
B
Write in FMT range of transmit CIP header.
(MSB: bit1 5, LSB: bit10)
MPEG2-TS at transmit: “100000” b
DSS at transmit: “100001” b
Write in channel range of transmit Isochronous packet header.
(MSB: bit8, LSB: bit3)
Write in transmit packet speed.
(MSB: bit2, LSB: bit1)
s100 at transmit: “00” b
s200 at tran smit: “01” b
s400 at transmit: “10” b
Tx channel-B Tx speed-B -
Read - Always indicates ‘0’.
0 reserved
Write - Always writes in ‘0’.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
52
7.19. Data Bridge Receive Information Setting Register
Data bridge receive information register performs the setting of receive packet.
Bit
Bit
Bit
Bit
Bit
Bit
AD R /W
3Ch R/
Initial Value ‘0’ ‘0’ “00 h” ‘0’ ‘0’ “00 h”
BIT Bit Name Action Value Function
15 Rx start -B
15
Rx
start
-B
14
Rx
end
-B
13
Read/
Write
12
11
Rx channel-B
0
1 Executes receive process by bridge-Bch.
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
Rx
Rx
start
end
-A
-A
Automatically clears when receive process is executed by bridge- Bch after setting
at ‘1’.
Rx channel-A
0
14 Rx end-B
13~8 Rx channel-B
7 Rx start -A
6 Rx end-A
5 - 0 Rx-channel-A
Read/
Write
Read/
Write
Read/
Write
Read/
Write
Read/
Write
Automatically clears when receive process is stopped by bridge-Bch after setting at
0
‘1’.
1 Stops receive process by bridge-Bch.
Write in Isochronous packet channel to be received by bridge-Bch.
(MSB: bit8, LSB: bit3)
Automatically clears when receive process is executed by bridge- Ach after setting
0
at ‘1’.
1 Starts receive process by bridge-Ach.
Automatically clears when receive process is stopped by bridge-Ach after setting at
0
‘1’.
1 Stops receive process by bridge-Ach.
Write in Isochronous packet channel to be received by bridge-Ach
(MSB: bit5, LSB: bit0)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
53
7.20. Transmit Packet Link/Split Setting Register
Transmit packet link/split setting register is the register that sets number of link and split of source packets to be transmitted.
Bit
Bit
Bit
Bit
Bit
Bit
AD R /W
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
o/e
Tx
3Eh R/W
Initial Value ‘0’ ‘0’ ‘0’ “000 b” “00 b” ‘0’ ‘0’ ‘0’ “000 b” “00 b”
BIT Bit Name Action Value Function
15 o/e select -B
14 Tx o/e -B
13 NF5SPB
12 - 10 SPQB
select-
B
o/e -B
NF5
SPB
Read/
Write
Read/
Write
Read/
Write
Read/
Write
SPQB DBQB
Selects odd/even value to be input from CP-IC as odd/even range of Isochronous
0
packet header to be transmitted by bridge-Bch.
Selects Tx o/e- B (bit14) setting value as odd/even range of Isochronous packet
1
header to be transmitted by bridge-Bch
Write in odd/even range of transmit Isochronous packet header.
-
Valid with o/e select- B (bit15) setting value ‘1’, and reads in this setting value to
transmit Isochronous packet header.
Executes 2SP combined transmission as FIFO NFULL operation when setting of
0
2SP separated transmission or combined transmission for less than 2SP.
With more than 3 SP, executes according to setting.
1 Executes 5 SP combined transmission at FIFO FULL.
- Write in number of link of source packet processed by bridge-Bch.
o/e
select-
A
Tx
o/e-A
NF5
SPA
SPQA DBQA
9 - 8 DBQB
7 o/e select -A
6 Tx o/e -A
Read/
Write
Read/
Write
Read/
Write
- Write in number of split of source packet processed by bridge-Bch.
Selects odd/even value to be input from CP-IC as odd/even range of Isochronous
0
packet header to be transmitted by bridge-Bch.
Selects Tx o/e-B b (bit6) setting value as odd/even range of Isochronous packet
1
header to be transmitted by bridge-Bch
Write in odd/even range of transmit Isochronous packet header.
-
Valid with o/e select-B (bit7) setting value ‘1’, and reads in this setting value to
transmit Isochronous packet header.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
54
BIT Bit Name Action Value Function
5 NF5SPA
Read/
Write
Executes 2SP combined transmission as FIFO NFULL operation when setting of
0
2SP separated transmission or combined transmission for less than 2SP.
With more than 3 SP, executes according to setting.
1 Executes 5 SP combined transmission at FIFO FULL.
4 - 2 SPQA
1 - 0 DBQA
Note)
>SPQ[2:0]----- Please specify link number of source packet.
Valid setting values are 0 - 5.
Processes assuming there are no settings from microcomputer during ‘0’ setting.
When 6 - 7 are set, it is regarded to be 5 source packet link.
>DBQ[1:0]----Please specify split number of source packet.
‘00’---No setting from microcomputer.
‘01’---2 splits
‘10’---4 splits
‘11’---8 splits, 4 splits at DSS
> When the setting values of both SPQ [2:0] and DBQ [1:0] are not ‘0’, follow the setting of SPQ [2:0].
When the setting values of both SPQ [2:0] and DBQ [1:0] are ‘0’ (no setting from microcomputer), LSI automatically executes link
process in 1 source packet unit.
Read/
Write
Read/
Write
- Write in number of links for source packet processed by bridge-Ach.
- Write in number of links for source packet processed by bridge-Ach.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
55
7.21. Late Packet Decision Range Setting Register [A]
Late packet decision range setting register [A] is the register that sets Late decision range of source packet to be transmitted by bridge -Ach.
Bit
Bit
Bit
Bit
Bit
Bit
AD R /W
40h R/W late range-A
Initial Value “0000 h”
BIT Bit Name Action Value Function
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
15 - 8
late range-A
7 - 0
Note)
Late packet decision is performed by comparing the time difference between SPH (Source Packet Header) and CTR (Cycle Time Monitor).
-Transmit:
Packet is transmitted normally when calculation result of “SPH” minus “CTR” for source packet transmitted from Bridhe-Ach is within the
“late range-A + ‘0000’h”.
If it is out of range, Late packet process is performed. The packet concerned is deleted and transmit late is reported.
Set the upper 16 bit of the setting value for transmit offset setting register[A] (14h to 16h).
-Receive:
Received packet is output at the point of “SPH = CTR” when calculation result of “ SPH” minus “CTR” for source packet received at
Bridhe-Ach is within the “late range-A + ‘0000’h” (the value this register is shifted 4 bits to the left).
If it is out of range, Late packet process is performed. The packet concerned is deleted and receive late is reported.
Read/
Write
Write in Late packet decision range.
Setting range is 0h to FFh (unit: 125µS).
-
Write in Late packet decision range.
Setting range is 0h to C0h (unit: 16/24.576MHz).
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
56
7.22. Late Packet Decision Range Setting Register [B]
Late packet decision range setting register [B] is the register that sets Late decision range of source packet to be transmitted by bridge -Bch.
Bit
Bit
Bit
Bit
Bit
Bit
AD R /W
42h R/W late range-B
Initial Value “0000 h”
BIT Bit Name Action Value Function
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
15 - 8
late range-B
7 - 0
Note)
Late packet decision is performed by comparing the time difference between SPH (Source Packet Header) and CTR (Cycle Time Monitor).
-T ransmit:
Packet is transmitted normally when calculation result of “SPH” minus “CTR” for source packet transmitted from Bridhe-Bch is within the
“late range-B + ‘0000’h”.
If it is out of range, Late packet process is performed. The packet concerned is de leted and transmit late is reported.
Set the upper 16 bit of the setting value for transmit offset setting register[B] (14h to 16h).
-Receive:
Received packet is output at the point of “SPH = CTR” when calculation result of “ SPH” minus “CTR” for source packet received at
Bridhe-Bch is within the “late range-B + ‘0000’h” (the value this register is shifted 4 bits to the left).
If it is out of range, Late packet process is performed. The packet concerned is deleted and receive late is reported.
Read/
Write
Write in Late packet decision range.
Setting range is 0h to FFh (unit: 125 µS).
-
Write in Late packet decision range.
Setting range is 0h to C0h (unit: 16/24.576MHz).
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
57
7.23. Receive Isochronous Packet Header Indicate Register 1 [A]
Receive Isochronous packet header indicate register 1 [A] is the register that indicates Isochronous packet header information received by
bridge-Ach.
Bit
Bit
Bit
Bit
Bit
Bit
AD R /W
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
44h R - - - - - - - Rx EMI-A
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ “00 b” ‘0’ “00 h”
BIT Bit Name Action Value Function
15 - 9 reserved Read - Always indicate ‘0’.
8 - 7 Rx EMI -A Read -
6 Rx o/e -A Read - Indicates odd/even range of receive Isochronous packet header.
5 - 0 Rx SID -A Read -
Indicate EMI range of receive Isochronous packet header.
(MSB: bit8, LSB: bit7)
Indicate SI range of CIP header of receive Isochronous packet.
(MSB: bit8, LSB: bit3)
Rx
o/e-A
Rx SID -A
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
58
7.24. Receive Isochronous Packet Header Indicate Register 2 [A]
Receive Isochronous packet header indicate register 2 [A] is the register that indicates Isochronous packet CIP header information received
by bridge -Ach.
Bit
Bit
Bit
Bit
Bit
Bit
AD R /W
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
46h R - - - - Rx FMT-A
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ “3F” ‘0’ “00 h”
BIT Bit Name Action Value Function
15 - 12 reserved Read - Always indicate ‘0’.
11 - 6 Rx FMT-A Read -
5 Rx 56-A Read -
4 - 0 Rx STYPE-A Read -
Indicate FMT range of receive Isochronous packet CIP header.
(MSB: bit11, LSB: bit 6)
Indicates 50/60 range of receive Isochronous packet CIP header when receiving
DV.
Indicates TSF range of receive Isochronous packet CIP header when receiving
MPEG2-TS or DSS.
Indicate STYPE range of CIP header of receive Isochronous packet.
(MSB: bit4, LSB: bit0)
Rx
56 -A
Rx STYPE-A
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
59
7.25. Receive Isochronous Packet Header Indicate Register 3 [B]
Receive Isochronous packet header indicate register 3 [B] is the register that indicates Isochronous packet header information received by
bridge-Bch.
Bit
Bit
Bit
Bit
Bit
Bit
AD R /W
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
48h R - - - - - - Rx EMI-B
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ “00 b” ‘0’ “00 h”
BIT Bit Name Action Value Function
15 - 9 reserved Read - Always indicate ‘0’.
8 - 7 Rx EMI -B Read -
6 Rx o/e -B Read - Indicates odd/even range of receive Isochronous packet header.
5 - 0 Rx SID -B Read -
Indicate EMI range of receive Isochronous packet header.
(MSB: bit8, LSB: bit7)
Indicate SI range of CIP header of receive Isochronous packet.
(MSB: bit5, LSB: bit0)
Rx
o/e-B
Rx SID -B
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
60
7.26. Receive Isochronous Packet Header Indicate Register 4 [B]
Receive Isochronous packet header indicate register 4 [B] is the register that indicates Isochronous packet CIP header information received
by bridge -Bch.
Bit
Bit
Bit
Bit
Bit
Bit
AD R /W
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
4Ah R - - - - Rx FMT -B
Initial value ‘0’ ‘0’ ‘0’ ‘0’ “3F” ‘0’ “00 h”
BIT Bit Name Action Value Function
15 - 12 reserved Read - Always indicate ‘0’.
11 - 6 Rx FMT-B Read -
5 Rx 56-B Read -
4 - 0 Rx STYPE-B Read -
Indicate FMT range of receive Isochronous packet CIP header.
(MSB: bit11, LSB: bit 6)
Indicates 50/60 range of receive Isochronous packet CIP header when receiving
DV.
Indicates TSF range of receive Isochronous packet CIP header when receiving
MPEG2-TS or DSS.
Indicate STYPE range of CIP header of receive Isochronous packet.
(MSB: bit4, LSB: bit0)
Rx
56 -B
Rx STYPE-B
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
61
7.27. FIFO Reset Setting Register
FIFO reset setting register sets force reset of bridge and each FIFO.
Bit
Bit
Bit
Bit
Bit
Bit
AD R /W
4Ch R/W reset-B
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
BIT Bit Name Action Value Function
15
14
resetT
SP
FIFO-
B
13
reset
BRG
FIFO-
B
12
11
- - - - -
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
reset
TSP
FIFO-
A
reset
BRG
FIFO-
A
- - - - -
reset-
A
0
15 reset-B
14
13
12 - 8 reserved
7 reset-A
6
reset TSP
FIFO -B
reset BRG
FIFO -B
reset TSP
FIFO -A
Read/
Write
Read/
Write
Read/
Write
Read - Always indicate ‘0’.
Write - Always write in ‘0’.
Read/
Write
Read/
Write
0 Releases forced reset of bridge-Bch.
1 Executes forced reset of bridge-Bch.
0 Releases FIFO reset on TSP -IC I/F side of bridge-Bch.
1 Resets FIFO on TSP-IC I/F side of bridge-Bch.
0 Releases FIFO reset on LINK-I/F side of bridge-Bch.
1 Resets FIFO on LINK I/F side of bridge-Bch.
0 Releases forced reset of bridge-Ach.
1 Execute forced reset of bridge-Ach.
0 Releases FIFO reset on TSP -IC I/F side of bridge -Ach.
1 Resets FIFO on TSP-IC I/F of bridge-Ach.
5
4 - 0 Reserved
Note 1) This register is not cleared automatically.
After writing ‘1’, check the state and then write ‘0’.
Note 2) Do not set ‘1’ to this register during transmit/receive execution.
reset BRG
FIFO -A
Read/
Write
Read - Always indicate ‘0’.
Write - Always write in ‘0’.
0 Releases FIFO reset on LINK-I/F side of bridge-Ach.
1 Resets FIFO on LINK I/F side of bridge-Ach.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
62
7.28. Data Bridge Transmit/Receive Status Register [A]
Data bridge transmit/receive status register indicates status of packet to be transmitted/received by bridge-Ach.
Bit
Bit
Bit
Bit
Bit
Bit
AD R /W
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
Tx
Rx
Rx
Rx
4Eh R
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’
BIT Bit Name Action Value Function
15 Tx busy -A Read
14 Rx busy -A Read
busy-
A
busy-
A
1STP-
A
EMI
chg-A
Rx o/e
chg-A
Rx
dlen
err -A
Indicates that bridge-Ach is not in the process of transmit.
0
Indicates ‘0’ when Tx end- A (10h -bit14) is set at ‘1’ and transmit process is
stopped.
Indicates that bridge-Ach is in the process of transmit.
1
Indicates ‘1’ when Tx start-A (10h-bit15) is set at ‘1’ and transmit process is
started.
Indicates that bridge-Ach is not in the process of receive.
0
Indicates ‘0’ when Rx end-A (3Ch- bit6) is set at ‘1’ and receive process is stopped.
Indicates that bridge-Ach is in the process of receive.
1
Indicates ‘1’ when Rx start -A (3Ch -bit7) is set at ‘1’ and receive process is started.
Tx
Rx
late-A
late-A
Rx 56
err-A
Rx
stype
err -A
BRG
FIFO
full-A
BRG
FIFO
emp-
A
Rx
DBC
err -A
Rx
CIP
err-A
Rx
FMT
err -A
Indicates that Isochronous packet received after starting receive process is not the
0
first packet received.
13 Rx 1STP-A Read
12
11 Rx o/e chg-A Read
Rx EMI
chg-A
Read
Indicates that the first Isochronous packet is received after receive process is
1
started.
Clears to ‘0’ by lead of this register.
Indicates that EMI information of received Isochronous packet header is not
0
changed.
Indicates that EMI information of received Isochronous packet header has changed
1
from just former EMI information of packet received by Isochronous-cycle.
Clears to ‘0’ by lead of this register.
Indicates that odd/even information of received Isochronous packet header is not
0
changed.
Indicates that odd/even information of received Isochronous packet header has
changed from just former odd/even information of packet received by
1
Isochronous-cycle.
Clears to ‘0’ by lead of this register.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
63
BIT Bit Name Action Value Function
Indicates that the data length of received packet is same as specified data length in
0
format.
10 Rx dlen-err-A Read
9 reserved Read - Always indicates ‘0’.
8 Tx late-A Read
7 Rx late-A Read
6 Rx 56 err-A Read
Indicates that the data length of received packet differs to the specified data length
in the format.
1
Clears to ‘0’ by lead of this register.
0 Indicates that transmit packet is transmitted normally.
Indicates that transmit packet became Late packet. Delete packet, and not
transmit.
1
Clears to ‘0’ by lead of this register.
0 Indicates that the received packet is normal.
Indicates that received packet was Late packet.
1
Delete packet, and not output to TSP-IC.
Clears to ‘0’ by lead of this register.
0 Indicates that 50/60 range of CIP header for received Isochronous packet is ‘0’.
Indicates that 50/60 range of CIP header of received Isochronous packet is ‘1’
1
Clears to ‘0’ by lead of this register.
5
4
3
2 Rx DBC err -A Read
Rx stype
err-A
BRG FIFO
full-A
BRG FIFO
emp-A
Read
Read
Read
Indicates that STYPE range of CIP header of received Isochronous packet is
0
‘00000’ or ‘00001’.
Indicates that STYPE range of CIP header of received Isochronous packet is other
1
than ‘00000’ or ‘00001’.
Clears to ‘0’ by lead of this register.
0 Indicates that FIFO on LINK I/F side of bridge-Ach is not full.
1 Indicates that FIFO on LINK I/F side of bridge-Ach is full.
0 Indicates that FIFO on LINK I/F side of bridge-Ach is not empty.
1 Indicates that FIFO on LINK I/F side of bridge-Ach is empty.
0 Indicates that DBC range of CIP header of received Isochronous packet is normal.
Indicates that DBC range of CIP header of received Isochronous packet received is
1
not consecutive.
Clears to ‘0’ by lead of this register.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
64
BIT Bit Name Action Value Function
1 Rx CIP err-A Read
0 R x FMT err-A Read
0 Indicates that CIP header of received Isochronous packet is normal.
Indicates that CIP header of received Isochronous packet has an error.
1
Clears to ‘0’ by lead of this register.
Indicates that FMT range of CIP header of received Isochronous packet is the value
allowed to be received at DV-EN, DSS-EN or TS-EN (1Ch –bit10 to 8)
0
(DV=‘00000’, MPEG2=‘10000’ or DSS= ‘100001’).
Indicates that FMT range of CIP header of received Isochronous packet is other
than the value allowed to be received at DV-EN, DSS-EN or TS- EN (1Ch –bit10 to
1
8) (DV=‘00000’, MPEG2=‘10000’ or DSS=‘100001’).
Clears to ‘0’ by reading of this register.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
65
7.29. Data Bridge Transmit/Receive Statu s Register [B]
Data bridge transmit/receive status register [B] indicates status of packet transmitted/received by bridge-Bch.
Bit
Bit
Bit
Bit
Bit
Bit
AD R /W
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
Tx
Rx
Rx
Rx
50h R
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’
BIT Bit Name Action Value Function
15 Tx busy -B Read
14 Rx busy -B Read
busy-
B
busy-
B
1STP-
B
EMI
chg-B
Rx o/e
chg-B
Rx
dlen
err -B
Indicates that bridge-Bch is not in the process of transmit.
0
Indicates ‘0’ when Tx end- B (12h -bit14) is set at ‘1’ and transmit process is
stopped.
Indicates that bridge-Bch is in the process of transmit.
1
Indicates ‘1’ when Tx start-B (12h-bit15) is set at ‘1’ and transmit process is
started.
Indicates that bridge-Bch is not in the process of receive.
0
Indicates ‘0’ when Rx end- B (3Ch -bit14) is set at ‘1’ and receive process is
stopped.
Indicates that bridge-Bch is in the process of receive.
1
Indicates ‘1’ when Rx start-B (3Ch-bit15) is set at ‘1’ and receive process is
started.
Tx
Rx
late-B
Rx 56
late-B
err-B
Rx
stype
err -B
BRG
FIFO
full-B
BRG
FIFO
emp-
B
Rx
DBC
err -B
Rx
CIP
err-B
Rx
FMT
err -B
Indicates that received Isochronous packet after starting receive process is not the
0
first receive packet.
13 Rx 1STP-B Read
Indicates that the first Isochronous packet is received after starting receive process.
1
Clears to ‘0’ by lead of this register.
Indicates that EMI information of receive Isochronous packet header is not
0
changed.
12
11 Rx o/e chg-B Read
Rx EMI
chg-B
Read
Indicates that EMI information of receive Isochronous packet header has changed
1
from just former EMI information of packet received by Isochronous-cycle.
Clears to ‘0’ by lead of this register.
Indicates that odd/even information of receive Isochronous packet header is not
0
changed.
Indicates that odd/even information of receive Isochronous packet header has
changed from just former odd/even information of packet received by
1
Isochronous-cycle.
Clea rs to ‘0’ by lead of this register.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
66
BIT Bit Name Action Value Function
Indicates that data length of receive packet is same as specified data length in
0
format.
10 Rx dlen -err-B Read
9 Reserved Read - Always indicates ‘0’.
8 Tx late-B Read
7 Rx late-B Read
6 Rx 56 err-B Read
Indicates that data length of receive packet differs to the specified data length in the
format.
1
Clears to ‘0’ by lead of this register.
0 Indicates that transmit packet is transmitted normally.
Indicates that transmit packet became Late packet. Delete packet, and not
transmit.
1
Clears to ‘0’ by lead of this register.
0 Indicates that received packet is normal.
Indicates that received packet was Late packet.
1
Deletes packet, and does not output to TSP-IC.
Clears to ‘0’ by lead of this register.
0 Indicates that 50/60 range of CIP header of received Isochronous packet is ‘0’.
Indicates that 50/60 range of CIP header of received Isochronous packet is ‘1’
1
Clears to ‘0’ by lead of this register.
Indicates that STYPE range of CIP header of received Isochronous packet is
0
‘00000’ or ‘00001’.
5 Rx stype err-B Read
4
3
2 Rx DBC err -B Read
BRG FIFO
full-B
BRG FIFO
emp-B
Read
Read
Indicates that STYPE range of CIP header of received Isochronous packet is other
than ‘00000’ or ‘00001’.
1
Clears to ‘0’ by lead of this register.
0 Indicates that FIFO on LINK I/F side of bridge-Ach is not full.
1 Indicates that FIFO on LINK I/F side of bridge-Ach is full.
0 Indicates that FIFO on LINK I/F side of bridge-Ach is not empty.
1 Indicates that FIFO on LINK I/F side of bridge-Ach is empty.
0 Indicates that DBC range of CIP header of received Isochronous packet is normal.
Indicates that DBC range of CIP header of received Isochronous packet is not
1
consecutive.
Clears to ‘0’ by lead of this register.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
67
BIT Bit Name Action Value Function
1 Rx CIP err-B Read
0 Rx FMT err -B Read
0 Indicates that CIP header of received Isochronous packet is normal.
Indicates that CIP header of received Isochronous packet has an error.
1
Clea red to ‘0’ by lead of this register.
Indicates that FMT range of CIP header of received Isochronous packet is the value
allowed to be received at DV-EN, DSS-EN or TS-EN (1Ch –bit10 to 8)
0
(DV=‘00000’, MPEG2=‘10000’ or DSS= ‘100001’).
Indicates that FMT range of CIP header of received Isochronous packet is other
than the value allowed to be received at DV-EN, DSS-EN or TS- EN (1Ch –bit10 to
1
8) (DV=‘00000’, MPEG2=‘10000’ or DSS=‘100001’).
Clears to ‘0’ by reading of this register.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
68
7.30. Isochronous Channel Monitor Register
Isochronous channel monitor register is the register that indicates Isochronous packet channel flowing through 1394 bus.
Bit
Bit
Bit
Bit
Bit
Bit
AD R/W
52h R Isochronous channel monitor1
54h R Isochronous channel monitor2
56h R Isochronous channel monitor3
58h R Isochronous channel monitor4
Initial Value “0000 h”
BIT Bit Name Action Value Function
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
Indicate that ‘1’ at Bit corresponding to channel number of Isochronous packet
15 - 0
Isochronous
channel
monitor
Read -
flowing through 1394 bus.
52h-bit15 - 0: channel0 - channel15
54h-bit15 - 0: channel16 - channel31
56h-bit15 - 0: channel32 - channel47
58h-bit15 - 0: channel48 - channel63
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
69
7.31. Cycle-timer-monitor Indicate Register
Cycle-timer-monitor indicate register indicates value of integrated cycle-timer register.
Bit
Bit
Bit
Bit
Bit
Bit
AD R/W
5Ah R cycle-timer-monitor (hi)
5Ch R cycle-timer-monitor (lo)
Initial Value “0000 h”
BIT Bit Name Action Value Function
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
15 - 0
Note) This register latches the lower word (5A h) by reading out lower word (5Ch), and releases latch by reading out upper word.
cycle-timer-m
onitor
To read out this register, make sure to read out in the order of 5C h → 5A h, two as a set.
Read -
Indicate value of built-in cycle-timer register.
(MSB: bit15, LSB: bit0)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
70
7.32. Ping Time Monitor Register
Ping time monitor register is the register that indicates time period of transmitting request packet to receiving response packet to the request.
Bit
Bit
Bit
Bit
Bit
Bit
AD R/W
5Eh R Ping time monitor
Initial Value “0000 h”
BIT Bit Name Action Value Function
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
15 - 0
Ping time
monitor
Read -
Indicate time period from transmitting request packet to receiving response packet
to the request. Counts by 20ns unit.
(MSB: bit15, LSB: bit0)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
71
7.33. PHY/LINK Register/Address Setting Register
PHY/LINK register/address setting register is the register that sets address in order to access PHY/LINK register indirectly. PHY/LINK
register indicated with address set by this register can be accessed from PHY/LINK register/access port.
Bit
Bit
Bit
Bit
Bit
Bit
AD R/W
60h R/W - - - - - - - - - phy/link-addr
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ “00 h”
BIT B it Name Action Value Function
15 - 7 reserved
15
14
13
12
11
Read - Always indicate ‘0’.
Write - Always write in ‘0’.
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
6 - 0 phy/link-addr
Read/
Write
Set address of PHY/LINK register to be accessed.
(MSB: 6, LSB: 0)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
72
7.34. PHY/LINK Register Access Port
PHY/LINK register access port is the port to access PHY/LINK register indirectly. PHY/LINK register indicated with address set by
PHY/LINK register/address setting register can be accessed from this port.
Bit
Bit
Bit
Bit
Bit
Bit
AD R/W
62h R/W phy/link-data
Initial Value “0000 h”
BIT Bit Name Action Value Function
15
14
13
12
11
Bit 9 B it 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
15 - 0 phy/link-data
Read -
Write -
Indicates PHY/LINK register contents defined by address set by PHY/LINK
register/address setting register. (MSB: 15, LSB: 0)
Executes write in the process of register defined by this address set by PHY/LINK
register/address setting register. (MSB: 15, LSB: 0)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
73
7.35. Revision Indicate Register
Revision indicate register is the register that indicates chip revision of this LSI.
Bit
Bit
Bit
Bit
Bit
Bit
AD R/W
64h Revision code (hi)
66h R Revision code (lo)
Initial Value Fixed
BIT Bit Name Action Value Function
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
15 - 0 Revision code Read -
Indicate Revision code.
(MSB: bit15, LSB: bit0)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
74
7.36. Transmit CGMS/TSCH Indicate Register [A]
Transmit CGMS/TSCH indicate register [A] indicates CGMS information and identification of TS type for source packet input from port A
at TSP IC I/F.
Bit
Bit
Bit
Bit
Bit
Bit
AD R/W
80h R CGMSA -2 TSCHA-2 CGMSA -1 TSCHA-1
Initial Value “00 b” “00 h” “00 b” “00 h”
BIT Bit Name Action Value Function
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
15 - 14 CGMSA -2 Read -
13 - 8 TSCHA-2 Read -
7 - 6 CGMSA-1 Read -
5 - 0 TSCHA-1 Read -
Indicates CGMS information for source packet indicated in TSCHA-2 (bit13 to 8).
(MSB: bit15, LSB: bit 14)
Indicates if ID of TS type for source packet input from port A at TSP IC I/F is
different from that in low bit (TSCHA-1).
(MSB: bit1 3, LSB: bit8)
Indicates CGMS information for source packet indicated in TSCHA-1 (bit5 to 0).
(MSB: bit7, LSB: bit6)
Indicates ID of TS type for source packet input first from port A at TSP IC I/F
(MSB: bit5, LSB: bit0)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
75
7.37. Transmit CGMS/TSCH Indicate Register [B]
Transmit CGMS/TSCH indicate register [B] indicates CGMS information and identification of TS type for source packet input from port B
at TSP IC I/F.
Bit
Bit
Bit
Bit
Bit
Bit
AD R/W
82h R CGMSB -2 TSCHB-2 CGMSB-1 TSCHB-1
Initial Value “00 b” “00 h” “00 b” “00 h”
BIT Bit Name Action Value Function
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
15 - 14 CGMSB -2 Read -
13 - 8 TSCHB-2 Read -
7 - 6 CGMSB-1 Read -
5 - 0 TSCHB-1 Read -
Indicates CGMS information for source packet indicated in TSCHB-2 (bit13 to 8).
(MSB: bit15, LSB: bit 14)
Indicates if ID of TS type for source packet input from port B at TSP IC I/F is
different from that in low bit (TSCHB-1).
(MSB: bit1 3, LSB: bit8)
Indicates CGMS information for source packet indicated in TSCHB-1 (bit5 to 0).
(MSB: bit7, LSB: bit6)
Indicates ID of TS type for source packet input first from port B at TSP IC I/F
(MSB: bit5, LSB: bit0)
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
76
7.38. Transmit CGMS/TSCH Indicate Status Register
Transmit CGMS/TSCH indicate status register indicates validity of source packet input from TSP IC I/F.
Bit
Bit
Bit
Bit
Bit
Bit
AD R/W
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
act-
vld- T
84h R/W - - - - -
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
BIT Bit Name Action Value Function
Read - Always indicate ‘0’.
15 - 11 reserved
Write - Always write in ‘0’.
Read
10 Act-TSCHB
Write - Clears to ‘0’ by writing “1”.
Read
9 Vld-TSCHB-2
TSC
HB
Indicates that the packet indicated in CGMSB-1 and TSCHB -1 (82h-bit7 to 0) was
0
finally input from port B at TSP IC I/F.
Indicates that the packet indicated in CGMSB-2 and TSCHB-2 (82h -bit15 to 8)
1
was finally input from port B at TSP IC I/F.
Indicates that the value indicated in CGMSB-2 and TSCHB-2 (82h-bit15 to 8) is
0
invalid.
Indicates that the value indicated in CGMSB-2 and TSCHB-2 (82h -bit15 to 8) is
1
valid.
SC
HB- 2
vld-T
SC
HB-1
- - - - -
act-
TSC
HA
vld- T
SC
HA- 2
vld-T
SC
HA -1
Write - Clears to ‘0’ by writing “1”.
Indicates that the value indicated in CGMSB -1 and TSCHB-1 (82h -bit7 to 0) is
0
Read
8 Vld-TSCHB-1
Write - Clears to ‘0’ by writing “1”.
Read - Always indicate ‘0’.
7 - 3 reserved
Write - Always write in ‘0’.
invalid.
Indicates that the value indicated in CGMSB -1 and TSCHB-1 (82h -bit7 to 0) is
1
valid.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
77
BIT Bit Name Action Value Function
2 act-TSCHA
1 vld-TSCHA-2
0 vld-TSCHA-1
Read
Write - Clears to ‘0’ by writing “1”.
Read
Write - Clears to ‘0’ by writing “1”.
Read
Indicates that the packet indicated in CGMSA-1 and TSCHA-1 (80h- bit7 to 0) was
0
finally input from port A at TSP IC I/F.
Indicates that the packet indicated in CGMSA-2 and TSCHA-2 (80h -bit15 to 8)
1
was finally input from port A at TSP IC I/F.
Indicates that the value indicated in CGMSA-2 and TSCHA-2 (80h -bit15 to 8) is
0
invalid.
Indicates that the value indicated in CGMSA-2 and TSCHA-2 (80h -bit15 to 8) is
1
valid.
Indicates that the value indicated in CGMSA-1 and TSCHA-1 (80h -bit7 to 0) is
0
invalid.
Indicates that the value indicated in CGMSA-1 and TSCHA-1 (80h -bit7 to 0) is
1
valid.
Write - Clears to ‘0’ by writing “1”.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
78
7.39. Transmit EMI/OE Setting Register
Transmit EMI/OE setting register sets EMI information and Odd/Even value added to empty packet until valid data is transmitted.
Bit
Bit
Bit
Bit
Bi t
Bit
AD R /W
15
14
13
12
11
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
Read/
Write
Read/
Write
IPH
OE-
B
- -
Sets the default value (EMI=‘00’, OE = ‘0’) as EMI information and Odd/Even
0
value added to IPH of empty packet until valid data is transmitted after starting
transmission.
Selects the setting value of IPH EMI -B (bit14 to 13) and IPH OE-B (bit 12) as EMI
1
information and Odd/Even value added to IPH of empty packet until valid data is
transmitted after starting transmission.
Set EMI information which are set in IPH of empty packet transmitted from
bridge-Bch.
Valid only when IPH select-B (bit15) is set to ‘1’.
(MSB: bit1 4, LSB: bit13)
EMI information after transmitting valid data depends on the setting of EMI
select-B (12h-bit4).
- -
IPH
select
-A
IPH EMI-A
86h R /W
Initial Value ‘0’ “00 b” ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ “00 b” ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
BIT Bit Name Action Value Function
15 IPH select-B
14 - 13 IPH EMI-B
IPH
select
-B
IPH EMI-B
IPH
OE-
A
- -
- -
Set Odd/Even value which is set in IPH of empty packet transmitted from
12 IPH OE -B
11 - 8 reserved
7 IPH select-A
Read/
Write
Read - Always indicate ‘0’.
Write - Always write in ‘0’.
Read/
Write
bridge-Bch.
-
Valid only when IPH select-B (bit15) is set to ‘1’.
EMI information after transmitting valid data depends on the setting of o/e select-B
(3Eh-bit15).
Sets the default value (EMI=‘00’, OE = ‘0’) as EMI information and Odd/Even
0
value added to IPH of empty packet until valid data is transmitted after starting
transmission.
Selects the setting value of IPH EMI -A (bit6 to 5) and IPH OE-A (bit 4) as EMI
1
information and Odd/Even value added to IPH of empty packet until valid data is
transmitted after starting transmission.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
79
BIT Bit Name Action Value Function
6 - 5 IPH EMI-A
4 IPH OE -A
3 - 0 reserved
Read/
Write
Read/
Write
Read - Always indicate ‘0’.
Write - Always write in ‘0’.
Set EMI information which are set in IPH of empty packet transmitted from
bridge-Ach.
Valid only when IPH select-A (bit7) is set to ‘1’.
-
(MSB: bit6, LSB: bit5)
EMI information after transmitting valid data depends on the setting of EMI
select-A (10h-bit4).
Set Odd/Even value which is set in IPH of empty packet transmitted from
bridge-Ach.
-
Valid only when IPH select-A (bit7) is set to ‘1’.
EMI information after transmitting valid data depends on the setting of o/e select-A
(3Eh-bit8).
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
80
Chapter 8 PHY/INK Register Function Description
This chapter explains the Physical Register and Link register that enables to access from PHY/LINK register access port (address 62h) by
setting PHYT/LINK register address setting register (address 60h) in detail.
8.1. PHY/LINK Register Table
8.2. Physical Register#00
8.3. Physical Register#01
8.4. Physical Register#02
8.5. Physical Register#03
8.6. Physical Register #04
8.7. Physical Register#05
8.8. Physical Register#07, 08, 09
8.9. Physical Register#0A, 0B, 0C
8.10. Physical Register#0D, 0E, 0F
8.11. Physical Register#10
8.12. Physical Register#11, 12, 13
8.13. Physical Register#14, 15, 16
8.14. Physical Register#17, 18, 19, 1A, 1B, 1C, 1D, 1E
8.15. Link Register#00
8.16. Link Register#01
8.17. Link Register#02
8.18. Link Register#03
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
81
8.1. PHY/ LINK Register Table
Table of Physical Register and Link Register is shown below.
PHY/LINK
addr
00h (reserved) Physical register #00
Write Read
02h Physical register # 01
04h (reserved) Physical register #02
06h (reserved) Physical register #03
08h Physical register # 04
0Ah Physical register # 05
0Ch (reserved) Physical register #07
0Eh (reserved) Physical register #08
10h (reserved) Physical register #09
12h Physical register # 0A ←
14h Physical register # 0B
16h Physical register # 0C
18h Physical register # 0D
1Ah Physical register # 0E
←
←
←
←
←
←
←
1Ch Physical register #0F
1Dh (reserved) Physical register #10
1Eh (reserved) Physical register #11
20h (reserved) Physical register #12
24h (reserved) Physical register #13
26h (reserved) Physical register #14
28h (reserved) Physical register #15
2Ah (reserved) Physical register #16
←
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
82
PHY/LINK
addr
Write Read
2Ch Physical register #17
2Eh Physical register #18
30h Physical register #19
32h Physical register #1A
34h Physical register #1B
36h Physical register #1C
38h Physical register #1D
3Ah Physical register #1E
3Ch Link register #00
3Eh Link register #01
40h Link register #02
42h Link register #03
←
←
←
←
←
←
←
←
←
←
←
←
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
83
8.2. Physical register #00 (read)
Physical Register#00 is the register that indicates Physical ID, root status, and cable power status of this node.
phy/
link-
addr
00 h R - - - - - - - - Physical_ID R PS
R/W
Initial value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ “00 h” ‘0’ ‘0’
Description of Each Bit
BIT Bit name Action Value Function
15 – 8 Reserved Read 0 Always indicate ‘0’.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
7 – 2 Physical_ID Read -
1 R Read
0 PS Read
Indicate node No. of this node determined by Self- identify during processing bus
reset. (MSB : 7 , LSB : 2)
Effective after completion of bus reset.
0 Indicates that this node is not root.
1 Indicates that this node is root.
0 Indicates that the supplied cable power is below specification.
1 Indicates that the supplied cable power is over specification.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
84
8.3. Physical register # 01 (read/write)
Physical Register#01 is the register that sets/indicates force-root and gap-count.
Do not write into this register except for the case that the node is Bus manager or Isochronous resource manager in the environment with
no Bus manager.
phy/
link-
addr
02 h R/W - - - - - - - - RHB IRB Gap_count
R/W
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’’ ‘0’ “3F h”
Description of Each Bit
BIT Bit Name Action Value Function
15 - 8 reserved
Bit
15
Bit
14
Bit
Bit
Bit
Bit
13
12
11
Read - Always indicate ‘0’.
Write - Always write ‘0’.
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
7
6 IRB
5 - 0
Note 1) This bit is automatically set by receiving the PHY configuration packet, too.
Note 2) This bit is automatically set by receiving the PHY configuration packet, too.
Also, this bit value returns to initial value at the second next bus reset.
RHB
Note 1)
Gap_count
Note 2)
Read/
Write
Read/
Write
Read - Indicate current gap-count value (MSB: 5 , LSB: 0).
Write - Set gap-count value (MSB: 5 , LSB: 0).
0 This node does not try to be root during next bus reset.
1 This node tries to be root during next bus reset.
0 Does not perform bus reset.
1 Performs bus reset. Automatically clears to “0” at the completion of bus reset.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
85
8.4. Physical register # 02 (read)
Physical Register#02 is the register that indicates if the extended PHY register map is in existence or not, and the number of ports (3
port).
phy/
link-
addr
04 h R - - - - - - - - Extended - Total_ports
R/W
Fixed value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ “7 h” ‘0’ “3h”
Description of each Bit
<<
BIT Bit Name Action Value Function
15 - 8 reserved Read - Always indicate ‘0’.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
7 - 5 Extended Read -
4 reserved Read - Always indicates ‘0’.
3 - 0 Total_ports Read -
Indicate that this node has the extended PHY register map. (MSB: 7 , LSB: 5)
Always indicate fixed value “7 h”.
Indicate the number of ports held by this node (MSB: 4 , LSB: 0).
Always indicate fixed value “3 h”.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
86
8.5. Physical register # 03 (read)
Physical Register#03 is the register that indicates max. transfer speed (S400) of this node.
phy/
link-
addr
06 h R - - - - - - - - Max _speed - Delay
R/W
Fixed value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
Description of Each Bit
<<
BIT Bit Name Action Value Function
15 - 8 reserved Read - Always indicate ‘0’.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
7 - 5 Max_speed Read -
4 reserved Read - Always indicates ‘0’.
3 - 0 Delay Read -
Indicate max. transfer speed supporting PHY of this node (MSB: 7 , LSB: 5).
Always indicates fixed value “010 b” (= S400).
Indicate Delay value at the receive signal repeat (MSB: 3 , LSB: 0).
Always indicate fixed value “0000 b”.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
87
8.6. Physical register # 04 (read/write)
Physical Register#04 is the register that sets the parameter of Self-ID packet to be transmitted by this node.
phy/
link-
addr
R/W
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
R Jitter
08 h
W
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
- - - - - - - -
Link_a
ctive
C onte
nder
Pwr_class
- - -
<< Description of Each Bit
BIT Bit Name Action Value Function
Read - Always indicate ‘0’.
15 - 8 reserved
Write - Always write in ‘0’.
7
6
Link_active
Note 1)
Contender
Note 2)
Read/
Write
Read/
Write
Read -
Write - Always write in ‘0’.
Set L bit (Link_active) value of Self-ID packet automatically transmitted by this
node with the system power ON.
Set c bit (CONTENDER) value of Self-ID packet automatically transmitted by this
node with the system power ON.
Indicate Jitter value at receive signal repeat.
(MSB : 5 , LSB : 3)
Always indicates fixed value “000 b”. 5 - 3 Jitter
2 - 0
Note 1) L bit value of Self-ID packet that is automatically transmitted by this node with the cable supply power ON is always set at ‘0’
Note 2) c bit value of Self -ID packet that is automatically transmitted by this node with the cable supply power ON is always set at ‘0’
Note 3) pwr field value of Self-ID packet which is automatically transmitted by this node with the cable supply powe r ON is always set
Pwr_class
Note 3)
regardless of the setting of this bit.
regardless of the setting of this bit.
at the value of PWR3 - 1 terminal regardless of the setting of this bit.
Read/
Write
Set pwr field (POWER_CLASS) value of Self-ID packet automatically transmitted
by this node with the system power ON.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
88
8.7. Physical register # 05 (read/write)
Physical Register#05 is the register indicating availability of cable supply power standard and timeout detect of arbitration state machine.
phy/
link-
addr
R/W
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
0A h R/W - - - - - - - -
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
Resume
_Int
ISBR Loop
Pwr
_fail
Time
out
Port_
event
Enab
_accel
<< Description of Each Bit
BIT Bit Name Action Value Function
Read - Always indicate ‘0’.
15 - 8 reserved
Write - Always write in ‘0’.
0 Does not indicate ‘1’ at Port_event bit during resume processing.
1 Indicates ‘1’ at Port_event bit during resume processing.
0 Does not perform short bus reset.
Performs short bus reset. Automatically clears to ‘0’ at the completion of bus
1
reset.
0 Indicates that port connection is in a loop.
1 Indicates that port connection is in a loop.
7 Resume_Int
6 ISBR
5 Loop
Read/
Write
Read/
Write
Read
Enab_
multi
Write - Clears the bit value to ‘0’ by writing in ‘1’.
0 Indicates that the cable supply power satisfies the standard.
Read
4 Pwr_fail
Write - Clears the bit value to ‘0’ by writing in ‘1’.
Read
3 Timeout
Write - Clears the bit value to ‘0’ by writing in ‘1’.
1 Indicates that the cable supply power does not satisfy the standard.
0 Indicates that timeout is not detected by arbitration state machine.
1 Indicates that timeout is detected by arbitration state machine.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
89
BIT Bit Name Action Value Function
0 Indicates that port event and resume processing have not occurred.
2 Port_event
1 Enab_accel
0 Enab_multi
Read
Write - Clears the bit value to ‘0’ by writing in ‘1’.
Read/
Write
Read/
Write
Indicates that Connected, Bias, Disabled, Fault bit has changed when Int_enable bit
1
is set at ‘1’.
Indicates that resume processing was performed when Resume_Int bit is set at ‘1’.
0 Disables arbitration acceleration function.
1 Enables arbitration acceleration function.
0 Disables multi-speed packet concatenation function.
1 Enables multi-speed packet concatenation function.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
90
8.8. Physical register # 07, 08, 09 (read)
Physical Register#07, 08, 09 are the registers that indicate signal condition of IEEE1394 port and cable connection condition.
phy/
link-
addr
0C h R - - - - - - - - Astat-0 Bstate-0
0E h R - - - - - - - - Astat-1 Bstate-1
10 h R - - - - - - - - Astat-2 Bstate-2
R/W
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
<< Description of Each Bit
BIT Bit Name Action Value Function
15 - 8 reserved Read - Always indicate ‘0’.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
Child -0 Connec
Child -1 Connec
Child -2 Connec
ted -0
ted -1
ted -2
- -
- -
- -
0
Indicate TPA line state of 1394 port n (MSB : 7 , LSB : 6).
7 - 6 Astat-n Read -
Indicate TPB line state of 1394 port n (MSB : 5 , LSB : 4).
5 - 4 Bstat-n Read -
0 Indicates that 1394 port n is parent port.
3 Child -n Read
1 Indicates that 1394 port n is children port.
0 Indicates that cable is not connected to 1394 port n.
2 Connected-n Read
1 Indicates that cable is connected to 1394 port n.
1 - 0 reserved Read - Always indicate ‘0’
00 = invalid
01 = ‘1’
10 = ‘0’
11 = ‘Z’
00 = invalid
01 = ‘1’
10 = ‘0’
11 = ‘Z’
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
91
8.9. Physical register # 0A, 0B, 0C (read/write)
Physical Register#0A, 0B, 0C are the registers that indicate bias detect condition of IEEE1394 installed in this node and performs setting
of enable/disable of IEEE1394 port.
phy/
link-
addr
R/W
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
R Bias-0
12 h
W
R Bias-1
14h
W
R Bias-2
16h
W
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
- - - - - - - - - - - - - -
-
- - - - - - - - - - - - - -
-
- - - - - - - - - - - - - -
-
<< Description of Each Bit
BIT Bit Name Action Value Function
Read - Always indicates’0’.
15 - 2 reserved
Write - Always write in ‘0’.
0 Indicates that bias voltage is not detected at 1394 port n.
Read
1 Bias-n
1 Indicates that bias voltage is detected at 1394 port n.
Disabl
ed-0
Disabl
ed-1
Disabl
ed-2
Write - Always indicates ‘0’.
0 Enables 1394 port n.
1 Disable 1394 port n.
0 Disabled-n
Read/
Write
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
92
8.10. Physical register #0D, 0E, 0F (read/write)
Physical Register#0D, 0E, 0F are the registers that indicate maximum transfer speed of the node connected to IEEE1394 port installed in
this node.
phy/
link-
addr
R/W
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
R Negotiated_speed-0
18 h
W
R Negotiated_speed-1
1A h
W
R Negotiated_speed-2
1C h
W
Initial value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’’ ‘0’’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
- - - - - - - -
- - -
- - - - - - - -
- - -
- - - - - - - -
- - -
Int_en
Fault-0 - - -
able-0
Int_en
Fault-1 - - -
able-1
Int_en
Fault-2 - - -
able-2
<< Description of Each Bit
BIT Bit Name Action Value Function
Read - Always indicates’0’.
15 - 8 reserved
Write - Always write in ‘0’.
Indicate max. transfer speed between nodes connected to 1394 port n.
(MSB: 7, LSB: 5)
000 = S100
001 = S200
010 = S400
011 - 111 = invalid
7 - 5
Negotiated_
speed-n
Read -
Write - Always write in ‘0’.
Does not indicate ‘1’ at Port_event bit when Connected, Bias, Disabled, Fault bit
0
changed.
1 Indicates ‘1’ at Port_event bit when Connected, Bias, Disabled, Fault bit changed.
0 Indicates that suspend or resume processing is normal.
1 Indicates that suspend or resume processing occurred error.
- Always indicates’0’.
- Always write in ‘0’.
4 Int_enable-n
3 Fault
2 - 0 reserved
Read/
Write
Read
Write - Clears the bit value to ‘0’ by writing in ‘1’.
Read /
Write
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
93
8.11. Physical register #10 (read)
Physical Register#10 is the register that indicates Compliance_level of this node.
phy/
link-
addr
1E h R - - - - - - - - Compliance_level
R/W
Fixed value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ “01 h”
Description of Each Bit
BIT Bit Name Action Value Function
15 - 8 reserved Read - Always indicate ‘0’.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
7 - 0
Compliance_l
evel
Read -
Indicate that this node supports P1394a standard.
(MSB: 7 , LSB: 0)
Always indicate fixe value “01 h”.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
94
8.12. Physical register #11, 12, 13 (read)
Physical Register#11, 12, 13 are the registers that indicate Vendor_ID of this node.
phy/
link-
addr
20 h R - - - - - - - - Vendor_ID-hi
22 h R - - - - - - - - Vendor_ID-mid
24 h R - - - - - - - - Vendor_ID-lo
R/W
Fixed Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ “00 h”
Fixed Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ “00 h”
Fixed Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ “0E h”
Description of Each Bit
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
BIT Bit Name Action Value Function
15 - 8 reserved Read - Always indicate ‘0’.
7 - 0 Vendor_ID Read -
Indicate Vendor ID of Fujitsu (MSB: 7, LSB: 0).
Always indicate fixed value “00000E h”.
Rev.1.0 Fujitsu VLSI
LSI Specification
MB86617A
95
8.13. Physical register #14, 15, 16 (read)
Physical Register#14, 15, 16 are the registers that indicate Product_ID of this node.
phy/
link-
addr
26 h R - - - - - - - - Product_ID-hi
28 h R - - - - - - - - Product_ID-mid
2A h R - - - - - - - - Product_ID-lo
R/W
Fixed Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ “08 h”
Fixed Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ “66 h”
Fixed Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ “17 h”
<< Description of Each Bit
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
10
0
BIT Bit Name Action Value Function
15 - 8 reserved Read - Always indicate ‘0’.
7 - 0 Vendor_ID Read -
Indicate Product ID of this chip (MSB: 7, LSB: 0).
Always indicate fixed value “086617 h”.
Rev.1.0 Fujitsu VLSI
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