Fujitsu MB3887 User Manual

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-27709-3E
ASSP F or Pow er Supply Applications (Secondary battery)
DC/DC Converter IC for Charging Li-ion battery
MB3887
The MB3887 is a DC/DC converter IC suitable for down-conversion, using pulse-width (PWM) charging and enabling output voltage to be set to any desired level from one cell to four cells. These ICs can dynamically control the secondary batter y’s charge current by detecting a voltage drop in an AC adapter in order to keep its power constant (dynamically-controlled charging) . The charging method enables quick charging, f or example, with the A C adapter during operation of a notebook PC.
The MB3887 provides a broad power supply voltage range and low standby current as well as high efficiency, making it ideal for use as a built-in charging device in products such as notebook PC. This product is covered by US Patent Number 6,147,477.

FEATURES

• Detecting a voltage drop in the AC adapter and dynamically controlling the charge current (Dynamically-controlled charging)
(Continued)

PACKAGE

24-pin plastic SSOP
(FPT-24P-M03)
MB3887
(Continued)
• Output voltage setting using external resistor : 1 cell to 4 cells
• High efficiency : 96% (VIN = 19 V, Vo = 16.8 V)
• Wide range of operating supply voltages : 8 V to 25 V
• Output voltage setting accuracy : 4.2 V ± 0.74% (T a = −10 °C to +85 °C , per cell)
• Charging current accuracy : ±5%
• Built-in frequency setting capacitor enables frequency setting using external resistor only
• Oscillation frequency range : 100 kHz to 500 kHz
• Built-in current detection amplifier with wide in-phase input voltage range : 0 V to VCC
• In standby mode, leave output voltage setting resistor open to prevent inefficient current loss
• Built-in standby current function : 0 µA (standard)
• Built-in soft-start function independent of loads
• Built-in totem-pole output stage supporting P-channel MOS FET devices
2

PIN ASSIGNMENT

INC2 :
OUTC2 :
+INE2 :
INE2 :
FB2 :
VREF :
FB1 :
MB3887
(TOP VIEW)
: +INC2
1
2
3
4
5
6
7
24
: GND
23
: CS
22
: VCC (O)
21
: OUT
20
: VH
19
: VCC
18
INE1 :
+INE1 :
OUTC1 :
OUTD :
INC1 :
10
11
12
: RT
8
9
17
16
15
14
13
: INE3
: FB3
: CTL
: +INC1
(FPT-24P-M03)
3
MB3887

PIN DESCRIPTION

Pin No. Symbol I/O Descriptions
1 INC2 I Current detection amplifier (Current Amp2) input terminal. 2 OUTC2 O Current detection amplifier (Current Amp2) output terminal. 3 +INE2 I Error amplifier (Error Amp2) non-inverted input terminal. 4 INE2 I Error amplifier (Error Amp2) inverted input terminal. 5 FB2 O Error amplifier (Error Amp2) output terminal. 6 VREF O Reference voltage output terminal. 7 FB1 O Error amplifier (Error Amp1) output terminal. 8 INE1 I Error amplifier (Error Amp1) inverted input terminal 9 +INE1 I Error amplifier (Error Amp1) non-inverted input terminal.
10 OUTC1 O Current detection amplifier (Current Amp1) output terminal.
With IC in standby mode, this terminal is set to “Hi-Z” to prevent loss
11 OUTD O
of current through output voltage setting resistance.
Set CTL terminal to “H” level to output “L” level. 12 INC1 I Current detection amplifier (Current Amp1) input terminal. 13 +INC1 I Current detection amplifier (Current Amp1) input terminal.
Power supply control terminal. 14 CTL I
15 FB3 O Error amplifier (Error Amp3) output terminal. 16 −INE3 I Error amplifier (Error Amp3) inverted input terminal.
17 RT 18 VCC Power supply terminal for reference power supply and control circuit.
19 VH O Power supply terminal for FET drive circuit (VH = VCC − 6 V) . 20 OUT O External FET gate drive terminal. 21 VCC (O) Output circuit power supply terminal. 22 CS Soft-start capacitor connection terminal. 23 GND Ground terminal. 24 +INC2 I Current detection amplifier (Current Amp2) input terminal.
Setting the CTL terminal at “L” level places the IC in the standby
mode.
Triangular-wave oscillation frequency setting resistor connection
terminal.
4

BLOCK DIAGRAM

OUTC1
INE1
+INC1
INC1
+INE1
FB1
INE2
8
10
<Current Amp1>
13 12
9
7 4
+ × 20
<Error Amp1>
VREF
− +
<PWM Comp.>
+ + +
<OUT>
Drive
MB3887
21
VCC (O)
20
OUT
OUTC2
+INC2
INC2 +INE2
FB2
INE3
OUTD
FB3
CS
2
<Current Amp2>
24
1 3
5
16
11
15
<SOFT>
VREF
22
+ × 20
10 µA
<Error Amp2>
VREF
− +
<Error Amp3>
VREF
− + +
4.2 V
45 pF
VCC
Bias
Voltage
<VH>
<UVLO>
(VCC UVLO)
4.2 V
<OSC>
17 6 23 RT
<REF> <CTL>
bias
VREF
2.5 V
1.5 V
0.91 V
(0.77 V)
VREF UVLO
VREF
5.0 V
(V
CC 6 V)
215 k
+
35 k
VCC
GND
VCC
19
18 14
VH
VCC CTL
5
MB3887

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Conditions
Unit
Min Max
Rating
Power supply voltage V
CC VCC, VCC (O) terminal 28 V
Output current IOUT 60 mA Peak output current I Power dissipation P
OUT
D Ta ≤ +25 °C 740* mW
Duty 5 % (t = 1 / f
OSC × Duty)
700 m A
Storage temperature TSTG −55 +125 °C
* : The package is mounted on the dual-sided epoxy board (10 cm × 10 cm) . WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
6

RECOMMENDED OPERATING CONDITIONS

MB3887
Parameter Symbol Conditions
Unit
Min Typ Max
Value
Power supply voltage V Reference voltage output
current VH terminal output current I
CC VCC, VCC (O) terminal 8 25 V
IREF
VH
V
INE
INE1 to INE3, +INE1, +INE2 terminal
1 0mA
0 30 mA 0 VCC 1.8 V
Input voltage
+INC1, +INC2, INC1,
INC2 terminal
0 VCC V
OUTD terminal output voltage
OUTD terminal output current
VINC
V
OUTD 0 17 V
I
OUTD 0 2mA
CTL terminal input voltage VCTL 0 25 V Output current I
Peak output current I
OUT −45 +45 mA
OUT
Duty 5 % (t = 1 / fosc × Duty)
600 +600 mA
Oscillation frequency fOSC 100 290 500 kHz Timing resistor R Soft-start capacitor C VH terminal capacitor C Reference voltage output
capacitor Operating ambient
temperature
T 27 47 130 kΩ S 0.022 1.0 µF
VH 0.1 1.0 µF
CREF 0.1 1.0 µF
Ta −30 +25 +85 °C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
7
MB3887

ELECTRICAL CHARACTERISTICS

Parameter
Output voltage
1. Reference voltage block [REF]
Input stability Line 6 VCC = 8 V to 25 V 310mV Load stability Load 6 VREF = 0 mA to 1 mA 110mV Short-circuit output
current
(Ta = +25 °C, VCC = 19 V, VCC (O) = 19 V, VREF = 0 mA)
Sym-
bol
V V
Pin No.
REF1 6Ta = +25 °C 4.967 5.000 5.041 V REF2 6Ta = −10 °C to +85 °C 4.95 5.00 5.05 V
Conditions
Min Typ Max
Value
Ios 6 VREF = 1 V −50 −25 −12 mA
Unit
2. Under voltage lockout protec­tion circuit block [UVLO]
3. Soft-start block [SOFT]
4. Triangular waveform os­cillator circuit block [OSC]
V
Threshold voltage
VTHL 18
Hysteresis width V
V
Threshold voltage
VTHL 6VREF = 2.4 2.6 2.8 V
Hysteresis width V
Charge current I
Oscillation frequency
f
Frequency temperature
f/fdt 20 Ta = 30 °C to +85 °C 1* %
stability
Input offset voltage V
Input bias current I
TLH 18
H 18 VCC = VCC (O) 1.0* V
TLH 6VREF = 2.6 2.8 3.0 V
H 6 0.2 V
CS 22 −14 10 −6 µA
OSC 20 RT = 47 k 260 290 320 kHz
IO
B
VCC = VCC (O) , VCC =
VCC = VCC (O) , VCC =
3, 4,
FB1 = FB2 = 2 V 15mV
8, 9
3, 4,
8, 9
−100 30 nA
6.2 6.4 6.6 V
5.2 5.4 5.6 V
In-phase input
5-1. Error amplifier block [Error Amp1, Error Amp2]
voltage range Voltage gain AV 5, 7 DC 100* dB Frequency
bandwidth
Output voltage
Output source current
Output sink current I
* : Standard design value.
8
3, 4,
V
CM
8, 9
 0 VCC 1.8 V
BW 5, 7 AV = 0 dB 2* MHz
FBH 5, 7 4.7 4.9 V
V
VFBL 5, 7 20 200 mV
I
SOURCE 5, 7 FB1 = FB2 = 2 V −2 1mA
SINK 5, 7 FB1 = FB2 = 2 V 150 300 µA
(Continued)
MB3887
(Ta = +25 °C, VCC = 19 V, VCC (O) = 19 V, VREF = 0 mA)
Parameter
Threshold voltage
Sym-
bol
V V
Pin No.
TH1 16 FB3 = 2 V, Ta = +25 °C 4.183 4.200 4.225 V TH2 16
Conditions
FB3 = 2 V, Ta = −10 °C to +85 °C
Min Typ Max
4.169 4.200 4.231 V
Input current IINE3 16 −INE3 = 0 V −100 −30 nA
Value
Unit
5-2. Error amplifier block [Error Amp3]
6. Current detec­tion amplifier block [Current Amp1, Current Amp2]
Voltage gain A Frequency
bandwidth
V 15 DC 100* dB
BW 15 AV = 0 dB 2* MHz
V
FBH 15 4.7 4.9 V
Output voltage
V
FBL 15 20 200 mV
Output source current
I
SOURCE 15 FB3 = 2 V −2 1mA
Output sink current ISINK 15 FB3 = 2 V 150 300 µA OUTD terminal
output leak current OUTD terminal
output ON resistor
I
LEAK 11 OUTD = 17 V 01µA
R
ON 11 OUTD = 1 mA 35 50
1,
12,
Input offset voltage V
IO
+INC1 = +INC2 = −INC1
13,
= −INC2 = 3 V to VCC
3 +3mV
24
+INC1 = +INC2 =
I
+INCH
13,
24
3 V to VCC, V
IN = 100 mV
20 30 µA
+INC1 = +INC2 =
I
Input current
INCH 1, 12
I
+INCL
I
INCL 1, 12
3 V to VCC, Vin = 100 mV
13, 24+INC1 = +INC2 = 0 V,
∆Vin = −100 mV +INC1 = +INC2 = 0 V,
Vin = −100 mV
0.1 0.2 µA
180 120 µA
195 130 µA
* : Standard design value
(Continued)
9
MB3887
Parameter
6. Current detection amplifier block [Current Amp1, Current Amp2]
Sym-
bol
V
OUTC1 2, 10
V
OUTC2 2, 10
Current detection voltage
V
OUTC3 2, 10
V
OUTC4 2, 10
In-phase input voltage range
V
Voltage gain A
Frequency bandwidth
BW 2, 10 AV = 0 dB 2* MHz
V
OUTCH 2, 10 4.7 4.9 V
Output voltage
V
(Ta = +25 °C, VCC = 19 V, VCC (O) = 19 V, VREF = 0 mA)
Pin No.
Conditions
Min Typ Max
Value
Unit
+INC1 = +INC2 = 3 V to VCC,
1.9 2.0 2.1 V
∆Vin = −100 mV +INC1 = +INC2 =
3 V to VCC,
0.34 0.40 0.46 V
∆Vin = −20 mV +INC1 = +INC2 =
0 V to 3 V,
1.8 2.0 2.2 V
∆Vin = −100 mV +INC1 = +INC2 =
0 V to 3 V,
0.2 0.4 0.6 V
Vin = 20 mV
1,
CM
12, 13,
0 V
CC V
24
+INC1 = +INC2 =
V 2, 10
3 V to VCC,
19 20 21 V/V
Vin = 100 mV
OUTCL 2, 10 20 200 mV
7. PWM comparator block [PWM Comp.]
* : Standard design value
10
Output source current
Output sink cur­rent
Threshold voltage
I
SOURCE 2, 10 OUTC1 = OUTC2 = 2 V −2 1mA
ISINK 2, 10 OUTC1 = OUTC2 = 2 V 150 300 µA
5, 7,
V
TL
TH
V
Duty cycle = 0 % 1.4 1.5 V
15
5, 7,
Duty cycle = 100 %2.5 2.6 V
15
(Continued)
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