Fujitsu MB15F74UV User Manual

FUJITSU SEMICONDUCTOR

DATA SHEET

ASSP

DS04-21381-1E

Dual S

PLL Frequency

erial Input

Synthesizer

MB15F74UV

DESCRIPTION

■■■■

The Fujitsu MB15F74UV is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 4000 MHz and
a 2000 MHz prescalers. A 64/65 or a 128/129 for the 4000 MHz prescaler, and a 32/33 or a 64/65 for the
2000 MHz prescaler can be selected for the prescaler that enables pulse swallow operation.

The BiCMOS process is used, as a result a supply current is typically 9.0 mA at 3.0 V. The supply voltage range
is from 2.7 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA
selectable by serial date. The serial data format is the same as MB15F74UL. F ast locking is achie ved f or adopting
the new circuit.

MB15F74UV is in the small package (BCC18) which decreases a mount area of MB15F74UV about 50% com­paring with the former BCC20 (for dual PLL) .

FEATURES

■■■■

• High frequency operation : RF synthesizer : 4000 MHz Max
: IF synthesizer : 2000 MHz Max

• Low power supply voltage : VCC = 2.7 V to 3.6 V

• Ultra low power supply current : I

PACKAGE

■■■■

CC = 9.0 mA Typ

(VCC = 3.0 V, Ta = +25 °C, SWIF = SWRF = 0 in IF/RF locking state)

(Continued)

18-pin plastic BCC

(LCC-18P-M05)

MB15F74UV

(Continued)

• Direct power saving function : Power supply current in power saving mode
Typ 0.1 µA (V

Max 10 µA (VCC = 3.0 V at 1 system)

• Software selectable charge pump current : 1.5 mA/6.0 mA Typ

• Dual modulus prescaler : 4000 MHz prescaler (64/65 or128/129) /2000 MHz prescaler (32/33 or 64/65)

• 23 bit shift register

• Serial input binary 14-bit programmable reference divider : R = 3 to 16,383

• Serial input programmable divider consisting of:

- Binary 7-bit swallow counter : 0 to 127

- Binary 11-bit programmable counter : 3 to 2,047

• Built-in high-speed tuning, low-noise phase comparator, current-switching type constant current circuit

• On-chip phase control for phase comparator

• On-chip phase comparator for fast lock and low noise

• Built-in digital locking detector circuit to detect PLL locking and unlocking

• Operating temperature : Ta = −40 °C to +85 °C

• Serial data format compatible with MB15F74UL

• Ultra small package BCC18 (2.4 mm × 2.7 mm × 0.45 mm)

CC = 3.0 V, Ta = +25 °C at 1 system)

PIN ASSIGNMENTS

■■■■

GND

fin

XfinIF

GNDIF

VCCIF

DOIF

TOP VIEW

Clock

IN

OSC

18 17

1
2

IF

3
4
5

789

6

PS

IF PSRF

LD/fout

(LCC-18P-M05)

Data
16

14
13
12
11
10

15

LE
fin

RF

XfinRF
GNDRF
VCCRF

DORF

2

PIN DESCRIPTION

■■■■

MB15F74UV

Pin no.

Pin

name

I/O Descriptions

1GND Ground pin for OSC input buffer and the shift register circuit.
2fin

3Xfin

IF I

IF I

Prescaler input pin for the IF-PLL.
Connection to an external VCO should be AC coupling.

Prescaler complimentary input for the IF-PLL section.
This pin should be grounded via a capacitor.

4GNDIF  Ground pin for the IF-PLL section.
5V
6Do

CCIF 

IF O Charge pump output for the IF-PLL section.

Power supply voltage input pin for the IF-PLL section, the shift register and the oscillator
input buffer.

Power saving mode control pin for the IF-PLL section. This pin must be set at “L” when

7PSIF I

the power supply is started up. (Open is prohibited.)
PS

IF = “H” ; Normal mode/PSIF = “L” ; Power saving mode

Lock detect signal output (LD) /phase comparator monitoring output (fout) pin. The out-

8 LD/fout O

put signal is selected by LDS bit in a serial data.
LDS bit = “H” ; outputs fout signal/LDS bit = “L” ; outputs LD signal

Power saving mode control for the RF-PLL section. This pin must be set at “L” when the

9PS

RF I

power supply is started up. (Open is prohibited. )
PS

RF = “H” ; Normal mode/PSRF = “L” ; Power saving mode

10 DoRF O Charge pump output for the RF-PLL section.
11 V
12 GND

13 Xfin

CCRF  Power supply voltage input pin for the RF-PLL section.

RF  Ground pin for the RF-PLL section

RF I

14 finRF I

15 LE I

16 Data I

17 Clock I

18 OSC

IN I

Prescaler complimentary input pin for the RF-PLL section.
This pin should be grounded via a capacitor.

Prescaler input pin for the RF-PLL.
Connection to an external VCO should be via AC coupling.

Load enable signal input pin (with the schmitt trigger circuit)
When LE is set “H”, data in the shift register is transferred to the corresponding latch ac­cording to the control bit in a serial data.

Serial data input pin (with the schmitt trigger circuit)
Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter,
RF-ref. counter, RF-prog. counter) according to the control bit in a serial data.

Clock input pin for the 23-bit shift register (with the schmitt trigger circuit)
One bit data is shifted into the shift register on a rising edge of the clock.

The programmable reference divider input pin. TCXO should be connected with an AC
coupling capacitor.

3

MB15F74UV

BLOCK DIAGRAM

■■■■

PSIF

finIF

XfinIF

OSCIN

finRF

XfinRF

(7)

(2)

(3)

(18)

(14)

( )

13

Intermittent

mode control

(IF-PLL)

Prescaler

(IF-PLL)

(32/33, 64/65)

OR

Prescaler

(RF-PLL)

(64/65, 128/129)

3 bit latch

LDS

SWIF

7 bit latch 11 bit latch

Binary 7-bit

swallow counter

FCIF

(IF-PLL)

Binary 11-bit

programmable

counter (IF-PLL)

2 bit latch 14 bit latch 1 bit latch

T1 T2

Binary 14-bit pro-

grammable ref.
counter(IF-PLL)

C/P setting

counter

frIF

frRF

T1 T2

Binary 14-bit pro-

grammable ref.

counter (RF-PLL))

C/P setting

counter

2 bit latch 14 bit latch 1 bit latch

VCCIF GNDIF

(5)

fpIF

fpRF

Phase
comp.

(IF-PLL)

(4)

Fast
lock

Tuning

Lock Det.

(IF-PLL)

LDIF

AND

LD

Lock Det.

(RF-PLL)

Charge

pump

(IF-PLL)

Current

Switch

(6)

DoIF

Fast
lock

Tuning

Selector

LD
frIF

(8)

frRF
fpIF

LD/
fout

fpRF

RF

PSRF

LE

(9)

(15)

Intermittent

mode control

(RF-PLL)

Schmitt

trigger

circuit

LDS

3 bit latch

Latch selector

Binary 7-bit

swallow counter

FCRF

SWRF

(RF-PLL)

Binary 11-bit

programmable

counter (RF-PLL)

Phase
comp.

(RF-PLL)

fpRF

7 bit latch 11 bit latch

Tuning

Fast lock

Charge

pump

(RF-PLL)

Current

Switch

(10)

DoRF

Schmitt

Data
Clock

(16)

(17)

trigger

circuit

Schmitt

trigger

C

C

N

N

23-bit shift register

1

2

circuit

(1)

GND

(11) (12)

V

CCRF

GNDRF

4

ABSOLUTE MAXIMUM RATINGS

■■■■

MB15F74UV

Parameter Symbol

Unit

Min Max

Rating

Power supply voltage V
Input voltage V

LD/fout V

CC −0.5 4.0 V

I −0.5 VCC + 0.5 V

O GND VCC V

Output voltage

DoIF, DoRF VDO GND VCC V

Storage temperature Tstg −55 +125 °C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

RECOMMENDED OPERATING CONDITIONS

■■■■

Value

Parameter Symbol

Unit Remarks

Min Typ Max

Power supply voltage V

CC 2.7 3.0 3.6 V VCCRF = VCCIF

Input voltage VI GND  VCC V
Operating temperature Ta −40 +85 °C

Note : • VCCRF and VCCIF must supply equal voltage.

Even if either RF-PLL or IF-PLL is not used, power must be supplied to V

CCRF and VCCIF to keep them

equal.
It is recommended that the non-use PLL is controlled by power saving function.

• Although this device contains an anti-static element to prevent electrostatic breakdown and the circuitry
has been improved in electrostatic protection, observe the f ollowing precautions when handling the device .

• When storing and transporting the device, put it in a conductive case.

• Before handling the device, confirm the (jigs and) tools to be used have been uncharged (grounded) as
well as yourself. Use a conductive sheet on working bench.

• Before fitting the device into or removing it from the socket, turn the power supply off.

• When handling (such as transporting) the device mounted board, protect the leads with a conductive
sheet.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

5

MB15F74UV

*

ELECTRICAL CHARACTERISTICS

■■■■

(VCC = 2.7 V to 3.6 V, Ta = −40 °C to +85 °C)

Parameter Symbol Condition

Min Typ Max

CCIF

V

CCIF = 3.0 V

2.1 2.5 3.2 mA

finIF = 2000 MHz

*1

I

Power supply current

CCRF

PSIF PSIF = PSRF = “L”  0.1

I

V

CCRF = 3.0 V

5.7 6.5 8.4 mA

finRF = 2500 MHz

*1

I

Power saving current

IPSRF PSIF = PSRF = “L”  0.1

*3

fin

Operating frequency

fin

IF

RF

finIF IF PLL 200  2000 MHz

*3

finRF RF PLL 2000  4000 MHz

OSCIN fOSC  3  40 MHz

IF PfinIF IF PLL, 50 Ω system −15 +2dBm

fin

Input sensitivity

fin

RF PfinRF RF PLL, 50 Ω system −10 +2dBm

Input available voltage OSCIN VOSC  0.5 1.0 1.5 VP-P

Value

*2

*2

Unit

10 µA
10 µA

“H” level input voltage

Data

VIH Schmitt trigger input

0.7 VCC

+ 0.4

V

LE

“L” level input voltage V
“H” level input voltage

“L” level input voltage VIL 0.3 VCC V
“H” level input current

Clock

PS

IF

PSRF
Data

IL Schmitt trigger input 

VIH  0.7 VCC V

*4

IH

I

−1.0 +1.0 µA

0.3 VCC

− 0.4

LE

“L” level input current I
“H” level output voltage

“L” level output voltage VOL VCC = 3.0 V, IOL = 1 mA 0.4 V
“H” level output voltage
“L” level output voltage V
High impedance cutoff

current
“H” level output current
“L” level output current I

“H” level output current

Clock
PS

LD/
fout

IF

Do
DoRF

DoIF
DoRF

LD/
fout

Do

IF

DoRF

*8

*4

IL

OH VCC = 3.0 V, IOH = −1 mA VCC − 0.4 V

V

−1.0 +1.0 µA

VDOH VCC = 3.0 V, IDOH = −0.5 mA VCC − 0.4 V

DOL VCC = 3.0 V, IDOL = 0.5 mA 0.4 V

IOFF

I

OH

IDOH *

VCC = 3.0 V
V

OFF = 0.5 V to VCC − 0.5 V

*4

VCC = 3.0 V −1.0 mA

OL VCC = 3.0 V 1.0 mA

VCC = 3.0 V,

4

V

DOH = VCC / 2,

Ta = +25 °C

CS bit = “1” −8.2 −6.0 −4.1 mA
CS bit = “0” −2.2 −1.5 −0.8 mA

2.5 nA

V

“L” level output current

6

Do
DoRF

*8

IF

IDOL

VCC = 3.0 V,
V

DOL = VCC / 2,

Ta = +25 °C

CS bit = “1” 4.1 6.0 8.2 mA
CS bit = “0” 0.8 1.5 2.2 mA

(Continued)

MB15F74UV

(Continued)

(VCC = 2.7 V to 3.6 V, Ta = −40 °C to +85 °C)

Parameter Symbol Condition

Min Typ Max

*5

VDO = VCC / 2  310%

*6

0.5 V ≤ VDO ≤ VCC − 0.5 V  10 15 %

−40 °C ≤ Ta ≤ 85 °C,

*7

V

DO = VCC / 2

 510%

Charge pump
current rate

I

DOL/IDOH IDOMT

vs V

DO IDOVD

vs Ta IDOTA

*1 : Conditions ; fosc = 12.8 MHz, Ta = +25 °C, SW = “0” in locking state.
*2 : V

CCIF = VCCRF = 3.0 V, fosc = 12.8 MHz, Ta = +25 °C, in power saving mode.

PS

IF = PSRF = GND

V

IH = VCC, VIL = GND (at CLK, Data, LE)

*3 : AC coupling. 1000 pF capacitor is connected under the condition of Min operating frequency.
*4 : The symbol “–” (minus) means the direction of current flow.
*5 : V

CC = 3.0 V, Ta = +25 °C (||I3| − |I4||) / [ (|I3| + |I4|) / 2] × 100 (%)

*6 : V

CC = 3.0 V, Ta = +25 °C [ (||I2| − |I1||) / 2] / [ (|I1| + |I2|) / 2] × 100 (%) (Applied to both lDOL and lDOH)

*7 : VCC = 3.0 V, [||IDO (+85 °C) | − |IDO (–40 °C) || / 2] / [|IDO (+85 °C) | + |IDO (–40 °C) | / 2] × 100 (%) (Applied to both IDOL and IDOH)

Value

Unit

*8 : When Charge pump current is measured, set LDS = “0” , T1 = “0” and T2 = “1”.

I3

I2

I4

I1

IDOL

IDOH

I1

I2

0.5 VCC/2 VCC − 0.5 VCC

Charge pump output voltage (V)

7

MB15F74UV

FUNCTIONAL DESCRIPTION

■■■■

1. Pulse swallow function

fVCO = [ (P × N) + A] × fOSC ÷ R

f

VCO : Output frequency of external voltage controlled oscillator (VCO)

P : Preset divide ratio of dual modulus prescaler (32 or 64 for IF-PLL, 64or 128 for RF-PLL)
N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127, A < N)
f

OSC : Reference oscillation frequency (OSCIN input frequency)

R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)

2. Serial Data Input

The serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF­PLL sections, programmable reference dividers of IF/RF-PLL sections are controlled individually.
The serial data of binary data is entered through Data pin.
On rising edge of Clock, one bit of the serial data is transferred into the shift register. On a rising edge of load
enable signal, the data stored in the shift register is transf erred to one of latches depending upon the control bit
data setting.

The programmable

reference counter

for the IF-PLL

CN1 0 1 0 1
CN2 0 0 1 1

Shift Register Configuration

(1)

•

Programmable Reference Counter

(LSB)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS X X X X

CS : Charge pump current select bit
R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383)
T1, T2 : LD/fout output setting bit
CN1, CN2 : Control bit
X : Dummy bits (Set “0” or “1”)

The programmable

reference counter

for the RF-PLL

The programmable

counter and the swallow

counter for the IF-PLL

The programmable

counter and the swallow

counter for the RF-PLL

(MSB)Data Flow

Note : Data input with MSB first.

8

MB15F74UV

• Programmable Counter

(LSB)

1 2 3 4 5 6 7 8 9 101112131415161718192021 22 23

SW

IF/

CN1 CN2 LDS

SW

RF

FCIF/
FC

RF

A1 A2 A3 A4 A5 A6 A7

A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)
N1 to N11 : Divide ratio setting bits for the programmable counter (3 to 2,047)
LDS : LD/fout signal select bit
SW

IF/SWRF : Divide ratio setting bit for the prescaler (IF : SWIF, RF : SWRF)

FCIF/FCRF : Phase control bit for the phase detector (IF : FCIF, RF : FCRF)
CN1, CN2 : Control bit

Note : Data input with MSB first.

Data Flow

(MSB)

N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11

(2) Data setting

Binary 14-bit Programmable Reference Counter Data Setting

•

Divide ratio R14R13R12R11R10R9R8R7R6R5R4R3R2R1

3 00000000000011
4

•

•

•

16383

0

0

0

0

0

0

0

0

0

0

0

1

0

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

1

1

1

1

1

1

1

1

1

1

1

1

1

Note : Divide ratio less than 3 is prohibited.

•

Binary 11-bit Programmable Counter Data Setting

Divide ratioN11N10N9N8N7N6N5N4N3N2N1

3 00000000011
4

•

•

•

2047

0

0

0

0

0

0

0

0

1

0

0

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

1

1

1

1

1

1

1

1

1

1

1

Note : Divide ratio less than 3 is prohibited

•

Binary 7-bit Swallow Counter Data Setting

Divide ratioA7A6A5A4A3A2A1

0 0000000
1

•

•

•

127

0

0

0

0

0

0

1

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

1

1

1

1

1

1

1

0

•

•

•

1

9

MB15F74UV

• Prescaler Data Setting

Divide ratio SW

====

“1” SW

Prescaler divide ratio IF-PLL 32/33 64/65
Prescaler divide ratio RF-PLL 64/65 128/129

• Charge Pump Current Setting

Current value CS

±6.0 mA 1
±1.5 mA 0

•

LD/fout output Selectable Bit Setting

LD/fout pin state LDS T1 T2

000

LD output

010
011

====

“0”

IF 100

fr

fout

output

frRF 110
fp

IF 101

fp

RF 111

• Phase Comparator Phase Switching Data Setting

====

IF, RF

FC

“1” FCIF, RF

Phase comparator input

IF

RF

, Do

Do

fr > fp H L
fr < fp L H
fr = fp Z Z

Z

: High-impedance

Depending upon the VCO and LPF polarity, FC bit should be set.

(1) VCO polarity FC = “1”
(2) VCO polarity FC = “0”

VCO Output

Frequency

====

DoIF, Do

High

“0”

RF

(1)

Note : Give attention to the polarity for using active type LPF.

10

LPF Output voltage

(2)

Max

MB15F74UV

3. Power Saving Mode (Intermittent Mode Control Circuit)

Status PS pin

Normal mode
Power saving mode

The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the po wer saving mode, reducing the current consumption. See

the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.

When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is
because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr)
which can cause a major change in the comparaor output, resulting in a VCO frequency jump and an increase
in lockup time.

H

L

To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error
signal from the phase detector when it returns to normal operation.

Notes : • When power (VCC) is first applied, the device must be in standby mode.

• PS pin must be set “L” at Power-ON.

ONOFF

VCC

Clock
Data
LE

PS

(1) (2) (3)

tV ≥ 1 µs

tPS ≥ 100 ns

(1) PS = L (power saving mode) at Power-ON
(2) Set serial data at least 1 µs after the power supply becomes stable (V
(3) Release power saving mode (PS

IF, PSRF : “L” → “H”) at least 100 ns later after setting serial data.

CC ≥ 2.2 V) .

11

MB15F74UV

4. Serial Data Data Input Timing

Divide ratio is performed through a serial interface using the Data pin, Clock pin, and LE pin.
Setting data is read into the shift register at the rise of the Clock signal, and transferred to a latch at the rise of
the LE signal. The following diagram shows the data input timing.

1st data 2nd data

Invalid data

t6

t4 t5

Data

Clock

LE

Control bit

LSBMSB

t1 t2 t3

t7

Parameter Min Typ Max Unit Parameter Min Typ Max Unit

t

1 20  ns t5 100  ns

t

2 20  ns t6 20  ns

t

3 30  ns t7 100  ns

12

t

4 30  ns

Note : LE should be “L” when the data is transferred into the shift register.

PHASE COMPARATOR OUTPUT WAVEFORM

■■■■

frIF/RF

fpIF/RF

tWU tWL

LD

(FC bit = “1”)

DoIF/RF

Z

H

MB15F74UV

L

(FC bit = “0”)

DoIF/RF

Z

L

H

• LD Output Logic

IF-PLL section RF-PLL section LD output

Locking state/Power saving state Locking state/Power saving state H
Locking state/Power saving state Unlocking state L
Unlocking state Locking state/Power saving state L
Unlocking state Unlocking state L

Notes : • Phase error detection range = −2π to +2π

• Pulses on Do

• LD output becomes low when phase error is t

• LD output becomes high when phase error is t

• t

WU and tWL depend on OSCIN input frequency as follows.

t

WU ≥ 2/fosc : e.g. tWU ≥ 156.3 ns when fosc = 12.8 MHz

t

WU ≤ 4/fosc : e.g. tWL ≤ 312.5 ns when fosc = 12.8 MHz

IF/RF signals during locking state are output to prevent dead zone.

WU or more.

WL or less and continues to be so for three cycles or more.

13

MB15F74UV

TEST CIRCUIT (for Measuring Input Sensitivity fin/OSC

■■■■

S.G.

1000 pF

Controller

(divide ratio setting)

50 Ω

IN

OSC

S.G.

1000 pF

50 Ω

VCCIF

GND

finIF

XfinIF

1000 pF

GNDIF

VCCIF

Do

1

2

3

MB15F74UV

4

5

IF

S.G.

IN

)

15161718

14

13

12

11

109876

1000 pF

50 Ω

LEDataClock

finRF

XfinRF

GNDRF

V

CCRF

DoRF

VCCRF

0.1 µF

1000 pF

0.1 µF

PS

IF

LD/
fout

PSRF

Oscilloscope

14

TYPICAL CHARACTERISTICS

■■■■

1.

fin input sensitivity

MB15F74UV

RF-PLL input sensitivity vs. Input frequency

10

0

Catalog guaranteed range

−10

−20

PfinRF [dBm]

−30

−40

−50

1500 2000 2500 3000 3500 4000 4500 5000

finRF [MHz]

IF-PLL input sensitivity vs. Input frequency

10

0

−10

−20

PfinIF [dBm]

−30

Catalog guaranteed range

Ta = +25 C

VCC = 2.7 V
V

CC = 3.0 V

V

CC = 3.6 V

SPEC

Ta = +25 C

VCC = 2.7 V
V

CC = 3.0 V

V

CC = 3.6 V

SPEC

−40

−50

0 500 1000 1500 2000 2500 3000

finIF [MHz]

15

MB15F74UV

2.

OSCIN input sensitivity

10

Catalog guaranteed
range

0

−10

−20

−30

−40

Input sensitivity VOSC (dBm)

−50
0 20 40 80 100 140 160

Input sensitivity vs. Input frequency

60 120

VCC = 2.7 V
V

CC = 3.0 V

V

CC = 3.6 V

SPEC

Input

frequency fOSC (MHz)

16

3. RF/IF-PLL Do output current

• 1.5 mA mode

MB15F74UV

IDO − VDO

• 6.0 mA mode

2.50

2.00

1.50

1.00

0.50

0.00

−0.50

−1.00

−1.50

−2.00

−2.50

Charge pump output current IDO (mA)

VCC = 2.7 V, Ta = +25 C

0.5 2.51.5

1.0 3.00.0 2.0

Charge pump output voltage VDO (V)

DO − VDO

I

8.00

6.00

4.00

2.00

0.00

−2.00

−4.00

−6.00

−8.00

Charge pump output current IDO (mA)

VCC = 2.7 V, Ta = +25 C

0.5 2.51.5

1.0 3.00.0 2.0

Charge pump output voltage VDO (V)

17

MB15F74UV

4.

fin input impedance

finIF input impedance

4 : 30.266 Ω

START 100.000 000 MHz STOP 2 000.000 000 MHz

RF input impedance

fin

−102.92 Ω

4

3

2 000.000 000 MHz

2

1

1

:

−

2

:

−

3

:

773.21 fF

494.28

874.84
200 MHz

58.094

216.47
1 GHz

39.773

148

−

1.5 GHz

Ω
Ω

Ω
Ω

Ω
Ω

4

: 20.93 Ω−39.352 Ω

4

1

2

3

START 2 000.000 000 MHz STOP 4 000.000 000 MHz

1.0111 pF

4 000.000 000 MHz

37.563

1

:

109.96

−

2 GHz

26.125

2

:

71.227

−

3 GHz

22.848

3

:

54.025

−

3.5 GHz

Ω
Ω

Ω
Ω

Ω
Ω

18

MB15F74UV

5. OSC

IN

input impedance

OSCIN input impedance

4

: 278.69 Ω−1.0537 kΩ

3.7761 pF

40.000 000 MHz

2.25 k

1

:

2.2373 k

−

10 MHz

881.62

2

:

1.8299 k

−

20 MHz

448.75

3

:

1.353 k

−

4
1

2

3

30 MHz

Ω
Ω

Ω
Ω

Ω
Ω

START 3.000 000 MHz STOP 40.000 000 MHz

19

MB15F74UV

REFERENCE INFORMATION

■■■■

(for Lock-up Time, Phase Noise and Reference Leakage)

Test Circuit

S.G.

Spectrum

Analyzer

OSC

fin

IN

Do

VCO

LPF

f

VCO = 2113.6 MHz

KV = 50 MHz/V
fr = 50 kHz
f

OSC = 19.2 MHz

LPF

0.01

F

CC = 3.0 V

V
Ta = + 25 °C
CP : 6 mA mode

7.5 k

Ω

1.6 kΩ

0.1

3300 pF

F

To VCO

• PLL Reference Leakage

• PLL Phase Noise

ATTEN 10 dB
RL 0 dBm

∆MKR

50.0 kHz

−80.83 dB

CENTER 2.1136000 GHz

∗

RBW 1.0 kHz VBW 1.0 kHz

ATTEN 10 dB
RL 0 dBm

VAVG 16

10 dB/

VAVG 16

10 dB/

∆MKR −80.83 dB

50.0 kHz

SPAN 200.0 kHz

SWP 500 ms

∆MKR −65.34 dB/Hz

1.00 kHz

20

∆MKR

1.00 kHz

−65.34 dB/Hz

CENTER 2.11360000 GHz

∗

RBW 30 Hz VBW 30 Hz

SPAN 10.00 kHz

SWP 1.92 s

(Continued)

(Continued)

MB15F74UV

PLL Lock Up time

2113.6 MHz→2173.6 MHz within ± 1 kHz
L ch→H ch 1.47 ms

A Mkr x: 439.99764 µs

y: 50.0009 MHz

2.173604000 GHz

2.173600000 GHz

2.173596000 GHz

2173.6 MHz→2113.6 MHz within ± 1 kHz
H ch→L ch 1.56 ms

A Mkr x: 400.00146 µs

y: −50.0013 MHz

2.113604000 GHz

2.113600000 GHz

2.113596000 GHz

-500 µs

-500 µs

2.000 ms

500 µs/div

PLL Lock Up time

2.000 ms

500 µs/div

4.500 ms

4.500 ms

21

MB15F74UV

APPLICATION EXAMPLE

■■■■

OUTPUT

VCO

LPF

TCXO

VCCIF

0.1 µF

1000 pF

1000 pF

1000 pF

GND

finIF

XfinIF

GNDIF

VCCIF

Do

Controller

(divide ratio setting)

IN

OSC

1

2

3

MB15F74UV

4

5

IF

LD/

IF

PS

fout

LEDataClock

PSRF

15161718

14

13

12

11

109876

finRF

XfinRF

GNDRF

V

CCRF

DoRF

1000 pF

1000 pF

VCCRF

0.1 µF

OUTPUT

VCO

LPF

Lock Detect

Note : Clock, Data, LE : The schmitt trigger circuit is provided (insert a pull-down or pull-up registor

to prevent oscillation when open-circuit in the input) .

22

MB15F74UV

USAGE PRECAUTIONS

■■■■

(1) VCCRF and VCCIF must be equal voltage.

Even if either RF-PLL or IF-PLL is not used, power must be supplied to V

equal. It is recommended that the non-use PLL is controlled by power saving function.
(2) To protect against damage by electrostatic discharge, note the following handling precautions :

• Store and transport devices in conductive containers.

• Use properly grounded workstations, tools, and equipment.

• Turn off power before inserting or removing this device into or from a socket.

• Protect leads with conductive sheet, when transporting a board mounted device

ORDERING INFORMATION

■■■■

Part number Package Remarks

MB15F74UVPVB

18-pin plastic BCC

(LCC-18P-M05)

CCRF and VCCIF to keep them

23

MB15F74UV

PACKAGE DIMENSION

■■■■

18-pin plastic BCC

(LCC-18P-M05)

2.70±0.10

15 10

(.106±.004)

0.45±0.05

(.018±.002)

(Mount height)

2.31(.090)
TYP

0.45(.018)
TYP.

1510

INDEX AREA

0.05(.002)

C

2003 FUJITSU LIMITED C18058S-c-1-1

2.40±0.10

(.094±.004)

61

0.14(.006)
MIN.

0.075±0.025
(.003±.001)

(Stand off)

0.25±0.06

(.010±.002)

0.25±0.06

(.010±.002)

2.01(.079)
TYP

0.45(.018)
TYP.

Details of "B" part Details of "C" partDetails of "A" part

C0.10(.004)

"C"

6

Dimensions in mm (inches

:

Note

The values in parentheses are reference values.

"A"

1.35(.053)
REF

2.28(.090)
REF

0.36±0.06

(.014±.002)

0.28±0.06

(.011±.002)

)

0.90(.035)

"B"

1

REF

0.36±0.06

(.014±.002)

0.28±0.06

(.011±.002)

1.90(.075)
REF

24

MB15F74UV

FUJITSU LIMITED

All Rights Reserved.

The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.

F0401

 FUJITSU LIMITED Printed in Japan