Fujitsu MB15F74UV User Manual

FUJITSU SEMICONDUCTOR

DATA SHEET

ASSP

DS04-21381-1E

Dual S

PLL Frequency

erial Input

Synthesizer

MB15F74UV

DESCRIPTION

■■■■

The Fujitsu MB15F74UV is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 4000 MHz and a 2000 MHz prescalers. A 64/65 or a 128/129 for the 4000 MHz prescaler, and a 32/33 or a 64/65 for the 2000 MHz prescaler can be selected for the prescaler that enables pulse swallow operation.

The BiCMOS process is used, as a result a supply current is typically 9.0 mA at 3.0 V. The supply voltage range is from 2.7 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA selectable by serial date. The serial data format is the same as MB15F74UL. F ast locking is achie ved f or adopting the new circuit.

MB15F74UV is in the small package (BCC18) which decreases a mount area of MB15F74UV about 50% comparing with the former BCC20 (for dual PLL) .

FEATURES

■■■■

• High frequency operation : RF synthesizer : 4000 MHz Max : IF synthesizer : 2000 MHz Max

• Low power supply voltage : VCC = 2.7 V to 3.6 V

• Ultra low power supply current : I

PACKAGE

■■■■

CC = 9.0 mA Typ

(VCC = 3.0 V, Ta = +25 °C, SWIF = SWRF = 0 in IF/RF locking state)

(Continued)

18-pin plastic BCC

(LCC-18P-M05)

MB15F74UV

(Continued)

• Direct power saving function : Power supply current in power saving mode Typ 0.1 µA (V

Max 10 µA (VCC = 3.0 V at 1 system)

• Software selectable charge pump current : 1.5 mA/6.0 mA Typ

• Dual modulus prescaler : 4000 MHz prescaler (64/65 or128/129) /2000 MHz prescaler (32/33 or 64/65)

• 23 bit shift register

• Serial input binary 14-bit programmable reference divider : R = 3 to 16,383

• Serial input programmable divider consisting of:

- Binary 7-bit swallow counter : 0 to 127

- Binary 11-bit programmable counter : 3 to 2,047

• Built-in high-speed tuning, low-noise phase comparator, current-switching type constant current circuit

• On-chip phase control for phase comparator

• On-chip phase comparator for fast lock and low noise

• Built-in digital locking detector circuit to detect PLL locking and unlocking

• Operating temperature : Ta = −40 °C to +85 °C

• Serial data format compatible with MB15F74UL

• Ultra small package BCC18 (2.4 mm × 2.7 mm × 0.45 mm)

CC = 3.0 V, Ta = +25 °C at 1 system)

PIN ASSIGNMENTS

■■■■

GND

fin

XfinIF

GNDIF

VCCIF

DOIF

TOP VIEW

Clock

OSC

18 17

1 2

3 4 5

789

IF PSRF

LD/fout

(LCC-18P-M05)

Data 16

14 13 12 11 10

LE fin

XfinRF GNDRF VCCRF

DORF

PIN DESCRIPTION

■■■■

MB15F74UV

Pin no.

name

I/O Descriptions

1GND Ground pin for OSC input buffer and the shift register circuit. 2fin

3Xfin

IF I

Prescaler input pin for the IF-PLL. Connection to an external VCO should be AC coupling.

Prescaler complimentary input for the IF-PLL section. This pin should be grounded via a capacitor.

4GNDIF  Ground pin for the IF-PLL section. 5V 6Do

CCIF 

IF O Charge pump output for the IF-PLL section.

Power supply voltage input pin for the IF-PLL section, the shift register and the oscillator input buffer.

Power saving mode control pin for the IF-PLL section. This pin must be set at “L” when

7PSIF I

the power supply is started up. (Open is prohibited.) PS

IF = “H” ; Normal mode/PSIF = “L” ; Power saving mode

Lock detect signal output (LD) /phase comparator monitoring output (fout) pin. The out-

8 LD/fout O

put signal is selected by LDS bit in a serial data. LDS bit = “H” ; outputs fout signal/LDS bit = “L” ; outputs LD signal

Power saving mode control for the RF-PLL section. This pin must be set at “L” when the

9PS

RF I

power supply is started up. (Open is prohibited. ) PS

RF = “H” ; Normal mode/PSRF = “L” ; Power saving mode

10 DoRF O Charge pump output for the RF-PLL section. 11 V 12 GND

13 Xfin

CCRF  Power supply voltage input pin for the RF-PLL section.

RF  Ground pin for the RF-PLL section

RF I

14 finRF I

15 LE I

16 Data I

17 Clock I

18 OSC

IN I

Prescaler complimentary input pin for the RF-PLL section. This pin should be grounded via a capacitor.

Prescaler input pin for the RF-PLL. Connection to an external VCO should be via AC coupling.

Load enable signal input pin (with the schmitt trigger circuit) When LE is set “H”, data in the shift register is transferred to the corresponding latch according to the control bit in a serial data.

Serial data input pin (with the schmitt trigger circuit) Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter, RF-ref. counter, RF-prog. counter) according to the control bit in a serial data.

Clock input pin for the 23-bit shift register (with the schmitt trigger circuit) One bit data is shifted into the shift register on a rising edge of the clock.

The programmable reference divider input pin. TCXO should be connected with an AC coupling capacitor.

MB15F74UV

BLOCK DIAGRAM

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PSIF

finIF

XfinIF

OSCIN

finRF

XfinRF

(7)

(2)

(3)

(18)

(14)

( )

Intermittent

mode control

(IF-PLL)

Prescaler

(IF-PLL)

(32/33, 64/65)

Prescaler

(RF-PLL)

(64/65, 128/129)

3 bit latch

LDS

SWIF

7 bit latch 11 bit latch

Binary 7-bit

swallow counter

FCIF

(IF-PLL)

Binary 11-bit

programmable

counter (IF-PLL)

2 bit latch 14 bit latch 1 bit latch

T1 T2

Binary 14-bit pro-

grammable ref. counter(IF-PLL)

C/P setting

counter

frIF

frRF

T1 T2

Binary 14-bit pro-

grammable ref.

counter (RF-PLL))

C/P setting

counter

2 bit latch 14 bit latch 1 bit latch

VCCIF GNDIF

(5)

fpIF

fpRF

Phase comp.

(IF-PLL)

(4)

Fast lock

Tuning

Lock Det.

(IF-PLL)

LDIF

AND

Lock Det.

(RF-PLL)

Charge

pump

(IF-PLL)

Current

Switch

(6)

DoIF

Fast lock

Tuning

Selector

LD frIF

(8)

frRF fpIF

LD/ fout

fpRF

PSRF

(9)

(15)

Intermittent

mode control

(RF-PLL)

Schmitt

trigger

circuit

LDS

3 bit latch

Latch selector

Binary 7-bit

swallow counter

FCRF

SWRF

(RF-PLL)

Binary 11-bit

programmable

counter (RF-PLL)

Phase comp.

(RF-PLL)

fpRF

7 bit latch 11 bit latch

Tuning

Fast lock

Charge

pump

(RF-PLL)

Current

Switch

(10)

DoRF

Schmitt

Data Clock

(16)

(17)

trigger

circuit

Schmitt

trigger

23-bit shift register

circuit

(1)

GND

(11) (12)

CCRF

GNDRF

ABSOLUTE MAXIMUM RATINGS

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MB15F74UV

Parameter Symbol

Unit

Min Max

Rating

Power supply voltage V Input voltage V

LD/fout V

CC −0.5 4.0 V

I −0.5 VCC + 0.5 V

O GND VCC V

Output voltage

DoIF, DoRF VDO GND VCC V

Storage temperature Tstg −55 +125 °C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

RECOMMENDED OPERATING CONDITIONS

■■■■

Value

Parameter Symbol

Unit Remarks

Min Typ Max

Power supply voltage V

CC 2.7 3.0 3.6 V VCCRF = VCCIF

Input voltage VI GND  VCC V Operating temperature Ta −40 +85 °C

Note : • VCCRF and VCCIF must supply equal voltage.

Even if either RF-PLL or IF-PLL is not used, power must be supplied to V

CCRF and VCCIF to keep them

equal. It is recommended that the non-use PLL is controlled by power saving function.

• Although this device contains an anti-static element to prevent electrostatic breakdown and the circuitry has been improved in electrostatic protection, observe the f ollowing precautions when handling the device .

• When storing and transporting the device, put it in a conductive case.

• Before handling the device, confirm the (jigs and) tools to be used have been uncharged (grounded) as well as yourself. Use a conductive sheet on working bench.

• Before fitting the device into or removing it from the socket, turn the power supply off.

• When handling (such as transporting) the device mounted board, protect the leads with a conductive sheet.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.

MB15F74UV

ELECTRICAL CHARACTERISTICS

■■■■

(VCC = 2.7 V to 3.6 V, Ta = −40 °C to +85 °C)

Parameter Symbol Condition

Min Typ Max

CCIF

CCIF = 3.0 V

2.1 2.5 3.2 mA

finIF = 2000 MHz

Power supply current

CCRF

PSIF PSIF = PSRF = “L”  0.1

CCRF = 3.0 V

5.7 6.5 8.4 mA

finRF = 2500 MHz

Power saving current

IPSRF PSIF = PSRF = “L”  0.1

fin

Operating frequency

fin

finIF IF PLL 200  2000 MHz

finRF RF PLL 2000  4000 MHz

OSCIN fOSC  3  40 MHz

IF PfinIF IF PLL, 50 Ω system −15 +2dBm

fin

Input sensitivity

fin

RF PfinRF RF PLL, 50 Ω system −10 +2dBm

Input available voltage OSCIN VOSC  0.5 1.0 1.5 VP-P

Value

Unit

10 µA 10 µA

“H” level input voltage

Data

VIH Schmitt trigger input

0.7 VCC

+ 0.4

V

“L” level input voltage V “H” level input voltage

“L” level input voltage VIL 0.3 VCC V “H” level input current

Clock

PSRF Data

IL Schmitt trigger input 

VIH  0.7 VCC V

−1.0 +1.0 µA

0.3 VCC

− 0.4

“L” level input current I “H” level output voltage

“L” level output voltage VOL VCC = 3.0 V, IOL = 1 mA 0.4 V “H” level output voltage “L” level output voltage V High impedance cutoff

current “H” level output current “L” level output current I

“H” level output current

Clock PS

LD/ fout

Do DoRF

DoIF DoRF

LD/ fout

DoRF

OH VCC = 3.0 V, IOH = −1 mA VCC − 0.4 V

−1.0 +1.0 µA

VDOH VCC = 3.0 V, IDOH = −0.5 mA VCC − 0.4 V

DOL VCC = 3.0 V, IDOL = 0.5 mA 0.4 V

IOFF

IDOH *

VCC = 3.0 V V

OFF = 0.5 V to VCC − 0.5 V

VCC = 3.0 V −1.0 mA

OL VCC = 3.0 V 1.0 mA

VCC = 3.0 V,

DOH = VCC / 2,

Ta = +25 °C

CS bit = “1” −8.2 −6.0 −4.1 mA CS bit = “0” −2.2 −1.5 −0.8 mA

2.5 nA

“L” level output current

Do DoRF

IDOL

VCC = 3.0 V, V

DOL = VCC / 2,

Ta = +25 °C

CS bit = “1” 4.1 6.0 8.2 mA CS bit = “0” 0.8 1.5 2.2 mA

(Continued)

MB15F74UV

(Continued)

(VCC = 2.7 V to 3.6 V, Ta = −40 °C to +85 °C)

Parameter Symbol Condition

Min Typ Max

VDO = VCC / 2  310%

0.5 V ≤ VDO ≤ VCC − 0.5 V  10 15 %

−40 °C ≤ Ta ≤ 85 °C,

DO = VCC / 2

 510%

Charge pump current rate

DOL/IDOH IDOMT

vs V

DO IDOVD

vs Ta IDOTA

*1 : Conditions ; fosc = 12.8 MHz, Ta = +25 °C, SW = “0” in locking state. *2 : V

CCIF = VCCRF = 3.0 V, fosc = 12.8 MHz, Ta = +25 °C, in power saving mode.

IF = PSRF = GND

IH = VCC, VIL = GND (at CLK, Data, LE)

*3 : AC coupling. 1000 pF capacitor is connected under the condition of Min operating frequency. *4 : The symbol “–” (minus) means the direction of current flow. *5 : V

CC = 3.0 V, Ta = +25 °C (||I3| − |I4||) / [ (|I3| + |I4|) / 2] × 100 (%)

*6 : V

CC = 3.0 V, Ta = +25 °C [ (||I2| − |I1||) / 2] / [ (|I1| + |I2|) / 2] × 100 (%) (Applied to both lDOL and lDOH)

*7 : VCC = 3.0 V, [||IDO (+85 °C) | − |IDO (–40 °C) || / 2] / [|IDO (+85 °C) | + |IDO (–40 °C) | / 2] × 100 (%) (Applied to both IDOL and IDOH)

Value

Unit

*8 : When Charge pump current is measured, set LDS = “0” , T1 = “0” and T2 = “1”.

IDOL

IDOH

0.5 VCC/2 VCC − 0.5 VCC

Charge pump output voltage (V)

MB15F74UV

FUNCTIONAL DESCRIPTION

■■■■

1. Pulse swallow function

fVCO = [ (P × N) + A] × fOSC ÷ R

VCO : Output frequency of external voltage controlled oscillator (VCO)

P : Preset divide ratio of dual modulus prescaler (32 or 64 for IF-PLL, 64or 128 for RF-PLL) N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047) A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127, A < N) f

OSC : Reference oscillation frequency (OSCIN input frequency)

R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)

2. Serial Data Input

The serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RFPLL sections, programmable reference dividers of IF/RF-PLL sections are controlled individually. The serial data of binary data is entered through Data pin. On rising edge of Clock, one bit of the serial data is transferred into the shift register. On a rising edge of load enable signal, the data stored in the shift register is transf erred to one of latches depending upon the control bit data setting.

The programmable

reference counter

for the IF-PLL

CN1 0 1 0 1 CN2 0 0 1 1

Shift Register Configuration

(1)

•

Programmable Reference Counter

(LSB)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS X X X X

CS : Charge pump current select bit R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383) T1, T2 : LD/fout output setting bit CN1, CN2 : Control bit X : Dummy bits (Set “0” or “1”)

The programmable

reference counter

for the RF-PLL

The programmable

counter and the swallow

counter for the IF-PLL

The programmable

counter and the swallow

counter for the RF-PLL

(MSB)Data Flow

Note : Data input with MSB first.

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