Fujitsu MB15F74UL User Manual

FUJITSU SEMICONDUCTOR

DATA SHEET

ASSP

DS04-21374-1E

Dual S

PLL Frequency

erial Input

Synthesizer

MB15F74UL

DESCRIPTION

■

The Fujitsu MB15F74UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 4000 MHz and
a 2000 MHz prescalers. A 64/65 or a 128/129 for the 4000 MHz prescaler, and a 32/33 or a 64/65 for the
2000 MHz prescaler can be selected for the prescaler that enables pulse swallow operation.

The BiCMOS process is used, as a result a supply current is typically 9.0 mA at 3.0 V. The supply voltage range
is from 2.7 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA
selectable by serial date. The pin assignments are the same as MB15F78UL. F ast locking is achie ved f or adopting
the new circuit.

The new package (BCC20) decreases a mount area of MB15F74UL more than 30% comparing with the former
BCC16 (for dual PLL) .

FEATURES

■

• High frequency operation : RF synthesizer : 4000 MHz Max
: IF synthesizer : 2000 MHz Max

• Low power supply voltage : VCC = 2.7 to 3.6 V

• Ultra low power supply current : I

PACKAGE

■

CC = 9.0 mA Typ

(VCC = Vp = 3.0 V, Ta = +25 °C, SWIF = SWRF = 0 in IF/RF locking state)

(Continued)

20-pad plastic BCC

(LCC-20P-M05)

MB15F74UL

(Continued)

• Direct power saving function : Power supply current in power saving mode
Typ 0.1 µA (V

Max 10 µA (VCC = Vp = 3.0 V)

• Software selectable charge pump current : 1.5 mA/6.0 mA Typ

• Dual modulus prescaler : 4000 MHz prescaler (64/65 or128/129) /2000 MHz prescaler (32/33 or 64/65)

• 23 bit shift register

• Serial input binary 14-bit programmable reference divider : R = 3 to 16,383

• Serial input programmable divider consisting of:

- Binary 7-bit swallow counter : 0 to 127

- Binary 11-bit programmable counter : 3 to 2,047

• Built-in high-speed tuning, low-noise phase comparator, current-switching type constant current circuit

• On-chip phase control for phase comparator

• On-chip phase comparator for fast lock and low noise

• Built-in digital locking detector circuit to detect PLL locking and unlocking

• Operating temperature : Ta = −40 °C to +85 °C

PIN ASSIGNMENTS

■

CC = Vp = 3.0 V, Ta = +25 °C)

finIF

XfinIF

GNDIF

VCCIF

PSIF

VpIF

(BCC-20)

TOP VIEW

OSC

GND

1
2

3
4
5

6

IN Data

Clock

20 19 18 17

78910

Do

IF DoRF

LD/fout VpRF

(LCC-20P-M05)

16
15

14
13
12

11

LE
fin

RF

XfinRF
GNDRF
VCCRF

PSRF

2

PIN DESCRIPTION

■

MB15F74UL

Pin no.

1fin

2Xfin
3GND
4VCCIF 

Pin

name

I/O Descriptions

IF I

IF I

IF  Ground pin for the IF-PLL section.

Prescaler input pin for the IF-PLL.
Connection to an external VCO should be AC coupling.

Prescaler complimentary input for the IF-PLL section.
This pin should be grounded via a capacitor.

Power supply voltage input pin for the IF-PLL section (except for the charge pump
circuit) , the shift register and the oscillator input buffer.

Power saving mode control pin for the IF-PLL section. This pin must be set at “L” when

5PS

6Vp

IF I

IF  Power supply voltage input pin for the IF-PLL charge pump.

the power supply is started up. (Open is prohibited.)
PS

IF = “H” ; Normal mode/PSIF = “L” ; Power saving mode

7DoIF O Charge pump output for the IF-PLL section.

Lock detect signal output (LD) /phase comparator monitoring output (fout) pin. The

8 LD/fout O

output signal is selected by LDS bit in a serial data.
LDS bit = “H” ; outputs fout signal/LDS bit = “L” ; outputs LD signal

9Do

RF O Charge pump output for the RF-PLL section.

10 VpRF  Power supply voltage input pin for the RF-PLL charge pump.

Power saving mode control for the RF-PLL section. This pin must be set at “L” when the

11 PS

RF I

power supply is started up. (Open is prohibited. )
PS

RF = “H” ; Normal mode/PSRF = “L” ; Power saving mode

12 V
13 GND

CCRF 

RF  Ground pin for the RF-PLL section

14 XfinRF I

15 fin

RF I

Power supply voltage input pin for the RF-PLL section (except for the charge pump
circuit)

Prescaler complimentary input pin for the RF-PLL section.
This pin should be grounded via a capacitor.

Prescaler input pin for the RF-PLL.
Connection to an external VCO should be via AC coupling.

Load enable signal input pin (with the schmitt trigger circuit)

16 LE I

When LE is set “H”, data in the shift register is transferred to the corresponding latch
according to the control bit in a serial data.

Serial data input pin (with the schmitt trigger circuit)

17 Data I

Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter, RF-ref.
counter, RF-prog. counter) according to the control bit in a serial data.

18 Clock I

19 OSC

IN I

Clock input pin for the 23-bit shift register (with the schmitt trigger circuit)
One bit data is shifted into the shift register on a rising edge of the clock.

The programmable reference divider input pin. TCXO should be connected with an AC
coupling capacitor.

20 GND  Ground pin for OSC input buffer and the shift register circuit.

3

MB15F74UL

BLOCK DIAGRAM

■

PSIF

finIF

XfinIF

OSCIN

finRF

XfinRF

(5)

(1)

(2)

(19)

(15)

( )

14

Intermittent

mode control

(IF-PLL)

Prescaler

(IF-PLL)

(32/33, 64/65)

OR

Prescaler

(RF-PLL)

(64/65, 128/129)

3 bit latch

LDS

SWIF

7 bit latch 11 bit latch

Binary 7-bit

swallow counter

FCIF

(IF-PLL)

Binary 11-bit

programmable

counter (IF-PLL)

2 bit latch 14 bit latch 1 bit latch

T1 T2

Binary 14-bit pro-

grammable ref.
counter(IF-PLL)

C/P setting

counter

frIF

frRF

T1 T2

Binary 14-bit pro-

grammable ref.

counter (RF-PLL))

C/P setting

counter

2 bit latch 14 bit latch 1 bit latch

VCCIF GNDIF

(4)

fpIF

fpRF

(3)

Phase
comp.

(IF-PLL)

Lock Det.

Lock Det.

(IF-PLL)

LDIF

AND

LD

RF

(RF-PLL)

VpIF
(6)

Charge

pump

(IF-PLL)

Current

Switch

Fast
lock

Tuning

Selector

LD
frIF
frRF
fpIF
fpRF

(7)

(8)

DoIF

LD/
fout

PSRF

LE

Data
Clock

(11)

(16)

(17)

(18)

Intermittent

mode control

(RF-PLL)

Schmitt

circuit

Schmitt

circuit

Schmitt

circuit

Latch selector

C

C

N

N

23-bit shift register

1

2

LDS

SWRF

3 bit latch

Binary 7-bit

swallow counter

FCRF

(RF-PLL)

7 bit latch 11 bit latch

Binary 11-bit

programmable

counter (RF-PLL)

(20)

GND

Phase
comp.

(RF-PLL)

fpRF

(12) (13) (10)

V

CCRF

GNDRF

Tuning

Fast lock

Charge

pump

(RF-PLL)

VpRF

Current

Switch

(9)

DoRF

4

ABSOLUTE MAXIMUM RATINGS

■

MB15F74UL

Parameter Symbol

Unit

Min Max

Rating

CC −0.5 4.0 V

V

Power supply voltage

Vp V

Input voltage V

I −0.5 VCC + 0.5 V

CC 4.0 V

LD/fout VO GND VCC V

Output voltage

Do

IF, DoRF VDO GND Vp V

Storage temperature Tstg −55 +125 °C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

RECOMMENDED OPERATING CONDITIONS

■

Value

Parameter Symbol

Unit Remarks

Min Typ Max

V

CC 2.7 3.0 3.6 V VCCRF = VCCIF

Power supply voltage

Vp VCC 3.0 3.6 V

Input voltage V

I GND  VCC V

Operating temperature Ta −40 +85 °C

Note : • VCCRF, VpRF, VCCIF and VpIF must supply equal voltage.

Even if either RF-PLL or IF-PLL is not used, power must be supplied to V

CCRF, VpRF, VCCIF and VpIF to keep

them equal.
It is recommended that the non-use PLL is controlled by power saving function.

• Although this device contains an anti-static element to prevent electrostatic breakdown and the circuitry
has been improved in electrostatic protection, observe the f ollowing precautions when handling the device .

• When storing and transporting the device, put it in a conductive case.

• Before handling the device, confirm the (jigs and) tools to be used hav e been uncharged (grounded) as
well as yourself. Use a conductive sheet on working bench.

• Before fitting the device into or removing it from the socket, turn the power supply off.

• When handling (such as transporting) the device mounted board, protect the leads with a conductiv e
sheet.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

5

MB15F74UL

*

ELECTRICAL CHARACTERISTICS

■

(VCC = 2.7 V to 3.6 V, Ta = −40 °C to +85 °C)

Parameter Symbol Condition

Min Typ Max

CCIF

V

CCIF = VpIF = 3.0 V

2.1 2.5 3.2 mA

finIF = 2000 MHz

*1

I

Power supply current

CCRF

PSIF PSIF = PSRF = “L”  0.1

I

V

CCRF = VpRF = 3.0 V

5.7 6.5 8.4 mA

finRF = 2500 MHz

*1

I

Power saving current

IPSRF PSIF = PSRF = “L”  0.1

*3

fin

Operating frequency

fin

IF

RF

finIF IF PLL 200  2000 MHz

*3

finRF RF PLL 2000  4000 MHz

OSCIN fOSC  3  40 MHz

IF PfinIF IF PLL, 50 Ω system −15 +2dBm

fin

Input sensitivity

fin

RF PfinRF RF PLL, 50 Ω system −10 +2dBm

Input available voltage OSCIN VOSC  0.5  VCC VP−P

Value

*2

*2

Unit

10 µA
10 µA

“H” level input voltage

Data

VIH Schmitt trigger input

0.7 VCC

+ 0.4

V

LE

“L” level input voltage V
“H” level input voltage

“L” level input voltage VIL 0.3 VCC V
“H” level input current

Clock

PS

IF

PSRF
Data

IL Schmitt trigger input 

VIH  0.7 VCC V

*4

IH

I

−1.0 +1.0 µA

0.3 VCC

− 0.4

LE

“L” level input current I

Clock
PS

“H” level input current

OSC

IN

“L” level input current IIL
“H” level output voltage
“L” level output voltage V
“H” level output voltage
“L” level output voltage V
High impedance cutoff

current
“H” level output current
“L” level output current I

LD/
fout

Do
DoRF

Do
DoRF

LD/
fout

IF

IF

*4

IL

−1.0 +1.0 µA

IIH  0 +100 µA

*4

V

OH VCC = Vp = 3.0 V, IOH = −1 mA VCC − 0.4 V
OL VCC = Vp = 3.0 V, IOL = 1 mA 0.4 V



−100  0 µA

VDOH VCC = Vp = 3.0 V, IDOH = −0.5 mA Vp − 0.4 V

DOL VCC = Vp = 3.0 V, IDOL = 0.5 mA 0.4 V

IOFF

IOH

VCC = Vp = 3.0 V
V

OFF = 0.5 V to Vp − 0.5 V

*4

VCC = Vp = 3.0 V −1.0 mA

OL VCC = Vp = 3.0 V 1.0 mA

2.5 nA

(Continued)

V

6

(Continued)

Parameter Symbol Condition

MB15F74UL

(VCC = 2.7 V to 3.6 V, Ta = −40 °C to +85 °C)

Value

Unit

Min Typ Max

“H” level output
current

“L” level output
current

Charge pump
current rate

*8

IF

Do
DoRF

*8

IF

Do
DoRF

DOL/IDOH IDOMT

I

IDOH

IDOL

vs VDO IDOVD
vs Ta I

DOTA

VCC = Vp = 3.0 V,

*4

V

DOH = Vp / 2,

Ta = +25 °C
VCC = Vp = 3.0 V,

V

DOL = Vp / 2,

Ta = +25 °C

*5

VDO = Vp / 2  310%

*6

0.5 V ≤ VDO ≤ Vp − 0.5 V  10 15 %

−40 °C ≤ Ta ≤ 85 °C,

*7

V

DO = Vp / 2

CS bit = “H” −8.2 −6.0 −4.1 mA
CS bit = “L” −2.2 −1.5 −0.8 mA
CS bit = “H” 4.1 6.0 8.2 mA
CS bit = “L” 0.8 1.5 2.2 mA

 510%

*1 : Conditions ; fosc = 12.8 MHz, Ta = +25 °C, SW = “L” in locking state.

CCIF = VpIF = VCCRF = VpRF = 3.0 V, fosc = 12.8 MHz, Ta = +25 °C, in power saving mode.

*2 : V

PS

IF = PSRF = GND

V

IH = VCC, VIL = GND (at CLK, Data, LE)

*3 : AC coupling. 1000 pF capacitor is connected under the condition of Min operating frequency.
*4 : The symbol “–” (minus) means the direction of current flow.
*5 : V

CC = Vp = 3.0 V, Ta = +25 °C (||I3| − |I4||) / [ (|I3| + |I4|) / 2] × 100 (%)

*6 : VCC = Vp = 3.0 V, Ta = +25 °C [ (||I2| − |I1||) / 2] / [ (|I1| + |I2|) / 2] × 100 (%) (Applied to both lDOL and lDOH)
*7 : V

CC = Vp = 3.0 V, [||IDO (+85 °C) | − |IDO (–40 °C) || / 2] / [|IDO (+85 °C) | + |IDO (–40 °C) | / 2] × 100 (%) (Applied to both

I

DOL and IDOH)

*8 : When Charge pump current is measured, set LDS = “L” , T1 = “L” and T2 = “H”.

I3

I2

I4

I1

IDOL

DOH

I

I1

I2

0.5 Vp/2 Vp − 0.5 Vp

Charge pump output voltage (V)

7

MB15F74UL

FUNCTIONAL DESCRIPTION

■

1. Pulse swallow function

fVCO = [ (P × N) + A] × fOSC ÷ R

f

VCO : Output frequency of external voltage controlled oscillator (VCO)

P : Preset divide ratio of dual modulus prescaler (32 or 64 for IF-PLL, 64or 128 for RF-PLL)
N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127, A < N)
f

OSC : Reference oscillation frequency (OSCIN input frequency)

R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)

2. Serial Data Input

The serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF­PLL sections, programmable reference dividers of IF/RF-PLL sections are controlled individually.
The serial data of binary data is entered through Data pin.
On rising edge of Clock, one bit of the serial data is transferred into the shift register. On a rising edge of load
enable signal, the data stored in the shift register is transf erred to one of latches depending upon the control bit
data setting.

The programmable

reference counter

for the IF-PLL

CN1 0 1 0 1
CN2 0 0 1 1

Shift Register Configuration

(1)

•

Programmable Reference Counter

(LSB)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS X X X X

CS : Charge pump current select bit
R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383)
T1, 2 : LD/fout output setting bit
CN1, 2 : Control bit
X : Dummy bits (Set “0” or “1”)

The programmable

reference counter

for the RF-PLL

The programmable

counter and the swallow

counter for the IF-PLL

The programmable

counter and the swallow

counter for the RF-PLL

(MSB)Data Flow

Note : Data input with MSB first.

8