Fujitsu MB15E07SL User Manual

FUJITSU SEMICONDUCTOR

DATA SHEET

ASSP

Single Serial Input
PLL Frequency Synthesizer
On-chip 2.5 GHz Prescaler

MB15E07SL

DESCRIPTION

■■■■

The Fujitsu MB15E07SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.5 GHz prescaler .
The 2.5 GHz prescaler has a dual modulus division ratio of 32/33 or 64/65 enabling pulse s wallowing operation.

The supply voltage range is between 2.4 V and 3.6 V. The MB15E07SL uses the latest BiCMOS process, as a
result the supply current is typically 3.5 mA at 2.7 V. A refined charge pump supplies well-balanced output currents
of 1.5 mA and 6 mA. The charge pump current is selectable by serial data.

MB15E07SL is ideally suited for wireless mobile communications, such as GSM (Global System for Mobile
Communications) and PCS.

DS04-21358-4E

FEATURES

■■■■

• High frequency operation: 2.5 GHz Max

• Low power supply voltage: VCC = 2.4 to 3.6 V

• Ultra Low power supply current:I

• Direct power saving function: Power supply current in power saving mode

PACKAGES

■■■■

16-pin plastic SSOP

(FPT-16P-M05)

CC = 3.5 mA Typ (VCC = Vp = 2.7 V, Ta = +25°C, in locking state)

ICC = 4.0 mA Typ (VCC = Vp = 3.0 V, Ta = +25°C, in locking state)

Typ 0.1 µA (V

CC = Vp = 3.0 V, Ta = +25°C), Max 10 µA (VCC = Vp = 3.0 V)

(Continued)

16-pad plastic BCC

(LCC-16P-M06)

MB15E07SL

(Continued)

• Dual modulus prescaler: 32/33 or 64/65

• Serial input 14-bit programmable reference divider: R = 3 to 16,383

• Serial input programmable divider consisting of:

- Binary 7-bit swallow counter: 0 to 127

- Binary 11-bit programmable counter: 3 to 2,047

• Software selectable charge pump current

• On-chip phase control for phase comparator

• Operating temperature: Ta = –40 to +85°C

• Pin compatible with MB15E07, MB15E07L

PIN ASSIGNMENTS

■

16-pin SSOP 16-pad BCC

OSCIN

OSCOUT

VP

VCC

DO

GND

Xfin

fin

1
2
3
4

Top view

5
6
7
8

16
15
14
13
12
11
10

9

(FPT-16P-M05)

φR
φP

LD/fout
ZC
PS
LE
Data
Clock

OSC

OUT

VP

VCC

DO

GND

Xfin

(LCC-16P-M06)

IN φR

OSC

1
2
3

Top view

4
5
678 9

fin Clock

141516
13
12
11
10

φP
LD/fout
ZC
PS
LE
Data

2

PIN DESCRIPTIONS

■

MB15E07SL

Pin no.

SSOP BCC

116OSC
21OSC
32V

Pin

name

OUT O Oscillator output.

P – Power supply voltage input for the charge pump.

I/O Descriptions

IN I Programmable reference divider input. Connection to a TCXO.

43VCC – Power supply voltage input.
54D

O O

Charge pump output.

Phase of the charge pump can be selected via programming of the FC bit.
6 5 GND – Ground.
7 6 Xfin I Prescaler complementary input, which should be grounded via a capacitor.

87finI

Prescaler input.

Connection to an external VCO should be done via AC coupling.

Clock input for the 19-bit shift register.
98ClockI

Data is shifted into the shift register on the rising edge of the clock.

(Open is prohibited.)

10 9 Data I

Serial data input using binary code.

The last bit of the data is a control bit. (Open is prohibited.)

Load enable signal input. (Open is prohibited.)

11 10 LE I

When LE is set high, the data in the shift register is transferred to a latch

according to the control bit in the serial data.

Power saving mode control. This pin must be set at “L” at Power-ON.

12 11 PS I

(Open is prohibited.)

PS = “H”; Normal mode

PS = “L”; Power saving mode

Forced high-impedance control for the charge pump (with internal pull up

13 12 ZC I

resistor.)

ZC = “H”; Normal Do output.

ZC = “L”; Do becomes high impedance.

Lock detect signal output (LD)/phase comparator monitoring output (fout).

14 13 LD/fout O

The output signal is selected via programming of the LDS bit.

LDS = “H”; outputs fout (fr/fp monitoring output)

LDS = “L”; outputs LD (“H” at locking, “L” at unlocking.)

15 14 φPO

16 15 φRO

Phase comparator N-channel open drain output for an external charge

pump. Phase can be selected via programming of the FC bit.

Phase comparator CMOS output for an external charge pump. Phase can

be selected via programming of the FC bit.

3

MB15E07SL

BLOCK DIAGRAM

■

OSCIN

OSC

V

OUT

VP

D

(16)

1

(1)

2

(2)

3

(3)

4

CC

(4)

O

5

Reference

oscillator

circuit

Charge pump

Current switch

Binary 14-bit

reference counter

14-bit latch

. .

C
N
T

19-bit shift register

. . .

7-bit latch

Binary 7-bit

swallow counter

SW FC CS

LDS

4-bit latch

. . .

11-bit latch

Binary 11-bit

programmable

counter

fr

Phase

comparator

Lock

detector

LD/fr/fp

fp

selector

Intermittent
mode control
(power save)

(15)

16

(14)

15

(13)

14

(12)

13

(11)

12

φR

φP

LD/fout

ZC

PS

(10)

11

(9)
10

(8)

98

LE

Data

Clock

GND

Xfin

fin

(5)

6

(6)

7

(7)

: SSOP

( ) : BCC

1-bit

control

latch

MD

Prescaler

32/33
64/65

4

ABSOLUTE MAXIMUM RATINGS

■

MB15E07SL

Parameter Symbol Condition

Unit Remark

Min Max

Rating

V

CC ––0.54.0V

Power supply voltage

V

P –VCC 6.0 V

Input voltage V

I ––0.5VCC +0.5 V

VO Except Do GND VCC V

Output voltage

V

O Do GND VP V

Storage temperature Tstg – –55 +125 °C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

RECOMMENDED OPERATING CONDITIONS

■

Value

Parameter Symbol

Unit Remark

Min Typ Max

V

CC 2.4 3.0 3.6 V

Power supply voltage

V

P VCC –5.5V

Input voltage VI GND – VCC V
Operating temperature Ta –40 – +85 °C

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

5

MB15E07SL

ELECTRICAL CHARACTERISTICS

■

(VCC = 2.4 to 3.6 V, Ta = –40 to +85°C)

Parameter Symbol Condition

Min Typ Max

Power supply current*

1

Power saving current I

ICC

fin = 2500 MHz, VCC = VP = 2.7 V

*1

(V

CC = VP = 3.0 V)

PS ZC = “H” or open – 0.1

–

fin fIN – 700 – 2500 MHz

Operating frequency

OSCIN OSCIN –3–40MHz

50 Ω system

*3

Input sensitivity

fin

OSC

“H” level input voltage Data,

Pfin

(Refer to the measurement

–15 – +2 dBm

circuit.)

*3

IN

VOSC –0.5–VCC Vp-p

VIH –VCC × 0.7 – –

Clock,

“L” level input voltage V

LE, PS,

IL –––VCC × 0.3

ZC

“H” level input current Data,
“L” level input current IIL

Clock,

LE, PS

“H” level input current

OSC

“L” level input current IIL

IN

“H” level input current
“L” level input current IIL

ZC

“L” level output voltage φφφφPV
“H” level output voltage
“L” level output voltage VOL VCC = VP = 3.0 V, IOL = 1 mA – – 0.4
“H” level output voltage

φφφφR,

LD/fout

Do

*4

I

IH

*4

––1.0–+1.0
––1.0–+1.0

IIH – 0 – +100

*4

*4

I

IH

*4

Pull up input –100 – 0

OL Open drain output – – 0.4 V

––100–0
––1.0–+1.0

VOH VCC = VP = 3.0 V, IOH = –1 mA VCC – 0.4 – –

V

DOH VCC = VP = 3.0 V, IDOH = –0.5 mA VP – 0.4 – –

“L” level output voltage VDOL VCC = VP = 3.0 V, IDOL = 0.5 mA – – 0.4
High impedance cutoff

current

Do I

“L” level output current φφφφPI
“H” level output current
“L” level output current IOL –1.0––

“H” level output current

φφφφR,

LD/fout

I

DOH

Do

“L” level output current IDOL

I

DOL/IDOH IDOMT

Charge pump current
rate

vs V

DO IDOVD

vs Ta IDOTA

VCC = VP = 3.0 V,

OFF

V

OFF = 0.5 V to VP – 0.5 V

OL Open drain output 1.0 – – mA

––2.5nA

IOH ––––1.0

*4

VCC = 3 V,
V

P = 3 V,

V

DO = VP/2

Ta = +25°C

*5

VDO = VP/2 –3–%

*6

0.5 V ≤ VDO ≤ VP – 0.5 V – 10 – %

*7

– 40°C ≤ Ta ≤ +85°C–10–%

CS bit = “H” – –6.0 –
CS bit = “L” – –1.5 –
CS bit = “H” – 6.0 –
CS bit = “L” – 1.5 –

Value

3.5

(4.0)

*2

Unit

–mA

10 µA

V

µA

µA

µA

V

V

mA

mA

*1 : Conditions; fosc = 12 MHz, Ta = +25°C, in locking state.

CC = VP = 3.0 V, fosc = 12.8 MHz, Ta = +25°C, in power saving mode

*2 : V

6

MB15E07SL

*3 : AC coupling. 1000 pF capacitor is connected under the condition of Min operating frequency.
*4 : The symbol “–” (minus) means direction of current flow.

CC = VP = 3.0 V, Ta = +25°C (|I3| – |I4|) / [(|I3| + |I4|) /2] × 100(%)

*5 : V
*6 : VCC = VP = 3.0 V, Ta = +25°C [(|I2| – |I1|) /2] / [(|I1| + |I2|) /2] × 100(%) (Applied to each IDOL, IDOH)

CC = VP = 3.0 V, VDO = VP/2 (|IDO(85°C) – IDO(–40°C)| /2) / (|IDO(85°C) + IDO(–40°C)| /2) × 100(%) (Applied to each IDOL, IDOH)

*7 : V

IDOL

IDOH

I1

I2

0.5

Charge Pump Output Voltage (V)

I3

I2

I4

I1

Vp/2VpVp − 0.5 V

7

MB15E07SL

FUNCTIONAL DESCRIPTION

■

1. Pulse Swallow Function

The divide ratio can be calculated using the following equation:
fVCO = [(M × N) + A] × fOSC ÷ R (A < N)

f

VCO : Output frequency of external voltage controlled oscillator (VCO)

N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
f

OSC : Output frequency of the reference frequency oscillator

R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
M : Preset divide ratio of modulus prescaler (32 or 64)

2. Serial Data Input

Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference
divider and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is taken
high, stored data is latched according to the control bit data as follows:

Table 1. Control Bit

Control bit (CNT) Destination of serial data

H For the programmable reference divider

L For the programmable divider

(1) Shift Register Configuration

Programmable Reference Counter

LSB

Data Flow

12345678910111213141516171819

C

R1R2R3R4R5R6R7R8R9R10R11R12R13R
N
T

CNT : Control bit [Table 1]
R1 to R14 : Divide ratio setting bit for the programmable reference counter (3 to 16,383) [Table 2]
SW : Divide ratio setting bit for the prescaler (32/33 or 64/65) [Table 5]
FC : Phase control bit for the phase comparator [Table 8]
LDS : LD/f
CS : Charge pump current select bit [Table 6]

OUT signal select bit [Table 7]

14 SW FC LDS CS

MSB

Note: Start data input with MSB first.

8