Fujitsu MB15C101 User Manual

FUJITSU MICROELECTRONICS

DATA SHEET

DS04-21215-3Ea

ASSP

IF Band
PLL Frequency Synthesizer

MB15C101

■ DESCRIPTION

The Fujitsu Microelectronics MB15C101 is an exclusive Int ermediate Frequency (IF) band Phase Locked Loop (PLL)
frequency synthesizer with pulse swallow operation. The r eference divider and comparison divider have fixed divide
ratios, so that it is not required to set the divide ratios by a microcontroller externally.

It operates with a supply voltage of 3.0 V typ. and dissipates 1.0 mA typ.(270MHz) of current realized through the
use of Fujitsu Microelectronics’s CMOS technology.

The MB15C101 is ideally suitable for PHS systems.

■ FEATURES

• Low power supply current: ICC = 1.0 mA typ. (VCC = 3 V, 270MHz)

• Pulse swallow function; Prescaler: 16/17

• Setting frequency (Selectable by Div input.)
– fosc = 19.2 MHz, fIF = 233.15 MHz (Div = “H”)
– fosc = 19.2 MHz, fIF = 259.20 MHz (Div = “L”)

• Lock detector

• Low power supply voltage: V

• Wide operating temperature: Ta = –40 to +85°C

■ PACKAGE

8-pin plastic SSOP

CC = 2.4 V min.

16-pad plastic BCC

1999.4

(FPT-8P-M03)

(LCC-16P-M06)

1Copyright©1999-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved

MB15C101

■ PIN ASSIGNMENT

(TOP VIEW)

N.C. N.C.

VCC

DO

GND

fin

(TOP VIEW)

1
2
3
4

(FPT-8P-M03)

■ PIN DESCRIPTIONS

Pin No.

SSOP-8BCC-

16

1,6,7,8,

–

9,14,

15,16

110V

Pin

name

N.C – No connection

16 15

DIV

fout

LD

1

2

3

4

5

6

78

N.C. N.C.

IN

OSC

8

LD

7

fout

6

DIV

5

N.C.

OSCin

N.C.

(LCC-16P-M06)

I/O Descriptions

CC – Po wer supply voltage input (2.4 V to 3.6 V).

14

13

12

11

10

N.C.

fin

GND

D

O

VCC

9

N.C.

211D

O O Charge pump output

312GND –Ground
4 13 fin I Prescaler input. Connection should be with AC coupling.

5 2 Div I

63fout O

Divide ratio switching input. Two kinds of divide ratios are
selectable by Div input “H” or “L”.

Test purpose output. This pin is an open drain output so that
should be left open usually.

Lock detector output.

74LD O

LD = H ; Lock
LD = L ; Unlock

8 5 OSCin I

Reference counter input. Connection should be with AC
coupling.

2

■ BLOCK DIAGRAM

VCC

OSCIN

Oscillator

input

buffer

Reference divider

Reference

counter

(R)

MB15C101

fr

Phase

comparator

fp

charge

pump

Do

DIV

fin

GND

Data

setting

circuit

Prescaler

16 / 17(P)

Comparison divider

Swallow

counter

(A)

Control circuit

Main

counter

(N)

Output

selector

Lock

detector

LD

fout

3

MB15C101

■ ABSOLUTE MAXIMUM RATINGS

Parameter Symbol

Unit

Min. Max.

Rating

Power supply voltage V
Input voltage V
Output voltage V
Output current I
Storage temperature T

CC –0.5 +4.0 V

I –0.5 VCC +0.5 V

OUT –0.5 VCC +0.5 V

OUT 0+5mA

STG –55 +125 °C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING CONDITIONS

Parameter Symbol

Min. Typ. Max.

Power supply voltage V
Input voltage V

CC 2.4 3.0 3.6 V

IN GND – VCC V

Operating temperature Ta –40 – +85 °C

Handling Precautions

• This device should be transported and stored in anti-static containers.

Value

Unit Note

• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel a nd equipment are
properly grounded. Cover workbenches with grounded conductive mats.

• Always turn the power supply off before inserting or removing the device from its socket.

• Protect leads with a conductive sheet when handling or transporting PC boards with devices.

4

■ ELECTRICAL CHARACTERISTICS

Parameter Symbol Condition

Power supply current I

CC

MB15C101

Recommended operating conditions unless otherwise noted.

Value

Min. Typ. Max.

PLL is locked.(270MHz)
V

CC = 3.0 V, Ta = +25°C

0.1 1.0 2.0 mA

Unit

fin fin

Operating frequency

OSC

fin Pfin

Input sensitivity

OSC

Input voltage Div

Input current Div

Input current OSC

Output voltage Do

Output current Do

High impedance cut off
current

Do I

AC coupling by 100 0 pF
capacitor

IN fosc

AC coupling by 100 0 pF
capacitor

AC coupling by 100 0 pF
capacitor

IN Vosc

V

V

I
I

IN IOSC – –100 – 100 µA

V
V

I

I

OFF 0 ≤ VDO ≤ VCC ––3nA

AC coupling by 100 0 pF
capacitor

IH –

IL –––

IH –––1.0µA
IL ––1.0––µA

OH VCC = 3.0 V, IOH=–0.3mA 2.6 – – V

OL VCC = 3.0 V, IOL= 0.3mA – – 0.4 V

VCC = 3.0 V, VOH = 2V,

OH

Ta = +25°C
VCC = 3.0 V, VOL = 1V,

OL

Ta = +25°C

50 – 270 MHz

3–26MHz

–10 – +2 dBm

0.5 – – Vpp

CC ×

V

0.7

––V

CC ×

V

0.3

V

– –6.0 – mA

–6.0–mA

5

MB15C101

■ FUNCTIONAL DESCRIPTIONS

Two different frequencies can be selected by Div input “H” or “L”.
The divide ratios are calculated using the following equation:

f

VCO = {(P × N) + A} × fOSC ÷ R (A < N)

Symbol Description Div = “H” Div = “L”

fvco Output frequency of external VCO 233.15 MHz 259.20 MHz
fosc Reference oscillation frequency 19.2 MHz 19.2 MHz

N Divide ratio of the main counter 291 33
A Divide ratio of the swallow counter 7 12

P
R Divide ratio of the reference counter 384 (fr = 50 kHz) 40 (fr = 480 kHz)

■ PHASE DETECTOR TIME CHART

Preset divide ratio of dual modulus
prescaler

16/17 16/17

fr

fp

WLtWU

t

LD

D

O High impedance

Note: • .Phase error detection range: –2π to +2π

• Pulses on Do output signal during locked state are output to prevent dead zone.

• LD output becomes low when phase is t

WU or more. LD output becomes high wh en phase error is tWL or

less and continues to be so for three cycles or more.

•.t

WU and tWL depend on OSCin input frequency.

t

WU > 8/fosc (s) (e. g.tWU > 625.0ns, foscin = 12.8 MHz)

tWL < 16/fosc (s) (e. g. tWL < 1250.0ns, foscin = 12.8 MHz)

6