Fujitsu MB15C02 User Manual

FUJITSU MICROELECTRONICS

DATA SHEET

DS04–21348–3Ea

ASSP

Single Serial Input PLL Frequency Synthesizer

On-Chip prescaler

MB15C02

■ DESCRIPTION

The Fujitsu Microelectronics MB15C02 is a serial input Phase Locked Loop (PLL) frequency synthesizer with a prescaler. A 64/65 division is available for the prescaler that enables pulse swallow operation.

This operates with a supply voltage of 1.0 V (min.). MB15C02 is suitable for mobile communications, such as paging systems.

■ FEATURES

• High frequency operation: 220 MHz max @VDD = 1.0 V to 1.5 V 330 MHz max @V 450 MHz max @V

• Single power supply : V

• Power saving function

• Pulse swallow function: 64/65

• Serial input 14-bit programmable reference divider: R = 5 to 16,383

• Serial input 18-bit programmable divider consisting of:

- Binary 6-bit swallow counter: 0 to 63

- Binary 12-bit programmable counte r: 5 to 4,0 95

• Wide operating temperature: Ta = –20 to 60°C

■ PACKAGES

16-pin, Plastic SSOP

DD = 1.0 to 1.5 V

DD = 1.2 V to 1.5 V DD = 1.3 V to 1.5 V

20-pin, Plastic SSOP

(FPT-16P-M05)

1999.2

(FPT-20P-M03)

MB15C02

■ PIN ASSIGNMENTS

SSOP-20 pin

SSOP-16 pin

VDD

Clock

Data

fin

PS NC

LD Do

1 2

3 4 5

8 9

(FPT-20P-M03)

Top

View

20 19 18 17 16 15

14 13 12 11

VSS OSC

NC OSCOUT

TEST FC

φP NC φR

VSS

Clock

Data

fin PS LD

3 4 5

6 7 8

Top

View

15 14

13 12 11

OSC

OSCOUT TEST

φP φR

(FPT-16P-M05)

■ PIN DESCRIPTIONS

MB15C02

Pin no.

SSOP16SSOP

1 1 VDD – Power supply voltage 2 2 Clock I – 3 NC – No connection

3 4 Data I Serial data input using binary code.(Schmitt trigger input)

4 5 LE I

5 6 fin I

6 7 PS I

– 8 NC – No connection

7 9 LD O

8 10 Do O

9 11 Vp – Power supply for the charge pump.

10 12 φR O

– 13 NC – No connection 11 14 φP O 12 15 FC I Phase comparator input select pin. 13 16 TEST I

name

I/O Descriptions

Clock input for the shift register.(Schmitt trigger input) Data is shifted into the shift register on the rising edge of the clock.

Load enable signal input (Schmitt trigger input) When LE is high, the data in the shift register is transferred to a latch, according to the control bit in the serial data.

Prescaler input. A bias circuit and amplifier are at input port. Connection with an external VCO should be done by AC coupling.

Power saving mode control. This pin must be set at “L” at Power-ON. PS = “H” ; Normal mode PS = “L” ; Power saving mode

Lock detector signal output. When a PLL is locking, LD outputs “H”. When a PLL is not locking, LD outputs “L”.

Charge pump output. Phase of the charge pump can be reversed by FC input. The Do output may be inverted by FC input. The relationships between the programmable reference divider out put (fr) and the programmable divider output (fp) are shown below; fr > fp :“H” level (FC = “L”), “L” level (FC = “H”) fr = fp : High impedance fr < fp :“L” level (FC = “L”), “H” level (FC = “H”)

Phase comparator output pin (for external charge pump). Relation between the programmabl e ref erence divider output ( fr) and the prog rammab le divider output (fp) are shown below; When FC = “L” fr > fp : φR = “L” level, φP = “L” level fr = fp : φR = “L” level, φP = High impedance fr < fp : φR = “H” level, φP = High impedance When FC = “H” fr > fp : φR = “H” level, φP = High impedance fr = fp : φR = “L” level, φP = High impedance fr < fp : φR = “L” level, φP = “L” level

Phase comparator output pin (for external charge pump). Refer to Pin description for φR. φP pin is a Nch open drain output.

Test mode select pin. (Pull down resistor) Please set this pin to ground or open usually.

(Continued)

MB15C02

(Continued)

Pin no.

SSOP16SSOP

14 17 OSCOUT O

– 18 NC – No connection

15 19 OSCIN I

16 20 VSS – Ground pin.

name

I/O Descriptions

Oscillator output. Connection for an external crystal.

Programmable reference divider input. Oscillator input. Clock can be input to OSC pin open and make connection with OSC

IN from outside. In the case, please leave OSCOUT

IN as AC coupling.

■ BLOCK DIAGRAM

VDD

Intermittent

mode control

circuit

Clock

Programmable

reference divider

Binary 14-bit

reference counter

14-bit latch

oscillator

Phase

comparator

MB15C02

Crystal

VSS

circuit

OSCIN

OSCOUT

TEST

Data

18-bit shift register Control register

18-bit latch

fin

Binary 6-bit

Prescaler

Lock detector

swallow counter

Control circuit

Binary 12-bit

programma-

ble counter

Output control circuit

Charge

pump

φP

φR

MB15C02

■ ABSOLUTE MAXIMUM RATINGS

Parameter Symbol

Unit Remark

Min. Max.

Rating

Power supply voltage V Input voltage V Output voltage V Output current I Storage temperature T

DD, VP GND–0.5 +2.0 V

IN GND–0.5 VDD +0.5 V

OUT GND–0.5 VDD +0.5 V

OUT –10 +10 mA

stg –40 +125 °C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING CONDITIONS

Parameter Symbol

Power supply voltage V

DD, VP

Input voltage V

Min. Typ. Max.

1.0 – 1.5

1.3 – 1.5 For 450 MHz

IN GND – VDD V

Value

Unit Remark

For 220 MHz

DD = VP1.2 – 1.5 For 330 MHz

Operating temperature Ta –20 – +60 °C

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.

Always use semiconductor de vi ces with in their reco mmended oper ating condition ra nges . Oper ation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinat ions not represented on the data sheet. Users considering application outside the listed conditio ns are advised to contact their representatives beforehand.

■ ELECTRICAL CHARACTERISTICS

MB15C02

(For 220 MHz :VDD = Vp = 1.0 to 1.5 V, Ta = –20 to +60°C) (For 330 MHz :V (For 450 MHz :V

DD = Vp = 1.2 to 1.5 V, Ta = –20 to +60°C) DD = Vp = 1.3 to 1.5 V, Ta = –20 to +60°C)

Parameter Symbol Condition

Power supply current Active Mode

Power saving current

Power saving mode

fin fin

Operating frequency

IN fOSC

OSC

fin Vfin AC coupling –2.0 – – dBm

Input sensitivity

OSCin V

Input voltage

Input current

Output voltage

Except for fin and OSCin

Except for fin, OSCin and TEST

Except for OSC

OUT

and φP

H level V

L level V

H level I

L level I

H level V

L level V

Value

Unit

µA

DDS

(VDD=1.0V/220MHz)

DD=1.2V/330MHz)

DD=1.3V/450MHz)

(VDD=1.0V)

(VDD=1.2V) (V

DD=1.3V)

Min.

– – –

Typ.

0.6

1.0

1.3 50

70 80

Max.

1.2

1.8

2.2

250 300 350

Programmable divider

DD=1.0 to 1.5V)

(V (V

DD=1.2 to 1.5V)

DD=1.3 to 1.5V)

Programmable reference divider

OSC AC coupling –2.0 – – dBm

IH – IL ––– 0.2

IH VIN=VDD ––+1.0

10 10 10

5–20MHz

DD –

0.2

– – –

220 330 450

MHz

––

µA

IL VIN=GND –1.0 – –

DD –

OH IOH = –0.2 mA

OL IOL = 0.2 mA – – 0.2

0.2

––

φPL levelV

High impedance cutoff current

Do I φPI

*1: Conditions; Inputs except for fin, OSC

Specifying the current flowing in V

OFF1 VOUT = GND to VP –100 – 100 nA OFF2 VOUT = VDD ––100nA

IN and TEST are grounded, Outputs are opened.

DD and Vp at operating state under conditions of VDD = Vp, fin =

220 MHz, or 330 MHz, and OSCIN = 12.8 MHz. The current at locking state shows I

DD Supply current (P.20).

*2: Conditions; PS = Low, Inputs except for fin, OSC *3: Condition; Ta = 25°C *4: Condition; Ta = –20 to +60°C

OL IOL = 0.2 mA – – 0.2 V

IN and TEST are grounded, Outputs are opened.

MB15C02

■ FUNCTION DESCRIPTIONS

1. Pulse Swallow Function

The divide ratio can be calculated using the following equation: f

VCO = [(M × N) + A] × fOSC ÷ R (A < N)

VCO : Output frequency of external voltage controlled oscillator (VCO)

N : Preset divide ratio of binary 12-bit programmable counter (5 to 4,095) A : Preset divide ratio of binary 6-bit swallow counter (0 to 63) f

OSC : Output frequency of the reference frequency oscillator

R : Preset divide ratio of binary 14-bit programmable reference counter (5 to 16, 383) M : Preset modulus of dual modulus prescaler (64)

2. Circuit Description

(1) Intermittent operation

The intermittent operation of the MB15C02 refers to the process of activating and deactivating its internal circuit thus saving power dissipation otherwise consumed by the circuit. If the circuit is simply restarted from the power saving state, however, the phase relation between the reference frequency (fr) and the programmable frequency (fp), which are the input to the phase comparator, is not stable even when they are of the same value. This may cause the phase comparator to gener ate an excessively large error signal, resulting in a n out-of-synth lock frequency

To preclude the occurrence of this problem, the MB15C02 has an intermittent mode control circuit wh ich for ces the frequencies into phase with each other when the IC is reactivated, thus minimizing the error signal and resultant lock frequency fluctuations. The inter mittent mode control circuit is controlled by the PS pin. Setting pin PS high provides the normal operation mode and setting the pin low provides the power saving mode. The MB15C02 behavior in the active and power saving modes is summarized below.

Active mode (PS = “H”) All MB15C02 circuits are active and provide the normal operation.

Power saving mode (PS = “L”) The MB15C02 stops any circuits that consume pow er heavily as well as cause little inconv enience when deactivated and enters the low-power dissipa tion state. Do , φR, φP, and LD pins take the same state as when the PLL is loc ked. Do pin becomes a high-impedance state and the input voltage to the voltage control oscillator (VCO) is maintained at the same level as in active mode(that is, locked state) according to a time constant of a low pass filter (LPF). Consequently , the output frequency from the VCO (f

Applying the intermittent operation by alternating the acti ve and power saving modes, and also forcing the phases of fr and fp to synchronize when it switches from stand by to active modes, the MB15C02 can keep the power dissipation of its entire circuitry to the minimum.

vco) is maintained at approximately the lock frequency.

(2) Programmable divider

The fvco input through fin pin is divided by the programmable divider and then output to the phase comparator as fp. It consists of a dual modulus prescaler, a 6-bit binary swallow counter, a 12-bit binary programmable counter, and a controller which controls the divide ratio of the prescaler

MB15C02

Divide ratio range:

Prescaler : M = 64, M+1=65 Swallow counter : A = 0 to 63 Programmable counter : N = 5 to 4095

The MB15C02 uses the pulse sw allow method; consequently , the divide ra tions of the swallow and programmable counters must satisfy the relationship N>A.

The total divide ratio of the programmable divider is calculated as follows:

Total divide ratio = (M + 1) × A + M × (N – A) = M × N + A = 64 × N + A

When N is set within 5< N must be greater than A. For example, 0< Consequently, N>

The fp and fin have the following relation:

fp = fin / (64 × N + A)

N<63, the possible divide ratio A of the s wallo w counter can take v alues 0<A<N-1 because

A<19 is allowed when N=20 but 20<A<63 is not allowed in that case.

64 must be satisfied for the total divider to be set within 0<A<63.

(3) Programmable reference divider

The programmable reference divider divides the reference oscillation frequency(fosc) from the crystal oscillator connected between OSCin and OSCout pins or from the external oscillator input taken in directly through OSCin, pin and then, sends the resultant fr to the phase compar ator. It consists of a 14-bit binary programmable refer ence counter. When the output from the external oscillator is to be input directly to OSCin, pin the connection must be AC coupled and OSCout pin is left open. Also, to prevent OSCout from malfunctioning, its traces on the printed circuit board must be kept minimal or eliminated entirely; whenever possible, it must b e free of any form of load. The following divider is used:

Programmable reference counter : R = 5 to 16383

The fr and f

fr = fosc / R

osc have the following relation:

(4) Phase comparator

The phase comparator detects the phase di ff erence betw een the outp uts fr and fp fro m the dividers and gener ates an error signal that is proportional to phase differ ence. The ou tputs from the phase compara tor include 1) Do which takes on one of the three states, namely, “L” (low), “H” (high), and “Z” (high impedance), and is sent to the LPF,

2)φR, 3)φP, 4)LD which indicates the PLL lock or unlock states.

(a) Phase comparator

The phase comparator detects the phase error between fr and fp, then generates an error signal that is proportional to the phase error. The roles of the fr and fp supplied to the phase comparator may be reversed by switching th e logical inpu t level of pin FC. This inverts the logical level of the Do output. The logical level of Do output may be selecte d according to the characteristics of the ex ternal LPF and the VCO. (Ref er to T able 1.)

Table. 1 Phase comparator inputs/output relationships

Phase

Output

relation

fr > fp H L L L H Z fr = fp Z L Z Z L Z fr < fp L H Z H L L

FC = “L” FC = “H”

Do φR φPDoφR φP

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