How it Works
Foxconn
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M9F1
Schematics
46 pgs533.35 Kb0
Schematic
47 pgs638.74 Kb0

Foxconn M9F1 Schematic

5
4
3
2
1
P27
P28
P21
R1.0
P12~P13
DDRII
SODIMM
USB#1
P27
USB#5
BT
P31
LAN + 4 in 1
Carder Reader
JMC261
P21P22
USB#0
USB#5
WiFi
DDRII 667
P27
USB2.0
P31
PCIE x 1
PCIE Interface
CPU PineView-M
22mm x 22mm
P6~P11
DMI x 2
Tiger Point
USB 2.0 (8 ports) SATA(2 Ports) AZALIA HD AUDIO 3X1PCIE IF 1PCI LPC I/F
17mm x 17mm
P14~P17
LPC,33MHZ
NUVOTON NPCE783LA0DX
EC
LVDS
VGA
HDA
P19
10.1"LCD PANEL
SATA
P28
D-Sub
P26
AUDIO CODEC
REALTEK ALC269Q
SATA HDD
SM Bus
P23
P25
HDP JACK
MIC JACK
Int. DMIC
Speaker
Thermal Sensor
EMC1412-1
P33
TI Charger BQ24753ARHDR
Inputs Outputs
DC_IN
Inputs Outputs
DCBATOUT
Inputs Outputs
DCBATOUT
CPU DC/DC
MAX8796GTJ+
INPUTS DCBATOUT
Inputs Outputs
+1_8VSUS +0_9VRUN
Inputs Outputs
+1_8VSUS +1_5VRUN
Inputs Outputs
+1_8VSUS
System DC/DC TPS51125RGER
System DC/DC TPS51124RGER
OUTPUT VHCORE
System DC/DC G2998BP11U
System DC/DC G9731F11U
System DC/DC G9731F11U
DCBATOUT BT+
+3VALW +5VALW +5VALW_LDO +ECVCC
+1_8VSUS
VCCGFX
+1_05VRUN
P.36
P.37
P.38
P.39
P.40
P.40
P.40
MM9F1 Block Diagram
D D
CLOCK GEN.
9LRS3165BKLFT
C C
B B
RJ45
P22
P18
USB#3
3G CON CON CON
USB#7
MM-SIM
P30
P30
Transformer
10/100Mb
3in1 Card Slot
USB#2
USB#6
CAMERA
SPI
A A
5
4
BIOS KBD
P20
TOUCH PAD
P20 P20
3
SM Bus
Battery Pack
2
P36
CCPBG
CCPBG
Title
Title
Title
Size DocumentNum ber Rev
Size DocumentNum ber Rev
Size DocumentNum ber Rev A2
A2
A2 Date: Sheet
Date: Sheet
Date: Sheet
CCPBG
Block Diagram
Block Diagram
Block Diagram
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144Wednesday,March17, 2010
144Wednesday,March17, 2010
144Wednesday,March17, 2010
5
4
3
2
1
CPUC0/CPUT0
CLK_CPU_BCLK# CLK_CPU_BCLK
D D
CPUC1/CPUT1
CLK_MCH_BCLK# CLK_MCH_BCLK
SRCC6/SRCT6
SRCC4/SRCT4
EXP_CLKIN#
25MHz
LAN
CLK_PCIE_LAN#
CLK_PCIE_LAN
EXP_CLKIN
SRCC1/SRCT1
CLK_PCIE_WLAN#
Wireless
C C
CLK_PCIE_WLAN
SRCC9/SRCT9
SRCC0/SRCT0
DREFSSCLK# DREFSSCLK
DREFCLK# DREFCLK
SRCC10/SRCT10
CPUC2/CPUT2
CLK_ICH_DMI#
3G
CLK_PCIE_3G# CLK_PCIE_3G
CLK_ICH_DMI
SRCC2/SRCT2
CLK_ICH_SATA# CLK_ICH_SATA
USB_48MHz
B B
PCI_F5
REF0
CLK_ICH48
CLK_ICH_PCI
CLK_ICH14
BCLKN
BCLKP
Pineview
HPL_CLKINN
HPL_CLKINP
EXP_CLKINN
EXP_CLKINP
DPL_REFSSCLKINN
DPL_REFSSCLKINP
DPL_REFCLKINN
DPL_REFCLKINP
DMI_CLKINN
DMI_CLKINP
SATA_CLKINN
SATA_CLKINP
CLK48
PCICLK
TPT
CLK14
DDR_A_CK0
DDR_A_CK#0
DDR_A_CK1
DDR_A_CK#1
HDA_BIT_CLK
M_CLK_DDR#0 M_CLK_DDR0
M_CLK_DDR#1 M_CLK_DDR1
32.768KHz
HDA_CODEC_BITCLK
CK0/CK0#
SO-DIMM
CK1/CK1#
BCLK
HD Audio
CK-505
14.318MHz
A A
5
4
PCI4
CLK_KBCPCI
3
LPCCLK
EC
32.768KHz
CCPBG
CCPBG
Title
Title
Title
Size DocumentNumber Rev
Size DocumentNumber Rev
Size Documen t Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
2
Date: Sheet
CCPBG
Clock distribution
Clock distribution
Clock distribution
M9F1
M9F1
M9F1
244Wednesday, March 17, 2010
244Wednesday, March 17, 2010
244Wednesday, March 17, 2010
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Pine Trail Power Flowchart for M9F1
2
1
D D
C C
Voltage Rails
power plane
State
S0
S3
S5/AC, S4
S5 Battery only
S5 S4/AC & Battery don't exist (G3)
O MEANS ON X MEANS OFF
+5VALW_LDO +ECVCC
+5VALW +3VALW
O O O O
X
O O O
X X
+5VRUN +3VSUS +1_8VSUS
+3VRUN
+1_8VRUN
+1_5VRUN
+1_05VRUN
+0_9VRUN
VCCGFX
VHCORE
O
O
X X
O
X X X
XX
S3 : STR S4 : STD S5 : SOFT OFF G3 : ME OFF
B B
A A
CCPBG
CCPBG
Title
Title
Title
Size DocumentNumber Rev
Size DocumentNumber Rev
Size Documen t Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
CCPBG
Power Flowchart
Power Flowchart
Power Flowchart
M9F1
M9F1
M9F1
344Wednesday, March 17, 2010
344Wednesday, March 17, 2010
344Wednesday, March 17, 2010
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Pine Trail Power On Sequence
REV : 2009/08/17
S4/S5 State S3 State S0 State
D D
DC_IN/BT+
DCBATOUT
+5VALW_LDO/+ECVCC
G3 to S5
+3VALW/+5VALW
ALW_PWRGD
PM_RSMRST#
C C
+3VSUS/+5VSUS/+1_8VSUS
+3VRUN/+5VRUN +0_9VRUN/+1_5VRUN
B B
PWRSW#
PWRBTN#
PM_SLP_S4#
SUS_ON
PM_SLP_S3#
RUN_ON
+1_5V_PWRGD
+1_05VRUN
+1_05V_PWRGD
+1_8VRUN/VCCGFX
S5 to S0
ALL_SYS_PWRGD
IMVP_VR_ON
VHCORE
CK_PWRGD
DELAY_VR_PWRGD
H_PWRGD
A A
PLT_RST#
5
CCPBG
CCPBG
Titl e
Titl e
Titl e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev Custom
Custom
Custom Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
CCPBG
Power On Sequence(1)
Power On Sequence(1)
Power On Sequence(1)
M9F1
M9F1
M9F1
444Wednesday, March 17, 2010
444Wednesday, March 17, 2010
444Wednesday, March 17, 2010
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Pine Trail Power On Sequence
4
3
2
1
REV : 2009/08/18
D D
-1
2
Battery Only
G3 to S5
ACMode
-1
Reset IC RN5VD30CA
2
SUS_ON RUN_ON
ALW_PWRGD
14
GFX_PWRGD
+1_5V_PWRGD
ECRST#
ALL_SYS_PWRGD
14
13
15
IMVP_VR_ON
EC NPCE783L
BAT
-1
AC
DCBATOUT
DCBATOUT
0
+5VALW_LDO +ECVCC
1
+ECVCC
8
C C
+5VALW
3a
ALW_ON
+3VALW
+3VSUS
SUS_ON
8
B B
11
RUN_ON
12
+1_5V_PWRGD
+1_8VSUS
+5VRUN +3VRUN +0_9VRUN +1_5VRUN
+1_05VRUN
11 3b
9
DDR_PWRGD
5
17
DELAY_VR_PWRGD
Power On Button
7
PM_SLP_S4#
10
PM_SLP_S3#
6
PWRBTN#
4
PM_RSMRST#
19
PLT_RST#
17
SYS_PWRGD_TPT
S5 to S0
CPUPWRGD
TTigerpoint
PWROK
VRMPWRGD
19
4
H_PWRGD
18
PLT_RST#
4
19
CPUPWRGOOD
RSTIN#
CPU Pineview
PWROK
13
+1_05V_PWRGD
A A
5
VCCGFX
+1_8VRUN
IMVP_CLK_EN#
IMVP
16
VHCORE
4
3
16
CK_PWRGD
CLK Gen. CK505
CCPBG
CCPBG
Titl e
Titl e
Titl e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev Custom
Custom
Custom Date: Sheet
Date: Sheet
2
Date: Sheet
CCPBG
Power On Sequence(2)
Power On Sequence(2)
Power On Sequence(2)
M9F1
M9F1
M9F1
1
544Wednesday, March 17, 2010
544Wednesday, March 17, 2010
544Wednesday, March 17, 2010
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5
D D
C C
DMI_RXP014 DMI_RXN014 DMI_RXP114 DMI_RXN114
4
C4 0.1U_10V_K 0402_X5RC4 0.1U_10V_K 0402_X5R
1 2
C1 0.1U_10V_K 0402_X5RC1 0.1U_10V_K 0402_X5R
1 2
C2 0.1U_10V_K 0402_X5RC2 0.1U_10V_K 0402_X5R
1 2
C3 0.1U_10V_K 0402_X5RC3 0.1U_10V_K 0402_X5R
1 2
DMI_RXP0 _C DMI_RXN0_C DMI_RXP1 _C DMI_RXN1_C
F3 F2 H4
G3
U1A
U1A
DMI_RXP_0 DMI_RXN_0 DMI_RXP_1 DMI_RXN_1
3
G2
DMI_TXP_0
G1
DMI_TXN_0
H3
DMI_TXP_1
J2
DMI
DMI
DMI_TXN_1
2
DMI_TXP0 14 DMI_TXN0 14 DMI_TXP1 14 DMI_TXN1 14
1
EXP_CLKIN#18 EXP_CLKIN18
B B
A A
5
4
N7 N6
R10
R9
N10
N9
K2
J1
M4
L3
EXP_CLKINN EXP_CLKINP
RSVD_2 RSVD_1 RSVD_3 RSVD_15
RSVD_18 RSVD_17 RSVD_16 RSVD_21
QLJB
QLJB null
null
EXP_RCOMPO
EXP_ICOMPI
RSVD_TP_2 RSVD_TP_1
3
EXP_RBIAS
RSVD_20 RSVD_19 RSVD_14
RSVD_7
L10 L9 L8
N11 P11
K3 L2 M2 N2
EXP_COMP EXP_RBIAS
1 1
TP126MIL TP126MIL TP226MIL TP226MIL
12
R1
R1 750_F
750_F 0402
0402
Pull-down must be placed within 500 mils of the processor.
2
12
R2
R2
49.9_F
49.9_F 0402
0402
CCPBG
CCPBG
Title
Title
Title
Size DocumentNumber Rev
Size DocumentNumber Rev
Size Documen t Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
Date: Sheet
CCPBG
CPU- Pineview (1)
CPU- Pineview (1)
CPU- Pineview (1)
M9F1
M9F1
M9F1
644Wednesday, March 17, 2010
644Wednesday, March 17, 2010
644Wednesday, March 17, 2010
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D D
C C
Place resistors close to MCH PINS ON MCH_VREF, Place 0.1uF CAP close to MCH.
B B
DDRDIMM_VRE F
A A
12
5
R5
R5 NC_0_J
NC_0_J 0402
0402
+1_8VSUS
12
12
R6
R6 1K_F
1K_F 0402
0402
R8
R8 1K_F
1K_F 0402
0402
12
C5
C5
0.1U_10V_K
0.1U_10V_K 0402_X5R
0402_X5R
+1_8VSUS
Place CAP close to pin DDR_RPU
4
U1B
M_A_A[14..0]12,13 M_A_DQ[63..0] 12
M_A_WE#12,13 M_A_CAS#12,13 M_A_RAS#12,13
M_A_BS012,13 M_A_BS112,13 M_A_BS212,13
M_CS#012,13 M_CS#112,13
M_CKE012,13 M_CKE112,13
M_ODT012,13 M_ODT112,13
M_CLK_ DDR012 M_CLK_ DDR#012 M_CLK_ DDR112 M_CLK_ DDR#112
NC_0_J
NC_0_J
R4
R7 80.6_F 0402R7 80.6_F 0402
R9 80.6_F 0402R9 80.6_F 0402
12
C6
C6
0.01U_6.3V_K
0.01U_6.3V_K 0402_X7R
0402_X7R
1 2
1 2
1 2
4
0402R4
0402
+1_8VSUS
12
R3
R3 10K_J
10K_J 0402
0402
TP3 26MILTP3 26MIL TP4 26MILTP4 26MIL
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14
CPU_VSS_173
MCH_VREF MCH_DDR_RPD MCH_DDR_RPU
U1B
AH19
DDR_A_MA_0
AJ18
DDR_A_MA_1
AK18
DDR_A_MA_2
AK16
DDR_A_MA_3
AJ14
DDR_A_MA_4
AH14
DDR_A_MA_5
AK14
DDR_A_MA_6
AJ12
DDR_A_MA_7
AH13
DDR_A_MA_8
AK12
DDR_A_MA_9
AK20
DDR_A_MA_10
AH12
DDR_A_MA_11
AJ11
DDR_A_MA_12
AJ24
DDR_A_MA_13
AJ10
DDR_A_MA_14
AK22
DDR_A_WE#
AJ22
DDR_A_CAS#
AK21
DDR_A_RAS#
AJ20
DDR_A_BS_0
AH20
DDR_A_BS_1
AK11
DDR_A_BS_2
AH22
DDR_A_CS#_0
AK25
DDR_A_CS#_1
AJ21
DDR_A_CS#_2
AJ25
DDR_A_CS#_3
AH10
DDR_A_CKE_0
AH9
DDR_A_CKE_1
AK10
DDR_A_CKE_2
AJ8
DDR_A_CKE_3
AK24
DDR_A_ODT_0
AH26
DDR_A_ODT_1
AH24
DDR_A_ODT_2
AK27
DDR_A_ODT_3
AG15
DDR_A_CK_0
AF15
DDR_A_CK#_0
AD13
DDR_A_CK_1
AC13
DDR_A_CK#_1
AC15
DDR_A_CK_3
AD15
DDR_A_CK#_3
AF13
DDR_A_CK_4
AG13
DDR_A_CK#_4
AD17
RSVD_22
AC17
RSVD_23
AB15
RSVD_24
AB17
RSVD_25
AB4
RSVD_26
AK8
RSVD_27
AB11
1
RSVD_TP_3
AB13
1
RSVD_TP_4
AL28
DDR_VREF
AK28
DDR_RPD
AJ26
DDR_RPU
AK29
RSVD_28
QLJB
QLJB null
null
DDR_A
DDR_A
3
M_A_DQS0
DDR_A_DQS_0
DDR_A_DQS#_0
DDR_A_DM_0 DDR_A_DQ_0
DDR_A_DQ_1 DDR_A_DQ_2 DDR_A_DQ_3 DDR_A_DQ_4 DDR_A_DQ_5 DDR_A_DQ_6 DDR_A_DQ_7
DDR_A_DQS_1
DDR_A_DQS#_1
DDR_A_DM_1 DDR_A_DQ_8
DDR_A_DQ_9 DDR_A_DQ_10 DDR_A_DQ_11 DDR_A_DQ_12 DDR_A_DQ_13 DDR_A_DQ_14 DDR_A_DQ_15
DDR_A_DQS_2
DDR_A_DQS#_2
DDR_A_DM_2 DDR_A_DQ_16
DDR_A_DQ_17 DDR_A_DQ_18 DDR_A_DQ_19 DDR_A_DQ_20 DDR_A_DQ_21 DDR_A_DQ_22 DDR_A_DQ_23
DDR_A_DQS_3
DDR_A_DQS#_3
DDR_A_DM_3 DDR_A_DQ_24
DDR_A_DQ_25 DDR_A_DQ_26 DDR_A_DQ_27 DDR_A_DQ_28 DDR_A_DQ_29 DDR_A_DQ_30 DDR_A_DQ_31
DDR_A_DQS_4
DDR_A_DQS#_4
DDR_A_DM_4 DDR_A_DQ_32
DDR_A_DQ_33 DDR_A_DQ_34 DDR_A_DQ_35 DDR_A_DQ_36 DDR_A_DQ_37 DDR_A_DQ_38 DDR_A_DQ_39
DDR_A_DQS_5
DDR_A_DQS#_5
DDR_A_DM_5 DDR_A_DQ_40
DDR_A_DQ_41 DDR_A_DQ_42 DDR_A_DQ_43 DDR_A_DQ_44 DDR_A_DQ_45 DDR_A_DQ_46 DDR_A_DQ_47
DDR_A_DQS_6
DDR_A_DQS#_6
DDR_A_DM_6 DDR_A_DQ_48
DDR_A_DQ_49 DDR_A_DQ_50 DDR_A_DQ_51 DDR_A_DQ_52 DDR_A_DQ_53 DDR_A_DQ_54 DDR_A_DQ_55
DDR_A_DQS_7
DDR_A_DQS#_7
DDR_A_DM_7 DDR_A_DQ_56
DDR_A_DQ_57 DDR_A_DQ_58 DDR_A_DQ_59
DDR_A_DQ_60 DDR_A_DQ_61 DDR_A_DQ_62 DDR_A_DQ_63
3
AD3 AD2 AD4
AC4 AC1 AF4 AG2 AB2 AB3 AE2 AE3
AB8 AD7 AA9
AB6 AB7 AE5 AG5 AA5 AB5 AB9 AD6
AD8 AD10 AE8
AG8 AG7 AF10 AG11 AF7 AF8 AD11 AE10
AK5 AK3 AJ3
AH1 AJ2 AK6 AJ7 AF3 AH2 AL5 AJ6
AG22 AG21 AD19
AE19 AG19 AF22 AD22 AG17 AF19 AE21 AD21
AE26 AG27 AJ27
AE24 AG25 AD25 AD24 AC22 AG24 AD27 AE27
AE30 AF29 AF30
AG31 AG30 AD30 AD29 AJ30 AJ29 AE29 AD28
AB27 AA27 AB26
AA24 AB25 W24 W22
AB24 AB23 AA23 W27
M_A_DQS#0 M_A_DM0
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7
M_A_DQS1 M_A_DQS#1 M_A_DM1
M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15
M_A_DQS2 M_A_DQS#2 M_A_DM2
M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23
M_A_DQS3 M_A_DQS#3 M_A_DM3
M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31
M_A_DQS4 M_A_DQS#4 M_A_DM4
M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39
M_A_DQS5 M_A_DQS#5 M_A_DM5
M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47
M_A_DQS6 M_A_DQS#6 M_A_DM6
M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55
M_A_DQS7 M_A_DQS#7 M_A_DM7
M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59
M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
2
Title
Title
Title
Size DocumentNumber Rev
Size DocumentNumber Rev
Size Documen t Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
2
Date: Sheet
1
M_A_DQS[7..0] 12 M_A_DQS#[7..0] 12 M_A_DM[7..0] 12
CCPBG
CCPBG
CCPBG
CPU- Pineview (2)
CPU- Pineview (2)
CPU- Pineview (2)
M9F1
M9F1
M9F1
744Wednesday, March 17, 2010
744Wednesday, March 17, 2010
744Wednesday, March 17, 2010
1
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5
D D
4
3
2
1
U1C
AA21
W21
D12
A7 D6 C5 C7 C6 D8 B7 A9 D9 C8
B8 C10 D10 B11 B10 B12 C11
L11
AA7 AA6
R5
R6
T21 V21
U1C
XDP_RSVD_0 XDP_RSVD_1 XDP_RSVD_2 XDP_RSVD_3 XDP_RSVD_4 XDP_RSVD_5 XDP_RSVD_6 XDP_RSVD_7 XDP_RSVD_8 XDP_RSVD_9 XDP_RSVD_10 XDP_RSVD_11 XDP_RSVD_12 XDP_RSVD_13 XDP_RSVD_14 XDP_RSVD_15 XDP_RSVD_16 XDP_RSVD_17
RSVD_4
RSVD_TP_6 RSVD_TP_7 RSVD_TP_8 RSVD_TP_5
RSVD_TP_11 RSVD_TP_10 RSVD_TP_9 RSVD_TP_12
CRT_HSYNC
CRT_VSYNC
CRT_RED
CRT_GREEN
CRT_BLUE
VGA
VGA
PM_EXTTS#_1/DPRSLPVR
MISC
MISC
CRT_IRTN
CRT_DDC_DATA
CRT_DDC_CLK
DAC_IREF
REFCLKINP REFCLKINN
REFSSCLKINP
REFSSCLKINN
PM_EXTTS#_0
PWROK
RSTIN#
HPL_CLKINN HPL_CLKINP
CRT_HSYNCXDP_RSVD_1
M30
CRT_VSYNC
M29
N31 P30 P29 N30
L31 L30
DACREFSET
P28 Y30
Y29 AA30 AA31
PM_DPRSLPVR_R
K29
PM_EXTTS#0
J30
IMVP_PWRGD_R
L5 AA3
W8 W9
TP5 26MILTP5 26MIL TP6 26MILTP6 26MIL TP7 26MILTP7 26MIL
NC_1K_J
NC_1K_J
R13
C C
B B
R14 R15
R18
1 2
1K_J
1K_J
1 2 1 2
NC_1K_J
NC_1K_J
1 2
NC_1K_J
NC_1K_J
0402R13
0402
0402R14
0402 0402R15
0402
0402R18
0402
XDP_RSVD_5
XDP_RSVD_9 XDP_RSVD_11
XDP_RSVD_17
XDP_RSVD_0
1 1
XDP_RSVD_2
1
XDP_RSVD_5
XDP_RSVD_11
XDP_RSVD_17
TP8 26MILTP8 26MIL TP9 26MILTP9 26MIL TP10 26MILTP 10 26MIL TP11 26MILTP 11 26MIL
TP12 26MILTP 12 26MIL TP13 26MILTP 13 26MIL TP14 26MILTP 14 26MIL TP15 26MILTP 15 26MIL
1 1 1 1
1 1 1 1
Locate Series resistor within 750 mils of MCH
R10 15_J 0402R10 15_J 0402
1 2
R11 15_J 0402R11 15_J 0402
1 2
RED_VGA 26 GREEN_VGA 26 BLUE_VGA 26
VGA_DDC_DAT 26
1 2
VGA_DDC_CLK 26
DREFCLK 18 DREFCLK# 18 DREFSS CLK 1 8 DREFSSCLK# 18
21 21
CLK_MCH_ B CLK# 18 CLK_MCH_ B CLK 1 8
PM_EXTTS#0
R12 665_F 0402R12 665_F 0402
R16 POWER_CLOSE_GAP_0402R16 POWER_CLOSE_GAP_0402 R17 POWER_CLOSE_GAP_0402R17 POWER_CLOSE_GAP_0402
HSYNC_VGA 26 VSYNC_VGA 26
Place DACIREF RES close to MCH: <500mils to MCH ball
PM_DPRSLPVR 16,39 PM_EXTTS#0 12 DELAY_VR_PWRGD 16,39 PLT_RST# 16,19,20,21,30,31,33
R22
R22
1 2
10K_J 0402
10K_J 0402
+3VRUN
Place VGA RGB resistors close to MCH: <250 mils to MCH balls.
RED_VGA GREEN_VGA BLUE_VGAXDP_RSVD_9
12
12
R20
R20 150_F
150_F 0402
0402
12
R21
R21 150_F
150_F 0402
0402
R19
R19 150_F
150_F 0402
0402
QLJB
QLJB null
null
A A
CCPBG
CCPBG
Title
Title
Title
Size DocumentNumber Rev
Size DocumentNumber Rev
Size Documen t Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
CCPBG
CPU- Pineview (3)
CPU- Pineview (3)
CPU- Pineview (3)
M9F1
M9F1
M9F1
844Wednesday, March 17, 2010
844Wednesday, March 17, 2010
844Wednesday, March 17, 2010
1
0.1
0.1
0.1
of
of
of
5
LVDS_CLKIN-28 LVDS_CLKIN+28 LVDS_RXIN0-28 LVDS_RXIN0+28
D D
R26 POWER_CLOSE_GAP_0402R26 POWER_CLOSE_GAP_0402
+3VRUN
R30 2.2K_J 0402R30 2.2K_J 0402
1 2
R31 2.2K_J 0402R31 2.2K_J 0402
1 2
+1_05VRUN
NC_51_J
C C
B B
NC_51_J
R34
1 2
R35 51_J 0402R35 51_J 0402
1 2
NC_62R_J
NC_62R_J
R36
1 2
R38 51_J 0402R38 51_J 0402
1 2
R40 51_J 0402R40 51_J 0402
1 2
R42 51_J 0402R42 51_J 0402
1 2
R44 51_J 0402R44 51_J 0402
1 2
R45 51_J 0402R45 51_J 0402
1 2
R306 100K_J 0402R306 100K_J 0402
1 2
R314 100K_J 0402R314 100K_J 0402
1 2
0402R34
0402
0402R36
0402
LDDC_CLK_EDID
LDDC_DAT _ E DID
H_BPM 4_PRDY# H_BPM5_PREQ#
CPU_RSVD_01 H_TDI H_TDO
H_TMS
H_TCK H_TRST _N
LCD_LVDDEN
R27 POWER_CLOSE_GAP_0402R27 POWER_CLOSE_GAP_0402
LCD_BLEN
LVDS_RXIN1-28 LVDS_RXIN1+28 LVDS_RXIN2-28 LVDS_RXIN2+28
R25 2.37K_F 0402R25 2.37K_F 0402
1 2
21 21
LCD_BLEN28 LCD_BLCTL28
TP31 26MILTP31 26MIL
TP32 26MILTP32 26MIL LDDC_CLK_EDID28 LDDC_DAT _ E DID28
LCD_LVDDEN28
TP21 26MILTP 21 26MIL TP22 26MILTP 22 26MIL TP23 26MILTP 23 26MIL TP24 26MILTP 24 26MIL
TP25 26MILTP 25 26MIL TP26 26MILTP 26 26MIL TP27 26MILTP 27 26MIL TP28 26MILTP 28 26MIL
H_THERMDA33 H_THERMDC33
4
LIBG
TP19 26MILTP 19 26MIL
LVREFH LVREFL
LCTLA_CLK
1
LCTLB_DAT
1
H_BPM#0
1
H_BPM#1
1
H_BPM#2
1
H_BPM#3
1
H_BPM_2#0
1
H_BPM_2#1
1
H_BPM_2#2
1
H_BPM_2#3
1
CPU_RSVD_01 H_TDI H_TDO H_TCK H_TMS H_TRST _N
U25 U26 R23 R24 N26 N27 R26 R27
R22
J28
1
N22 N23
L27 L26 L23 K25 K23 K24
H26
G11
E15
G13
F13 B18
B20
C20
B21
G5 D14 D13
B14 C14 C16
D30
E30
C30 D31
U1D
U1D
LA_CLKN LA_CLKP LA_DATAN_0 LA_DATAP_0 LA_DATAN_1 LA_DATAP_1 LA_DATAN_2 LA_DATAP_2
LIBG LVBG LVREFH LVREFL LBKLT_EN LBKLT_CTL LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA LVDD_EN
BPM_1_0# BPM_1_1# BPM_1_2# BPM_1_3#
BPM_2_0#/RSVD BPM_2_1#/RSVD BPM_2_2#/RSVD BPM_2_3#/RSVD
RSVD_5 TDI TDO TCK TMS TRST#
THRMDA_1 THRMDC_1
THRMDA_2/RSVD THRMDC_2/RSVD
QLJB
QLJB null
null
3
E7
SMI#
H7
A20M#
H6
FERR#
F10
LINT0
F11
LINT1
E5
IGNNE#
ICH
ICH
LVDS
LVDS
STPCLK#
DPRSTP#
DPSLP#
INIT# PRDY# PREQ#
THERMTRIP#
PROCHOT#
CPUPWRGOOD
GTLREF
VSS_1
RSVD_11 RSVD_10
BCLKN BCLKP
BSEL_0 BSEL_1
CPU
CPU
BSEL_2
VID_0 VID_1 VID_2 VID_3 VID_4 VID_5 VID_6
RSVD_9
RSVD_12
RSVD_8 RSVD_6
RSVD_TP_14 RSVD_TP_13
EXTBGREF
H_STPCLK#
F8
G6
H_DPSLP#
G10 G8
H_BPM 4_PRDY#
E11
H_BPM 5_PREQ#
F15
E13
PROCHOT#
C18 W1
1
CPU_GTL RE F
A13 H27
L6 E17
H10 J10
BSEL0
K5
BSEL1
H5
BSEL2
K6
VID0
H30
VID1
H29
VID2
H28
VID3 BSEL1
G30
VID4
G29
VID5
F29
VID6
E29 L7
D20 H13 D18
K9 D19 K7
TP2926MIL TP2926MIL
1
TP3026MIL TP3026MIL
1
EXTBGREF
12
TP2026MIL TP2026MIL
C9
C9 1U_10V_K
1U_10V_K 0402_X5R
0402_X5R
H_SMI# 1 5 H_A20M# 15
H_FERR# 15
H_INTR 1 5 H_NMI 15 H_IGNNE# 1 5 H_STPCLK# 15
PM_DPRSTP# 16,39 H_DPSLP# 16 H_INIT# 15
PM_THERMTRIP# 15
H_PWRGD 16
CLK_CP U_BCLK# 18 CLK_CP U_BCLK 18
+1_05VRUN
BSEL0 18 BSEL1 18 BSEL2 18
12
R43
R43 976_F
976_F 0402
0402
12
R46
R46
3.32K_F
3.32K_F 0402
0402
2
H_DPSLP# H_SMI#H_SMI# H_STPCLK#
TP1826MIL TP1826MIL
1
TP1626MIL TP1626MIL
1
TP1726MIL TP1726MIL
1
Place within 500 mils of GTLREF'S pin.Zo=50ohm.
+1_05VRUN
12
R32
R32 1K_F
1K_F 0402
0402
12
R33
R33 2K_F
2K_F 0402
0402
R37 470_J 0402R37 470_J 0402
1 2
R39 470_J 0402R39 470_J 0402
1 2
R41 470_J 0402R41 470_J 0402
1 2
+1_05VRUN
VID[6..0] 39
12
C7
C7 220P_50V_J
220P_50V_J 0402_NPO
0402_NPO
BSEL0
BSEL2
12
C8
C8 1U_10V_K
1U_10V_K 0402_X5R
0402_X5R
1
Place within 500 mils of Processor pin.
+1_05VRUN
12
R47
R47 68_J
68_J 0402
PROCHOT#
A A
5
4
3
0402
R48
R48
21
POWER_CLOSE_GAP_0402
POWER_CLOSE_GAP_0402
OVT_EC# 16,19,39
2
CCPBG
CCPBG
Title
Title
Title
Size DocumentNumber Rev
Size DocumentNumber Rev
Size Documen t Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
Date: Sheet
CCPBG
CPU- Pineview (4)
CPU- Pineview (4)
CPU- Pineview (4)
M9F1
M9F1
M9F1
944Wednesday, March 17, 2010
944Wednesday, March 17, 2010
944Wednesday, March 17, 2010
1
of
of
of
0.1
0.1
0.1
5
2.2 uF x 1 uF x 7
1
C16
C16 1U_6.3V_K
1U_6.3V_K 0402_X5R
0402_X5R
R49
R49
12
12
21
12
D D
12
C27
C27 10U_6.3V_M
10U_6.3V_M 0603_X5R
0603_X5R
+1_8VSUS
power_close_gap_0805
power_close_gap_0805
Splitting VCCA_DDR and VCCA_CK_DDR power shapes are proven effective to reduce the DDR2 clock jitter.
C C
VCCA_DDR and VCCA_CK_DDR rails are split near Pineview-M to avoid noise coupling.
C17
C17 1U_6.3V_K
1U_6.3V_K 0402_X5R
0402_X5R
C28
C28
0.1U_10V_K
0.1U_10V_K 0402_X5R
0402_X5R
12
C32
C32 33P_50V_J
33P_50V_J 0402_NPO
0402_NPO
+1_05VRUN
12
C18
C18 1U_6.3V_K
1U_6.3V_K 0402_X5R
0402_X5R
12
C209
C209 33P_50V_J
33P_50V_J 0402_NPO
0402_NPO
2.2 uF x 4
12
C33
C33 NC_2.2U_6.3V_M
NC_2.2U_6.3V_M 0402_X5R
0402_X5R
+1_8VSUS
R53
R53
power_close_gap_0805
power_close_gap_0805
12
C19
C19 1U_6.3V_K
1U_6.3V_K 0402_X5R
0402_X5R
12
C30
C30 NC_330U_2.5V_M
NC_330U_2.5V_M
+
+
3.5x2.8x1.9
3.5x2.8x1.9
power_close_gap_0805
power_close_gap_0805
21
R55
R55 POWER_CLOSE_GAP_0402
POWER_CLOSE_GAP_0402
12
C20
C20 1U_6.3V_K
1U_6.3V_K 0402_X5R
0402_X5R
21
D34
D34 NC_SED0603-050D900-10-LF
NC_SED0603-050D900-10-LF null
null
Place beside C30
12
C34
C34
2.2U_6.3V_M
2.2U_6.3V_M 0402_X5R
0402_X5R
12
C35
C35
2.2U_6.3V_M
2.2U_6.3V_M 0402_X5R
0402_X5R
Place CAPS and resistor close to MCH Balls for VCK_DDR
R51
R51
21
10 uF x
4.7 uF x
1 1 uF x 1
1
12
C31
C31 33P_50V_J
33P_50V_J 0402_NPO
0402_NPO
12
C40
C40 22U_6.3V_M
22U_6.3V_M 0805_X5R
0805_X5R
2 1
B B
+1_8VRUN
POWER_CLOSE_GAP_0402
POWER_CLOSE_GAP_0402
A A
+VCCSFR_AB_DPL
R59
R59
21
12
C49
C49 1U_6.3V_K
1U_6.3V_K 0402_X5R
0402_X5R
+1_05VRUN
POWER_CLOSE_GAP_0402
POWER_CLOSE_GAP_0402
1 uF x 2
12
R61
R61
C50
C50 1U_6.3V_K
1U_6.3V_K 0402_X5R
0402_X5R
21
12
+VCC_RING
12
C202
C202 33P_50V_J
33P_50V_J 0402_NPO
0402_NPO
1 uF x 2
C56
C56
1U_6.3V_K
1U_6.3V_K 0402_X5R
0402_X5R
+1_8VRUN
L2
L2
600R-100MHZ_0603
600R-100MHZ_0603 EBMS160808A601
EBMS160808A601
12
C58
C58 1U_6.3V_K
1U_6.3V_K 0402_X5R
0402_X5R
1 uF x 1
Place Caps close to CPU Pin C3,C2,B2.
5
12
C10
C10
2.2U_6.3V_M
2.2U_6.3V_M 0402_X5R
0402_X5R
12
C38
C38 22U_6.3V_M
22U_6.3V_M 0805_X5R
0805_X5R
12
C51
C51 1U_10V_K
1U_10V_K 0402_X5R
0402_X5R
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
1 uF x 2
12
C54
C54
4
12
C21
C21 1U_6.3V_K
1U_6.3V_K 0402_X5R
0402_X5R
12
C36
C36
2.2U_6.3V_M
2.2U_6.3V_M 0402_X5R
0402_X5R
22 uF x 1
12
C39
C39 NC_0.1U_6.3V_K
NC_0.1U_6.3V_K 0402_X5R
0402_X5R
+VCCA_VCCD
12
C45
C45 1U_6.3V_K
1U_6.3V_K 0402_X5R
0402_X5R
C41
C41 1U_6.3V_K
1U_6.3V_K 0402_X5R
0402_X5R
VCCD_HMP LL
12
12
C46
C46 1U_6.3V_K
1U_6.3V_K 0402_X5R
0402_X5R
154mA
+VCCACRTDAC
12
4
1 uF x 1
+VCC_RING +VCC_LGI_VID
R62
R62
+3VRUN
+1_05VRUN
+1_05VRUN
POWER_CLOSE_GAP_0402
POWER_CLOSE_GAP_0402
12
C11
C11 1U_6.3V_K
1U_6.3V_K 0402_X5R
0402_X5R
12
C37
C37
2.2U_6.3V_M
2.2U_6.3V_M 0402_X5R
0402_X5R
C42
C42
4.7U_6.3V_K
4.7U_6.3V_K 0603_X5R
0603_X5R
21
VCCGFX
+VCC_DDR
+VCCCK_DDR
5mA
12
C57
C57 NC_1U_6.3V_M
NC_1U_6.3V_M 0402_X5R
0402_X5R
W14 W16 W18 W19
AK13 AK19
AL11 AL16 AL21 AL25
W10 W11
AA10 AA11
AA19
AC31
T13 T14 T16 T18 T19 V13 V19
AK9
AK7 AL7
U10
U5 U6 U7 U8 U9 V2 V3 V4
V11
T30
T31
J31
C3 B2 C2
A21
QLJB
QLJB null
null
U1E
U1E
VCCGFX_1 VCCGFX_2 VCCGFX_3 VCCGFX_4 VCCGFX_5
1.38A
VCCGFX_6 VCCGFX_7 VCCGFX_8 VCCGFX_9 VCCGFX_10 VCCGFX_11
VCCSM_1 VCCSM_5 VCCSM_6 VCCSM_7 VCCSM_2 VCCSM_3 VCCSM_4
2.27A
VCCCK_DDR_1 VCCCK_DDR_2
VCCA_DDR_1 VCCA_DDR_2 VCCA_DDR_3 VCCA_DDR_4 VCCA_DDR_5 VCCA_DDR_6 VCCA_DDR_7
1.32A
VCCA_DDR_8 VCCA_DDR_9 VCCA_DDR_10 VCCA_DDR_11
VCCACK_DDR_1 VCCACK_DDR_2
VCCD_AB_DPL
VCCD_HMPLL
VCCSFR_AB_DPL
305mA
VCCACRTDAC
VCC_GIO VCCRING_EAST VCCRING_WEST_3 VCCRING_WEST_1 VCCRING_WEST_2 VCC_LGI
GFX/MCH
GFX/MCH
PINEVIEW_M
PINEVIEW_M
DDR
DDR
EXP\CRT\PLL
EXP\CRT\PLL
3
POWER
POWER
480mA
DMI
DMI
3
VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8
VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17
CPU
CPU
VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42
VCCSENSE VSSSENSE
VCCA
80mA
VCC_43 VCCP_1
VCCP_2
60mA
VCCALVDS
VCCDLVDS
LVDS
LVDS
VCCA_DMI_1 VCCA_DMI_2 VCCA_DMI_3
RSVD_13
VCCSFR_DMIHMPLL
VCCP_3
A23 A25 A27 B23 B24 B25 B26 B27 C24 C26 D23 D24 D26 D28 E22 E24 E27 F21 F22 F25 G19 G21 G24 H17 H19 H22 H24 J17 J19 J21 J22 K15 K17 K21 L14 L16 L19 L21 N14 N16 N19 N21
C29 B29 Y2
D4 B4
B3
V30 W31
T1 T2 T3
P2 AA1
E2
VHCORE
3500mA
12
12
C29
C29 NC_330U_2.5V_M
NC_330U_2.5V_M
+
+
3.5x2.8x1.9
3.5x2.8x1.9
+TPEV_VCCP
+VCCAD18 0_LVD_R
+VCCSFR_ DMIHMPLL
12
C55
C55 1U_6.3V_K
1U_6.3V_K 0402_X5R
0402_X5R
+VCC_RING
C12
C12 1U_10V_K
1U_10V_K 0402_X5R
0402_X5R
22 uF x 1
1 uF x 2
104mA
POWER_CLOSE_GAP_0402
POWER_CLOSE_GAP_0402
12
12
12
C47
C47 22U_6.3V_M
22U_6.3V_M 0805_X5R
0805_X5R
VHCORE
+VCCPC6
2
C13
C13 1U_10V_K
1U_10V_K 0402_X5R
0402_X5R
C25
C25 22U_6.3V_M
22U_6.3V_M 0805_X5R
0805_X5R
12
R50
R50 100_F
100_F 0402
0402
12
R52
R52 100_F
100_F 0402
0402
12
C44
C44
POWER_CLOSE_GAP_0402
POWER_CLOSE_GAP_0402
0.1U_10V_K
0.1U_10V_K 0402_X5R
0402_X5R
POWER_CLOSE_GAP_0402
POWER_CLOSE_GAP_0402
L1
L1
1 2
0.1UH_0603
0.1UH_0603 LQM18NNR10K00D
LQM18NNR10K00D
+1_8VRUN
R63
R63
21
2
1 uF x 4
12
C14
C14 1U_10V_K
1U_10V_K 0402_X5R
0402_X5R
12
C22
C22 NC_22U_6.3V_M
NC_22U_6.3V_M 0805_X5R
0805_X5R
+1_05VRUN
12
C15
C15 1U_10V_K
1U_10V_K 0402_X5R
0402_X5R
21
D36
D36 NC_SED0603-050D900-10-LF
NC_SED0603-050D900-10-LF null
null
Place beside R56
PU & PD avoid to route with stub
Layout Note: Route VCCSENSE & VSSSENSE traces at 27.4 Ohms
VCCSENSE 39 VSSSENSE 39
R56
R56
R57
R57
with 25 mil spacing to other signals. Place PU and PD within 2 inch of CPU.
0.01 uF x 1
+1_05VRUN
21
+1_05VRUN
21
+VCCAD180_LVDS
12
+VCCA_DM I
12
C223
C223 33P_50V_J
33P_50V_J 0402_NPO
0402_NPO
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Documen t Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
Date: Sheet
12
C24
C24 NC_1U_10V_K
NC_1U_10V_K 0402_X5R
0402_X5R
VHCORE
+VCCA
12
12
C43
C43
0.01U_6.3V_K
0.01U_6.3V_K 0402_X7R
0402_X7R
12
C23
C23 NC_22U_6.3 V_M
NC_22U_6.3 V_M 0805_X5R
0805_X5R
Place near PIN Y2
1 uF x 1
C48
C48 1U_6.3V_K
1U_6.3V_K 0402_X5R
0402_X5R
12
C52
C52 1U_6.3V_M
1U_6.3V_M 0402_X5R
0402_X5R
12
CPU- Pineview (5)
CPU- Pineview (5)
CPU- Pineview (5)
1
21
D35
C26
C26 33P_50V_J
33P_50V_J 0402_NPO
0402_NPO
D35 NC_SED0603-050D900-10-LF
NC_SED0603-050D900-10-LF null
null
Place beside C23
R54
R54
21
POWER_CLOSE_GAP_0402
POWER_CLOSE_GAP_0402
R58
R58
21
POWER_CLOSE_GAP_0402
POWER_CLOSE_GAP_0402
R60
R60
C53
C53 1U_6.3V_M
1U_6.3V_M 0402_X5R
0402_X5R
CCPBG
CCPBG
CCPBG
M9F1
M9F1
M9F1
21
POWER_CLOSE_GAP_0603
POWER_CLOSE_GAP_0603
1
+1_5VRUN
+1_8VRUN
+1_05VRUN
10 44Wednesday, March 17, 2010
10 44Wednesday, March 17, 2010
10 44Wednesday, March 17, 2010
0.1
0.1
0.1
of
of
of
5
D D
C C
B B
A A
5
4
U1F
U1F
A11
VSS_72
A16
VSS_71
A19
VSS_70
A29
RSVD_NCTF_19
A3
RSVD_NCTF_18
A30
RSVD_NCTF_17
A4
RSVD_NCTF_16
AA13
VSS_69
AA14
VSS_68
AA16
VSS_67
AA18
VSS_66
AA2
VSS_65
AA22
VSS_64
AA25
VSS_63
AA26
VSS_62
AA29
VSS_61
AA8
VSS_60
AB19
VSS_59
AB21
VSS_58
AB28
VSS_57
AB29
VSS_56
AB30
VSS_55
AC10
VSS_54
AC11
VSS_53
AC19
VSS_52
AC2
VSS_51
AC21
VSS_50
AC28
VSS_49
AC30
VSS_48
AD26
VSS_47
AD5
VSS_46
AE1
VSS_45
AE11
VSS_44
AE13
VSS_43
AE15
VSS_42
AE17
VSS_41
AE22
VSS_40
AE31
VSS_39
AF11
VSS_38
AF17
VSS_37
AF21
VSS_36
AF24
VSS_35
AF28
VSS_34
AG10
VSS_33
AG3
VSS_32
AH18
VSS_31
AH23
VSS_30
AH28
VSS_29
AH4
VSS_28
AH6
VSS_27
AH8
VSS_26
AJ1
RSVD_NCTF_15
AJ16
VSS_25
AJ31
VSS
AK1
RSVD_NCTF_13
AK2
RSVD_NCTF_12
AK23
VSS_24
AK30
RSVD_NCTF_11
AK31
RSVD_NCTF_10
AL13
VSS_23
AL19
VSS_22
AL2
RSVD_NCTF_9
AL23
VSS_21
AL29
RSVD_NCTF_8
AL3
RSVD_NCTF_7
AL30
RSVD_NCTF_6
AL9
VSS_20
B13
VSS_19
B16
VSS_18
B19
VSS_17
B22
VSS_16
B30
RSVD_NCTF_5
B31
RSVD_NCTF_4
B5
VSS_15
B9
VSS_14
C1
RSVD_NCTF_3
C12
VSS_13
C21
VSS_12
C22
VSS_11
C25
VSS_10
C31
RSVD_NCTF_2
D22
VSS_9
E1
RSVD_NCTF_1
E10
VSS_8
E19
VSS_7
E21
VSS_6
E25
VSS_5
E8
VSS_4
F17
VSS_3
F19
VSS_2
QLJB
QLJB null
null
4
3
F24
VSS_153
F28
VSS_152
F4
VSS_151
G15
VSS_150
G17
VSS_149
G22
VSS_148
G27
VSS_147
G31
VSS_146
H11
VSS_145
H15
VSS_144
H2
VSS_143
H21
VSS_142
H25
VSS_141
H8
VSS_140
J11
VSS_139
J13
VSS_138
J15
VSS_137
J4
VSS_136
K11
VSS_135
K13
VSS_134
K19
VSS_133
K26
VSS_132
K27
VSS_131
K28
VSS_130
K30
VSS_129
K4
VSS_128 VSS_127 VSS_126 VSS_125 VSS_124 VSS_123 VSS_122 VSS_121 VSS_120 VSS_119 VSS_118 VSS_117 VSS_116 VSS_115 VSS_114 VSS_113 VSS_112 VSS_111 VSS_110 VSS_109 VSS_108 VSS_107 VSS_106 VSS_105 VSS_104 VSS_103 VSS_102 VSS_101 VSS_100
VSS_99 VSS_98 VSS_97 VSS_96 VSS_95 VSS_94 VSS_93 VSS_92 VSS_91 VSS_90 VSS_89 VSS_88 VSS_87 VSS_86 VSS_85 VSS_84 VSS_83 VSS_82 VSS_81 VSS_80 VSS_79 VSS_78 VSS_77 VSS_76 VSS_75 VSS_74
VSS_73
K8 L1 L13 L18 L22 L24 L25 L29 M28 M3 N1 N13 N18 N24 N25 N28 N4 N5 N8 P13 P14 P16 P18 P19 P21 P3 P4 R25 R7 R8 T11 U22 U23 U24 U27 V14 V16 V18 V28 V29 W13 W2 W23 W25 W26 W28 W30 W4 W5 W6 W7 Y28 Y3 Y4
T29
3
GND
GND
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Documen t Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
2
Date: Sheet
CPU- Pineview (6)
CPU- Pineview (6)
CPU- Pineview (6)
CCPBG
CCPBG
CCPBG
M9F1
M9F1
M9F1
1
0.1
0.1
11 44Wednesday, March 17, 2010
11 44Wednesday, March 17, 2010
11 44Wednesday, March 17, 2010
1
0.1
of
of
of
5
4
3
2
1
M_A_DQ4 M_A_DQ5
M_A_DM0 M_A_DQ6
M_A_DQ7 M_A_DQ12
M_A_DQ13 M_A_DM1
M_A_DQ14 M_A_DQ15
M_A_DQ20 M_A_DQ21
DDR2_EXTTS#0 M_A_DM2
M_A_DQ22 M_A_DQ23
M_A_DQ28 M_A_DQ29
M_A_DQS#3 M_A_DQS3
M_A_DQ30 M_A_DQ31
M_A_A14 M_A_A11
M_A_A7 M_A_A6
M_A_A4 M_A_A2 M_A_A0
M_A_A13
M_A_DQ36 M_A_DQ37
M_A_DM4 M_A_DQ38
M_A_DQ39 M_A_DQ44
M_A_DQ45 M_A_DQS#5
M_A_DQS5 M_A_DQ46
M_A_DQ47 M_A_DQ52
M_A_DQ53
M_A_DM6 M_A_DQ54
M_A_DQ55 M_A_DQ60
M_A_DQ61 M_A_DQS#7
M_A_DQS7 M_A_DQ62
M_A_DQ63 DIMM0_SA0
DIMM0_SA1
1.8V DIMM=3.08A
M_CLK_DDR0 7 M_CLK_DDR#0 7
NC_0_J
NC_0_J
R66
1 2
M_CKE1 7,13
M_A_BS1 7,13 M_A_RAS# 7,13 M_CS#0 7,13
M_ODT0 7,13
M_CLK_DDR1 7 M_CLK_DDR#1 7
NC_10K_J
NC_10K_J
R68
1 2
R69 10K_J 0402R69 10K_J 0402
1 2
R70 10K_J 0402R70 10K_J 0402
1 2
3
0402R68
0402
0402R66
0402
+3VRUN
PM_EXTTS#0 8
DDR2_VREF
(20 mil)
+1_8VSUS
12
C62
C62
2.2U_6.3V_M
2.2U_6.3V_M 0402_X5R
0402_X5R
12
C63
C63
2.2U_6.3V_M
2.2U_6.3V_M 0402_X5R
0402_X5R
12
Place these Caps near So-DIMM0
+1_8VSUS
12
C67
C67
0.1U_6.3V_K
0.1U_6.3V_K 0402_X5R
0402_X5R
12
C68
C68
0.1U_6.3V_K
0.1U_6.3V_K 0402_X5R
0402_X5R
12
Place these Caps near So-DIMM0
2
M_A_DQ[63:0]7
M_A_A[14..0]7,13 M_A_DQS[7..0]7 M_A_DQS#[7..0]7
M_A_DM[7..0]7
DDRDIMM_VREF+1_8VSUS
12
R64
R64 1K_F
1K_F 0402
0402
12
R67
12
C65
C65
2.2U_6.3V_M
2.2U_6.3V_M 0402_X5R
0402_X5R
12
C70
C70
0.1U_6.3V_K
0.1U_6.3V_K 0402_X5R
0402_X5R
R67 1K_F
1K_F 0402
0402
12
C61
C61
0.1U_6.3V_K
0.1U_6.3V_K 0402_X5R
0402_X5R
C64
C64
2.2U_6.3V_M
2.2U_6.3V_M 0402_X5R
0402_X5R
C69
C69
0.1U_6.3V_K
0.1U_6.3V_K 0402_X5R
0402_X5R
Title
Title
Title
Size D ocument Number Rev
Size D ocument Number Rev
Size D ocument Number Rev Custom
Custom
Custom Date: Sheet
Date: Sheet
Date: Sheet
12
R65
R65 NC_0_J
NC_0_J 0402
0402
12
C66
C66
2.2U_6.3V_M
2.2U_6.3V_M 0402_X5R
0402_X5R
12
C71
C71 33P_50V_J
33P_50V_J 0402_NPO
0402_NPO
CCPBG
CCPBG
CCPBG
DDRII(SO-DIMM0)
DDRII(SO-DIMM0)
DDRII(SO-DIMM0)
M9F1
M9F1
M9F1
1
0.1
0.1
0.1
of
of
of
12 44Wednesday,March17, 2010
12 44Wednesday,March17, 2010
12 44Wednesday,March17, 2010
Place close to VREF pin.
12
C60
C60
2.2U_6.3V_M
2.2U_6.3V_M 0402_X5R
D D
C C
B B
A A
0402_X5R
12
C59
C59
0.1U_6.3V_K
0.1U_6.3V_K 0402_X5R
0402_X5R
+3VRUN
5
M_A_BS27,13
M_A_BS07,13
M_A_WE#7,13
M_A_CAS#7,13
SMB_DATA16,18
SMB_CLK16,18
12
12
M_CKE07,13
M_CS#17,13 M_ODT17,13
C72
C72
0.1U_6.3V_K
0.1U_6.3V_K 0402_X5R
0402_X5R
C224
C224 33P_50V_J
33P_50V_J 0402_NPO
0402_NPO
DDR2_VREF
M_A_DQ0 M_A_DQ1
M_A_DQS#0 M_A_DQS0
M_A_DQ2 M_A_DQ3
M_A_DQ8 M_A_DQ9
M_A_DQS#1 M_A_DQS1
M_A_DQ10 M_A_DQ11
M_A_DQ16 M_A_DQ17
M_A_DQS#2 M_A_DQS2
M_A_DQ18 M_A_DQ19
M_A_DQ24 M_A_DQ25
M_A_DM3
M_A_DQ26 M_A_DQ27
M_A_A12 M_A_A9 M_A_A8
M_A_A5 M_A_A3 M_A_A1
M_A_A10
M_A_DQ32 M_A_DQ33
M_A_DQS#4 M_A_DQS4
M_A_DQ34 M_A_DQ35
M_A_DQ40 M_A_DQ41
M_A_DM5 M_A_DQ42
M_A_DQ43 M_A_DQ48
M_A_DQ49
M_A_DQS#6 M_A_DQS6
M_A_DQ50 M_A_DQ51
M_A_DQ56 M_A_DQ57
M_A_DM7 M_A_DQ58
M_A_DQ59
12
C73
C73
0.1U_6.3V_K
0.1U_6.3V_K 0402_X5R
0402_X5R
+1_8VSUS
12
C225
C225 33P_50V_J
33P_50V_J 0402_NPO
0402_NPO
1
VREF
3
VSS47
5
DQ0
7
DQ1
9
VSS37
11
DQS#0
13
DQS0
15
VSS48
17
DQ2
19
DQ3
21
VSS38
23
DQ8
25
DQ9
27
VSS49
29
DQS#1
31
DQS1
33
VSS39
35
DQ10
37
DQ11
39
VSS50
41
VSS18
43
DQ16
45
DQ17
47
VSS1
49
DQS#2
51
DQS2
53
VSS19
55
DQ18
57
DQ19
59
VSS22
61
DQ24
63
DQ25
65
VSS23
67
DM3
69
NC4
71
VSS9
73
DQ26
75
DQ27
77
VSS4
79
CKE0
81
VDD7
83
NC1
85
A16_BA2
87
VDD9
89
A12
91
A9
93
A8
95
VDD5
97
A5
99
A3
101
A1
103
VDD10
105
A10/AP
107
BA0
109
WE#
111
VDD2
113
CAS#
115
S1#
117
VDD3
119
ODT1
121
VSS11
123
DQ32
125
DQ33
127
VSS26
129
DQS#4
131
DQS4
133
VSS2
135
DQ34
137
DQ35
139
VSS27
141
DQ40
143
DQ41
145
VSS29
147
DM5
149
VSS51
151
DQ42
153
DQ43
155
VSS40
157
DQ48
159
DQ49
161
VSS52
163
NCTEST
165
VSS30
167
DQS#6
169
DQS6
171
VSS31
173
DQ50
175
DQ51
177
VSS33
179
DQ56
181
DQ57
183
VSS3
185
DM7
187
VSS34
189
DQ58
191
DQ59
193
VSS14
195
SDA
197
SCL
199
VDD(SPD)
DDR2 SO-DIMM_2x100P
DDR2 SO-DIMM_2x100P FOX_AS0A426-N4SC-4H
FOX_AS0A426-N4SC-4H
4
201
202
CN1
CN1
VSS46
DQ4 DQ5
SMDFIX1
SMDFIX2
VSS15
DM0
VSS5
DQ6 DQ7
VSS16
DQ12 DQ13
VSS17
DM1
VSS53
CK0
CK0#
VSS41
DQ14 DQ15
VSS54 VSS20
DQ20 DQ21 VSS6
NC3
DM2
VSS21
DQ22 DQ23
VSS24
DQ28 DQ29
VSS25
DQS#3
DQS3
VSS10
DQ30 DQ31 VSS8 CKE1 VDD8
A15 A14
VDD11
A11
A7 A6
VDD4
A4 A2 A0
(200P)
(200P)
VDD12
BA1
RAS#
S0# VDD1 ODT0
A13 VDD6
NC2
VSS12
DQ36 DQ37
VSS28
DDR2 SDRAM SO-DIMM
DDR2 SDRAM SO-DIMM
DM4
VSS42
DQ38 DQ39
VSS55
DQ44 DQ45
VSS43 DQS#5
DQS5
VSS56
DQ46 DQ47
VSS44
DQ52 DQ53
VSS57
CK1
CK1#
VSS45
DM6
VSS32
DQ54 DQ55
VSS35
DQ60 DQ61 VSS7
DQS#7
DQS7
VSS36
DQ62 DQ63
VSS13
SA0 SA1
+1_8VSUS
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
SMBus A ddress: A0H(W)/A1H(R)
5
D D
4
3
+0_9VRUN
2
1
12
C74
C74
0.1U_6.3V_K
0.1U_6.3V_K 0402_X5R
0402_X5R
C C
12
C75
C75
0.1U_6.3V_K
0.1U_6.3V_K 0402_X5R
0402_X5R
12
C76
C76
0.1U_6.3V_K
0.1U_6.3V_K 0402_X5R
0402_X5R
12
C77
C77
0.1U_6.3V_K
0.1U_6.3V_K 0402_X5R
0402_X5R
12
C78
C78
0.1U_6.3V_K
0.1U_6.3V_K 0402_X5R
0402_X5R
12
C79
C79
0.1U_6.3V_K
0.1U_6.3V_K 0402_X5R
0402_X5R
12
C80
C80
0.1U_6.3V_K
0.1U_6.3V_K 0402_X5R
0402_X5R
12
C81
C81
0.1U_6.3V_K
0.1U_6.3V_K 0402_X5R
0402_X5R
Place one cap close to every two pull-up resistors terminated to +0_9VRUN.
+0_9VRUN
R74 47_J 0402R74 47_J 0402
1 2
R76 47_J 0402R76 47_J 0402
M_CS#17,12
M_CKE07,12
B B
M_CKE17,12
M_ODT07,12 M_ODT17,12
1 2
R83 47_J 0402R83 47_J 0402
1 2
R85 47_J 0402R85 47_J 0402
1 2
R87 47_J 0402R87 47_J 0402
1 2
R89 47_J 0402R89 47_J 0402
1 2
M_A_BS07,12M_CS#07,12 M_A_BS17,12
M_A_BS27,12 M_A_CAS#7,12 M_A_RAS#7,12
M_A_WE#7,12
12
C82
C82
0.1U_6.3V_K
0.1U_6.3V_K 0402_X5R
0402_X5R
R75 47_J 0402R75 47_J 0402
1 2
R77 47_J 0402R77 47_J 0402
1 2
R82 47_J 0402R82 47_J 0402
1 2
R84 47_J 0402R84 47_J 0402
1 2
R86 47_J 0402R86 47_J 0402
1 2
R88 47_J 0402R88 47_J 0402
1 2
12
+0_9VRUN
C83
C83
0.1U_6.3V_K
0.1U_6.3V_K 0402_X5R
0402_X5R
12
C84
C84
0.1U_6.3V_K
0.1U_6.3V_K 0402_X5R
0402_X5R
12
C85
C85
0.1U_6.3V_K
0.1U_6.3V_K 0402_X5R
0402_X5R
M_A_A[14..0]7,12
12
C86
C86
0.1U_6.3V_K
0.1U_6.3V_K 0402_X5R
0402_X5R
12
C87
C87
0.1U_6.3V_K
0.1U_6.3V_K 0402_X5R
0402_X5R
M_A_A0 M_A_A1 M_A_A2
M_A_A3 M_A_A4 M_A_A5 M_A_A6
M_A_A7 M_A_A8 M_A_A9 M_A_A10
M_A_A11 M_A_A12 M_A_A13 M_A_A14
12
C88
C88 33P_50V_J
33P_50V_J 0402_NPO
0402_NPO
R71 47_J 0402R71 47_J 0402
1 2
R72 47_J 0402R72 47_J 0402
1 2
R73 47_J 0402R73 47_J 0402
1 2
R78 47_J 0402R78 47_J 0402
1 2
R79 47_J 0402R79 47_J 0402
1 2
R80 47_J 0402R80 47_J 0402
1 2
R81 47_J 0402R81 47_J 0402
1 2
R90 47_J 0402R90 47_J 0402
1 2
R91 47_J 0402R91 47_J 0402
1 2
R92 47_J 0402R92 47_J 0402
1 2
R93 47_J 0402R93 47_J 0402
1 2
R94 47_J 0402R94 47_J 0402
1 2
R95 47_J 0402R95 47_J 0402
1 2
R96 47_J 0402R96 47_J 0402
1 2
R97 47_J 0402R97 47_J 0402
1 2
+0_9VRUN
A A
CCPBG
CCPBG
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Documen t Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
CCPBG
DDRII (Termination)
DDRII (Termination)
DDRII (Termination)
M9F1
M9F1
M9F1
13 44Wednesday, March 17, 2010
13 44Wednesday, March 17, 2010
13 44Wednesday, March 17, 2010
1
0.1
0.1
0.1
of
of
of
5
DMI_TXN06 DMI_TXP06
DMI_RXN06
DMI_RXP06 DMI_TXN16 DMI_TXP16
DMI_RXN16
D D
WLAN_RXN131 WLAN_RXP131
WLAN_TXN131 WLAN_TXP131
LAN_RX N221 LAN_RX P 221
LAN_T XN221
LAN_TXP221 WWAN_RXN330 WWAN_RXP330
WWAN_TXN330 WWAN_TXP330
C C
C89 0.1U_10V_K 0402_X5RC89 0.1U_10V_K 0402_X5R
1 2
C90 0.1U_10V_K 0402_X5RC90 0.1U_10V_K 0402_X5R
1 2
C91 0.1U_10V_K 0402_X5RC91 0.1U_10V_K 0402_X5R
1 2
C92 0.1U_10V_K 0402_X5RC92 0.1U_10V_K 0402_X5R
1 2
C93 NC_0.1U_10V_K 0402_X5RC93 NC_0.1U_10V_K 0402_X5R
1 2
C252 NC_0.1U_10V_K 0402_X5RC252 NC_0.1U_10V_K 0402_X5R
1 2
+1_5VRUN
R99 24.9_F 0402R99 24.9_F 0402
DMI_RXP16
LAN_TXN1_C LAN_TXP1_C
LAN_TXN2_C LAN_TXP2_C
WWAN_TXN3_C WWAN_TXP3_C
Place the resistor within 500 mils of TPT.
1 2
CLK_ICH_DMI#18 CLK_ICH_DMI18
DMICOMP
Straping Options Flash
STRAP2#/ GPIO17
0 1
B B
A A
1
STRAP2#/GPIO17 and STRAP1#/GPIO48 have weak internal pull-ups
NC_1K_J
NC_1K_J
0402 R104
0402
NC_1K_J
NC_1K_J
0402 R106
0402
+3VRUN
1 2
R110 NC_1K_J 0402R110 NC_1K_J 0402
1 2
5
R104
12
R106
12
12
STRAP1#/ GPIO48
FLASH_SEL0
FLASH_SEL1
R1088.2K_J0402 R1088.2K_J0402
R10910K_J0402 R10910K_J0402
Routing
1 0 1
TPT_M13_RSVD_PU
TPT_K9_RSVD_PU
RSVD_TPT_D11
STRAP0#:Top-Block Swap Override. If the signal is sampled low, this indicates that the system is strapped to the "top-block swap" mode (Tiger Point inverts A16 for all cycles targeting FWH BIOS space)
R105
R107
SPI PCI LPC
NC_10K_J
NC_10K_J
1 2
NC_10K_J
NC_10K_J
1 2
+3VRUN
0402R105
0402
0402R107
0402
U23
M18 M19
M21
N25 N24
H24
W23 W24
R23 R24 P21 P20 T21 T20 T24 T25 T19 T18
U24 V21 V20 V24 V23
K21 K22 J23 J24
K24 K25 L23 L24 L22
P17 P18
J22
4
U2B
U2B
DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP
PERn1 PERp1 PETn1 PETp1 PERn2 PERp2 PETn2 PETp2 PERn3 PERp3 PETn3 PETp3 PERn4 PERp4 PETn4 PETp4
DMI_ZCOMP DMI_IRCOMP
DMI_CLKN DMI_CLKP
QV56
QV56 null
null
4
3
2
1
USB port table
H7
USBP0N
H6
USBP0P
H3
USBP1N
H2
USBP1P
J2
USBP2N
J3
USB
USB
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
OC0# OC1# OC2# OC3#
OC4# OC[5]#/GPIO29 OC[6]#/GPIO30 OC[7]#/GPIO31
USBRBIAS
USBRBIAS#
CLK48
2
2
K6 K5 K1 K2 L2 L3 M6 M5 N1 N2
USB_OC#0
D4
USB_OC#1
C5
USB_OC#2
D3
USB_OC#3
D2
USB_OC#4
E5
USB_OC#5
E6
USB_OC#6
C2
USB_OC#7
C3
USBRBIAS
USBRBIAS
G2 G3
F4
PCI_DEVSEL#
PCI_IRDY# PCI_SERR#
PCI_STOP# PCI_PLOCK# PCI_TRDY# PCI_PERR# PCI_FRAME#
P_REQ1# P_REQ2#
FLASH_SEL0 FLASH_SEL1 TPT_GPIO22_PU RUNTIME_SCI#
PCI_PIPQA# PCI_PIPQB# PCI_PIPQC# PCI_PIPQD# PCI_PIPQE# PCI_PIPQF# PCI_PIPQG# PCI_PIPQH#
RSVD_TPT_D11 TPT_K9_RSVD_PU TPT_M13_RSVD_PU
Traces tied together close to Pin Length no longer than 200 mil to Resistor.
A5
B15
J12 A23
B7 C22 B11
F14
A8
A10
D10
A16
A18
E16 G16
A20
G14
A2 C15
C9
B2
D7
B3 H10
E8
D6
H8
F8 D11
K9 M13
DMI
DMI
PCI-E
PCI-E
CLK_ICH_PCI18
PCI_RST#20
RUNTIME_SCI#19
R98
R98
1 2
22.6_F 0402
22.6_F 0402
CLK_ICH48 18
U2A
U2A
PAR DEVSEL# PCICLK PCIRST# IRDY# PME# SERR# STOP# PLOCK# TRDY# PERR# FRAME#
GNT1# GNT2#
REQ1# REQ2#
GPIO48/STRAP1# STRAP2#/GPIO17 GPIO22 GPIO1
PIRQA# PIRQB# PIRQC# PIRQD# PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5
STRAP0# RSVD_1 RSVD_2
QV56
QV56 null
null
3
USB_PN0 27 USB_PP0 27 USB_PN1 27 USB_PP1 27 USB_PN2 27 USB_PP2 27 USB_PN3 30 USB_PP3 30 USB_PN4 31 USB_PP4 31 USB_PN5 31 USB_PP5 31 USB_PN6 28 USB_PP6 28 USB_PN7 30 USB_PP7 30
USB_OC#0 27 USB_OC#1 27 USB_OC#2 27
PCI
PCI
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8
AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
C/BE0# C/BE1# C/BE2# C/BE3#
1
1
Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7
B22 D18 C17 C18 B17 C19 B18 B19 D16 D15 A13 E14 H14 L14 J14 E10 C11 E12 B9 B13 L12 B8 A3 B5 A6 G12 H12 C8 D9 C7 C1 B1
H16 M15 C13 L16
External USB1 External USB2 External USB3 WWAN (3G/GPS) WLAN(WIFI) Bluetooth Camera module MM-SIM
PCI_PIPQA# PCI_PIPQC# PCI_PIPQF# PCI_PIPQG#
PCI_PIPQB# PCI_IRDY# PCI_PIPQH# PCI_PIPQE#
TPT Strap Pin
Strap Pin STRAP0# STRAP1# STRAP2#
2
RP3
RP3
1 2 3 4 5
8.2K
8.2K 0804_8P4R
0804_8P4R
RP5
RP5
1 2 3 4 5
8.2K
8.2K 0804_8P4R
0804_8P4R
8 7 6
8 7 6
1 2 3 4 5
1 2 3 4 5
+3VRUN
CCPBG
CCPBG
CCPBG
M9F1
M9F1
M9F1
+3VALW
+3VALW
RP4
RP4
8.2K
8.2K 0804_8P4R
0804_8P4R
RP6
RP6
8.2K
8.2K 0804_8P4R
0804_8P4R
1
RP11
USB_OC#5 USB_OC#4 USB_OC#0 USB_OC#2
USB_OC#3 USB_OC#1 USB_OC#6 USB_OC#7
+3VRUN
8 7 6
+3VRUN +3VRUN
8 7 6
P_REQ1#
P_REQ2#
TPT_GPIO22_PU
RUNTIME_SCI#
R100 8.2K_J 0402R100 8.2K_J 0402
R101 8.2K_J 0402R101 8.2K_J 0402
R102 8.2K_J 0402R102 8.2K_J 0402
R103 8.2K_J 0402R103 8.2K_J 0402
Internal PU/PD
PU 20K PU 20K PU 20K
PU 10K(NC) to +3VRUN/PD 1K(NC) PU 10K(NC) to +3VRUN/PD 1K(NC) PU 10K(NC) to +3VRUN/PD 1K(NC)
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Documen t Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
Date: Sheet
RP11
1 2 3 4 5
8.2K
8.2K 0804_8P4R
0804_8P4R RP2
RP2
1 2 3 4 5
8.2K
8.2K 0804_8P4R
0804_8P4R
PCI_SERR# PCI_STOP# PCI_DEVSEL# PCI_FRAME#
PCI_PLOCK# PCI_PIPQD# PCI_PERR# PCI_TRDY#
1 2
1 2
1 2
1 2
External PU/PD
Tiger Point (1)
Tiger Point (1)
Tiger Point (1)
8 7 6
8 7 6
+3VRUN
14 44Wednesday, March 17, 2010
14 44Wednesday, March 17, 2010
14 44Wednesday, March 17, 2010
0.1
0.1
0.1
of
of
of
5
D D
R12
RSVD_3
AE20
RSVD_4
AD17
RSVD_5
AC15
RSVD_6
AD18
RSVD_7
Y12
RSVD_8
AA10
RSVD_9
AA12
RSVD_10
Y10
RSVD_11
AD15
RSVD_12
W10
RSVD_13
V12
RSVD_14
AE21
RSVD_15
AE18
RSVD_16
AD19
RSVD_17
U12
RSVD_18
AC17
RSVD_19
AB13
RSVD_20
AC13
RSVD_21
AB15
RSVD_22
Y14
C C
+3VRUN
12
R112
R112 10K_J
10K_J 0402
0402
DBGSTRP_SET_UP
AB16 AE24 AE23
AA14
AD16
AB11 AB10
AD23
RSVD_23 RSVD_24
RSVD_25 RSVD_26
RSVD_27
V14
RSVD_28
RSVD_29 RSVD_30 RSVD_31 GPIO36
QV56
QV56 null
null
4
U2C
U2C
AE6
SATA0RXN
AD6
SATA0RXP
AC7
SATA0TXN
AD7
SATA0TXP
AE8
SATA1RXN
AD8
SATA1RXP
AD9
SATA1TXN
AC9
SATA
SATA
SATA1TXP
SATARBIAS
SATALED#
A20GATE
A20M#
CPUSLP#
IGNNE#
INIT3_3V#
INIT#
INTR
FERR#
RCIN#
SERIRQ
SMI#
STPCLK#
3
3
AD4 AC4
AD11 AC11 AD25
U16 Y20 Y21 Y18 AD21 AC25 AB24 Y22 T17
NMI
AC21 AA16 AA21 V18 AA20
SATARBIAS HDD_LED#
H_A20GATE
H_RCIN# INT_S ERIRQ
H_THERMTRIP_R
SATA_CLKN SATA_CLKP
SATARBIAS#
HOST
HOST
THRMTRIP#
3
SATA_RXN0 25
SATA_RXP0 25 SATA_TXN0 25 SATA_TXP0 25
CLK_ICH_SATA# 18 CLK_ICH_SATA 18
HDD_LED# 29
H_A20GATE 19
H_A20M # 9 H_IGNNE# 9 H_INIT# 9
H_INTR 9
H_FERR# 9
H_NMI 9
H_RCIN# 19 INT_S ERIRQ 19,20 H_SMI# 9 H_STPCLK# 9
2
PLACE SATARBIAS RESISTORS CLOSE TO ICH: <500 MILS TO ICH BALLS
SATARBIAS
HDD_LED#
H_A20GATE H_RCIN# INT_S ERIRQ
R111 24.9_F 0402R111 24.9_F 0402
1 2
R113 10K_J 0402R113 10K_J 0402
1 2
R114 8.2K_J 0402R114 8.2K_J 0402
1 2
R115 10K_J 0402R115 10K_J 0402
1 2
R116 8.2K_J 0402R116 8.2K_J 0402
1 2
+3VRUN
1
B B
+1_05VRUN
PLACE CLOSE TO TPT AA20 < 1000MILS
12
R118
R118
pull-up at PAGE 32
56_J
56_J 0402
0402
R120
H_THERMTRIP_R
A A
5
R120
POWER_CLOSE_GAP_0402
POWER_CLOSE_GAP_0402
4
21
PM_THERMTRIP# 9
3
H_FERR#
R117 56_J 0402R117 56_J 0402
1 2
Place close to TPT
2
+1_05VRUN
CCPBG
CCPBG
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Documen t Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
Date: Sheet
CCPBG
Tiger Point (2)
Tiger Point (2)
Tiger Point (2)
M9F1
M9F1
M9F1
1
15 44Wednesday, March 17, 2010
15 44Wednesday, March 17, 2010
15 44Wednesday, March 17, 2010
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of
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0.1
0.1
0.1
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