Title of Schematics Page
Express Card
Mini-PCIE Card (WLAN)
LAN (88E8057) 1/2
LAN (Transformer) 2/2
SATA HDD
SATA CD-ROM
eSATA COMBO
PCIE (MS) 1/2
PCIE (SD) 1/2
Camera Connector
Bluetooth Connector
Felica Connector
Status LED & LID
FAN
Touch Pad
Thermal Sensor
Switch DB Conn.
AUDIO SPEAKER CONNECTOR
Audio/USB DB Conn.
Switch (Botton & KB LED)
Audio (CODEC)
Audio (MUTE)
Audio (Power)
Audio (Audio & USB Conn.)
Audio (Head Phone Jack)
Audio (Ext MIC Jack)
Audio (USB Port)
Power Design Diagram
DCIN&Charger
Discharge Circuit
Identify IC
SYS Power (+3_3V/+5V)
VTT&PCH Power(+1_1/1_05V)
DDR3 Power(+1_5V/+0_75V)
SYS Power(+1_8V)
CPU Power_VHCORE
CPU Power_VID
VGA Power(ATI_VDD)
Others power plane
OVP protection
HOLE & AMI LABEL
History(1)
Rev.Title of Schematics PagePage
SA
SA
SA
SA
SA
SA
SA
SA
SA
Design by
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
CCPBG - R&D Division
CCPBG - R&D Division
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Title
Title
Title
Index Page
Index Page
Index Page
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
A3
A3
A3
M960&M970 H ModelSA
M960&M970 H ModelSA
M960&M970 H ModelSA
Date:Sheet
Date:Sheet
5
4
3
2
Date:Sheet
CCPBG - R&D Division
186Thursday, December 24, 2009
186Thursday, December 24, 2009
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M960&M970 H Model Calpella Platform+ AMD Madison/Park Discrete
Graphic+ VRAM*8
8
AA
HDMI
Page 38
LVDS
WSXGA
Page 37
CRT
Page 34
BB
Camera Module
CAM(0.3M)
Page 52
TMDS
LVDS
CRT
GFX
AMD
Madison-LP M2
Park-XT M2
29mm X 29mm
DDR3 VRAM
Madison
DDR3 1GB(1Gbx8pcs)
Park
DDR3 512MB(1Gbx4pcs)
Page 22~27
Page 28~33
PCIE X16
Digital Mic
Int. Speaker
1.0 Walt x 2
Page 60
Realtek
ALC269
w/ Class D Amp.
Ext. Mic In Jack
Ext. Mic In Jack
CC
Headphone Jack
Page 68
Page 67
Pre-AMP
Page 63
HDA
USB2.0
SATA 3Gb/s
SATA 3Gb/s
3
USB 2.0
CONN.X3
Page 69
Audio/USB DB
Page 63~69
USB 2.0 / eSATA
Combo CONN.
Page 49
Arrandale
Processor
Micro-FCPGA-989
(989-pin rPGA socket)
37.5 mm X 37.5 mm
DMI X4
PCH
Ibex Peak-M
(HM55)
676 mBGA
25 mm X 27 mm
LPC
Winbond
NPCE783L
LQFP-128
Page 3~9
(USB x 12)
(PCIE x 8)
(SATA x 4)
Page 10~18
Page 39
800/1066 MHZ
800/1066 MHZ
4
PCIE
4
USB
SATA 3Gb/s
SATA 3Gb/s
SPI
Flash BIOS
32M bit X 1
SATA
HDD
SATA
ODD
Page 10
SO-DIMM 0
800/1066 MHZ
DDR(III)
SO-DIMM 1
800/1066 MHZ
DDR(III)
Page 47
Page 48
204 pin
Page 20
204 pin
Page 21
CK505
SL28748CLC
Ethernet GbE
88E8059
Marvell
Page 45
10/100/1000
Ricoh R5U231
CardReader
Page 50
ExpressCard
34mm
Mini-PCIE Card
(WLAN)
Bluetooth
Felica
Page 43
Page 44
Page 53
Page 54
Page 19
Transformer
LANKom
LG-2413S-1
MS Duo(HG)
SD Card
14.318MHZ
Page 46
Page 51
X,TAL
RJ45
CHARGER
BQ24753A
INPUTS
DC_IN
BATTERY
OUTPUTS
DCBATOUT
SYSTEM DC/DC
SN0608098
INPUTS
DCBATOUT
OUTPUTS
+3VALW
+5VALW
+5VALW_LDO
+12V For Load
SYSTEM DC/DC
TPS51218+G2998
INPUTS
DCBATOUT
OUTPUTS
+1_5VSUS
+0_75VRUN
SYSTEM DC/DC
TPS51218
INPUTS
DCBATOUT
OUTPUTS
+1_05V_VTT
CPU DC/DC
MAX17030
INPUTS
DCBATOUT
OUTPUTS
VHCORE
SYSTEM DC/DC
TPS51217
INPUTS
DCBATOUT
OUTPUTS
VDD CORE
PWM/TACH
GPIO
PS/2
SPI
35001 Bus
DD
SMBus 2
Flash BIOS
2
1M bit x1
BATT ID
BATT CONN
3
FANLid Switch
1
SMBus 1
4
Thermal Sensor
W83L771AWG
(VGA)
Page 58Page 71Page 73Page 41Page 55Page 56
Touch PAD
Page 57
5
Switch DB
Page 59
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
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Title
Title
Title
Block Diagram
Block Diagram
Block Diagram
Size Document NumberRev
Size Document NumberRev
Size Document NumberRev
Custom
Custom
Custom
M960&M970 H Model
M960&M970 H Model
M960&M970 H Model
Date:Sheet
Date:Sheet
6
Date:Sheet
7
HON HAI Precision Ind. Co., Ltd.
CCPBG - R&D Division
CCPBG - R&D Division
CCPBG - R&D Division
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SA
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286Thursday, December 24, 2009
286Thursday, December 24, 2009
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Page 3
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2
3
4
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7
8
AA
DMI_TXN[3:0]12
DMI_TXP[3:0]12
DMI_RXN[3:0]12
DMI_RXP[3:0]12
BB
R16021K_J0402R16021K_J0402
12
R16001K_J0402R16001K_J0402
12
R16011K_J0402R16011K_J0402
12
R16141K_J0402R16141K_J0402
12
R16031K_J0402R16031K_J0402
12
CC
For Disable Arrandale Graphic
In addition, FDI_RXN_[7:0] and FDI_RXP_[7:0] can be left floating on the PCH.
FDI_TX[7:0] and FDI_TX#[7:0] can be left floating on the Arrandale. The
DD
GFX_IMON,FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and FDI_INT
signals on the Arrandale side should be tied to GND (through 1-kΩ ±5% resistors).
FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1] can be ganged together with
one resistor.
FDI_FSYNC[0], FDI_FSYNC[1],
FDI_LSYNC[0], FDI_LSYNC[1]
can be ganged together with
one resistor
HON HAI Precision Ind. Co., Ltd.
CCPBG - R&D Division
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CCPBG - R&D Division
386Tuesday, December 29, 2009
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386Tuesday, December 29, 2009
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Page 4
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Layout Note:
Comp0,1 connect with Zo=49.9 ohm,
Comp2,3 connect with Zo=20 ohm,
In order to minimize resistance,
use thick traces to route all
COMP signals, use 10-mils
(0.254-mm) wide trace for
routing less than 500 mils (12.7
mm), or 20-mils (0.508-mm)
wide trace for routing between
500 mils (12.7 mm) and
1000 mils (25.4 mm). Keep 20-mils
DD
(0.508-mm) spacing to
any other signals in order to
minimize crosstalk.
For Disable Arrandale Graphic
DPLL_REF_SSCLK and DPLL_REF_SSCLK# can be connected to GND on
Arrandale directly if motherboard only supports discrete graphics.
R129051_J0402R129051_J0402
12
R1258NC_51_J0402R1258NC_51_J0402
12
R1259NC_51_J0402R1259NC_51_J0402
12
R1260NC_51_J0402R1260NC_51_J0402
12
R1261NC_51_J0402R1261NC_51_J0402
12
R126251_J0402R126251_J0402
R1231
R1231
NC_12.4K_F
NC_12.4K_F
0402
0402
12
R962 0_J0402R962 0_J0402
12
CLK_DP_P_R
CLK_DP_N_R
+1_05V_VTT
PM_EXTTS#0 20
PM_EXTTS#1 20,21
12
R1607
R1607
0_J
0_J
0402
0402
JTAG Mapping -Scan Chain (Default)
For Intel S3 Power Reduction issue
R5948 NC_0_J 0402R5948 NC_0_J 0402
12
Q72
Q72
2N7002W
2N7002W
null
null
S
S
D
D
DDR3_DRAMRST#_Q
12
R5949
R5949
100K_J
100K_J
0402
0402
2
DVT
G
G
1
RST_GATE15
DDR3_DRAMRST#
32
C6317
C6317
12
0.047U_16V_K
0.047U_16V_K
0402_X7R
0402_X7R
FOXCONN
FOXCONN
FOXCONN
Title
Title
Title
ARD (CLK,MISC,JTAG)
ARD (CLK,MISC,JTAG)
ARD (CLK,MISC,JTAG)
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
A3
A3
A3
M960&M970 H ModelSA
M960&M970 H ModelSA
M960&M970 H ModelSA
Date:Sheet
Date:Sheet
Date:Sheet
DDR_ALERT# 58
12
R1608
R1608
0_J
0_J
0402
0402
XDP_TDO_M
XDP_TDI_M
12
0402
0402
1K_J
1K_J
R5925
R5925
2
1
+1_05V_VTT
+3VRUN
12
R262
R262
4.7K_J
4.7K_J
0402
0402
61
Q14B
Q14B
D
D
G
G
S
S
+1_5VSUS
DDR3_DRAMRST# 20,21
A0205
2N7002DW
2N7002DW
null
null
12
R969
R969
0_J
0_J
0402
0402
G
G
5
DVT
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
CCPBG - R&D Division
For Disable Arrandale Graphic
In addition, FDI_RXN_[7:0] and FDI_RXP_[7:0] can be left floating on the PCH.
FDI_TX[7:0] and FDI_TX#[7:0] can be left floating on the Arrandale. The
GFX_IMON,FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and FDI_INT
signals on the Arrandale side should be tied to GND (through 1-kΩ ±5% resistors).
GFX_IMON
R1604
R1604
1K_J
1K_J
0402
0402
12
3A (VDDQ)
12
C1146
C1146
1U_10V_K
1U_10V_K
0603_X5R
0603_X5R
12
12
12
C941
C941
1U_10V_K
1U_10V_K
0603_X5R
0603_X5R
12
C1147
C1147
1U_10V_K
1U_10V_K
0603_X5R
0603_X5R
C940
C940
10U_10V_M
10U_10V_M
0805_X5R
0805_X5R
C830
C830
22U_6.3V_M
22U_6.3V_M
0805_X5R
0805_X5R
12
12
C939
C939
10U_10V_M
10U_10V_M
0805_X5R
0805_X5R
12
C942
C942
1U_10V_K
1U_10V_K
0603_X5R
0603_X5R
12
C1148
C1148
1U_10V_K
1U_10V_K
0603_X5R
0603_X5R
C829
C829
22U_6.3V_M
22U_6.3V_M
0805_X5R
0805_X5R
12
C943
C943
2.2U_10V_M
2.2U_10V_M
0603_X5R
0603_X5R
12
C1149
C1149
1U_10V_K
1U_10V_K
0603_X5R
0603_X5R
12
EVT
12
C944
C944
4.7U_10V_K
4.7U_10V_K
0805_X5R
0805_X5R
C1150
C1150
1U_10V_K
1U_10V_K
0603_X5R
0603_X5R
+1_05V_VTT
C832
C832
22U_6.3V_M
22U_6.3V_M
0805_X5R
0805_X5R
12
C833
C833
22U_6.3V_M
22U_6.3V_M
0805_X5R
0805_X5R
12
18A (SV) (VTT)
+1_05V_VTT
+1_8VRUN
EVT
12
C831
C831
22U_6.3V_M
22U_6.3V_M
0805_X5R
0805_X5R
EVT
12
+
CAP23
+
CAP23
NC_100U_6.3V_M
NC_100U_6.3V_M
3528
3528
1.35A (VCCPLL)
+1_5VRUN
PVT
EVT
CPU SOCKET_989P
CPU SOCKET_989P
FOX_PZ98927-3641-01F
FOX_PZ98927-3641-01F
DD
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
CCPBG - R&D Division
3393727 The VIL Voltage DC Specification for CFG[0] Pin is in Violation of the
EDS Value by a Large Amount
The Clarksfield EDS Vol1 documents the CFG[1:0] pins for PCI Express Port
Bifurcation, the straps may not work correctly when using a pull down resistor
of value other than 250 Ohms to drive a value of zero on the CFG[0] pin. When
left floating a value of one is sensed and there is no impact in this case.
DD
CFG0
12
R1272
R1272
NC_3.01K_F
NC_3.01K_F
0402
0402
CFG3 PCI Express Static Lane Reversal
CFG3 1 : Normal Operation
CC
BB
0 : Lane Numbers Reversed
15 ->0 , 14-> 1 , ...
CFG3
12
R1273
R1273
3.01K_F
3.01K_F
0402
0402
CFG4 Display Port Presence
CFG4 1 : Disabled ; No Physical Display Port
attached to Embedded Display Port
0 : Enable ; An external Display Port device
is connected to the Embedded Display Port
2611030 PCI Express Interface May Not Meet PCI Express 2.0 Jitter
Specifications
AA
Intel has determined that the workaround (3.01K pull down to Vss on
signal CFG[7]) is not robust. Intel recommends not implementing this
workaround at this time (CFG[7] should not be pulled down).
Intel recommends not to test for PCI-E Express 2.0 Jitter specification
compliance for the affected steppings.
5
4
HON HAI Precision Ind. Co., Ltd.
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FOXCONN
FOXCONN
FOXCONN
Title
Title
Title
ARD (RESERVED)
ARD (RESERVED)
ARD (RESERVED)
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
A3
A3
A3
M960&M970 H ModelSA
M960&M970 H ModelSA
M960&M970 H ModelSA
Date:Sheetof
Date:Sheet
3
2
Date:Sheet
HON HAI Precision Ind. Co., Ltd.
CCPBG - R&D Division
Low (0) – Flash Descriptor Security will be overridden. Also, when
this signals is sampled on the rising edge of PWROK then it will also
disable Intel ME and its features.
High (1) – Security measure defined in the Flash Descriptor will be
enabled
12
R158
R158
NC_4.7K_J
NC_4.7K_J
0402
0402
1
+3VRUN
G
G
12
32
D
D
S
S
R154
R154
1K_J
1K_J
0402
0402
Q12
Q12
2N7002W
2N7002W
null
null
R156
R156
12
0_J 0402
0_J 0402
HDA_DOCK_EN#
+ECVCC
R155
R155
100_J
100_J
0402
0402
FW_HW39
12
EXTERNAL SPI0 ROM INTERFACE(FOR U98)
+ECVCC
SPI0_CLK
SPI0_MOSI
SPI0_MISO_R
SPI_ROM_CS0#
12
CARD_INSERT0
SPI_ROM_CS0#
R542
R542
NC_10K_J
NC_10K_J
0402
0402
MB_FLASH0_EN
CARD_INSERT0
MB_FLASH0_EN15
12
11
10
PVT
53
1
2
R1551 0_J0402R1551 0_J0402
12
SMDFIX2
SMDFIX2
CN18
CN18
FOX_GB5RF120-1203-7F
FOX_GB5RF120-1203-7F
NC_FPC_12P
NC_FPC_12P
9
8
7
6
5
4
3
2
1
SMDFIX1
SMDFIX1
1314
+ECVCC
SPI0_CS#
4
U43
U43
NC_MC74HC1G32DTT1G
NC_MC74HC1G32DTT1G
DVT
12
C815
C815
NC_0.1U_16V_Y
NC_0.1U_16V_Y
0402_Y5V
0402_Y5V
MP
MP
EVT
FOXCONN
FOXCONN
FOXCONN
Title
Title
Title
Size Document NumberRev
Size Document NumberRev
Size Document NumberRev
Custom
Custom
Custom
Date:Sheet
Date:Sheet
2
Date:Sheet
1
12
R1613
R1613
NC_1K_J
NC_1K_J
0402
0402
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
CCPBG - R&D Division
2009/11/19 Add reserve 10k pull-low resistor for Intel FCIM function
EVT
12
Calpella Platform – Design Guide - Addendum /
Update – Rev. 1.52 (Doc #414044).).
XTAL_IN should be pulled to GND via a 0ohm by
default.
This pull-down resistor on XTAL_IN should only
be un-stuffed when 25MHz crystal is used.
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1186Tuesday, December 29, 2009
1186Tuesday, December 29, 2009
1186Tuesday, December 29, 2009
8
Page 12
1
AA
+1.05V_VCC_EXP
BB
2
DMI_RXN03
DMI_RXN13
DMI_RXN23
DMI_RXN33
DMI_RXP03
DMI_RXP13
DMI_RXP23
DMI_RXP33
DMI_TXN03
DMI_TXN13
DMI_TXN23
DMI_TXN33
DMI_TXP03
DMI_TXP13
DMI_TXP23
DMI_TXP33
R87449.9_F0402R87449.9_F0402
12
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_COMP
3
BC24
BJ22
AW20
BJ20
BD24
BG22
BA20
BG20
BE22
BF21
BD20
BE18
BD22
BH21
BC20
BD18
BH25
BF25
U69C
U69C
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
DMI_ZCOMP
DMI_IRCOMP
DMI
DMI
4
FDI
FDI
5
For Disable Arrandale Graphic
In addition, FDI_RXN_[7:0] and FDI_RXP_[7:0] can be left floating on the PCH.
FDI_TX[7:0] and FDI_TX#[7:0] can be left floating on the Arrandale. The
GFX_IMON,FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and FDI_INT
signals on the Arrandale side should be tied to GND (through 1-kΩ ±5% resistors).
Ball AH16:
For M96 this pin NC.
For Madison-M2 and Park-M2
the PWRGOOD ball must be conneccted to ground.
For M97-M2 PWRGOOD input must be provided externally.
5
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CCPBG - R&D Division
AC (Performance mode) = 3.3 V
Battery saving mode = 0.0 V
Power Control signals control the core voltage regulator.
At Reset, these signals will be inputs with weak internal pull-down resistors.
VBIOS can define these signals to be either 3.3-V outputs or open drain outputs.
The output state (high/low) of these signals is programmable for each PowerPlay state.
When GPIO_21_BB_EN = 0 V, then back bias is disabled on the PCB (i.e. BPP = VDDC).
When GPIO_21_BB_EN = 3.3 V, then back bias is enabled on the PCB (i.e. BPP = VDDC +Offset).
Can function as a GPIO if not required for BB control.
Active high.
If not needed as the backlight enable signal, it can alternatively be used as a GPIO or an open drain type output.
Note: External pull-down recommended
1: The device will not be recognized as the system’s VGA controller
If BIOS_ROM_EN = 0, then Config[2:0] defines the primary memory aperture size.
0: Disable external BIOS ROM device
1: Enable external BIOS ROM device
down spread of -2.5%). Requires a spread version of 27 MHz(The modulation rate is 30-50 KHz.)
1) An input from an external temperature sensor (ALERTb) , or
2) An output signaling that the ASIC temp (measured by the internal sensor) is above the high
threshold or below the low threshold.Output can be open drain or 3.3-V output.(active low by default)
RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE
BB
1 Enable HD Audio
0 Disable HD Audio
1 Enable HDMI
0 Disable HDMI
AA
5
ATI_DAC1VSYNC24,34
ATI_DAC1HSYNC24,34
R5774 10K_J0402R5774 10K_J0402
12
R108
R108
NC_10K_J
NC_10K_J
0402
0402
12
R116 10K_J0402R116 10K_J0402
12
R5775
R5775
NC_10K_J
NC_10K_J
0402
0402
12
4
HON HAI Precision Ind. Co., Ltd.
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CCPBG - R&D Division
CCPBG - R&D Division
FOXCONN
FOXCONN
FOXCONN
Title
Title
Title
VGA (Strap) 2/6
VGA (Strap) 2/6
VGA (Strap) 2/6
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
A3
A3
A3
M960&M970 H ModelSA
M960&M970 H ModelSA
M960&M970 H ModelSA
Date:Sheet
Date:Sheet
3
2
Date:Sheet
CCPBG - R&D Division
2386Tuesday, December 29, 2009
2386Tuesday, December 29, 2009
1
2386Tuesday, December 29, 2009
of
of
of
Page 24
1
AA
EVT
MEM ID
Ball AM17:
For M96 this pin can be not used.
For M97-M2 When PWRGOOD is deasserted, the CTF
will return to its default state (high impedance)
For Park-M2 and Madison-M2:
GPIO_19_CTF has an internal latch, such
that if the pad has been operating normally,
and then the internal PWRGOOD deasserts
(because CTF was triggered), the GPIO_19 will
continue to drive high to keep the
VDDC regulator shut down.
Clearing this state will require power-cycling
of the VDDR3 rail.
BB
These two can be unused on M96,M97,Madison and Park.
Ball AH26:
For M97-M2 GENERICF (no HPD function).
For Park-M2 NC.
For Madison-M2 GENERICF- can provide HPD5 function
Ball AH24:
For M97-M2 GENERICF (no HPD function).
For Park-M2 NC.
For Madison-M2 GENERICF- can provide HPD6 function
PWRCNTL_080
R_XTALSSIN19
09/11/17 Connect a stable clock source
(from clock gen SS 27MHz)
to GPIO26_TCK.
CC
DEPENDING ON OSC USED
SELECT VOLTAGE DIVIDER
RESISTOR VALUES C AND B
TO ENSURE XTALIN VOLTAGE
LEVEL OF 1.8V
R5793
R5793
12
R6003
R6003
NC_1M_J
NC_1M_J
0402
0402
DVT
ATI_XTALIN_R
12
1
12
100_F
100_F
0402
0402
R6002
R6002
12
NC_0_J 0402
NC_0_J 0402
Y9
Y9
NC_27MHZ_20P_30PPM
NC_27MHZ_20P_30PPM
ITTI_L5030-27.000-20
ITTI_L5030-27.000-20
R_XTALIN19
PVT
C6342
C6342
12
NC_22P_50V_J
NC_22P_50V_J
0402_NPO
0402_NPO
C6343
C6343
DD
12
NC_22P_50V_J
NC_22P_50V_J
0402_NPO
0402_NPO
Reserve for Intel FCIM function
R57840_J 0402R57840_J 0402
OVT_GFX#39,58
PWRCNTL_180
TP1115 26MILTP1115 26MIL
+3V3_DELAY
R6001
R6001
R_XTALSSINR_XTALSSIN_R
TP1107
TP1107
26MIL
26MIL
EVT
+1_8VRUN
12
R5790
R5790
499_F
499_F
0402
0402
12
R5791
R5791
249_F
249_F
0402
0402
12
R5794
R5794
120_F
120_F
0402
0402
DVT
ATI_XTALIN
ATI_XTALOUT
For M96 these two pins connect to GND.
GND Option If XO_IN/XO_IN2 not used
For M97, XO_IN and XO_IN2 should be grounded
Ball AW34:
For M97-M2 GND
For Madison-M2 and Park-M2 27MHz oscillator can be resvered.
Ball AW35:
For M97-M2 DPE_VSSR
For Madison-M2 and Park-M2 100MHz oscillator can be resvered.
DP_D channel is available for M97-M2,Madison-M2,M96-M2.
DP Channel D is NC on Park.
R5776 0_J0402R5776 0_J0402
R5777 0_J0402R5777 0_J0402
R5778 0_J0402R5778 0_J0402
ATI_DAC1HSYNC 23,34
ATI_DAC1VSYNC 23,34
499_F
499_F
12
R5782
AVDD
VDD1DI
1 2
C60900.1U_6.3V_K0402_X5RC60900.1U_6.3V_K0402_X5R
1 2
C60910.1U_6.3V_K0402_X5RC60910.1U_6.3V_K0402_X5R
1 2
C60920.1U_6.3V_K0402_X5RC60920.1U_6.3V_K0402_X5R
1 2
C60930.1U_6.3V_K0402_X5RC60930.1U_6.3V_K0402_X5R
1 2
C60940.1U_6.3V_K0402_X5RC60940.1U_6.3V_K0402_X5R
1 2
C60950.1U_6.3V_K0402_X5RC60950.1U_6.3V_K0402_X5R
1 2
C60960.1U_6.3V_K0402_X5RC60960.1U_6.3V_K0402_X5R
1 2
12
12
12
PLACE OR RESISTORS CLOSE TO ASIC
0402R5782
0402
ATI_DAC1RED 34
ATI_DAC1RED_RB 34
ATI_DAC1GREEN 34
ATI_DAC1GREEN_GB 34
ATI_DAC1BLUE 34
ATI_DAC1BLUE_BB 34
MP
EVT
VDD1DI
VDD3
A2VDDQ
12
R5792 715_F 0402R5792 715_F 0402
ATI_CRT_SCL 34
ATI_CRT_SDA 34
DVT
For Park-M2:
DDC/Aux Pairs 1,2,3,5,6 are available
DDC/Aux Pair 4,7 is not connected.
For M96-M2,M97-M2,Madison-M2:
DDC/Aux Pairs 1,2,3,4,5,6 are available
DDC/Aux Pair 7 is not connected.
ATI_HDMI_SCL 38
ATI_HDMI_SDA 38
4
ATI_HDMI_TXCA 38
ATI_HDMI_TXCA# 38
ATI_HDMI_D0 38
ATI_HDMI_D0# 38
ATI_HDMI_D1 38
ATI_HDMI_D1# 38
ATI_HDMI_D2 38
ATI_HDMI_D2# 38
OPTIONAL STRAP TO GROUND
FOR RB,GB,BB
SEE DAC1_RGB SHEET
5
ATI_DAC1RED
ATI_DAC1GREEN
12
R5780
R5780
150_F
150_F
0402
0402
NC_10K_J
NC_10K_J
12
NC_10K_J
NC_10K_J
12
NC_10K_J
NC_10K_J
12
NC_10K_J
NC_10K_J
12
ATI_DAC1BLUE
12
R5781
R5781
150_F
150_F
0402
0402
0402R5906
0402
0402R5907
0402
0402R5909
0402
0402R5908
0402
12
R5779
R5779
150_F
150_F
0402
0402
OPTIONAL STRAP TO GROUND
FOR R2B,G2B,B2B
SEE DAC2_RGB SHEET
IF Y,C,COMP OR R2,G2,B2 ARE USED
R2B,G2B,B2B MUST BE CONNECTED
TO GROUND OR TERMINATED AT
CONNECTOR
DAC2 CAN BE TV SIGNALS (C,Y,COMP) OR SECONDARY CRT (R2,B2,G2
SIGNALS AS CONTROLLED BY AN INTERNAL MUX
ATI_JTAG_RST
ATI_JTAG_TDI
ATI_JTAG_TMS
R_XTALSSIN
R5906
R5907
R5909
R5908
5
+3V3_DELAY
6
ATI_JTAG_RST
R5991
NC_10K_J
NC_10K_J
12
7
8
PVT
0402R5991
0402
EVT
09/11/17 Add 5991 pull-down with 10K ohm to ground for the Park/Madison JTAG test block
intermittently fails to initialize correctly. Incorrect initialization may
result in a failure to boot.
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
FOXCONN
FOXCONN
FOXCONN
Title
Title
Title
VGA (I/O) 3/6
VGA (I/O) 3/6
VGA (I/O) 3/6
Size Document NumberRev
Size Document NumberRev
Size Document NumberRev
A2
A2
A2
M960&M970 H Model
M960&M970 H Model
M960&M970 H Model
Date:Sheet
Date:Sheet
6
7
Date:Sheet
HON HAI Precision Ind. Co., Ltd.
CCPBG - R&D Division
HON HAI Precision Ind. Co., Ltd.
CCPBG - R&D Division
CCPBG - R&D Division
FOXCONN
FOXCONN
FOXCONN
Title
Title
Title
VGA (LVDS) 5/6
VGA (LVDS) 5/6
VGA (LVDS) 5/6
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
A3
A3
A3
M960&M970 H ModelSA
M960&M970 H ModelSA
M960&M970 H ModelSA
Date:Sheet
Date:Sheet
1
2
3
4
5
6
Date:Sheet
7
CCPBG - R&D Division
2686Tuesday, December 29, 2009
2686Tuesday, December 29, 2009
2686Tuesday, December 29, 2009
8
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Page 27
5
+1_5VRUN
12
12
C6206
C6206
C6207
C6207
0.1U_6.3V_K
0.1U_6.3V_K
0.1U_6.3V_K
0.1U_6.3V_K
0402_X5R
0402_X5R
0402_X5R
0402_X5R
12
12
C6214
C6214
C6215
C6215
1U_6.3V_M
1U_6.3V_M
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
0402_X5R
0402_X5R
DD
+3VRUN+3V3_DELAY
R5826 75K_J 0402R5826 75K_J 0402
CC
+1_8VRUN
470R-100MHZ_1608
470R-100MHZ_1608
HCB1608KF-471T10
HCB1608KF-471T10
BB
+1_0VPEG
120R-100MHZ_0402
120R-100MHZ_0402
EBMS100505A121 0.5A
EBMS100505A121 0.5A
RUN_ON139,75,76,77,80,81
(Park: 1.8V@75mA MPV18)
L90
L90
(M97, Broadway and Madison: 1.8V@150mA MPV18)
12
C6196
C6196
10U_6.3V_M
10U_6.3V_M
0603_X5R
0603_X5R
L48
L48
12
C6153
C6153
0.1U_16V_M
0.1U_16V_M
0402_X5R
0402_X5R
Optional RC network
to fine tune power sequence
+1_5VRUN
+1_5VRUN
Place all decoupling caps close to the ASIC and RUN
dedicated traces from ASIC pins to join the ground
plane with one VIA at the cap
12
12
C6195
C6195
C6194
C6194
1U_6.3V_M
1U_6.3V_M
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
0402_X5R
0402_X5R
(1.1V @ 200 mA DPA_VDD10)
12
12
C543
C543
10U_6.3V_M
10U_6.3V_M
0603_X5R
0603_X5R
C555
C555
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
12
12
12
C6209
C6209
C6208
C6208
0.1U_6.3V_K
0.1U_6.3V_K
0.1U_6.3V_K
0.1U_6.3V_K
0402_X5R
0402_X5R
0402_X5R
0402_X5R
12
12
C6113
C6113
C6107
C6107
1U_6.3V_M
1U_6.3V_M
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
0402_X5R
0402_X5R
Co-lay for R5822 and Q76 pin2,3
R5822 NC_0_J 0603R5822 NC_0_J 0603
12
23
D
S
D
S
12
G
G
Q76
Q76
R5823
R5823
1
CHT2301PT
CHT2301PT
100K_J
100K_J
0402
0402
32
Q77
Q77
D
D
1
G
G
S
S
12
2N7002W
2N7002W
null
null
M96/92 ONLY
L76
L76
VDDRHA
NC_120R-100MHZ_0402
NC_120R-100MHZ_0402
NC_120R-100MHZ_0402
NC_120R-100MHZ_0402
EBMS100505A121 0.5A
EBMS100505A121 0.5A
L77
L77
EBMS100505A121 0.5A
EBMS100505A121 0.5A
12
VDDRHB
12
C6155
C6155
NC_1U_6.3V_M
NC_1U_6.3V_M
0402_X5R
0402_X5R
C6158
C6158
NC_1U_6.3V_M
NC_1U_6.3V_M
0402_X5R
0402_X5R
DVT
12
12
C6192
C6192
C6193
C6193
0.1U_6.3V_K
0.1U_6.3V_K
0.1U_6.3V_K
0.1U_6.3V_K
0402_X5R
0402_X5R
0402_X5R
0402_X5R
DPAB_VDD10
C569
C569
0.1U_6.3V_K
0.1U_6.3V_K
0402_X5R
0402_X5R
EVT
EVT
L3
L3
+1_8VRUN
120R-100MHZ_0402
120R-100MHZ_0402
EBMS100505A121 0.5A
EBMS100505A121 0.5A
+1_8VRUN
120R-100MHZ_0402
120R-100MHZ_0402
EBMS100505A121 0.5A
EBMS100505A121 0.5A
AA
+1_8VRUN
120R-100MHZ_0402
120R-100MHZ_0402
EBMS100505A121 0.5A
EBMS100505A121 0.5A
+1_8VRUN
120R-100MHZ_0402
120R-100MHZ_0402
EBMS100505A121 0.5A
EBMS100505A121 0.5A
(3.3V @ 2mA A2VDDQ)
12
12
C530
C530
C84
C84
10U_6.3V_M
10U_6.3V_M
0.1U_6.3V_K
0.1U_6.3V_K
0603_X5R
0603_X5R
0402_X5R
L7
L7
( 1.8V @ 100MA VDD1DI)
L86
L86
(1.8V @ 70mA AVDD)
L50
L50
(1.8V @ 120mA DPLL_PVDD)
12
C538
C538
10U_6.3V_M
10U_6.3V_M
0603_X5R
0603_X5R
12
C521
C521
10U_6.3V_M
10U_6.3V_M
0603_X5R
0603_X5R
12
C542
C542
10U_6.3V_M
10U_6.3V_M
0603_X5R
0603_X5R
0402_X5R
12
C6169
C6169
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
12
C519
C519
0.1U_6.3V_K
0.1U_6.3V_K
0402_X5R
0402_X5R
12
C552
C552
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
5
12
C71
C71
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
12
C126
C126
0.1U_6.3V_K
0.1U_6.3V_K
0402_X5R
0402_X5R
12
C520
C520
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
12
C564
C564
0.1U_6.3V_K
0.1U_6.3V_K
0402_X5R
0402_X5R
A2VDDQ
VDD1DI
AVDD
DPLL_PVDD
VDDR1+VDDRHA
M71-S 1.1A(GDDR3 VRAM)
12
12
12
12
12
C6216
C6216
10U_6.3V_M
10U_6.3V_M
0805_X5R
0805_X5R
C6210
C6210
0.1U_6.3V_K
0.1U_6.3V_K
0402_X5R
0402_X5R
C6118
C6118
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
C6211
C6211
0.1U_6.3V_K
0.1U_6.3V_K
0402_X5R
0402_X5R
12
C6114
C6114
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
12
C6115
C6115
10U_6.3V_M
10U_6.3V_M
0805_X5R
0805_X5R
C6212
C6212
0.1U_6.3V_K
0.1U_6.3V_K
0402_X5R
0402_X5R
12
C6110
C6110
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
12
C6116
C6116
10U_6.3V_M
10U_6.3V_M
0805_X5R
0805_X5R
DVT
MPV18:
(Park: 1.8V@75mA MPV18)
(M97, Broadway and Madison: 1.8V@150mA MPV18)
For M96 no connect.
SPV18:
M97, Broadway, Madison and Park only.
For M96 no connect.
VDDRHA
VDDRHB
MPV18
+1_8VRUN
+1_8VRUN
+1_8VRUN
PCIE_VDDC
VDD_CORE
+3V3_DELAY
EVT
+1_8VRUN
+1_0VPEG
(For M96 SPV10 = VDDC)
(For M97, Broadway, Madison and Park
SPV10 = PCIE_VDDC)
XO_IN: 27MHz (3.3V tolerant) oscillator clock input.
Can be connected to ground if unused.
XO_IN2: 100MHz (3.3V tolerant) oscillator clock input.
Can be connected to ground if unused.
Recommended Clock Inputs Configuration – GDDR3/DDR3
a) 27MHz (± 30 ppm) crystal connected to XTALIN/XTALOUT, or
b) 27MHz (1.8V) oscillator connected to XTALIN, or
c) 27MHz (3.3V) oscillator connected to XO_IN (Park,
DPF_PVDD
Madison, and Broadway
only)
DVT
12
C180
C180
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
C6236
C6236
0.1U_6.3V_K
0.1U_6.3V_K
0402_X5R
0402_X5R
DPAB_VDD18
12
12
C6163
C6163
C172
C172
1U_6.3V_M
1U_6.3V_M
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
0402_X5R
0402_X5R
For M97,Madison,Park Only,for M96 no connect.
DVT
VDD_CORE
12
C6127
C6127
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
12
C6139
C6139
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
12
C6152
C6152
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
12
C6129
C6129
10U_6.3V_M
10U_6.3V_M
0805_X5R
0805_X5R
12
C6226
C6226
10U_6.3V_M
10U_6.3V_M
0805_X5R
0805_X5R
12
C6128
C6128
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
12
C6140
C6140
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
12
C6154
C6154
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
12
C6141
C6141
10U_6.3V_M
10U_6.3V_M
0805_X5R
0805_X5R
12
C6294
C6294
22P_50V_J
22P_50V_J
0402_NPO
0402_NPO
12
12
12
C6130
C6130
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
C6143
C6143
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
C6220
C6220
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
12
C6131
C6131
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
12
C6144
C6144
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
12
C6221
C6221
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
12
C6147
C6147
10U_6.3V_M
10U_6.3V_M
0805_X5R
0805_X5R
For RF noise
12
12
12
12
C6222
C6222
10U_6.3V_M
10U_6.3V_M
0805_X5R
0805_X5R
C6132
C6132
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
C6145
C6145
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
C6217
C6217
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
12
C6133
C6133
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
12
C6146
C6146
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
12
C6218
C6218
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
12
C6223
C6223
10U_6.3V_M
10U_6.3V_M
0805_X5R
0805_X5R
12
C6134
C6134
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
12
C6148
C6148
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
12
C6219
C6219
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
EVT
For M97/M96, DPF_VDD18 can be shared with DPE_VDD18
For M97/M96, DPF_VDD10 can be shared with DPE_VDD10
EVT
C6182
C231
C231
C6179
C6179
C6178
C6178
1U_6.3V_M
1U_6.3V_M
1U_6.3V_M
1U_6.3V_M
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
0402_X5R
0402_X5R
0402_X5R
0402_X5R
12
12
12
12
C6183
C6183
C6184
C6184
10U_6.3V_M
10U_6.3V_M
0603_X5R
0603_X5R
DPA_PVDD
DPE_PVDD
For M97,Madison and Park(GDDR3/DDR3 1.12V@4A VDDCI)
10U_6.3V_M
10U_6.3V_M
For M96/92, 0.95V-1.1V@2A VDDCI
0603_X5R
0603_X5R
L89
L89
+1_8VRUN
120R-100MHZ_0402
120R-100MHZ_0402
EBMS100505A121 0.5A
EBMS100505A121 0.5A
+1_0VPEGPCIE_VDDC
L5
L5
120R-100MHZ_0603
120R-100MHZ_0603
ACMS160808A121 RDC05
ACMS160808A121 RDC05
For M96/M92 PEG = 1.1V
For M97,Madison and Park PEG = 1.0V
HON HAI Precision Ind. Co., Ltd.
CCPBG - R&D Division
CCPBG - R&D Division
FOXCONN
FOXCONN
FOXCONN
Title
Title
Title
SWITCH (BOTTON & KB LED)
SWITCH (BOTTON & KB LED)
SWITCH (BOTTON & KB LED)
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
A3
A3
A3
M960&M970 H ModelSA
M960&M970 H ModelSA
M960&M970 H ModelSA
Date:Sheet
Date:Sheet
5
4
3
2
Date:Sheet
CCPBG - R&D Division
6286Thursday, December 24, 2009
6286Thursday, December 24, 2009
1
6286Thursday, December 24, 2009
of
of
of
Page 63
A
DVDD_IO can be either 1.5V or 3.3V Resume well
power, regardless iHDMI is implemented or not.
However, external codec/MDC must have the same
voltage level as PCH VCCSUSHDA power.
09/11/21 Add PC584 680pf,PC585 0.1uf near PQ26 for
EMI request.
1A
12
+5VRUN
3
S
S
2
1
G
G
4
PVT
PC584
PC584
680P_50V_K
680P_50V_K
0603_X7R
0603_X7R
RUN_ON127,39,75,76,77,80
4.5A
tpc40t_50
tpc40t_50
TP180
TP180
12
PC188
PC188
1U_10V_K
1U_10V_K
0603_X5R
0603_X5R
+3VRUN
12
12
PC585
PC585
0.1U_50V_K
0.1U_50V_K
0603_X7R
0603_X7R
1
PVT
tpc40t_50
tpc40t_50
TP179
TP179
4A
1
PC117
PC117
NC_10U_6.3V_M
NC_10U_6.3V_M
0805_X5R
0805_X5R
12
PR192
PR192
100_J
100_J
0402
0402
12
C6334
C6334
NC_680P_50V_K
NC_680P_50V_K
0603_X7R
0603_X7R
RUN_ON1#76
1
12
PC108
PC108
NC_10U_6.3V_M
NC_10U_6.3V_M
0805_X5R
0805_X5R
+12V_1
12
PR131
PR131
100K_J
100K_J
0402
0402
61
PQ29B
PQ29B
D
D
G
G
S
S
null
null
TP184 tpc40t_50TP184 tpc40t_50
12
For EMI
RUN_ON_LOAD
12
2N7002DW
2N7002DW
PC120
PC120
0.01U_25V_M_B
0.01U_25V_M_B
0402
0402
C6332
C6332
680P_50V_K
680P_50V_K
0603_X7R
0603_X7R
+5VALW
+3VALW
12
C6333
C6333
680P_50V_K
680P_50V_K
0603_X7R
0603_X7R
PQ47
PQ47
SI7326DN-T1-E3
SI7326DN-T1-E3
D
D
5
PR128
PR128
NC_470K_J
NC_470K_J
0603
0603
5
3
S
S
2
1
G
G
4
12
PQ27
PQ27
SI7326DN-T1-E3
SI7326DN-T1-E3
D
D
G
G
5
12
12
PR189
PR189
100K_J
100K_J
0402
0402
RUN_ON1#
34
PQ45A
PQ45A
D
D
S
S
2N7002DW
2N7002DW
null
null
PQ71A
PQ71A
ME2N7002KW
ME2N7002KW
RUN_ON1#
C6335
C6335
NC_680P_50V_K
NC_680P_50V_K
0603_X7R
0603_X7R
G
G
2
12
C6336
C6336
NC_680P_50V_K
NC_680P_50V_K
0603_X7R
0603_X7R
12
PR193
PR193
100K_J
100K_J
0402
0402
61
PQ45B
PQ45B
D
D
S
S
PVT
ON_1_5VRUN
12
PC173
PC173
2N7002DW
2N7002DW
0.047U_16V_K
0.047U_16V_K
null
null
0402_X7R
0402_X7R
+0_75VRUN+1_5VRUN
12
PR661
PR661
33_F
33_F
0402
0402
34
D
D
G
G
5
S
S
PQ44
PQ44
IRFH3707PBF
IRFH3707PBF
3
PQ71B
PQ71B
ME2N7002KW
ME2N7002KW
2
1
+1_5VRUN+1_5VSUS+5VALW+12V_1
7A
TP152
D
D
S
S
1
G
G
12
PC177
12
61
D
D
S
S
PR194
PR194
PR660
PR660
330_J
330_J
0603
0603
NC_470K_J
NC_470K_J
PC177
NC_10U_6.3V_M
NC_10U_6.3V_M
0805_X5R
0805_X5R
0603
0603
2
12
G
G
1
TP152
tpc40t_50
tpc40t_50
For EMI
AA
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
CCPBG - R&D Division
CCPBG - R&D Division
FOXCONN
FOXCONN
FOXCONN
Title
Title
Title
Others power plan
Others power plan
Others power plan
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
A3
A3
A3
M960&M970 H ModelSA
M960&M970 H ModelSA
M960&M970 H ModelSA
Date:Sheet
Date:Sheet
5
4
3
2
Date:Sheet
CCPBG - R&D Division
8193Tuesday, December 29, 2009
8193Tuesday, December 29, 2009
1
8193Tuesday, December 29, 2009
of
of
of
Page 82
5
4
3
2
1
PQ33B
12
0805_X5R
0805_X5R
PC43
2.2U_10V_M
PC43
2.2U_10V_M
B
B
1
1
NC_0.1U_6.3V_K
NC_0.1U_6.3V_K
BQ24753A_IADAPT71
BT+
VHCORE
3
32
D
D
S
S
1
PQ9
PQ9
2N7002W
2N7002W
null
null
+1_05V_VTT
PD15
PD15
CHN222PT
CHN222PT
UL_IN#
21
12
12
32
C
C
E
E
PQ11
PQ11
2PC4617Q
2PC4617Q
12
PR40
PR40
10K_F
10K_F
0402
0402
12
PR30
PR30
100K_F
100K_F
0402
0402
PD17
MMSZ5234BPT
PD17
MMSZ5234BPT
PR172
PR172
27K_F
27K_F
0402
0402
PR171
PR171
18.2K_F
18.2K_F
0402
0402
2
1
G
G
PWRLIMIT Protect
PC46
PC46
0402_X5R
0402_X5R
12
BQ24753A_IADAPT
2
1
PD11
PD11
CF_CHN222PT
CF_CHN222PT
3
12
PR380_J 0402PR380_J 0402
2
3
1
PD18
PD18
NC_CHN222PT
NC_CHN222PT
AC_OFF_3#
PU31
PU31
1
2
3
NC_FP9922S6GTR
NC_FP9922S6GTR
PWRLIMIT_FB
4
TCAP
VSS
VIP
PR78
PR78
NC_0_J
NC_0_J
0402
0402
VCC
VO#
PR141
PR141
0_J
0_J
0402
0402
12
VIN
DC_IN_MOS
DC_IN
BT+
PQ35A
PQ35A
PUMB2.115
PUMB2.115
null
null
B
B
5
A6005A6011
12
A6009
PR139
PR139
200K_J
200K_J
12
0402
0402
PR137
PR137
200K_J
200K_J
0402
0402
A6012
3
1
MAIN_DC_SW_OFF#
PC567
PC567
NC_2.2U_10V_M0603_X5R
NC_2.2U_10V_M0603_X5R
12
12
PR651
PR651
NC_39.2K_F
NC_39.2K_F
0402
0402
+5VALW_LDO_R
6
G1336_VOUT1
5
G1336_VIN
4
12
PR629 NC_0_J 0402PR629 NC_0_J 0402
PR219
PR219
12
NC_10K_F
NC_10K_F
0402
0402
12
PC48
0402_X5RPC48
0402_X5R
NC_0.1U_6.3V_K
NC_0.1U_6.3V_K
VCCRTC
PD9
PD9
MMSZ5234BPT
MMSZ5234BPT
DC_IN_MOS
4
E
E
C
C
3
PQ35B
PQ35B
PUMB2.115
PUMB2.115
2
B
B
61
DC_IN_G1 ACDRV#
PD20
PD20
BAT54WAPT
BAT54WAPT
2
PR223
PR223
NC_0_J
NC_0_J
0402
0402
12
PR218
PR218
12
NC_45.3K_F
NC_45.3K_F
0402
0402
12
PR16
PR16
1K_J
1K_J
0402
0402
23
S
S
G
G
1
A6006
null
null
E
E
12
C
C
12
+5VALW_LDO
+5VALW_LDO
3
PC21
PC21
0.1U_6.3V_K
0.1U_6.3V_K
12
0402_X5R
0402_X5R
21
UL_IN#
17
PU1A
PU1A
74AHC3G14DC
74AHC3G14DC
12
84
12
PR10
PR10
100K_J
100K_J
0402
0402
PJ15 Near the DDR socket door
PQ3
PQ3
PR6
PR6
PRG18BB330MB1RB
PRG18BB330MB1RB
A6007
12
D
D
SI2303BDS
SI2303BDS
PD6
PD6
MMVZ5231BPT
MMVZ5231BPT
21
PR140
PR140
10K_F
10K_F
0402
0402
A6008
12
PR3
PR3
47K_J
47K_J
0402
0402
G
G
5
System SCP Protect
PWRLIMIT#
PWRLIMIT# 39
PD8
PD8
CH520S-30PT
CH520S-30PT
PJ15
PJ15
OPEN_JUMP_OPEN2
OPEN_JUMP_OPEN2
A6010
34
D
D
S
S
PQ4A
PQ4A
2N7002DW
2N7002DW
PR23
PR23
10K_J
10K_J
0402
0402
12
21
12
PC19
PC19
PR2
PR2
100K_J
100K_J
0402
0402
12
MAIN_DC_SW_OFF#
G
G
2
0402_X5R
0402_X5R
0.1U_6.3V_K
0.1U_6.3V_K
61
D
D
S
S
12
0402
0402
470K_J
470K_J
PR21
PR21
DC_IN_R
DC_IN_MOS
12
PD5
PD5
1SS400PT
1SS400PT
PQ4B
PQ4B
2N7002DW
2N7002DW
35
12
PC18
PC18
1U_6.3V_M
1U_6.3V_M
0402_X5R
0402_X5R
2
1
12
MMHZ5234BPT
MMHZ5234BPT
PVT
+5VALW
12
PC190
PC190
0402_X5R
0402_X5R
0.1U_6.3V_K
0.1U_6.3V_K
PC36
PC36
0.1U_6.3V_K
0.1U_6.3V_K
0402_X5R
0402_X5R
12
PR168
PR168
27K_F
27K_F
0402
0402
12
PR167
PR167
26.1K_F
26.1K_F
0402
0402
SC70_CD
12
PC41
PC41
1000P_50V_K
1000P_50V_K
0402_X7R
0402_X7R
2
1
PD14
PD14
3
CHN222PT
CHN222PT
PR88
PR88
100K_J
100K_J
0402
0402
12
4
5
S-80925CNMC-G8V-T2G
S-80925CNMC-G8V-T2G
+3VALW+1_5VSUS
PU4
PU4
12
PR170
PR170
27K_F
27K_F
0402
0402
12
PR169
PR169
80.6K_F
80.6K_F
0402
0402
2
NC
VDD
OUT
CD
VSS
3
+0_75VRUNVDD_CORE
DD
2
PD16
PD16
3
CHN222PT
CHN222PT
12
PR31
PR31
1K_J
1K_J
0603
0603
21
PD12
CC
PD12
System OVP protect
09/11/13 change pc41 from 1000P_16V_0402_X7R to
1000pF_50V_0402_X7R for MOR request
PWRLIMIT_FB
32
PQ17
BB
PQ17
NC_2N7002W
NC_2N7002W
null
null
D
D
1
G
G
S
S
EC_PWRLIMIT_CTRL 39,71
L --> 75W
H --> 64W
DVT
For Power limit
DVT
H M/B(75W)
L M/B(64W)
AA
PQ17PR218 PR78
NC68.1K 2.05K
PWRLIMIT
3.76A/71.41W
3.2A/60.82W
5
84
PU1C
PU1C
74AHC3G14DC
74AHC3G14DC
ALW_ON 39,74
PQ33B
2N7002DW
2N7002DW
61
D
D
G
G
2
S
S
84
62
PU1B
PU1B
74AHC3G14DC
74AHC3G14DC
ALW_ON
Battery UVP Protect
FOXCONN
FOXCONN
FOXCONN
Title
Title
Title
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
A3
A3
A3
Date:Sheet
Date:Sheet
Date:Sheet
SYS_PRS# 71
PS_ERR#
PQ33A
PQ33A
2N7002DW
2N7002DW
PD30
PD30
1SS400PT
1SS400PT
34
D
D
G
G
5
S
S
+5VALW_LDO
PR227
PR227
100K_J
100K_J
0402
0402
12
S80925C_OUT
12
S-80925CNMC-G8V-T2G
S-80925CNMC-G8V-T2G
OVP protection
OVP protection
OVP protection
M960&M970 H ModelSA
M960&M970 H ModelSA
M960&M970 H ModelSA
PD2 1SS355PTPD2 1SS355PT
12
PD1 NC_1SS355PTPD1 NC_1SS355PT
12
2
1
OUT
3
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
CCPBG - R&D Division
CCPBG - R&D Division
CCPBG - R&D Division
ALW_ON
S80925C_VDD
PU15
PU15
NC
VDD
CD
VSS
PC195
PC195
0.01U_10V_K
0.01U_10V_K
0402_X7R
0402_X7R
1
AC_OFF_3# 71
DCBATOUT
2
PD29
PD29
CHN222PT
CHN222PT
4
5
12
8293Tuesday, December 29, 2009
8293Tuesday, December 29, 2009
8293Tuesday, December 29, 2009
3
12
12
of
of
of
BT+
1
PR225
PR225
215K_F
215K_F
0402
0402
PR226
PR226
100K_F
100K_F
0402
0402
Page 83
A
B
C
D
E
Wireless cardBlue Tooth
null
null
null
BOSS_4x5.2
BOSS_4x5.2
null
BOSS_3.8x4
BOSS_3.8x4
EVT
BOSS3
BOSS1
BOSS1
44
SystemThermalKB
H1
H1
1
1
hole_tsh236x315bsh315x315d98u
hole_tsh236x315bsh315x315d98u
H2
H2
1
1
DVT
hole_tsh236x315bsh354x315d98
hole_tsh236x315bsh354x315d98
hole_tsh236x260bsh315x374d98
H4
H4
hole_tr236x260br406x315d98
hole_tr236x260br406x315d98
1
33
1
PVT
hole_tsh236x260bsh315x374d98
H5
H5
1
1
1
H3
H3
1
1
EVTDVT
hole_tsh236x315bsh354x315d98u
hole_tsh236x315bsh354x315d98u
H6
H6
1
1
EVTDVT
hole_tsh236x315bsh354x315d98
hole_tsh236x315bsh354x315d98
MP
H31
H31
1
1
hole_tsh236x315bsh315x315d98
hole_tsh236x315bsh315x315d98
BOSS3
DVT
null
null
BOSS_3.8x4
BOSS_3.8x4
BOSS4
1
BOSS4
1
H7
H7
PTH
PTH
NPTH
NPTH
2
hole_tshbs315x236d98do106x98n
hole_tshbs315x236d98do106x98n
1
EVT
H9
H9
hole_tsh236x315bsh315x236d98
hole_tsh236x315bsh315x236d98
1
1
AMI Label (For MP Only)
H8
H8
hole_tsh236x315bshaped98_30
hole_tsh236x315bshaped98_30
1
1
PVT
LABLE1
LABLE1
AMI-APTIO
AMI-APTIO
MP
H10
H10
hole_tc236br236x315d98
hole_tc236br236x315d98
1
1
PVT
ODD BKT
H14
H14
hole_tsh270x236bsh309x315d98
hole_tsh270x236bsh309x315d98
1
1
EVT
22
EVT
EVT
H21
H21
hole_c158d158n
hole_c158d158n
1
1
H22
H22
hole_c158d158n
hole_c158d158n
1
1
H23
H23
hole_c158d158n
hole_c158d158n
1
1
EVT
H24
H24
hole_c158d158n
hole_c158d158n
1
1
EVT
CPU Plate
hole_ts236x398bs315x437d91d98n
hole_tsh228x465bsh268x465d98
hole_tsh228x465bsh268x465d98
H29
H29
11
1
1
U_GNDU_GND
hole_tsh228x433bsh268x472d98
hole_tsh228x433bsh268x472d98
H30
H30
PTH
1
1
PTH
H25
H25
NPTH
NPTH
2
hole_tr295x276br315x354d98od95n
hole_tr295x276br315x354d98od95n
hole_trsh276x256bc217d98d87n
hole_trsh276x256bc217d98d87n
1
DVT
U_GNDP_GND
Audio BoardFunction Board
PVT
A
B
hole_ts236x398bs315x437d91d98n
H26
H26
PTH
PTH
NPTH
NPTH
2
1
H27
H27
PTH
PTH
NPTH
NPTH
2
1
C
DVT
hole_tbc197d91d87n
hole_tbc197d91d87n
P_GNDU_GND
H28
H28
PTH
PTH
NPTH
NPTH
2
1
EVT
PAD1
PAD1
pad_smdsh591x374
pad_smdsh591x374
pad_smdsh591x374
pad_smdsh591x374
1
P_GND P_GND P_GND
PAD2
PAD2
D
PAD3
PAD3
pad_smdsh591x374
pad_smdsh591x374
1
1
DVT
FOXCONN
FOXCONN
FOXCONN
Title
Title
Title
HOLE
HOLE
HOLE
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
A3
A3
A3
M960&M970 H ModelSA
M960&M970 H ModelSA
M960&M970 H ModelSA
Date:Sheet
Date:Sheet
Date:Sheet
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
CCPBG - R&D Division
CCPBG - R&D Division
CCPBG - R&D Division
of
of
of
8386Thursday, December 24, 2009
8386Thursday, December 24, 2009
E
8386Thursday, December 24, 2009
Page 84
5
M960/M970 EVT
(2009/06/22)
P.25 [VGA(I/O)]Delete R5858 and R5859 for needless from AMD suggestion.
P.25 [VGA(I/O)]Connect VDD2DI to +1_8VRUN directly and delete.
P.28 L98,C[6254:6256] for AMD suggestion.
P.25 [VGA(I/O)]Connect A2VDD to +3V3_DELAY directly and delete.
P.28 L12,C529,C91,C85 for AMD suggestion.
DD
P.28 [VGA(Power)]Delete net BIF_VDDC and C6156,C6157 for needless
from AMD suggestion.
P.28 [VGA(Power)]Change VDD3 power plan from +1_8VRUN to +3V3_DELAY
from AMD suggestion.
P.28 [VGA(Power)]Connect Ball AH29 to GND from AMD suggestion.
P.28 [VGA(Power)]The power for DPB can be shared with DPA from AMD suggestion.
P.28 [VGA(Power)]DPC and DPD can be powered directly without filters
from AMD suggestion.
P.40 [EC]Add R5877,R5878 for SYSTEM_ID2 used from SW's requested.
(2009/06/23)
P.25 [VGA(I/O)]Delete R5846, R5847, R5848, R5849, R5838, R5839, R5840,
C6188, C6189, U215 for needless from AMD suggestion.
P.73 [DCIN & Charger]Add test points TP1148~TP1155 for BFT test.
P.53 [Camera Connector]Add test points TP1156~TP1161 for BFT test.
CC
P.57 [FAN]Add test points TP1162~TP1165 for BFT test.
P.35 [LAN]Add test points TP1166~TP1181 for BFT test.
P.43 [Debug Port]Add test points TP1186~TP1193 for BFT test.
P.61 [AUDIO Speaker Conn]Add test points TP1194~TP1197 for BFT test.
P.41 [KB Connector]Add test points TP1198~TP1207 for BFT test.
P.60 [SWITCH DB Conn.]Add test points TP1208~TP1211 for BFT test.
P.73 [DCIN&Charger]Add test points TP1212~TP1218 for BFT test.
P.41 [KB Connector]Del CN4 because M960 and M970 KB connectors are decided
to co-use.
P.67 [AUDIO Speaker AMP]Del this page
because AMP is combined with ALC275
P.39 [PCIE (MS&iLINK)]Change the net name from "SDMS_VCC" to "VCC_MS"
because this net is for MS power only.
P.26 [VGA (Memory BUS) 4/6]Change the power source from +1_8VRUN to +1_5VRUN
because the power source of DDR3 VRAM is +1_5VRUN.
BB
(2009/06/24)
P.23 [CRT]Add and NC Q11,D9,R469,C279,R767,U9 for Semi-PNP.
P.39 [HDMI]Del C100,C107,C105,C106,C108,C109,C111,C112 for redundant design.
P.10 [PCH (HDA,JTAG,SAT)]Del R302 for redundant design.
P.24 [VGA (Strap) 2/6]Change net name "ATI_DVPDATA[23:20]" to ATI_DVPDATA[3:0]
for AMD recommend.
P.24 [VGA (Strap) 2/6]Del R5767,R5768 for AMD recommend.
4
3
2
1
(2009/06/25)
P.45 [Mini-PCIE Card (WLAN)]Add R5901 on WLAN_EN for RF VEDS test.
P.23 [VGA (PCI-E) 1/6]NC R5831 for AMD M96.
P.26 [VGA (Memory BUS) 4/6]NC R5798,R5800,R5799,R5802,R5803,R5804 for AMD M96.
P.26 [VGA (Memory BUS) 4/6]NC R5779,R5880 for AMD M96.
P.28 [VGA (Power) 6/6]NC L90,C6196,C6194,C6195,C6192,C6193 for AMD M96.
P.28 [VGA (Power) 6/6]NC L91,C6197,C6194,C6199,C6200 for AMD M96.
P.28 [VGA (Power) 6/6]NC L26 for AMD M96.
P.28 [VGA (Power) 6/6]Add L30 and connect between VDD_CORE and SPV10
for AMD M96.
P.28 [VGA (Power) 6/6]NC L92,C6233,C6234,C6236 for AMD comment.
P.28 [VGA (Power) 6/6]NC L96,L97,C6248,C6251,C6249,C6252,C6250,C6253
for AMD comment.
P.26 [VGA (Memory BUS) 4/6]Change C6100 from 2200P to 1U for AMD comment.
P.28 [VGA (Power) 6/6]NC R5833,R5834 because M96 not support for PowerXpress.
P.28 [VGA (Power) 6/6]Add R587 and connect to GND for PowerXpress function
of Park and Madison.
P.29 [VRAM(DDR3)# 1/4]Change R4030,R4019,R4027,R4028 from 1.33K to 4.99K
for AMD comment.
P.29 [VRAM(DDR3)# 1/4]Add R5874,R5875,C6303 for AMD comment.
P.63 [SWITCH (Botton & KB LED)*]Change P_VR1,P_VR2,P_VR3,P_VR4,P_VR5
for EMC team request.
P.20 [DDRIII(SO-DIMM_0) 1/2]Del SPR1,J1.
P.20 [DDRIII(SO-DIMM_0) 1/2]Connect CN34 207 Pin to GND.
P.21 [DDRIII(SO-DIMM_0) 2/2]Connect CN35 G2 Pin to GND.
P.46 [LAN (88E8057) 1/2]Del R1462 for Marvell comment.
P.46 [LAN (88E8057) 1/2]NC C997,R94 for Marvell comment.
P.37 [Inverter Connector]Add U89C,R809,R684,C902,R772 for MOR's request.
P.37 [Inverter Connector]Change the off-page from "BL_OFF#" to "INV_EN"
for MOR's request.
P.37 [Inverter Connector]Add U89A,U89B,C877,R687 for MOR's request.
P.37 [Inverter Connector]Add an off-page of BL_OFF# on U89D
for MOR's request.
P.38 [LVDS Connector]Change the off-page of 35/36 pin of CN13
to INV_BRADJ/INV_ENABLE
for MOR's request.
P.10 [PCH (HDA,JTAG,SAT)]Add R5905 to let JTAG_TCK pull down for MOR's request.
P.11 [PCH (PCI-E,SMBUS,CLK)]Add R539,R540 to let PCIECLKRQ3#,PCIECLKRQ4#
to pull high to +3VRUN for MOR's request.
P.11 [PCH (PCI-E,SMBUS,CLK)]Add R579 to connect WLAN_CLKREQ# to +3VSUS
for MOR's request.
P.11 [PCH (PCI-E,SMBUS,CLK)]NC R577 for MOR's request.
P.14 [PCH (PCI,USB,NVRAM)]Change Bluetooth function from port 13 to port10
to meet Freedom Project Product Specifications.
P.15 [PCH (GPIO,VSS_NCTF,RSVD)]Del GPIO39 related circuit
because this pin is for LCDID3
P.51 [PCIE (MS&iLINK) 1/2]Delete i-Link function from Freedom_specV0.6.
P.25 [VGA (I/O) 3/6]Del R5837 for AMD recommend.
P.26 [VGA (Memory BUS) 4/6]Add C6105,C6106,R5871,R5872 for AMD recommend.
P.13 [PCH (LVDS,DDI)]Del R1571 and place TP1219 on DDPD_HPD
because this pin is not necessary for pull-low to GND.
P.55 [Felica Connector]Del F14,R5874,R5875
because the F14 related circuit is out of Felica spec.
P.55 [Felica Connector]Stuff C869,U48,R630,C845
because F14 related circuit is out of Felica spec.
P.72 [DCIN&CHARGE]Change DC-IN current form 8A to 5A.
P.72 [DCIN&CHARGE]Change PD7 from SMD15C to TVS2315PT.
AA
P.74 [Idendify ID]Change PC61 from 1Uf_10V_k to 220Pf_50v_J,then NC PC61.
P.76 [VTT&PCH Power(+1_05V)]Change PR116 from 100k to 470k.
P.77 [DDR3 Power(+1_5V/+0_75V)]Change PR655 from 100k to 470k.
P.79 [CPU Power_VHCORE]Delete PC67,PC155.
P.82 [Other plane power]Change PQ29,PQ45,PQ48: from 2N7002DW to 2N7002SPT.
P.93 [OVP protection]Change PC41 from 0.01Uf to 1000Pf.
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History(1)
History(1)
History(1)
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A3
M960&M970 H ModelSA
M960&M970 H ModelSA
M960&M970 H ModelSA
Date:Sheet
Date:Sheet
3
2
Date:Sheet
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
CCPBG - R&D Division
CCPBG - R&D Division
CCPBG - R&D Division
of
of
of
8486Thursday, December 24, 2009
8486Thursday, December 24, 2009
1
8486Thursday, December 24, 2009
Page 85
5
M960/M970 EVT
(2009/06/26)
P.19 [CLOCK GEN]Change U31 from SL28748ALC to SL28748CLC.
P.14 [PCH (PCI,USB,NVRAM)]Del USB_PN12,USB_PP12 off-page and add TP365,TP452
on tha same ports.
P.45 [Mini-PCIE Card (WLAN)]Del U45,C891 for disable WIMAX function
P.45 [Mini-PCIE Card (WLAN)]NC 36pin,38pin of CN12 for disable WIMAX function
DD
P.15 [PCH (GPIO,VSS_NCTF,RSVD)]Add an off-page "LCDID4" on GPIO48
and change the net name to LCDID4 for LCDID[4:0].
P.15 [PCH (GPIO,VSS_NCTF,RSVD)]Del R5867 for LCDID[4:0].
P.63 [SWITCH (Botton & KB LED)*]Del "VAIO" button
from Freedom Project Product Specifications V0.6.
P.63 [SWITCH (Botton & KB LED)*]Change the button names "Web" and "Display Off"
to "Instant On" and "VAIO" from Freedom Project Product Specifications V0.6.
P.51 [PCIE (MS&iLINK) 1/2]Connect TPB+/- to GND and NC TPAP0/TPAN0/TPBIAS0
to disable i-Link function for Realtek comment.
P.51 [PCIE (MS&iLINK) 1/2]Add R1468 and NC it to disable i-Link function
for Realtek comment.
P.12 [PCH (DMI,FDI,GPIO)]Connect SYS_PWROK line to ALW_PWRGD through D33
for MOR's request.
P.44 [Express Card]Add R5457 between the gate and the source of Q38
for MOR's request.
P.68 [AUDIO (Head Phone Jack)*]Add U_R220 pull-high to U_VDDA on U_HP_IN_5
CC
for Realtek comment.
P.68 [AUDIO (Head Phone Jack)*]Change U_GND ground to U_A_GND
for Realtek comment.
P.69 [AUDIO (Ext MIC Jack)*]Add U_R221 pull-high to U_VDDA on U_EXTMIC_IN
for Realtek comment.
P.69 [AUDIO (Ext MIC Jack)*]Change U_C35/U_C36 to 4.7u X5R for Realtek comment.
P.84 [HOLE & AMI LABEL]Add H1~H20 for ME request.
P.25 [VGA (I/O) 3/6]Add 10K ohm resistors to let ATI_JTAG_TRSTB,ATI_JTAG_TDI,
ATI_JTAG_TCLK,ATI_JTAG_TMS,ATI_JTAG_TDO pull up to +3V3_DELAY.
(2009/06/29)
P.68 [AUDIO (Head Phone Jack)*]Change U_A_GND which is connected to U_C9 pin2
to U_GND.
P.72 [DCIN&Charger]Change PCN1 connector to BP91071-B51E3-7H for ME request.
P.50 [eSATA Combo Conn.]Change CN27 connector to 3Q38111-R21C3-8H
BB
for ME request.
P.58 [Touch Pad]Change SW2/SW3/SW6/SW7 to 19-SKRPABE-1000 for ME request.
P.22 [Braidwood Connector]Change NC39 to 1N-0078002-F1G0 for ME request.
P.51 [PCIE (MS&iLINK) 1/2]Del R1468 and connect XOUT to U71 A2
for Ricoh's comment.
P.28 [VGA (Power) 6/6]NC AH29 U204E for AMD's comment.
P.16 [PCH (POWER) 1/2]Change R366,R325 to 100 ohm for Intel'comment.
P.16 [PCH (POWER) 1/2]Change C141 to 1U for Intel'comment.
P.09 [ARD (RESERVED)]Change R1274 to 3.3K for Intel's comment.
(2009/06/30)
P.25 [VGA (I/O) 3/6]Change JTAG_TCK to pull-low to GND
through a 10K ohm resistor for MOR's request.
P.25 [VGA (I/O) 3/6]Del R5910 for MOR's request.
P.25 [VGA (I/O) 3/6]NC R5906,R5907,R5908,R5909 for MOR's request.
P.26 [VGA (Memory BUS) 4/6]Del C6105,C6106,R5879,R5880 for MOR's request.
P.28 [VGA (Power) 6/6]Del R5802,R5803 and connect DPE_VDD18/DPE_VDD10
AA
to DPF_VDD18_[2:1]/DPF_VDD10_[2:1] for MOR's request.
P.28 [VGA (Power) 6/6]Del L96/C6248/C6249/C6250/L97/C6251/C6252/C6253
for MOR's request.
P.80 [CPU Power_VID]Stuff PR638,PR646 for Power request.
P.80 [CPU Power_VID]NC PR637,PR645 for Power request.
P.28 [VGA (Power) 6/6]Del L80/C859/C858/C860/L81/C862/C861/C6291/L82
/C6165/C6164/C866 for MOR's comment.
5
4
3
2
1
P.45 [Mini-PCIE Card (WLAN)]Del R824 for MOR's request.
P.12 [PCH (DMI,FDI,GPIO)]Change R911 to 10K for MOR's request.
P.54 [Bluetooth Connector]Del C378 for MOR's request.
P.28 [VGA (Power) 6/6]Del L6,Q7,Q9,R5828,R5829,R5830
because M960/M970 do not use BBP function.
P.45 [Mini-PCIE Card (WLAN)]NC CN12 15pin and del R18 for RF request.
P.56 [Status LED & LID]Add LED6/LED7/LED8/LED9 for M970 only.
P.45 [Mini-PCIE Card (WLAN)]Add R17 and NC it for MOR's request.
(2009/07/01)
P.25 [VGA (I/O) 3/6]Del TP1104,TP1105,TP1106,TP1230
because these test points are redundant.
P.28 [VGA (Power) 6/6]Change net name DPE_VDD18/DPE_VDD10 to
DPEF_VDD18/DPEF_VDD10 for the co-use power DPE_VDD/DPF_VDD.
P.84 [HOLE & AMI LABEL]Del BOSS9,BOSS10 for ME request.
P.84 [HOLE & AMI LABEL]Add CPU hole H21,H22,H23,H24 for CPU socket.
P.50 [eSATA Combo Conn.]Del eSATA repeater schematic (U214,C766,C776,C759,C745,
R5754,R5835,R5756,R5755,R5757,R5758,R5759,C718,C387) for over-design.
P.10 [PCH (HDA,JTAG,SAT)]Change SPI_CLK_SW/SPI_MOSI_SW/SPI_MISO_SW
to SPI_CLK_L/SPI_MOSI_L/SPI_MISO_L for modifing the SW reserve design.
P.28 [VGA (Power) 6/6]Del R5833,R5834,R5837 and connect U204F AL21 to GND
because M960/M970 do not have PowerXpress function.
P.25 [VGA (I/O) 3/6]Add two connection ATI_LVDS_SCL/ATI_LVDS_SDA to CN13 5/6 pin
and pull-high 4.7K to +3V3_DELAY for SW request to add EDID function.
(2009/07/02)
P.38 [LVDS Connector]Connect CN13 Pin1 to LCDVCC for LCD power supply.
P.38 [LVDS Connector]Connect CN13 Pin34 to GND for LCD power supply.
P.51 [PCIE (MS&iLINK) 1/2]NC R820/C868/R817/C865/R818/C864
because SD_CD#/SD_WP#/MS_CD# has an internal pull-up resistor
and the debouching circuit.
P.36 [LVDS]Update Panel ID and related information.
(2009/07/03)
P.10 [PCH (HDA,JTAG,SAT)]Del TP119/TP123/TP133/TP136/TP137/TP138 and R442
because this is SW reserve design.
P.14 [PCH (PCI,USB,NVRAM)]Del Q39/Q37/R5456/SW5/R300 for changing
GNT1#/GNT0# control method.
P.14 [PCH (PCI,USB,NVRAM)]Add R345/R346 pull-high to +3VRUN
for controling GNT1#/GNT0#.
P.14 [PCH (PCI,USB,NVRAM)]Change R344/R392/R345/R346 to 10K ohm.
P.45 [Mini-PCIE Card (WLAN)]Del R17 and change the net name "MINI_PCIE_+3_3V_R"
to "MINI_PCIE_+3_3V" to del RF reserve circuit.
P.70 [AUDIO (USB)*]Change U_CN2/U_CN3/U_CN6 to 2N-0004009-MKG0 for ME request.
P.64 [AUDIO (CODEC)*]Change U_R5774 to 100K ohm and change the power source
on it from U_VDDA to U_+12V because Gate voltage of U_Q55 is too low.
P.67 [AUDIO (AUDIO & USB Conn)*]Move U_SUS_ON to U_CN1 Pin22 and add U_+12V
on Pin7.
P.62 [AUDIO/USB DB Conn.]Move SUS_ON to CN31 Pin29 and add +12V on Pin44.
P.37 [Inverter Connector]Del R400 for MOR's request.
P.38 [LVDS Connector]Add Q177/Q178/R5736/R5737/C575 and change L98
for rush current issue.
P.36 [LVDS]Del R136 for redundant design.
P.15 [PCH (GPIO,VSS_NCTF,RSVD)]Add a NC resistor R979 to let GPIO8 pull-low
to GND.
P.14 [PCH (PCI,USB,NVRAM)]Change Bluetooth USB port to port13.
P.14 [PCH (PCI,USB,NVRAM)]Change USB External Port-1 to USB port5
and eSATA change to port0.
(2009/07/04)
P.45 [Mini-PCIE Card (WLAN)]Restore U45,C891 for WIMAX function.
P.45 [Mini-PCIE Card (WLAN)]Connect 36pin,38pin of CN12 to USB_PN12_L/USB_PP12_L
for WIMAX function.
P.45 [Mini-PCIE Card (WLAN)]Add J5 to connect
Pin42 and Pin44 of CN12 for MOR's request.
4
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Title
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Title
History(2)
History(2)
History(2)
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SizeDocument NumberRev
SizeDocument NumberRev
A3
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M960&M970 H ModelSA
M960&M970 H ModelSA
M960&M970 H ModelSA
Date:Sheet
Date:Sheet
Date:Sheet
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
CCPBG - R&D Division
P.54 [Bluetooth Connector]Add C378 pull-low to GND refer to M930.
P.56 [Status LED & LID]Del POWER/SUSPEND LED and its related circuit
for ID changing.
P.12 [PCH (DMI,FDI,GPIO)]Change R973 to 2.2K ohm for MOR's requirement.
DD
P.28 [VGA (Power) 6/6]Add R5816 between GND to PX_EN and set N.C
for MOR's request.
P.38 [LVDS Connector]Add Q177 and related RC for protecting rush current.
P.61 [AUDIO Speaker Conn]Del Q28/Q30/Q53 and connect Q25 and Q27
because short protection circuit can marge L channel and R channel.
P.04 [ARD (CLK,MISC,JTAG)]Add Q72 for Intel S3 Power Reduction issue.
P.72 [DCIN&Charger]Delete PR17.
P.75 [SYS Power (+3_3V/+5V)]Delete close_jump GP2.
P.77 [DDR3 Power(+1_5V/+0_75V)]Change 1.5VSUS full load from 12A to 13A.
P.77 [DDR3 Power(+1_5V/+0_75V)]Change PR654 from 46.4k to 49.9k
P.82 [Others power plane]Change 1.5VRUN full load form 6A to 7A.
P.82 [Others power plane]Add 1.5VRUN discharge circuit
(add PR660 330ohm,PQ71 2N7002EPT).
P.38 [LVDS Connector]Del R474/R473 and related EDID circuit for disabling EDID.
(2009/07/08)
P.56 [Status LED & LID]Add Q18/Q21/Q48/Q51/R384/R390/R690/R691/R694/R695
CC
for POWER/SUSPEND LED location changing.
P.54 [Bluetooth Connector]Del C378 because C377 has the same function.
P.40 [EC+KBC(NPCE783L)]Add SYSTEM_ID3 (R5891/R5900) for SKU control.
P.25 [LVDS Connector]NC CN13 Pin3 because EDID is disabled.
for MOR's request.
P.51 [PCIE (MS&iLINK) 1/2]Add damping resistors (R5911~R5919) on each MS signal.
P.52 [PCIE (SD) 2/2]Change C518/C522 to X5R type for MOR's request.
P.52 [PCIE (SD) 2/2]Add damping resistors (R5920~R5924) on each SD signal.
P.52 [PCIE (SD) 2/2]Change C767 to 10pF for MOR's request.
P.56 [Status LED & LID]Del LED7/LED8/LED10 for ME request.
P.38 [LVDS Connector]Add NC Cap. (C6306~C6313)
between each LVDS differential lane.
P.46 [LAN (88E8057) 1/2]Modify R94/R97/C997 description.
P.46 [LAN (88E8057) 1/2]Change all resistors and caps to 88E8059 setting.
P.84 [HOLE & AMI LABEL]Add H25/H26/H27/H28 for ME request.
P.35 [CRT]Change CN20 type for ME request.
P.70 [AUDIO (USB)*]Change U_CN2/U_CN3/U_CN6 type for ME request.
P.84 [HOLE & AMI LABEL]Del H11/H12/H13/H15/H16/H17/H18/H19/H20 for ME request.
P.44 [Express Card]Rename PCIE_EXPRESS_WAKE# to PCIE_WAKE# to del reserve design.
P.12 [PCH (DMI,FDI,GPIO)]Del R290 and PCIE_EXPRESS_WAKE# off-page
to del reserve design.
P.82 [Others power plane]Add 0.75V_RUN discharge circuit(add PR661 330ohm).
P.82 [Others power plane]Change PQ71 from 2N7002EPT to ME2N7002KW.
P.04 [ARD (CLK,MISC,JTAG)]Del the description of RST_GATE
and add a 1k ohm resister R5925 between +1_5VSUS and DDR3_DRAMRST#.
P.04 [ARD (CLK,MISC,JTAG)]Add R5926/R5927/U217
for Intel S3 Power Reduction issue.
P.04 [ARD (CLK,MISC,JTAG)]Del R928/R929 and related description
for Intel S3 Power Reduction issue.
P.53 [Camera Connector]Add R5928/R5929/C6314/C6315 For EMI verification.
P.37 [Inverter Connector]Add R5930 For EMI verification.
P.63 [SWITCH (Botton & KB LED)*]Del P_SW3 and add P_CN4
for POWER/SUSPEND LED location changing.
P.56 [Status LED & LID]Change Q18/Q21/Q50 to DTC114EUB for MOR's request.
P.07 [ARD (GRAPHICS POWER)]Change VDDQ power source from +1_5VSUS to +1_5VRUN
for Intel S3 Power Reduction issue.
P.60 [SWITCH DB Conn.]Change CN2 to 14pin type
for POWER/SUSPEND LED location changing.
P.63 [SWITCH (Botton & KB LED)*]Change P_CN3 to 14pin type
for POWER/SUSPEND LED location changing.
P.51 [PCIE (MS&iLINK) 1/2]Change CN36 type for ME request.
P.15 [PCH (GPIO,VSS_NCTF,RSVD)]Set GPIO27 as RST_GATE
for Intel S3 Power Reduction issue.
P.75 [SYS Power (+3_3V/+5V)]Change NC PR118 to NO NC PR118 and NC PR234,PR235.
BB
P.83 [OVP protection]Delete reserved Power limit circuit(delete PU2,PU11,PD22
,PR22,PR24,PR142,PR143,PR149,PR153,PR159,PR213,PR214,PC26,PC27,PC28).
P.83 [OVP protection]change PR218 from 37k to 45.3k.
P.11 [PCH (PCI-E,SMBUS,CLK)]Del R1590/R1591/R1592/Q73/Q74
and rename SMB_DATA_SB/SMB_CLK_SB to SMB_DATA_R/SMB_CLK_R.
P.10 [PCH (HDA,JTAG,SAT)]Del R1552/R1554 and rename SPI_CLK_L/SPI_MOSI_L
to SPI0_CLK/SPI0_MOSI for redundant design.
P.10 [PCH (HDA,JTAG,SAT)]Add R5910 on SATA_LED# which is pull-high to +3VRUN
for Intel comment.
P.04 [ARD (CLK,MISC,JTAG)]NC R1451/R1452 and stuff R1450/R1453 refer to M930.
P.52 [PCIE (SD) 2/2]Change CN29 type for ME request.
P.58 [Touch Pad]Change SW2/SW3/SW6/SW7 type for ME request.
(2009/07/10)
P.22 [Braidwood Connector]Del P.22 and change the page number from 23~87
to 22~86 for removing Braidwood function.
P.14 [PCH (PCI,USB,NVRAM)]Del all Braidwood-related off-page
for removing Braidwood function.
P.49 [eSATA Combo]Swap L62/L66/L67 for layout request.
P.62 [SWITCH (Botton & KB LED)*]Change the description "Instant On"
to "Web(Instant On) for SW request".
P.50 [PCIE (MS&iLINK) 1/2]Del R820/C868/R817/C865/R818/C864
for Ricoh's FAE suggest.
P.50 [PCIE (MS&iLINK) 1/2]Add description of C794/C771/C774/C992
for Ricoh's FAE suggest.
P.50 [PCIE (MS&iLINK) 1/2]Add description of C790/C769/C770/C772/C799
for Ricoh's FAE suggest.
P.50 [PCIE (MS&iLINK) 1/2]Add description of C716/C717
for Ricoh's FAE suggest.
P.38 [HDMI]Connect Q57 D/S to +5VRUN_L188/+5VRUN_F.
P.37 [LVDS Connector]Connect Q177 D/S to DCBATOUT_L/DCBATOUT.
P.39 [EC+KBC(NPCE783L)]Change net name "KB_PRESENCE#" to "INST_ON_SW#"
for SW request.
P.71 [DCIN&Charger]Delete NC PR12.
P.71 [DCIN&Charger]Change charge voltage form 12.48V to 12.465V for MOR request
(change PR25 form 200k_F to 210K_F, change PR27 from 100K_F to 100K_D).
P.73 [Identify IC]Change PC66 from 0.1u_16v_0402_Y5V to 0.1u_10v_0402_X5R.
P.73 [Identify IC]Change NC PC65 1u_10v_0603_X5R to NC PC65 1u_10v_0402_X5R.
(2009/07/09)
P.24 [VGA (Strap) 2/6]Change memory aperture size description for SW request.
P.68 [AUDIO (Head Phone Jack)*]Change Pin7/Pin8 of U_CN4 to U_A_GND
AA
for Layout request.
P.78 [CPU Power_VHCORE]Change PC112 from 100U_25V_M_Φ6.3*7.7mm
to 68uF_25V_M_Φ6.3*5.8mm.
P.14 [PCH (PCI,USB,NVRAM)]Change USB_OC#5/USB_OC#4 to Pin7/Pin8 of RP18
for Layout request.
P.07 [ARD (GRAPHICS POWER)]Add a Open-Jump PJ43 between +1_5VRUN to VDDQ.
P.06 [ARD (POWER)]Del R856/R857 for MOR's request.
5
4
FOXCONN
FOXCONN
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Title
Title
Title
History(3)
History(3)
History(3)
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SizeDocument NumberRev
SizeDocument NumberRev
A3
A3
A3
M960&M970 H ModelSA
M960&M970 H ModelSA
M960&M970 H ModelSA
Date:Sheet
Date:Sheet
3
2
Date:Sheet
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
CCPBG - R&D Division
CCPBG - R&D Division
CCPBG - R&D Division
of
of
of
8693Thursday, December 24, 2009
8693Thursday, December 24, 2009
1
8693Thursday, December 24, 2009
Page 87
5
4
3
2
1
(2009/07/15)
M960/M970 EVT
(2009/07/11)
P.36 [Inverter Connector]Reverse CN5.
P.62 [SWITCH (Botton & KB LED)*]Reverse P_CN3.
P.37 [LVDS Connector]Add description on the circuit
for inrush current issue of M870.
DD
P.34 [CRT]Change F2 type for PUR request.
P.63 [AUDIO (CODEC)*]Change U_C459/U_C476/U_C787 type for PUR request.
P.07 [ARD (GRAPHICS POWER)]Add net name "+1_5VRUN_J".
P.14 [PCH (PCI,USB,NVRAM)]Del R344/R392 and the description about Boot-BIOS
for SW request.
P.52 [Camera Connector]Add net name DMIC_CLK_R/DMIC_DAT_R
and connect TP1160/TP1161 to the new net for TE request.
P.20 [DDRIII(SO-DIMM_0) 1/2]Reconnect SPR2/J2 to CN34 and CN35 for EMC request.
P.10 [PCH (HDA,JTAG,SAT)]Reverse CN26.
P.38 [HDMI]Change CN21 type for ME request.
P.60 [AUDIO Speaker Conn]Swap JSPK1 for ME request.
(2009/07/13)
P.51 [PCIE (SD) 2/2]Change U22 to G553E1P11U to meet MOR's request for SD.
P.57 [Touch Pad]Reverse CN8 for ME request.
P.62 [SWITCH (Botton & KB LED)*]NC P_VR2 for EMC reserve.
P.50 [PCIE (MS) 1/2]Del all i-Link related description.
CC
P.36 [Inverter Connector]Reverse CN5.
P.83 [HOLE & AMI LABEL]Change H2/H3/H4/H5/H6/H7/H10/H14 type for ME request.
P.25 [VGA (Memory BUS) 4/6]Change C6100 type for PUR request.
P.71 [DCIN&Charger]Delete EC3 and C907.
P.79 [CPU Power_VHCORE]Change PC566 from 0.1U_6.3V_K to 0.1U_16V_K
(HH PN:1C-2B20104-K300).
P.82 [OVP protection]Change PQ3 from IRLML5103TRPbF to SI2303BDS.
P.04 [ARD (CLK,MISC,JTAG)]Change U217 SUS_PWRGD to RUN_PWRGD.
P.63 [AUDIO (CODEC)*]Paste the schematic from P.48 of L model
for MOR's request and Layout concern.
P.64 [AUDIO (MUTE)*]Paste the schematic from P.49 of L model
for MOR's request and Layout concern.
P.65 [AUDIO (Power)*]Paste the schematic from P.50 of L model
for MOR's request and Layout concern.
P.66 [AUDIO (AUDIO & USB Conn)*]Paste the schematic from P.51 of L model
for MOR's request and Layout concern.
P.67 [AUDIO (Head Phone Jack)*]Paste the schematic from P.52 of L model
BB
for MOR's request and Layout concern.
P.68 [AUDIO (Ext MIC Jack)*]Paste the schematic from P.53 of L model
for MOR's request and Layout concern.
P.69 [AUDIO (USB)*]Paste the schematic from P.54 of L model
for MOR's request and Layout concern.
P.04 [ARD (CLK,MISC,JTAG)]Change R5926/R5927 to 1.5K/750 ohm
for intel's comment.
P.81 [Others power plane]Change PR661 from 330ohm to 33ohm.
(2009/07/14)
P.38 [HDMI]Swap RP55/RP57/RP59/RP61 for Layout request.
P.49 [eSATA Combo]Swap L62/L66/L67 for Layout request.
P.37 [LVDS Connector]Swap Pin1 CN13 to Pin3 CN13 for cable design.
P.83 [HOLE & AMI LABEL]Change H4/H5/H7 footprint for ME request.
P.71 [DCIN&Charger]NC PR76 and PR77.
P.78 [CPU Power_VHCORE]Change PR555 and PR569 from 2.7K to 2.21K.
AA
P.78 [CPU Power_VHCORE]NC PC260 ,NC PC261.
P.39 [EC+KBC(NPCE783L)]Pull-high INST_ON_SW# to +ECVCC for SW request.
P.76 [DDR3 Power(+1_5V/+0_75V)]Add PQ59(2N7002EPT)/PR600(100K)/PC570(1U_10V_K),
then NC PQ59/PR600/PC570.
5
4
P.48 [SATA CD-ROM]NC CN37 for ME request.
P.39 [EC+KBC(NPCE783L)]Del R5858 for redundant design.
p.78 [CPU Power_VHCORE]change PC112 from NOCHICON to Panasonic.
P.24 [VGA (I/O) 3/6]Connect GPIO_3/GPIO_4 to SMB_THRM_DATA/SMB_THRM_CLK
for MOR's request.
P.09 [ARD (RESERVED)]Del RP83 and DQ_VREF off-page and add two test point
to CPU for Intel's comment.
P.20 [DDRIII(SO-DIMM_0) 1/2]Del C35/C45/R1283 and DQ_VREF0 off-page
for Intel's comment.
P.20 [DDRIII(SO-DIMM_0) 1/2]Connect VREF_DQ ato VREF_CA for Intel's comment.
P.21 [DDRIII(SO-DIMM_1) 2/2]Del C37/C44/R1284 and DQ_VREF1 off-page
for Intel's comment.
P.21 [DDRIII(SO-DIMM_1) 2/2]Connect VREF_DQ ato VREF_CA for Intel's comment.
P.83 [HOLE & AMI LABEL]Add H29/H30/PAD1/PAD2/PAD3 for EMC request.
P.83 [HOLE & AMI LABEL]Change H28/H25 type for ME request.
(2009/07/16)
P.83 [HOLE & AMI LABEL]Change PAD1/PAD2/PAD3 for CIS request.
P.23 [VGA (Strap) 2/6]Modify description of VRAM.
P.20 [DDRIII(SO-DIMM_0) 1/2]Restore C35/C41 for MOR's request.
P.21 [DDRIII(SO-DIMM_1) 2/2]Restore C37/C44 for MOR's request.
(2009/07/17)
P.78 [CPU Power_VHCORE]Change PR565 from 10k to 1.8k,
change PC566 from 0.1u to 0.022u.
M960/M970 DVT
(2009/07/21)
p.1~88 [Page Data]Update all page data.
(2009/07/24)
P.84 [Braidwood Connector]Add CN39 and its related schematic
for layout estimation.
P.14 [PCH (PCI,USB,NVRAM)]Add Braidwood related schematic
for layout estimation.
(2009/07/30)
P.84 [Braidwood Connector]Del CN39 and its related schematic
for layout estimation.
P.78 [CPU Power_VHCORE]Delete PJ42.
P.80 [VGA Power(ATI_VDD)]Delete PJ30, NC PR210, Change PR183 from 20K
to 15.4K, Change PR550 from 2.7k to 5.36k.
(2009/08/13)
P.39 [EC+KBC(NPCE783L)]Del R5852 for OVT_EC# double pull-high.
P.13 [PCH (LVDS,DDI)]Change R223 from 0.5% to 5% for RGB disable guide.
P.60 [AUDIO Speaker Conn]Change JSPK1 to 1N-0004003-M1T0 for ME request.
P.66 [AUDIO (AUDIO & USB Conn)*]Reverse U_CN1 for moving U_CN1
from TOP to BOT side.
P.67 [AUDIO (Head Phone Jack)*]Changen U_CN4 to 2N-000600N-FKG0.
P.68 [AUDIO (Ext MIC Jack)*]Change U_CN5 to 2N-000600C-FRG0.
P.69 [AUDIO (USB)*]Change U_USB_OC#1/2/3 to U_USB_OC#0/2.
P.66 [AUDIO (AUDIO & USB Conn)*]NC U_USB_OC#3 and Change U_USB_OC#1/2
to U_USB_OC#0/2.
P.61 [AUDIO/USB DB Conn.]NC U_USB_OC#3 and Change U_USB_OC#1/2 to U_USB_OC#0/2.
P.14 [PCH (PCI,USB,NVRAM)]Del off-page USB_OC#1/3.
P.27 [VGA (Power) 6/6]Change Q77 to 17-2N7002W-0000 for PUR request.
P.04 [ARD (CLK,MISC,JTAG)]Change Q72 to 17-2N7002W-0000 for PUR request.
P.38 [HDMI]Change Q13 to 17-2N7002W-0000 for PUR request.
P.78 [CPU Power_VHCORE]Delete NC_PC260, NC_PC261.
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
FOXCONN
FOXCONN
FOXCONN
Title
Title
Title
History(4)
History(4)
History(4)
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
A3
A3
A3
M960&M970 H ModelSA
M960&M970 H ModelSA
M960&M970 H ModelSA
Date:Sheet
Date:Sheet
3
2
Date:Sheet
HON HAI Precision Ind. Co., Ltd.
CCPBG - R&D Division
CCPBG - R&D Division
CCPBG - R&D Division
8793Thursday, December 24, 2009
8793Thursday, December 24, 2009
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Page 88
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(2009/09/03)
M960/M970 DVT
(2009/08/18)
P.34 [CRT]Change F2 to 0.35A.
P.83 [HOLE & AMI LABEL]Add H31 and change H1/H27/PAD1/PAD2/PAD3 for ME request.
P.49 [eSATA Combo]Swap CN27B.
P.43 [Express Card]Change R5457 to 470K and add NC R686 for MOR request.
P.15 [PCH (GPIO,VSS_NCTF,RSVD)]Change RST_GATE from GPIO27 to GPIO46
DD
, Stuff R982,NC R977.
P.46 [LAN (Transformer) 2/2]Change L70 for cost down.
P.51 [AUDIO (CODEC)*]Change U_U215.
P.25 [VGA (Memory BUS) 4/6]Change R5795,R5809,R5796,R5810 from 1R-000402X-F200
to 1R-0000101-F200 for vendor request.
P.27 [VGA (Power) 6/6]Stuff R5816 for vendor request.
P.24 [VGA (I/O) 3/6]Change R5793 from 1R-0000000-J200 to 1R-0000101-F200 and
change R5794 from 1R-0000000-J200 to 1R-0000121-F200 for vendor request.
P.31 [VRAM(DDR3)# 4/4]NC R5727 for vendor request.
P.55 [Status LED & LID]Change U21 to 15-EC2648B-0000 for cost down.
P.71 [DCIN&Charger] Change PQ5,PQ16,PQ34 to 17-2N7002W-0000
for materials shortage.
P.76 [DDR3 Power(+1_5V/+0_75V)] Change PQ59 to 17-2N7002W-0000
for materials shortage.
P.82 [OVP protection] Change PQ9,PQ17 to 17-2N7002W-0000
for materials shortage.
P.81 [Others power plane] Change PQ29,PQ45,PQ48 to 17-2N7002D-W001
CC
for materials shortage.
P.83 [HOLE & AMI LABEL]Change H29/H30 for ME request.
(2009/08/24)
P.69 [AUDIO (USB)*]Change U_CN2/U_CN3/U_CN6 for ME request.
P.60 [AUDIO Speaker Conn]Change JSPK1 for ME request.
P.34 [CRT]Change CN20 for ME request.
P.15 [PCH (GPIO,VSS_NCTF,RSVD)]Change R977 from NC to Stuff and change R982
from Stuff to NC.
(2009/08/25)
P.83 [HOLE & AMI LABEL]Change H26 for ME request.
(2009/08/27)
P.83 [HOLE & AMI LABEL]Change H30 for ME request.
(2009/08/31)
P.71 [DCIN&Charger]Change PCN1 to BP92071-B81E2-7H for ME request.
BB
P.48 [SATA HDD]Change CN33 to LN21131-D40L-9H for ME request.
P.15 [PCH (GPIO,VSS_NCTF,RSVD)]Add R5931/R5932/R5933/R5934 and change R5866
to 100K to pull-high LCDID for PE request.
P.35 [LVDS]Add R5935/R5936/R5937/R5938/R5939/R5940 to pull-low LCDID
for PE request.
P.25 [VGA (Memory BUS) 4/6]Stuff R5798, R5800, R5799, R5802, R5803, R5804
for Madison/Park only.
P.25 [VGA (Memory BUS) 4/6]Change R5806, R5807 to 0 ohm for Madison/Park only.
P.27 [VGA (Power) 6/6]Stuff L89,C6187,C6186,C6185 for Madison/Park only.
P.27 [VGA (Power) 6/6]Stuff R5811 for Madison/Park only.
P.22 [VGA (PCI-E) 1/6]Stuff R5831 for Madison/Park only.
P.27 [VGA (Power) 6/6]NC L76,L77,C6155,C6158 for Madison/Park only.
P.27 [VGA (Power) 6/6]Stuff L92, C6233, C6234, C6236, R5812
for Madison/Park only.
P.27 [VGA (Power) 6/6]Stuff L26, NC L30 for Madison/Park only.
P.27 [VGA (Power) 6/6]Stuff L90, C6192, C6193, C6194, C6195, C6196
for Madison/Park only.
P.27 [VGA (Power) 6/6]Stuff L91, C6197, C6199, C6200 for Madison/Park only.
P.27 [VGA (Power) 6/6]NC R5815 for Madison/Park only.
P.55 [Status LED & LID]Move R390/R384 to Drain side of Q51/Q48 for MOR comment.
P.37 [LVDS Connector]Change CN13 to M870 type (1N-0040000-FWG0).
P.59 [SWITCH DB Conn.]Change CN2 to 12pin type (1N-0012002-F0T0).
P.62 [SWITCH (Botton & KB LED)*]Change P_CN3 to 12pin type (1N-0012002-F0T0).
P.62 [SWITCH (Botton & KB LED)*]Move NUM LOCK LED/CAP LED/SCROLL LOCK LED
driving circuit to MB for MOR comment.
P.55 [Status LED & LID]Add NUM LOCK LED/CAP LED/SCROLL LOCK LED
driving circuit for MOR comment.
P.09 [ARD (RESERVED)]Del test points for MOR comment.
P.11 [PCH (PCI-E,SMBUS,CLK)]Del test points for MOR comment.
P.15 [PCH (GPIO,VSS_NCTF,RSVD)]Del test points for MOR comment.
Test Points[TP109/TP193/TP181/TP208/TP209/TP211/TP210/TP212/T213/TP214/
TP235/TP236/TP265/TP266/TP237/TP239/TP327/TP328/TP329/TP256/TP257/TP259/
TP260/TP262/TP263/TP264/TP284/TP287/TP288/TP289/TP290/TP291/TP292/TP293/
TP294/TP295/TP296/TP297/TP298/TP425/TP1116/TP1117/TP1118/TP1119/TP140/
TP147/TP148/TP149/TP148/TP145/TP144/TP134TP1120/TP1121/TP1122/TP1123/
TP1124/TP188/TP183/TP88/TP91/TP93/TP101/TP412/TP416/TP415/TP417/TP414/
TP421/TP422/TP423/TP424]
P.09 [ARD (RESERVED)]Del RP87 for MOR and Intel comment.
P.43 [Status LED & LID]Add LED test points TP1223/TP1224/TP1225/TP1226/TP1227/
TP1228/TP1229/TP1230.
P.10 [PCH (HDA,JTAG,SAT)]Change U98 to W25Q32BVSSIG.
P.63 [AUDIO (CODEC)*]Del U_U7 and U_C155 for Realtek suggestion.
P.16 [PCH (POWER) 1/2]Del R897, R989 for MOR comment.
P.17 [PCH (POWER) 2/2]Del R428, R958 for MOR comment.
P.04 [ARD (CLK,MISC,JTAG)]Add R5950, C6316, R5951, R5949, R5948, C6317
for Intel S3 issue.
(2009/09/01)
P.56 [FAN]Del TP1163.
P.63 [AUDIO (CODEC)*]Add ALC269 co-lay schematic and del U_TP229, U_TP231,
U_TP228.
P.14 [PCH (PCI,USB,NVRAM)]Del R1575 for redundant design (double pull-low).
P.64 [AUDIO (MUTE)*]Add ALC265 co-lay schematic.
P.10 [PCH (HDA,JTAG,SAT)]NC R5910 for redundant design (double pull-high).
P.74 [SYS Power (+3_3V/+5V)]Move TP215 from +5VALW_PWM to +5VALW for power test.
P.74 [SYS Power (+3_3V/+5V)]Move TP219 from +3VALW_PWM to +3VALW for power test.
P.75 [SYS Power(+1_05V_VTT)]Add TP504 for +1.05V_VTT power test.
P.78 [CPU Power_VHCORE]Add TP507,TP223,TP224 for VHCORE power test.
AA
P.79 [CPU Power_VID]Add TP225~ TP233 for power test.
P.80 [VGA Power (ATI_VDD)]Change PR184 rome 1K to 100ohm, NC PC160
for vendor suggest.
P.80 [VGA Power (ATI_VDD)]Add TP221,TP222 for power test.
P.80 [VGA Power (ATI_VDD)]Add PR662 and PC571 for vendor suggest.
P.80 [VGA Power (ATI_VDD)]Add PC572(NC) for vendor suggest.
5
4
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Title
Title
Title
History(5)
History(5)
History(5)
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
A3
A3
A3
M960&M970 H ModelSA
M960&M970 H ModelSA
M960&M970 H ModelSA
Date:Sheet
Date:Sheet
3
2
Date:Sheet
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
CCPBG - R&D Division
CCPBG - R&D Division
CCPBG - R&D Division
of
of
of
8893Thursday, December 24, 2009
8893Thursday, December 24, 2009
1
8893Thursday, December 24, 2009
Page 89
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M960/M970 DVT
(2009/09/08)
P.63 [AUDIO (CODEC)*]Change U_R327 to 1K.
P.71 [DCIN&Charger]NC PR33 for costdown.
P.80 [VGA Power (ATI_VDD)]Add PR663(NC) and PC573(NC) for vendor suggest.
P.82 [OVP protection]PR167 change to 26.1K, PR169 change to 80.6K ,
PR171 change to 18.2K for OVP Adjust
DD
P.82 [OVP protection]Use SW PWRLIMIT function replaced HW PWRLIMIT circuit
for costdown.(NC PU31,PC567,PR223,PR629,PR219,PR218,PR78,PC46.)
P.62 [SWITCH (Botton & KB LED)*]Change P_VR1/P_VR2/P_VR3/P_VR4
to 19-MLVS060-5000.
P.39 [EC+KBC(NPCE783L)]Change C27/C26 to 15p for Crystal vendor comment.
P.10 [PCH (HDA,JTAG,SAT)]Change C727/C702 to 15p for Crystal vendor comment.
P.50 [PCIE (MS) 1/2]Change C785/C786 to 22p for Crystal vendor comment.
P.49 [eSATA Combo Conn.]Add eSATA reperater schematic and NC it.
P.10 [PCH (HDA,JTAG,SAT)]Change CN18 to GB5RF120-1203-7F for Halgen Free.
P.42 [Debug Port]Change CN30 to GB5RF120-1203-7F for Halgen Free.
P.54 [Felica Connector]Add Felica power supply schematic as Pokerman type
for MOR request.
P.14 [PCH (PCI,USB,NVRAM)]Change USB_OC# signal to EVT type for MOR request.
P.41 [SPI Flash ROM]Change U23 to W25X10BVSNIG for SW comment.
P.63 [AUDIO (CODEC)*]Move U_R5774 to P.60 and rename to R5968.
P.61 [AUDIO/USB DB Conn.]NC +12V and add a +5VALW pin for USB VEVS test.
P.66 [AUDIO (AUDIO & USB Conn)*]NC U_+12V to a U_+5VALW pin for USB VEVS test.
CC
P.61 [AUDIO/USB DB Conn.]Change CN31 to 1N-0050004-F0T0 for ME request.
P.66 [AUDIO (AUDIO & USB Conn)*]Change U_CN1 to 1N-0050004-F0T0 for ME request.
P.45 [LAN (88E8057) 1/2]Add R5965/R5966/R5967 for 88E8057/88E8059 co-lay.
P.61 [AUDIO/USB DB Conn.]Change CN31 Pin 43 to GND.
P.66 [AUDIO (AUDIO & USB Conn)*]Change U_CN1 Pin 43 to GND.
P.55 [Status LED & LID]Change Q49/Q179/Q180/Q181 to 17-DTA114Y-UB00
for PUR suggest.
P.44 [Mini-PCIE Card (WLAN)]Change Q5 to 17-DTC144E-UB00 for PUR suggest.
P.56 [FAN]Change Q80 to 17-DTC144E-UB00 for PUR suggest.
P.71 [DCIN&Charger]Change TP1148,TP1149,TP1150,TP1151 from DC_IN_1 to
P+ for power test.
P.71 [DCIN&Charger]Change PQ16,PR76,PR77 from NC to mount
for EC PWRLIMIT function.
P.71 [DCIN&Charger]Change PR79 from 0 to 3.48K, change PR11 from 20K to 12K
for EC PWRLIMIT function.
P.73 [Identify IC]Add PD31 and change PR68 from 10K to 4.7K
for MOR side request.
BB
P.81 [Others power plan]Delete TP189,TP203 for power test.
4
3
2
1
P.42 [Felica Connector]Change Felica power supply from +5VSUS to +3VSUS.
P.51 [PCIE (SD) 2/2]Change R391 to 100K for MOR request.
P.43 [Express Card]NC Q38, R5457 and mount R686 for MOR comment.
(2009/09/10)
P.37 [LVDS Connector]Add CN13 Pin40 for EDID function.
P.44 [Mini-PCIE Card (WLAN)]Add C6329/C6330 for EMI request.
P.16 [PCH (POWER) 1/2]Add C6326/C6327/C6328 for EMI request.
P.62 [SWITCH (Botton & KB LED)*]Change P_LED1/P_LED2/P_LED3 to HT-170UYG.
P.81 [Others power plane]Add C6332/C6333 on +3VSUS for EMI request.
P.81 [Others power plane]Add C6334/C6335/C6336 on +3VRUN for EMI request.
P.45 [LAN (88E8059) 1/2]Del R97 and add C6341 for Marvell FAE request.
P.45 [LAN (88E8059) 1/2]Del R5966, R5967 for Marvell FAE request.
P.45 [LAN (88E8059) 1/2]Change C993 to 10u for Marvell FAE request.
P.43 [Express Card]Correct Express Card SPEC.
P.48 [SATA CD-ROM]Del CN37 for MOR request.
P.61 [AUDIO/USB DB Conn.]Add F1 for MOR comment.
P.66 [AUDIO (AUDIO & USB Conn)*]rename U_+5VALW to U_+5VALW_IN for MOR comment.
P.69 [AUDIO (USB)*]Del U_F1 and rename U_+5VALW to U_+5VALW_IN for MOR comment.
P.83 [HOLE & AMI LABEL]Del BOSS2 for MOR request.
P.63 [AUDIO (CODEC)*]Change U_R321 to 100K for MOR request.
P.64 [AUDIO (MUTE)*]NC U_C472 for MOR comment.
P.68 [AUDIO (Ext MIC Jack)*]NC U_R42, U_R46 for MOR comment.
P.68 [AUDIO (Ext MIC Jack)*]Del U_C26, U_C31 and add U_R5791, U_R5792
for MOR comment.
P.68 [AUDIO (Ext MIC Jack)*]NC U_R42, U_R46 for MOR comment.
P.63 [AUDIO (CODEC)*]NC U_C923.
P.67 [AUDIO (Head Phone Jack)*]Change U_GND to U_A_GND for Realtek FAE suggest.
P.37 [LVDS Connector]NC CN13 Pin7.
(2009/09/11)
P.71 [DCIN&Charger]Change PR15 to RLM12FTSR020 for PUR request.
P.71 [DCIN&Charger]Change PF1 to 0437007.WR for PUR request.
P.37 [LVDS Connector]Change CN13 for Halgen-free.
P.60 [AUDIO Speaker Conn]Swap JSPK1 for layout concern.
P.44 [Mini-PCIE Card (WLAN)]Change SW4 to 1BS007-12110-002-7H for ME request.
P.55 [Status LED & LID]Change LED3/LED4 vendor to Everlight.
P.67 [AUDIO (Head Phone Jack)*]Change U_A_GND to U_GND for Realtek FAE suggest.
P.63 [PCIE (SD) 2/2]Change CN29 to WK21923-S6P3-4H for ME request.
P.10 [PCH (HDA,JTAG,SAT)]Change CN18 to No Halgen-free.
P.42 [Debug Port]Change CN30 No Halgen-free.
P.62 [SWITCH (Botton & KB LED)*]Change P_CN3 to No Halgen-free.
P.59 [SWITCH DB Conn.]Change CN2 to No Halgen-free.
P.56 [FAN]Change CN14 to No Halgen-free.
P.60 [AUDIO Speaker Conn]Change JSPK1 to No Halgen-free.
(2009/09/09)
P.42 [Debug Port]Del TP1186~TP1193.
P.24 [VGA (I/O) 3/6]Add ATI_LVDS_SCL/ATI_LVDS_SDA for EDID function.
P.37 [LVDS Connector]Add ATI_LVDS_SCL/ATI_LVDS_SDA for EDID function.
P.74 [SYS Power (+3_3V/+5V)]Change PR652,PR245 from NC to mount 4.7ohm.
Change PC568,PC272 from NC to mount 680pF for EMI suggest.
P.75 [SYS Power(+1_05V_VTT)]Change PR188 from NC to mount 4.7ohm,
Change PC170 from NC to 680pF for EMI suggest.
P.76 [DDR3 Power(+1_5V/+0_75V)]Change PR41 from NC to mount 4.7ohm,
Change PC42 from NC to mount 680pF for EMI suggest.
P.80 [VGA Power (ATI_VDD)]Change PR163 from NC to mount 4.7ohm,
Change PC133 from NC to mount 680pF for EMI suggest.
P.52 [Camera Connector]Del R5928/R5929 and add L93/L94 for EMC request
AA
for DMIC noise.
P.83 [HOLE & AMI LABEL]Change H2/H4/H5 for ME request.
P.39 [EC+KBC(NPCE783L)]NC U216 Pin8 and del R575.
P.15 [PCH (GPIO,VSS_NCTF,RSVD)]Connect DIS_FAN_MON# to U69F GPIO57
and pull-high to +3VRUN.
P.39 [EC+KBC(NPCE783L)]NC U4A Pin20 and add SYSTEM_ID1 off-page.
P.15 [PCH (GPIO,VSS_NCTF,RSVD)]Connect SYSTEM_ID1 to U69F GPIO17 and del R965.
P.39 [EC+KBC(NPCE783L)]NC U4A Pin27 and add SYSTEM_ID0 off-page.
P.15 [PCH (GPIO,VSS_NCTF,RSVD)]Connect SYSTEM_ID0 to U69F GPIO16
and NC RP19 Pin7.
P.39 [EC+KBC(NPCE783L)]NC U216 Pin9.
P.15 [PCH (GPIO,VSS_NCTF,RSVD)]Connect PM_SLP_ME# to U4B GPIO26.
P.39 [EC+KBC(NPCE783L)]Del R5853 and connect INST_ON_SW# to GPIO12.
P.39 [EC+KBC(NPCE783L)]NC U216 Pin3 and connect WLAN_EN to U4A Pin20.
P.39 [EC+KBC(NPCE783L)]NC U216 Pin4 and connect BT_ON to U4A Pin27.
P.52 [Camera Connector]Mount C6314/C6315 for EMC request for DMIC noise.
P.60 [AUDIO Speaker Conn]Del R5870, R5871, R5872, R5873
and Add L95, L96, L97, L98 for EMC request to filtrate SPK noise.
P.37 [LVDS Connector]Add C6324/C6325 for EMC request for 150MHz powerbase issue.
5
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History(6)
History(6)
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A3
M960&M970 H ModelSA
M960&M970 H ModelSA
M960&M970 H ModelSA
Date:Sheet
Date:Sheet
3
2
Date:Sheet
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
CCPBG - R&D Division
CCPBG - R&D Division
CCPBG - R&D Division
of
of
of
8993Thursday, December 24, 2009
8993Thursday, December 24, 2009
1
8993Thursday, December 24, 2009
Page 90
5
M960/M970 DVT
(2009/09/11)
P.39 [EC+KBC(NPCE783L)]NC U216 Pin5/Pin6 and connect AC_OFF/EC_PWRLIMIT_CTRL
to U4A Pin119/Pin120.
P.39 [EC+KBC(NPCE783L)]Del R5855/R5856/C6201/C6202.
P.39 [EC+KBC(NPCE783L)]Connect AC_Present to U4A Pin124.
P.39 [EC+KBC(NPCE783L)]Del U216/R5857/C6203.
DD
P.25 [VGA (Memory BUS) 4/6]Change C6100 to UMK105CH680KW-F for PUR request.
P.34 [CRT]Del F2 for MOR comment.
P.63 [AUDIO (CODEC)*]Del U_R5773/U_Q64/U_R5771/U_R5783/U_U215/U_R5784
for MOR comment.
P.63 [AUDIO (CODEC)*]Move U_AMP_PD# to U_U18 Pin4.
P.64 [AUDIO (MUTE)*]Mount U_R352/U_R351/U_Q17/U_R349/U_Q15/U_R341
for MOR comment.
P.25 [VGA (Memory BUS) 4/6]Change R5795/R5796/R5809/R5810 to 40.2 ohm
for AMD comment.
P.34 [CRT]NC R5752 for no need of semi-PNP function.
(2009/09/12)
P.80 [VGA Power (ATI_VDD)] Change PC159/PC160 to 1C-2B20105-K100(NC)
for more stability.
P.01 [Index page]Update information.
P.02 [BLOCK DIAGRAM]Update information.
P.10 [PCH (HDA,JTAG,SAT)]Update SPI ROM information.
CC
P.49 [eSATA Combo Conn.]Del F10 for no need.
P.49 [LVDS Connector]Add F15/L99 to follow M870.
P.10 [PCH (HDA,JTAG,SAT)]Add 100K pull-low resistors R5969/R5970/R5971
4
3
2
1
P.65 [AUDIO (Power)*]Change U_C467 to 1C-2B20103-K200
for MOR comment to use the same kind of Capacitor.
P.50 [PCIE (MS) 1/2]Change R5912/R5913/R5914/R5911/R5915/R5916/R5917/R5918
/R5919 to 33ohm for correcting SI test fail.
P.51 [PCIE (SD) 2/2]Change R5920/R5921/R5922/R5923/R5924 to 33ohm
for correcting SI test fail.
(2009/09/13)
P.34 [CRT]Change CN20 to DZ11A91-SB281-4H for different package.
P.68 [AUDIO (Ext MIC Jack)*]Change U_CN5 to JA63331-R1T0-7H for ME request.
(2009/09/14)
P.45 [LAN (88E8059) 1/2]Change C995 to 10uF for Marvell comment.
P.74 [SYS Power (+3_3V/+5V)] Change PR122/PR201 to 2.2 ohm for RF noise.
P.78 [CPU Power_VHCORE] Change PR563 to NC, change PU28 pin25 connect
to PROCHOT# for design change.
P.04 [ARD (CLK,MISC,JTAG)]Add off-page PROCHOT#.
P.54 [Felica Connector]NC R5963/F14, stuff C869/U48/R630/C845/R5964
for Felica fuse solution fail.
P.49 [eSATA Combo Conn.]Add R5974/R5975/R5976/R5977 to reduce the trace length
on U214 for vendor request.
(2009/09/15)
P.11 [PCH (PCI-E,SMBUS,CLK)]Make R902/R903 from +3VRUN pull-high
to +3VALW pull-high for Intel recommendation.
P.38 [HDMI]Change CN21 to DF03-577-1931.
(2009/09/16)
P.14 [PCH (PCI,USB,NVRAM)]NC R1466 for Intel Braidwood disable guideline.
on SPI0_MOSI/SPI0_CLK/SPI0_CS# for Intel EDS request.
P.15 [PCH (GPIO,VSS_NCTF,RSVD)]Change R943/R974/R982/R1626 to 1R-0000103-J200.
P.63 [AUDIO (MUTE)*]Change U_R340/U_R350/U_R663 to 1R-0000103-J200.
P.62 [AUDIO (CODEC)*]Change U_R652/U_R662 to 1R-0000103-J200.
P.52 [Camera Connector]Add R5972/F16 for adding fuse solution.
P.25 [LVDS Connector]NC CN13 Pin1/Pin5/Pin6 for del EDID function.
P.24 [VGA (I/O) 3/6]NC U204B ATI_LVDS_SCL/ATI_LVDS_SDA for del EDID function.
P.20 [DDRIII(SO-DIMM_0) 1/2]NC CAP13 for no need.
P.21 [DDRIII(SO-DIMM_1) 2/2]NC CAP22 for no need.
P.25 [VGA (Memory BUS) 4/6]Change Madison/Park description.
P.25 [VGA (Memory BUS) 4/6]NC R5806/R5807/R5808 for AMD comment.
P.63 [AUDIO (CODEC)*]Change the setting to ALC269
(NC: U_C441/R5943/U_R5789, Stuff U_C930/R5944/U_R5790).
P.71 [DCIN&Charger]Change PL3 to NC for costdown.
BB
P.75 [VTT&PCH Power(+1_05V)]Change PR44 from 0ohm to 2.2ohm for vendor suggest.
P.76 [DDR3 Power (+1_5V/+0_75V)]Change PR39 from 0ohm to 2.2ohm
for vendor suggest.
P.80 [VGA Power (ATI_VDD)]Change PR549 from 0ohm to 2.2ohm for vendor suggest.
P.57 [Touch Pad]Del F12 for no need.
P.35 [LVDS]Update Panel ID information.
P.51 [AUDIO (CODEC)*]Change U_C787/U_C476/U_C459 to 1C-2B20103-K200.
P.28 [VRAM(DDR3)# 1/4]Change C6303 to 1C-2B20103-K200 for MOR comment
to use the same kind of Capacitor.
P.29 [VRAM(DDR3)# 2/4]Change C6304 to 1C-2B20103-K200 for MOR comment
to use the same kind of Capacitor.
P.30 [VRAM(DDR3)# 3/4]Change C6257 to 1C-2B20103-K200 for MOR comment
to use the same kind of Capacitor.
P.31 [VRAM(DDR3)# 4/4]Change C6258 to 1C-2B20103-K200 for MOR comment
to use the same kind of Capacitor.
AA
P.28 [VRAM(DDR3)# 1/4]Change C4028/C4036 to 1C-2B20103-K200
for MOR comment to use the same kind of Capacitor.
P.80 [VGA Power(ATI_VDD)]Change PC172 to 1C-2B20103-K200
for MOR comment to use the same kind of Capacitor.
P.77 [SYS Power(+1_8V)]Change PC247 to 1C-2B20103-K200
for MOR comment to use the same kind of Capacitor.
5
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M960&M970 H ModelSA
M960&M970 H ModelSA
M960&M970 H ModelSA
Date:Sheet
Date:Sheet
3
2
Date:Sheet
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
CCPBG - R&D Division
CCPBG - R&D Division
CCPBG - R&D Division
of
of
of
9093Thursday, December 24, 2009
9093Thursday, December 24, 2009
1
9093Thursday, December 24, 2009
Page 91
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4
3
2
1
M960/M970 PVT
(2009/09/19)
P.25 [VGA (Memory BUS) 4/6]Change R5805 to 10k
for AMD comment.
P.25 [VGA (Memory BUS) 4/6]Add R5981 pull-high to +3VRUN on TESTEN
for AMD hang-up workaround.
P.24 [VGA (I/O) 3/6]Add R5978 pull-low to GND on ATI_JTAG_RST
DD
for AMD hang-up workaround.
P.24 [VGA (I/O) 3/6]Add R5979 pull-high to +3VRUN on ATI_JTAG_TMS
for AMD hang-up workaround.
P.24 [VGA (I/O) 3/6]Add R5980 between R_XTALSSIN and ATI_JTAG_TCLK
for AMD hang-up workaround.
(2009/11/04)
P.07 [ARD (GRAPHICS POWER)] Delete PJ43 for redundant design of
EVT & DVT
P.34 [CRT] Add F17 for current limit by MOR comment
P.74 [SYS Power (+3_3V/+5V)] Delete PJ11 and PJ12 for redundant
design of EVT & DVT
P.75 [VTT&PCH Power(+1_05V)] Delete PJ22 and PJ23 for redundant
design of EVT & DVT
P.76 [DDR3 Power(+1_5V/+0_75V)] Delete PJ26 and PJ27 for redundant
design of EVT & DVT
P.77 [SYS Power(+1_8V)] Delete PJ36 for redundant design of EVT & DVT
CC
P.78 [CPU Power_VHCORE] Change PC112 from 68u_25V to
OS_Con cap 47u_25V by MOR request
P.80 [VGA Power(ATI_VDD)] Delete PJ31 and PJ37 for redundant
design of EVT & DVT
(2009/11/12)
P.25 [VGA (Memory BUS)] Change R5805 to NC & Mount R5981 for AMD suggestion
P.39 [EC+KBC(NPCE783L)] Add R5982 on OVT_EC# for GPIO70 need pull high
P.62 [SWITCH (Botton & KB LED)*] Exchange function name for Assist &
Web button
P.35 [LVDS] No mount R5940 to cancell Instant_On function by MOR request
P.39 [EC+KBC(NPCE783L)] No mount R5851 to cancell Instant_On function
by MOR request
P.55 [Status LED & LID] R689 change resistor value to 300 Ohm, R692 change
resistor value to 909 Ohm, R693 change value to 300 Ohm, R5945~R5947
change resistor value to 392 Ohm for LED brightness by MOR request
P.37 [LVDS Connector] Change CN13 to 1N-004000E-FKG0 for better L6 process
BB
P.40 [KB Connector] Add TP1233,TP1234 for BFT test
P.35 [LVDS] Add TP1231,TP1232 for BFT test
P.51 [PCIE(SD) 2/2] Add TP1239,TP1240 for BFT test
P.57 [Touch Pad] Add TP1245~TP1250 for BFT test
P.54 [Felica Connector] Add TP1241~TP1244 for BFT test
(2009/11/16)
P.71 [DCIN&Charger] Change pc126 from 1000P_50V_0603_X7R to 1000pF_50V_0402_X7R
for MOR request
P.78 [CPU Power_VHCORE] Change pc253 from 1000P_16V_0402_X7R to
1000pF_50V_0402_X7R for MOR request
P.82 [OVP protection] Change pc41 from 1000P_16V_0402_X7R to 1000pF_50V_0402_X7R
for MOR request
P.10 [PCH (HDA,JTAG,SAT)] Update U43 schematic symbol
P.73 [Identify IC] Update PU5 schematic symbol
P.52 [Camera Connector] L93,L94 change to Bead,MAX ECHO,EBMS100505A121 0.5A,
AA
120ohm/100MHz,25%,0402(1005mm) by MOR request
P.67 [Audio] U_L4,U_L5 change to Bead,MAX ECHO,EBMS100505A121 0.5A,
120ohm/100MHz,25%,0402(1005mm) by MOR request
P.45 [LAN (88E8059) 1/2] C6077 change to SMD,MLCC,X7R,1000pF,50V,10%,0402
by MOR request
5
4
P.63 [AUDIO (CODEC)*] U_C440 change to SMD,MLCC,X7R,1000pF,50V,10%,0402
by MOR request
P.46 [LAN (Transformer) 2/2] C568 change to SMD,MLCC,X7R,1000pF,50V,10%,0402
by MOR request
P.57 [Touch Pad] C130,C133 change to SMD,MLCC,NPO,47pF,50V,5%,0402
by MOR request
P.39 [EC+KBC(NPCE783L)] C22 change to SMD,MLCC,NPO,22pF,50V,5%,0402
by MOR request
P.50 [PCIE (MS) 1/2] C544,C785,C786 change to SMD,MLCC,NPO,22pF,50V,5%,0402
by MOR request
P.63 [AUDIO (CODEC)*] U_C439 change to SMD,MLCC,NPO,22pF,50V,5%,0402
by MOR request
P.64 [AUDIO (MUTE)*] U_R351 change to SMD,RES,200K,1/16W,5%,0402
by MOR request
P.64 [AUDIO (MUTE)*] U_R352 change to SMD,RES,33K,1/16W,5%,0402
by MOR request
P.64 [AUDIO (MUTE)*] U_R341,U_R349, change to SMD,RES,10K,1/16W,5%,0402
by MOR request
P.10 [PCH (HDA,JTAG,SAT)] R5905, change to SMD,RES,51ohm,1/16W,5%,0402
by MOR request
P.39 [EC+KBC(NPCE783L)] RP1,RP20,RP90 change to SMD,RES,10K,1/16W,5%,0402
and locations are R5991~R5996 by MOR request
P.39 [EC+KBC(NPCE783L)] RP21, change to SMD,RES,2.2K,1/16W,5%,0402
and locations are R5987,R5988 by MOR request
P.39 [EC+KBC(NPCE783L)] RP22, change to SMD,RES,4.7K,1/16W,5%,0402
and locations are R5989,R5990 by MOR request
P.43 [Express Card] Update U42 Schematic symbol
P.55 [Status LED & LID] Change TP1224~TP1230 to top for BFT test
(2009/11/17)
P.83 [HOLE & AMI LABEL] Add BOSS2 for M960 wireless card use only
P.44 [Mini-PCIE Card (WLAN)] Add TP1235~TP1238 on BT_WLAN_SW# &
GND for BFT test
P.45 [LAN (88E8059) 1/2] LAN chip 88E8059 change packing method to
tapping for better L6 process
P.24 [VGA (I/O) 3/6]Connect a stable clock source (from clock gen SS 27MHz) to
GPIO26_TCK.
Add 5991 pull-down with 10K ohm to ground for the Park/Madison JTAG test
block intermittently fails to initialize correctly. Incorrect
initialization may result in a failure to boot.
P.35 [LVDS] SW1 change from 12-pin to 8-pin panel ID SW
P.15 [PCH (GPIO,VSS_NCTF,RSVD)] NC_R5931 & move R5939 from P.35
to P.15
P.39 [EC+KBC(NPCE783L)] Move R5940 from P.35 to P.39
(2009/11/18)
P.57 [Touch Pad] Add F12 for cable short test fail
P.35 [LVDS] Add test point from TP1251~TP1260 for panel ID switch BFT test
P.58 [Thermal Sensor] Delete VGA thermal sensor function, NC_U26,
NC_R946, NC_C534, NC_C547 because GPU support DTS function
P.25 [VGA (Memory Bus) 4/6] Change R5878 resistor value from
680 Ohm to 51 Ohm for memory reset circuit update from AMD
P.55 [Status LED & LID)] Change U21 to E-CMOS EC2618NLB1GR
for distance can't meet MOR spec
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
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History(8)
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M960&M970 H ModelSA
M960&M970 H ModelSA
M960&M970 H ModelSA
Date:Sheet
Date:Sheet
3
2
Date:Sheet
HON HAI Precision Ind. Co., Ltd.
CCPBG - R&D Division
CCPBG - R&D Division
CCPBG - R&D Division
9193Thursday, December 24, 2009
9193Thursday, December 24, 2009
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M960/M970 PVT
(2009/11/19)
P.24 [VGA (I/O) 3/6] Add TP1261,TP1262 on GPIO8 & GPIO 22 for reserve
AMD errata solution
P.11 [PCH (PCI-E,SMBUS,CLK)] Reserve R5992~R6000 for Intel FCIM function
P.78 [CPU Power_VHCORE] Change PR554 and PR558 from 0ohm to 2.20hm for EMI
request
DD
P.80 [VGA Power(ATI_VDD)] Change PR183 from 15.4k to 15k for VGA Park high
level request
change PR210 from NC_7.15K to 68k for VGA Madison high level request
(2009/11/20)
P.24 [VGA (I/O) 3/6]Delete R5978,R5979,R5980 for needless
P.24 [VGA (I/O) 3/6]NC R5991 and add R6001(NC) for AMD Errata suggestion
P.25 [VGA (Memory BUS]NC R5981 for AMD Errata suggestion
P.15 [PCH]Change R5939 to mount for Panel ID setting requirement
P.64 [Audio(Mute)]Change U_R364 from 33kohm to 3.3kohm for satisfy hFE under
100 as MOR's suggestion.
P.45 [LAN]Change R84 from 4.7kohm to 0ohm for vendor modification
(2009/11/21)
P.24 [VGA]Add R6002,R6003,Y9,C6342,C6343 and NC them, it reserve for
Intel FCIM function.
P.69 [Audio (USB)*]Change the footprint of U_CN2,U_CN3,U_CN6 as SMT suggestion.
CC
P.42 [Debug Port]Add C6344 for EMI request.
P.66 [AUDIO]Add C6345 for EMI request.
P.46 [LAN]Change L47 from 100R to 300R for EMI request.
P.71 [DCIN&Charger]: Dcbatout Add PC574 0.1uf,PC575 0.1uf,PC576 4700pf ,
PC577 4700pf for EMI request
4
3
2
1
(2009/11/23)
P.57 [TouchPad]Change CN8 from FOX_GB5RF060-1203-7H to FOX_GB5RF060-1203-8F
as ME's request.
P.10 [PCH]Change C6352 from 0.1uF to 33pF(mount) and R618 from 33ohm
to 47ohm as EMC request.
P.81 [Other power plan]Change PC188 from 10uF to 1uF(mount) for improve
power signal.
P.63 [Audio]Change U_R661,U_R671,U_R676,U_673,U_R321 from 0402 to 0201 for
layout space concern.
(2009/11/24)
P.25 [VGA]Change R5805 from 10k to 5.1k as AMD's suggestion
P.35 [LVDS]Change SW1 from DHNF-04-T-Q-T-R_SW-SMD8P to
DHNF-06-T-Q-T/R_SW-SMD12 for shortage issue.
(2009/11/28)
P.74 [SYS Power]Change PC578,PC579 from 1C-2B20681-M000 to 1C-2B20681-K000
for PUR's suggestion.
P.46 [LAN]Change L47 from 1L-BACMS16-0809 to 1L-BTB1608-080D for PUR's
suggestion.
P.42 [Debug Port]NC CN30 for EMC solution.
P.41 [SPI Flash ROM]NC U3,R43,C20 and mount R775 for EMC solution.
P.80 [VGA Power(ATI_VDD)]:
1.PR183=10.5k for VGA M92 XT high voltage level request
2.PR183=10.5k for VGA M92 XTX high voltage level request
3.PR183=34.8k for VGA M96 high level request
4.PR183=75k for VGA madision high level request
5.PR183=15K for VGA Park high level request
6.NC PR210
P.74 [SYS Power (+3_3V/+5V)]:Add PC578 and PC579 680pf near PQ70 for EMI request
P.78 [CPU Power_VHCORE]:change PC151 and PC156 from NC to mount 0.1uf
for EMI request
P.81 [Others power plane]:Add PC584 680pf,PC585 0.1uf near PQ26 for EMI request.
(2009/11/22)
P.60 [Audio]Add C6348~C6351 for speaker noise issue.
P.10 [PCH]Add C6352,C6353 and NC them, reserve for EMI request.
P.63 [AUDIO]NC U_C439 and add U_C931(NC) for EMI request.
P.55 [LED]Change R5945,R5946,R5947 from 392ohm to 649ohm and R390 from
120ohm to 261ohm as DQA&ME request.
P.63 [Audio]Change U_R668,U_R665,U_R660,U_R670,U_R672,U_R659(22ohm)
BB
from 0402 to 0201 for implement ME solution and layout space is not enough.
And change U_R667,U_R664(33kohm), and R5943(NC),R5944(0ohm),
and U_R339(20kohm), and U_R338(39.2kohm), and U_R652,U_662(10kohm)
from 0402 to 0201 for implement ME solution and layout space is not enough.
(2009/11/23)
P.39 [EC]Delete R5983,R5984 and add RP20 for layout space concern
P.81 [Other power plane]Change PR661 from 0603 to 0402 for MOR request
to cost down.
P.15 [PCH]Delete RP19 and add R6004,R6005,R6006 for MOR request to cost down.
P.52 [Camera]Change C9 from 1C-2Y70106-Y001 to 1C-2Y70106-Y000 for MOR request
to cost down.
P.64 [Audio]Change U_Q20 form 2N7002W to SRK7002 for ESD issue.
P.25 [VGA]Change R5805 from NC to mount for AMD suggestion.
P.83 [HOLE]Change H30,H29,H8,H10,H4 hole size as ME's request.
P.34 [CRT]Change CN20 from FOX_DZ11A91-SB281-4H to FOX_DZ11AE1-SB1SD-4H
as ME's request.
AA
P.61 [Audio/USB DB CONN]Change CN31 from FOX_GB5RF500-1203-7H to
M960/M970 MP
(2009/12/22)
P.76 [DDR3 Power(+1_5V/+0_75V)] Mount PQ59, change PR600 resistor to 0 Ohm &
no mount PR145 to change the enable signal to RUN_PWRGD by MOR request.
P.38 [HDMI] Change CN21 symbol from 2N-0019007-MKG0 to 2N-0019003-MKG0
to improve factory process
(2009/12/23)
P.80 [VGA Power(ATI_VDD)] 1.PR222=39.2k for VGA M92 XTX 1.0VPEG 1.1V voltage
request
2.PR222=27k for VGA Park 1.0VPEG 1.0V voltage
request
3.PR222=27k for VGA Madison 1.0VPEG 1.0V voltage
request
P.25 [VGA (Memory Bus 4/6)] 1.R5795, R5796, R5809, R5810=100 for VGA M92XTX
voltage reference
2.R5795, R5796, R5809, R5810=40.2 for VGA Park
voltage reference
3.R5795, R5796, R5809, R5810=40.2 for VGA Madison
voltage reference
P.83 [HOLE & AMI LABEL] Mount AMI label for AMI certifcate
P.10 [PCH (HDA,JTAG,SAT)] No mount CN18, U43, C815, R542 & Mount R1551 for
needless in MP
P.64 [AUDIO (MUTE)*] Change U_Q15 with ESD protection for factory ESD issue
FOX_GB5RF500-1203-8H for ME's request.
P.66 [Audio (Audio/USB CONN)*]Change U_CN1 from FOX_GB5RF500-1203-7H to
FOX_GB5RF500-1203-8H as ME's request.
P.54 [Felica]Change CN7 from FOX_GB5RF060-1203-7H to FOX_GB5RF060-1203-8F
as ME's request.
5
4
FOXCONN
FOXCONN
FOXCONN
Title
Title
Title
History(9)
History(9)
History(9)
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
A3
A3
A3
M960&M970 H ModelSA
M960&M970 H ModelSA
M960&M970 H ModelSA
Date:Sheet
Date:Sheet
3
2
Date:Sheet
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
CCPBG - R&D Division
CCPBG - R&D Division
CCPBG - R&D Division
of
of
of
9293Thursday, December 24, 2009
9293Thursday, December 24, 2009
1
9293Thursday, December 24, 2009
Page 93
5
4
3
2
1
M960/M970 MP
(2009/12/24)
P.83 [HOLE & AMI LABEL]Delete BOSS2 for needless from ME's request
P.46 [LAN(Transformer)]Change L70 from LANKOM to DELTA for LANKOM transformer issue
in PVT
P.45 [LAN]Add R6010 reserve for 8057 solution
P.04 [ARD]Delete R937,R930 for MOR's request
DD
P.06 [ARD]Delete R860 for MOR's request
P.24 [VGA]Delete R5785,R5788,R5789 for MOR's request
P.39 [EC]Delete R39,R46 for MOR's request
P.44 [Mini-PCIE Card]Delete R5901 for MOR's request
P.57 [Touch Pad]Delete R5869,R5868 for MOR's request
(2009/12/28)
P.10 [PCH]Change R618 from 47ohm to 68ohm and Change C6353 from NC_0.1uF to mount 22pF
for EMC audio FFC issue
P.63 [Audio]Change U_R326 from 22ohm to 0ohm for EMC audio FFC issue
CC
BB
AA
HON HAI Precision Ind. Co., Ltd.
HON HAI Precision Ind. Co., Ltd.
FOXCONN
FOXCONN
FOXCONN
Title
Title
Title
History(10)
History(10)
History(10)
SizeDocument NumberRev
SizeDocument NumberRev
SizeDocument NumberRev
A3
A3
A3
M960&M970 H ModelSA
M960&M970 H ModelSA
M960&M970 H ModelSA
Date:Sheet
Date:Sheet
5
4
3
2
Date:Sheet
HON HAI Precision Ind. Co., Ltd.
CCPBG - R&D Division
CCPBG - R&D Division
CCPBG - R&D Division
of
of
of
9393Monday, December 28, 2009
9393Monday, December 28, 2009
1
9393Monday, December 28, 2009
Page 94
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